Course Title

ASIC Design

Time: 3 Hrs Max. Marks: 75

Section A
Answer all the Questions (10 x 1 = 10)

1. The manufacturing lead time is typically ____ for a full custom IC.
A 8 weeks B 25 weeks
C 1 day D 8 days
2. The expander logic is used to ______.
A decrease the number of product terms B increase the number of product terms
C decrease the number of sum terms D increase the number of sum terms
3. VHDL stands for
A Very High Speed Integrated circuits Hardware Development Language
B Very High Speed Internal circuits Hardware Description Language
C Variable High Speed Integrated circuits Hardware Description Language
D Very High Speed Integrated circuits Hardware Description Language
4. A pure function that returns the ___ each time the function is called with the same actual.
A zero B different value
C same value D one
5. The IEEE standard for Verilog HDL is __________.
A IEEE Std 1364-1994 B IEEE Std 1364-1993
C IEEE Std 1364-1991 D IEEE Std 1364-1995
6. Which is not a correct method of specifying time scale in verilog?
A 1ns/1ps B 10ns/1ps
C 100ns/100ps D 100ns/110ps
7. _________ provides a link between an HDL and a netlist.
A Partitioning B Simulation
C Logic synthesis D Routing
8. Which one is not a goal of floor planning?
A Arrange the blocks on a chip B Decide the location of the I/O pads
C Decide the type of power distribution D Minimize all the critical net delays
9. The error analysis is reduced in _________ method of testing.
A D- Algorithm B Boolean difference
C Stuck at D none of these
10. The LFSR in BIST stands for
A Linear Fractional Stable Noise B linear feedback shift register
C Local Fixed Service Provider D line feedback shift register
 Section B
Answer all the Questions (5 x 5 = 25)

11. a) Write note on semicustom ASIC.

(OR)
b) Explain briefly the PLA.
12. a) Explain the data objects in VHDL.
(OR)
b) Write a VHDL program for 4:1 multiplexer using dataflow modeling.
13. a) Explain the operators in Verilog HDL.
(OR)
b) Discuss the procedural assignment statements in Verilog HDL.
14. a) Write note on FSM synthesis.
(OR)
b) Briefly explain the global routing.
15. a) Write about the D- Algorithm.
(OR)
b) Write note on sequential logic circuit testing.

Section C
Answer all the Questions (5 x 8 = 40)

16. a) Explain in detail the programmable ASIC technologies.

(OR)
b) Describe the Xilinx XC 4000 family architecture.
17. a) Write a VHDL program for MOD-8 counter using behavioral model.
(OR)
b) Explain about the package declaration and package body in VHDL.
18. a) Explain the gate level modeling with example.
(OR)
b) Write the Verilog HDL program for ALU using behavioral modeling.
19. a) Explain the types of simulation.
(OR)
b) Discuss the placement in detail.
20. a) Explain the Path sensitization and Boolean difference with an example.
(OR)
b) Explain in detail the built-in self test.
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