IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, VOL. 5, NO.
4, JULY 2015
THz Letters
A 0.3 THz Radiating Active 27 Frequency Multiplier Chain With 1 mW
Radiated Power in CMOS 65-nm
Samuel Jameson, Student Member, IEEE, and Eran Socher, Senior Member, IEEE
Abstract—In this paper, a 27 radiating active frequency multi-
plier chain at 288 GHz is presented. The circuit output is connected
to a single on-chip ring antenna radiating a record high total radi-
ated power of 1 mW for a DC power consumption of 284 mW at
288 GHz. The circuit has a 3 dB bandwidth of 15 GHz (277–292
GHz), an EIRP of 10.2 dBm and a record radiated DC-to-RF
efficiency of 0.34% for a radiating frequency multiplying chain,
enabled by direct drain transistor to on-chip antenna connection.
The antenna has a measured directivity of 10.2 dBi at 288 GHz.
Realized in a 65-nm technology, this is the first CMOS integrated
locked radiating source to achieve 1 mW of radiated power above
0.2 THz.
Index Terms—Antenna, CMOS, frequency multiplier, J-band,
mm wave, power amplifier, ring, source, sub-mm wave, THz,
X-band.
I. INTRODUCTION
O VER THE LAST decades, CMOS technology innova-
tions open the door to the possibility of designing full
CMOS integrated systems reaching THz frequencies. However,
large output power remains a real challenge at these frequencies.
The major challenges of THz transmitter realization in CMOS
are signal generation above the transistor cut-off frequency and
radiating the signal out of the silicon with significant power and
overall efficiency. The most common way to generate a signal
in the J-band (220–325 GHz) is by the use of either a VCO or
an active multiplier chain. Previous J-band VCO in standard
CMOS [1]–[4] and SOI CMOS [5] were realized. VCOs can
offer high output power [1]–[3] and efficiency [3], but need to
be locked in order to be useful in most system applications.
Such frequency locking is not trivial at THz frequencies and
would require a PLL implementation at very high frequencies
with very large locking range. The alternative is to take a locked
lower frequency signal below 20 GHz (for easier and cost ef-
fective implementation) and to feed it into a cascade of multi-
pliers and amplifiers until it reaches THz frequencies. Previous
active multiplier chains were realized in SiGe [6]–[8] and in
SOI CMOS [9]. The main reason why most of the active multi-
Manuscript received February 25, 2015; accepted May 20, 2015. Date of pub-
lication June 15, 2015; date of current version July 16, 2015.
The authors are with the School of Electrical Engineering, Tel Aviv
University, Tel Aviv 69978, Israel (e-mail: Mr.jamesonsamuel@gmail.com;
socher@eng.tau.ac.il).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TTHZ.2015.2439056
2156-342X © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
645
pliers are not designed in CMOS is due to the lower
which are barely above 200 GHz in this technology. A doubler
or a tripler [6]–[8] proceeded by a power amplifier is generally
designed at the output in the W-band or D-band to reach the
J-band and then the output is connected through a matching net-
work to the G-S-G pads on-chip. In both cases in CMOS, major
concerns are faced: large design and non-efficient PA for the
D-band to J-band doubler topology and low output power for
the W-band to J-band tripler topology. To radiate out the signal,
either an on-chip or off-chip antenna can be used but connecting
elements such as wire-bonds or flip-chip bumps are very lossy
at THz frequencies so an on-chip antenna seems to be a more vi-
able solution if it could be made efficient and wideband enough.
In order to connect the circuit output to the on-chip antenna, a
matching network is generally required introducing additional
loss but also radiating energy therefore decreasing the power in-
jected into the antenna. To maximize the radiated output power,
the ideal is to connect directly the antenna to the transistor drain.
In [3], we presented a ring antenna topology, demonstrating the
possibility of connecting an on-chip antenna directly to the tran-
sistor drains while being perfectly matched.
Based on this technique and an improved common-source
topology for the W-band to J-band tripler, a 27 active mul-
tiplier chain connected to an on-chip antenna in CMOS was de-
veloped and is presented in this paper. The circuit achieves a
record high total radiated power of 1 mW at 288 GHz with an
EIRP of 10.2 dBm from a single active circuit and antenna
chain. With a DC power consumption of 284 mW a record ra-
diated DC-to-RF efficiency (TRP/PDC) of 0.34% is achieved,
even the large multiplication number implemented. The circuit
architecture is detailed in Section II and Section III explains the
measurement setup and results.
II. CIRCUIT ARCHITECTURE
The circuit was designed using TSMC 65-nm process tech-
nology with a silicon thickness of 230 m. Fig. 1 shows the
circuit topology of the active frequency multiplier chain. The
output circuit frequency was designed to be around 275 GHz. To
reach a frequency of 275 GHz, the signal is multiplied 3 times
by 3 and is amplified twice: in -band and in the W-band. All
the transformers between the stages were designed using the 3.4
m thick top metal 9 layer and the 0.9 m thick metal 8 layer.
Decoupling capacitors based on MOSFET transistors were used
for each DC supply as well as ESD P-type diodes and a resistor
of 1 k in series to each gate to enable the chip packaging.
646
Fig. 1. Circuit topology with the transistor number of fingers.
Fig. 2. Simulated output power of the X-to-Ka-band tripler, Ka-band amplifier
and Ka-to-W-band tripler.
A. Frequency Multiplication From X-Band to W-Band
The first three stages (X-to- band tripler, -band ampli-
fier and -to-W band tripler) were designed with differential
cascodes. The bulk of the common gate transistor was shorted to
its source in the three cascode stages using isolated p-well tran-
sistors to deliver more power. The main advantage of the differ-
ential topology is the natural rejection of the even harmonics.
The three stages were designed with transistor finger width of
2 m and a gate length of 60 nm. The number of fingers of
and (common source and common gate, respectively) for
each stage are shown in Fig. 1. Fig. 2 below shows the output
power of each stage against input frequency. An input power of
8 dBm at X-band is assumed.
B. W-Band Power Amplifier
Because the bare transistor in this 65-nm CMOS
technology is only around 210 GHz, power amplifiers above
IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, VOL. 5, NO. 4, JULY 2015
Fig. 3. Simulated output power of the W-band to J-band tripler (injected power
into the on-chip antenna).
120 GHz do not provide much gain. Below 100 GHz, cas-
code topology can deliver more power than a common-source
topology but with reduced gain due to added parasitics. There-
fore to design the power amplifier centered at 92 GHz, a
cascade of common-source stages was chosen showing good
efficiency. All the transistors in the W-band power amplifier
were chosen with a 2 m finger width. Fig. 1 shows the
transistor number of fingers for each stage. The W-band PA
injects a maximum power of dBm at 92 GHz with a
dB bandwidth from 85 GHz to 96.3 GHz (12.5%) into the
W-to-J-band tripler transistors gates.
C. W-Band to J-Band Tripler
The last tripler was also designed using a common-source
topology. The transistors were chosen with a width of 1 m.
It demonstrates much better results compared with a cascode
topology around 300 GHz. To further reduce the W-band to
J-band conversion loss, degeneration inductors of 15 pH were
connected. As a result, it increases the transistor VGS amplitude
and therefore the 3rd harmonic transistor drain current. More
details can be found in [10] about the correlation between the
transistor Gate-Source voltage and the 3rd harmonic drain cur-
rent generation. Thanks to this technique, the conversion loss
from the fundamental to the 3rd harmonic signal was reduced to
10 dB compared to 13 dB without the degenerating inductors.
Fig. 3 below shows the simulated tripler output power against
the output frequency.
D. The On-Chip Ring Antenna
To radiate the energy out of the chip, an on-chip antenna was
implemented at the last tripler output. Since no PA can be de-
signed at 275 GHz in this technology, it is very important to
conserve the power delivered by the last tripler. In order to con-
nect the on-chip antenna to the circuit output, a matching net-
work is generally required introducing loss but also radiating
energy decreasing the injected power into the antenna. In [3], a
ring antenna topology was proposed so that direct connection to
the transistor drain replaces the matching network. This antenna
plays a double role: it acts both as an RF-choke loop inductor
at W-band frequencies and as a ring antenna radiating out the
JAMESON AND SOCHER: A 0.3 THz RADIATING ACTIVE 27 FREQUENCY MULTIPLIER CHAIN
Fig. 4. Simulated on-chip antenna model in CST Microwave Studio and its 3D
radiation pattern at 275 GHz.
Fig. 5. Simulated on-chip antenna -parameters and realized gain.
transistor 3rd harmonic signal by having its impedance close
to 50 around 275 GHz. The ring antenna was simulated as-
suming a silicon substrate of 230 m height with a 12
resistivity. In the 3D antenna model, the circuit elements close
to the ring antenna (last tripler transformer, pads, wire-bonds,
DC ground-plane, NT_N layer) were included to better match
the real antenna environment, having a non-negligible impact
on performance.
The ring antenna achieves a dB bandwidth of 120 GHz
(42%) and a realized gain of 8 dBi at 275 GHz (Figs. 4–5).
The antenna realized gain through the 120 GHz bandwidth is
between 1.5 dBi and 8 dBi. The simulated power injected
in the antenna is 1.6 dBm at 275 GHz (Fig. 3) and therefore
the simulated circuit EIRP is close to 9.5 dBm at 278 GHz.
III. MEASUREMENT RESULTS
The radiating active multiplier chain (RAMC) was fabricated
using TSMC 65 nm RF CMOS process and its die photo is
shown Fig. 6. The circuit occupies just 0.49 mm of silicon
area including pads. The RAMC was measured using an OML
220–325 GHz VNA extender used as a harmonic mixer (18th
harmonic of an LO signal provided by a E8257D Agilent signal
generator). The IF of the mixer was connected then to a N900A
Agilent signal analyzer. To calibrate the measurements, a ref-
erence active multiplier chain was built composed by an OML
6 multiplier S10MS-AG 75–110 GHz Millimeter wave source
module, a Millitech W-band GaN power amplifier and a Vir-
ginia Diode W-band to J-band tripler. The output power of this
chain was then measured with an Erickson PM4 calorimeter.
647
Fig. 6. Microscope photo of the circuit and photo of the circuit package for
measurement.
Fig. 7. Signal analyzer photo of the maximum received power at a distance of
5 mm from the extender with mm (WR-03) and 2D scan
results of the measured radiated power.
The OML J-band extender IF conversion loss was then de-em-
bedded for each frequency between 220 and 325 GHz. The cir-
cuit was glued on a Rogers 4350B PCB as shown in Fig. 6, with
the DC pads wire-bonded to a different line with parallels decou-
pling capacitors of 100 pF and 0.1 F. The X-band input G-S-G
pads of the circuit were wire-bonded to a 25 mm 50 PCB line
terminated by an SMA end-launch connector. The open wave-
guide of the WR-03 straight section connected to the OML ex-
tender was used as an antenna to detect the signal radiated from
the on-chip ring antenna. A distance of 5 mm was taken between
the open waveguide and the RAMC to ensure far-field beam
scanning measurements. The measurements were realized for a
nominal DC supply of 1.2 V for common-source topology and
2 V for cascode stages. Higher output power was measured for
larger than nominal supplies.
A minimum X-band input signal of dBm was required to
compensate for the LO path loss and deliver around 8.5 dBm
to the input pads. As shown in Fig. 7, the maximum single point
radiated power of the circuit achieved is 20 dBm at 288 GHz
(with an open waveguide at 5 mm) corresponding to an EIRP of
10.2 dBm. The setup conversion loss at 288 GHz is 10 dB.
The EIRP was also measured at distances from 5 mm to 120
mm and values between 10 dBm and 10.2 dBm were found.
The EIRP was also verified with a pyro-electric sensor using
a 10 Hz modulation and with a PM4 Erickson calorimeter and
EIRPs of 10 to 10.4 dBm were measured, respectively. To
measure the circuit total power radiated, a maximum mechan-
ically allowed scan of 15 16 mm was realized as in [3], [4].
As can be seen in the 2D scan shown in Fig. 7, the radiation
pattern presents a wide beam with 2 peaks spaced by 22 that
were also observed in simulation. The sum of all the radiated
powers collected in the scan area results in a record total radiated
power (TRP) of 1 mW for a single radiating active multiplying
648 IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, VOL. 5, NO. 4, JULY 2015

TABLE I
COMPARISON WITH PREVIOUS STATE-OF-THE-ART SOURCES ABOVE 200 GHZ

for a radiating frequency multiplier chain, especially consid-

ering the 27 frequency multiplication. This circuit occupies just
0.49 mm of silicon area.

Fig. 8. Measured EIRP and TRP against the frequency.
chain. The EIRP and TRP were also measured for frequencies
between 260 and 315 GHz which are the extreme frequencies at
which radiated signals could be observed. As shown in Fig. 8,
the RAMC has a 3 dB bandwidth of 5.3% (277–292 GHz).
From the measured EIRP and TRP, a 10.2 dBi antenna direc-
tivity was calculated. A comparison with state-of-the-art radi-
ating sources above 200 GHz is shown in Table I.
IV. CONCLUSION
A radiating 27 frequency multiplier chain at 288 GHz in
TSMC 65 nm CMOS was presented in this paper. This circuit
has a TRP of 1 mW and an EIRP of dBm, which is the
highest for silicon chips without a lens. It consumes only 284
mW resulting in a record radiated DC-to-RF efficiency of 0.34%
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