Percobaan IV

Perancangan dan Implementasi Display LCD

Menggunakan Modul VGA pada FPGA
Rinaldi Madani Pakpahan (14s16032)
Tanggal Percobaan : 08/12/2017
[ELS2104] [Sistem Digital]
[Laboratorium Sistem Kendali] – Teknik Elektro
Institut Teknologi Del

eg GPIO, serial communication using RS232, Audio

Abstrak—In practice of LCD Display Design and
Implementation using VGA Module on FPGA will do some
experiment. The experiment will be implemented in the design of
FPGA board, in the experiment of design implementation on
FPGA board will be conducted three experiments, the first
experiment will be carried out the experiment of drawing red and
white flag, the second will draw a box / square measuring 50 pixel
x 50 pixel on VGA screen . Objectives of the following practicum
Gain knowledge and experience of using interfaces on the FPGA
evaluation board and Understanding how VGA works in general.
Kata Kunci— FPGA, VGA, LCD Display.
I. PENDAHULUAN
In practice of design and implementation of LCD display
using VGA module on FPGA will be implemented VGA
module. In the following lab will do the output by
producing a red and white flag and a small box measuring
50 pixels x 50 pixels and will also produce a rainbow color
output. In this lab is a continuation of previous practice so if
you do not know the previous practicum it will be difficult
to practice this time. The purpose of practicum design and
implementation of LCD display using VGA module on
FPDA is as follows:
Gain knowledge and experience using the interface on
the FPGA evaluation board and Understand how VGA
works in general.
II. LANDASAN TEORETIS
Video Graphics Array (VGA) is still a popular interface
for a display. VGA interface is still found in several devices
now, such as LCD screens and projectors. VGA interface is
also available on Altera board that we use today. In this
experiment VGA display is used to display the design
results that we designed to be more interesting, not limited
to just LED or 7-Segment. The purpose of this experiment
is also to illustrate the use of I / O interface on the FPGA,
CODEC, 16x2 character LCD.
The FPGA is an integrated circuit that can be configured
and programmed over and over again. The FPGA consists
of programmable logic, which is called logic blocks. In this
experiment, FPGA is used as a link between the VGA
module used with the LCD display display.
III. METODOLOGI
Alat Percobaan:
 Board FPGA tipe UP2 atau DE1
 Catu daya + kabel dan konektor tambahan serta kabel
downloader
 Monitor LCD
Prosedur Percobaan:
Percobaan berikut dibagi menjadi 3 percobaan yaitu
percobaan pertama pelangi, kedua menggambar merah putih
pada layar LCD, ketiga menggambar kotak merah 50 pixel x
50 pixel.
Pada percobaan pertama akan dilakukan
pengimplementasian dari code yang diberikan lalu diupload ke
laya LCD. Dan pada percobaan berikut akan dilakukan dengan
menggunakan modul VGA yang telah tersedia.
Pada percobaan kedua akan menggambar merah putih pada
layar LCD dengan menggunakan modul VGA dan juga code
yang diberikan dimodifikasi sehingga menghasilkan output
merah putih pada layar LCD.
Pada percobaan ketiga yaitu menggambar kotak kecil
berwarna merah berukuran 50 pixel x 50 pixel pada layar
LCD. Percobaan ketiga sama halnya dengan percobaan kedua
yaitu code akan dimodifikasi sehingga menghasilkan output
pada layar yaitu kotak kecil berukuran 50 pixel x 50 pixel.
IV. HASIL DAN ANALISIS
A. Percobaan 1.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; END IF;

ENTITY VGA IS -- IF (v_cnt >= 0) AND (v_cnt <= 240) THEN

PORT( -- red_signal0 <= '1';
clk : IN STD_LOGIC; -- red_signal1 <= '1';
hsync, -- red_signal2 <= '1';
vsync, -- green_signal0 <= '0';
red0, -- green_signal1 <= '0';
red1, -- green_signal2 <= '0';
red2, -- blue_signal0 <= '0';
green0, -- blue_signal1 <= '0';
green1, -- END IF;
green2,
blue0, -- IF (v_cnt >= 241) AND (v_cnt <= 799) THEN
blue1 : OUT STD_LOGIC); -- red_signal0 <= '1';
end VGA; -- red_signal1 <= '1';
-- red_signal2 <= '1';
ARCHITECTURE behavior of VGA IS -- green_signal0 <= '1';
-- green_signal1 <= '1';
SIGNAL clk25 :STD_LOGIC; -- green_signal2 <= '1';
-- blue_signal0 <= '1';
SIGNAL h_sync, v_sync : STD_LOGIC; -- blue_signal1 <= '1';
-- END IF;
SIGNAL video_en, horizontal_en, vertical_en :
STD_LOGIC;
IF (h_cnt >= 0) AND (h_cnt <= 240) THEN
SIGNAL red_signal0,red_signal1,red_signal2, red_signal0 <= '1';
green_signal0,green_signal1,green_signal2, red_signal1 <= '1';
blue_signal0,blue_signal1 : STD_LOGIC; red_signal2 <= '1';
green_signal0 <= '1';
SIGNAL h_cnt, green_signal1 <= '1';
v_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0); green_signal2 <= '1';
blue_signal0 <= '1';
blue_signal1 <= '1';
BEGIN END IF;

video_en <= horizontal_en AND vertical_en;

IF (h_cnt >= 239) AND (h_cnt <= 399) THEN

process (clk) red_signal0 <= '0';
begin red_signal1 <= '0';
if clk'event and clk='1' then red_signal2 <= '0';
if (clk25 = '0')then green_signal0 <= '1';
clk25 <= '1'; green_signal1 <= '1';
else green_signal2 <= '1';
clk25 <= '0'; blue_signal0 <= '0';
end if; blue_signal1 <= '0';
end if; END IF;
end process;
IF (h_cnt >= 400) AND (h_cnt <= 479) THEN
PROCESS red_signal0 <= '1';
variable cnt: integer range 0 to 25000000; red_signal1 <= '1';
red_signal2 <= '1';
BEGIN green_signal0 <= '0';
green_signal1 <= '0';
WAIT UNTIL(clk25'EVENT) AND (clk25 = '1'); green_signal2 <= '0';
IF(cnt = 25000000)THEN blue_signal0 <= '0';
cnt := 0; blue_signal1 <= '0';
ELSE END IF;
cnt := cnt + 1;
IF (h_cnt >= 480) AND (h_cnt <= 799) THEN blue0 <= blue_signal0 AND video_en;
red_signal0 <= '0'; blue1 <= blue_signal1 AND video_en;
red_signal1 <= '0'; hsync <= h_sync;
red_signal2 <= '0'; vsync <= v_sync;
green_signal0 <= '0';
green_signal1 <= '0'; END PROCESS;
green_signal2 <= '0'; END behavior;
blue_signal0 <= '1';
blue_signal1 <= '1'; Di atas merupakan code dari percobaan pertama yaitu pelangi
END IF; pada layar LCD.

IF (h_cnt <= 755) AND (h_cnt >= 659) THEN

h_sync <= '0';
ELSE
h_sync <= '1';
END IF;

IF (h_cnt = 799) THEN

h_cnt <= "1111111111";
ELSE
h_cnt <= h_cnt + 1;
END IF;

IF (v_cnt >= 524) AND (h_cnt >= 699) THEN

v_cnt <= "0000000000";
ELSIF (h_cnt = 699) THEN B. Percobaan 2.
v_cnt <= v_cnt + 1; LIBRARY IEEE;
END IF; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
IF (v_cnt <= 494) AND (v_cnt >= 493) THEN
v_sync <= '0'; ENTITY VGA IS
PORT(
ELSE clk : IN STD_LOGIC;
v_sync <= '1'; hsync,
END IF; vsync,
red0,
red1,
IF (h_cnt <= 639) THEN red2,
horizontal_en <= '1'; green0,
green1,
ELSE green2,
horizontal_en <= '0'; blue0,
END IF; blue1 : OUT STD_LOGIC);
end VGA;
IF (v_cnt <= 479) THEN
vertical_en <= '1'; ARCHITECTURE behavior of VGA IS
ELSE
vertical_en <= '0'; SIGNAL clk25 :STD_LOGIC;
END IF;
SIGNAL h_sync, v_sync : STD_LOGIC;

red0 <= red_signal0 AND video_en; SIGNAL video_en, horizontal_en, vertical_en :

red1 <= red_signal1 AND video_en; STD_LOGIC;
red2 <= red_signal2 AND video_en;
green0 <= green_signal0 AND video_en; SIGNAL red_signal0,red_signal1,red_signal2,
green1 <= green_signal1 AND video_en; green_signal0,green_signal1,green_signal2,
green2 <= green_signal2 AND video_en;
 blue_signal0,blue_signal1 : STD_LOGIC; ELSE
h_sync <= '1';
SIGNAL h_cnt, END IF;
v_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0);

BEGIN IF (h_cnt = 799) THEN

h_cnt <= "1111111111";
video_en <= horizontal_en AND vertical_en; ELSE
h_cnt <= h_cnt + 1;
END IF;
process (clk)
begin IF (v_cnt >= 524) AND (h_cnt >= 699) THEN
if clk'event and clk='1' then v_cnt <= "0000000000";
if (clk25 = '0')then ELSIF (h_cnt = 699) THEN
clk25 <= '1'; v_cnt <= v_cnt + 1;
else END IF;
clk25 <= '0';
end if;
end if; IF (v_cnt <= 494) AND (v_cnt >= 493) THEN
end process; v_sync <= '0';

PROCESS ELSE
variable cnt: integer range 0 to 25000000; v_sync <= '1';
END IF;
BEGIN

WAIT UNTIL(clk25'EVENT) AND (clk25 = '1'); IF (h_cnt <= 639) THEN

IF(cnt = 25000000)THEN horizontal_en <= '1';
cnt := 0;
ELSE ELSE
cnt := cnt + 1; horizontal_en <= '0';
END IF; END IF;

IF (v_cnt >= 0) AND (v_cnt <= 240) THEN IF (v_cnt <= 479) THEN
red_signal0 <= '1'; vertical_en <= '1';
red_signal1 <= '1'; ELSE
red_signal2 <= '1'; vertical_en <= '0';
green_signal0 <= '0'; END IF;
green_signal1 <= '0';
green_signal2 <= '0';
blue_signal0 <= '0'; red0 <= red_signal0 AND video_en;
blue_signal1 <= '0'; red1 <= red_signal1 AND video_en;
END IF; red2 <= red_signal2 AND video_en;
green0 <= green_signal0 AND video_en;
IF (v_cnt >= 241) AND (v_cnt <= 799) THEN green1 <= green_signal1 AND video_en;
red_signal0 <= '1'; green2 <= green_signal2 AND video_en;
red_signal1 <= '1'; blue0 <= blue_signal0 AND video_en;
red_signal2 <= '1'; blue1 <= blue_signal1 AND video_en;
green_signal0 <= '1'; hsync <= h_sync;
green_signal1 <= '1'; vsync <= v_sync;
green_signal2 <= '1';
blue_signal0 <= '1'; END PROCESS;
blue_signal1 <= '1'; END behavior;
END IF;
Code diatas merupakan code dari hasil output pada layar LCD
yaitu bendera merah putih.

IF (h_cnt <= 755) AND (h_cnt >= 659) THEN

h_sync <= '0';
 BEGIN

video_en <= horizontal_en AND vertical_en;

process (clk)
begin
if clk'event and clk='1' then
if (clk25 = '0')then
clk25 <= '1';
else
clk25 <= '0';
end if;
end if;
end process;
Pada hasil berikut merupakan modifikasi dari percobaan
pertama. Pada percobaan pertama merupakan warna pelangi
PROCESS
sedangkan untuk percobaan kedua dimodifikasi pada code
variable cnt: integer range 0 to 25000000;
program sehingga menghasilkan keluaran pada layar LCD
berwarna bendera merah putih.
BEGIN

C. Percobaan 3. WAIT UNTIL(clk25'EVENT) AND (clk25 = '1');

LIBRARY IEEE; IF(cnt = 25000000)THEN
USE IEEE.STD_LOGIC_1164.ALL; cnt := 0;
USE IEEE.STD_LOGIC_ARITH.ALL; ELSE
USE IEEE.STD_LOGIC_UNSIGNED.ALL; cnt := cnt + 1;
END IF;
ENTITY VGA IS
PORT(
clk : IN STD_LOGIC;
hsync, IF (h_cnt >= 0) AND (h_cnt <= 800) THEN
vsync, red_signal0 <= '1';
red0, red_signal1 <= '1';
red1, red_signal2 <= '1';
red2, green_signal0 <= '1';
green0, green_signal1 <= '1';
green1, green_signal2 <= '1';
green2, blue_signal0 <= '1';
blue0, blue_signal1 <= '1';
blue1 : OUT STD_LOGIC); END IF;
end VGA;
IF (v_cnt >= 100) AND (v_cnt <= 200) AND (h_cnt >=
ARCHITECTURE behavior of VGA IS 100) AND (h_cnt <= 180) THEN
red_signal0 <= '1';
SIGNAL clk25 :STD_LOGIC; red_signal1 <= '1';
red_signal2 <= '1';
SIGNAL h_sync, v_sync : STD_LOGIC; green_signal0 <= '0';
green_signal1 <= '0';
SIGNAL video_en, horizontal_en, vertical_en : green_signal2 <= '0';
STD_LOGIC; blue_signal0 <= '0';
blue_signal1 <= '0';
SIGNAL red_signal0,red_signal1,red_signal2, END IF;
green_signal0,green_signal1,green_signal2,
blue_signal0,blue_signal1 : STD_LOGIC;

SIGNAL h_cnt, IF (h_cnt <= 755) AND (h_cnt >= 659) THEN
v_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0); h_sync <= '0';
ELSE
 h_sync <= '1';
END IF;

IF (h_cnt = 799) THEN

h_cnt <= "0000000000";
ELSE
h_cnt <= h_cnt + 1;
END IF;

IF (v_cnt >= 524) AND (h_cnt >= 699) THEN

v_cnt <= "0000000000";
ELSIF (h_cnt = 699) THEN
v_cnt <= v_cnt + 1;
END IF;
Untuk menghasilkan seperti gambar diatas maka dilakukan
modifikasi pada code pada percobaan pertama sehingga
IF (v_cnt <= 494) AND (v_cnt >= 493) THEN --
menghasilkan keluaran pada layar LCD seperti gambar diatas.
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v_sync <= '0';
V. SIMPULANS
ELSE
v_sync <= '1'; Untuk pengimplementasian rangkaian sekuensial
END IF; diperlukan perantara yaitu layar LCD yang
dilanjutkan akan diimplementasikan melalui modul
VGA pada FPGA. Sinyal yang digunakan untuk
IF (h_cnt <= 639) THEN pengimplementasian dari modul VGA ada 2 yaitu
horizontal_en <= '1'; sinyal warna dan sinyal sinkron yang nantinya akan
dilanjuti menjadi sinyal analog sebelum
ELSE ditransmisikan ke layar LCD.
horizontal_en <= '0';
END IF; REFERENSI

IF (v_cnt <= 479) THEN 1. PANDAPOTAN SIAGIAN,”PETUNJUK PRAKTIKUM

vertical_en <= '1'; SISTEM DIGITAL, LABORATORIUM DASAR TEKNIK
ELSE ELEKTRO”, SITOLUAMA,2015.
vertical_en <= '0'; 2. Stephen Brown and Zvonko Vranesic, Fundamentals
END IF; of Digital Logic with VHDL Design Third Edition,
hal 109-114, McGraw-Hill, SanFrancisco, 2009.
3. https://en.wikipedia.org/wiki/Field-
red0 <= red_signal0 AND video_en; programmable_gate_array.
red1 <= red_signal1 AND video_en; Diakses pada 10 Desember 2017.
red2 <= red_signal2 AND video_en;
green0 <= green_signal0 AND video_en;
green1 <= green_signal1 AND video_en;
green2 <= green_signal2 AND video_en;
blue0 <= blue_signal0 AND video_en;
blue1 <= blue_signal1 AND video_en;
hsync <= h_sync;
vsync <= v_sync;

END PROCESS;
END behavior;

Di atas merupakan code dari percobaan ketiga yaitu

menggambar kotak kecil berwarna merah berukuran 50 pixel x
50 pixel.
Lampiran