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PCS-985B

Generator Relay
Instruction Manual

NR Electric Co., Ltd.


Preface

Preface

Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.

Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.

Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.

This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.

Health and Safety


The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.

When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.

Before working in the terminal strip area, the equipment must be isolated.

Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.

Qualified personnel are individuals who:

 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;

 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;

 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;

 Are trained in emergency procedures (first aid).

Instructions and Warnings


The following indicators and standard definitions are used:

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Preface

DANGER!

It means that death, severe personal injury, or considerable equipment damage will occur if safety
precautions are disregarded.

WARNING!

It means that death, severe personal, or considerable equipment damage could occur if safety
precautions are disregarded.

CAUTION!

It means that light personal injury or equipment damage may occur if safety precautions are
disregarded. This particularly applies to damage to the device and to resulting damage of the
protected equipment.

WARNING!

The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.

WARNING!

During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.

Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.

In particular, the general facility and safety regulations for work with high-voltage equipment must
be observed. Noncompliance may result in death, injury, or significant equipment damage.

DANGER!

Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.

WARNING!

 Exposed terminals

Do not touch the exposed terminals of this equipment while the power is on, as the high voltage
generated is dangerous

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Preface

 Residual voltage

Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. It
takes a few seconds for the voltage to discharge.

CAUTION!

 Earth

The earthing terminal of the equipment must be securely earthed

 Operating environment

The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.

 Ratings

Before applying AC voltage and current or the DC power supply to the equipment, check that they
conform to the equipment ratings.

 Printed circuit board

Do not attach and remove printed circuit boards when DC power to the equipment is on, as this
may cause the equipment to malfunction.

 External circuit

When connecting the output contacts of the equipment to an external circuit, carefully check the
supply voltage used in order to prevent the connected circuit from overheating.

 Connection cable

Carefully handle the connection cable without applying excessive force.

Copyright

Version: R1.00 NR ELECTRIC CO., LTD.

69 Suyuan Avenue. Jiangning, Nanjing 211102, China

P/N: EN_YJBH2601.0086.0001 Tel: +86-25-87178185, Fax: +86-25-87178208

Website: www.nrelect.com, www.nari-relays.com

Copyright © NR 2011. All rights reserved Email: nr_techsupport@nari-relays.com

We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.

The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.

We reserve the rights to make technical improvements without notice.

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Table of Contents

Preface ..................................................................................................... i
Introduction ................................................................................................................i
Health and Safety .......................................................................................................i
Instructions and Warnings ........................................................................................i

Table of Contents ................................................................................... v


1 Introduction ......................................................................................... 1
1.1 Application...........................................................................................................1
1.2 Function ...............................................................................................................1
1.2.1 Protection Function ............................................................................................................... 1

1.2.2 Typical Applications ............................................................................................................... 4

1.2.3 Congiruation Explanation ...................................................................................................... 7

1.3 Features ...............................................................................................................9


1.4 Order Information.............................................................................................. 13

2 Technical Data ................................................................................... 15


2.1 Electrical Specifications ................................................................................... 15
2.1.1 AC Current Input ................................................................................................................. 15

2.1.2 AC Voltage Input ................................................................................................................. 15

2.1.3 Power Supply ...................................................................................................................... 15

2.1.4 Binary Input ......................................................................................................................... 16

2.1.5 Binary Output ...................................................................................................................... 16

2.2 Mechanical Specifications ............................................................................... 16


2.3 Ambient Temperature and Humidity Range .................................................... 17
2.4 Communication Port ......................................................................................... 17
2.4.1 EIA-485 Port ....................................................................................................................... 17

2.4.2 Ethernet Port ....................................................................................................................... 17

2.4.3 Optical Fibre Port ................................................................................................................ 17

2.4.4 Print Port ............................................................................................................................. 18

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2.4.5 Clock Synchronization Port ................................................................................................. 18

2.5 Type Tests .......................................................................................................... 18


2.5.1 Environmental Tests ............................................................................................................ 18

2.5.2 Mechanical Tests................................................................................................................. 19

2.5.3 Electrical Tests .................................................................................................................... 19

2.5.4 Electromagnetic Compatibility ............................................................................................. 19

2.6 Certifications ..................................................................................................... 20


2.7 Protective Functions......................................................................................... 20
2.7.1 Generator-transformer Unit/Main Transformer Differential Protection ................................. 20

2.7.2 Restricted Earth Fault Protection of Main Transformer (REF) ............................................. 21

2.7.3 Generator/Excitor Differential Protection ............................................................................. 21

2.7.4 Step-down Transformer/Excitation Transfomer Differential Protection ................................ 21

2.7.5 Generator Inter-turn Protection ........................................................................................... 21

2.7.6 Generator Stator Earth-fault Protection ............................................................................... 22

2.7.7 Stator Earth-fault Protection with External Inject Principle .................................................. 22

2.7.8 Generator Rotor Earth-fault Protection ............................................................................... 22

2.7.9 Generator Stator Overload Protection ................................................................................. 23

2.7.10 Generator Negative-sequence Overload Protection ......................................................... 23

2.7.11 Excitation Windings Overload Protection .......................................................................... 23

2.7.12 Generator Loss-of-excitation Protection ............................................................................ 23

2.7.13 Generator Out-of-step Protection ...................................................................................... 24

2.7.14 Generator Overvoltage Protection .................................................................................... 24

2.7.15 Generator/Main Transformer Over-excitation Protection ................................................... 24

2.7.16 Generator Reverse Power Protection ............................................................................... 24

2.7.17 Generator Frequency Protection ....................................................................................... 24

2.7.18 Generator Inadvertent Energization Protection ................................................................. 25

2.7.19 Generator Startup/shutdown Protection ............................................................................ 25

2.7.20 Pole Discrepancy Protection ............................................................................................. 25

2.7.21 Low-impedance Protection................................................................................................ 25

2.7.22 Voltage Controlled Overcurrent Protection ........................................................................ 26

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2.7.23 Main Transformer Zero-sequence Overcurrent Protection ................................................ 26

2.7.24 Main Transformer Gap Zero-sequence Protection ............................................................ 26

2.7.25 Mechanical Protection ....................................................................................................... 26

3 Operation Theory .............................................................................. 27


3.1 Overview ............................................................................................................ 27
3.2 Fault Detector (FD) ............................................................................................ 27
3.2.1 Generator-transformer Unit/Main Transformer Differential Protection ................................. 28

3.2.2 Phase-to-phase Backup Protection of Main Transformer .................................................... 28

3.2.3 Earth Backup Protection of Main Transformer .................................................................... 28

3.2.4 Differential Protection of Step-down Transformer................................................................ 28

3.2.5 Backup Protection of Step-down Transformer ..................................................................... 28

3.2.6 Differential Protection of Generator ..................................................................................... 29

3.2.7 Differential Protection of Generator ..................................................................................... 29

3.2.8 Stator Earth-fault Protection of Generator ........................................................................... 29

3.2.9 Rotor Earth-fault Protection of Generator ........................................................................... 29

3.2.10 Stator Overload Protection of Generator ........................................................................... 29

3.2.11 Negative-sequence Overload Protection of Generator ...................................................... 30

3.2.12 Loss-of-excitation Protection of Generator ........................................................................ 30

3.2.13 Out-of-step Protection of Generator .................................................................................. 30

3.2.14 Overvoltage Protection of Generator ................................................................................ 30

3.2.15 Over-excitation Protection of Generator ............................................................................ 30

3.2.16 Generator Power Protection.............................................................................................. 30

3.2.17 Generator Frequency Protection ....................................................................................... 30

3.2.18 Generator Inadvertent Energization Protection ................................................................. 30

3.2.19 Generator Startup/shutdown Protection ............................................................................ 31

3.2.20 Differential Protection of Exciter/Excitation Transformer ................................................... 31

3.2.21 Overcurrent Protection/Overload Protection of Exciter/Excitation Transformer ................. 31

3.2.22 Pole Discrepancy Protection ............................................................................................. 31

3.2.23 Breaker Failure Protection ................................................................................................ 31

3.2.24 Mechanical Protection ....................................................................................................... 31

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3.3 Differential Protection (GTU, MT, ST and ET) ................................................. 32


3.3.1 Operation Characteristic ..................................................................................................... 32

3.3.2 Inrush Current Detection Element ....................................................................................... 34

3.3.3 CT Saturation Detection Element ........................................................................................ 35

3.3.4 High-setting Percentage Differential Protection Element (HSDP) ....................................... 36

3.3.5 Unrestrained Instantaneous Differential Protection Element (UIDP) ................................... 37

3.3.6 Differential Current Abnormality Alarm and CT Circuit Failure Blocking .............................. 37

3.3.7 Overexcitation Detection Element ....................................................................................... 37

3.3.8 Logic Scheme ..................................................................................................................... 38

3.4 Differential Protection (Gen and Exc).............................................................. 39


3.4.1 Percentage Differential Protection (SPDP) ......................................................................... 39

3.4.2 High Performance Blocking Technique in Case of CT Saturation ....................................... 40

3.4.3 High-setting Percentage Differential Protection (HSDP) ..................................................... 41

3.4.4 Unrestrained Instantaneous Differential Protection (UIDP) ................................................. 41

3.4.5 Differential Current Abnormality Alarm and CT Circuit Failure Blocking .............................. 41

3.4.6 Logic Scheme ..................................................................................................................... 41

3.5 DPFC Differential Protection ............................................................................ 42


3.5.1 Operation Characteristic ..................................................................................................... 43

3.5.2 Differential Current Abnormality Alarm and CT Circuit Failure Blocking .............................. 44

3.5.3 Logic Scheme ..................................................................................................................... 44

3.6 Phase-to-phase Backup Protection of Main Transformer ............................. 45


3.6.1 Voltage Controlled Overcurrent Protection .......................................................................... 45

3.6.2 Impedance Protection ......................................................................................................... 47

3.6.3 Protection for Other Abnormality ......................................................................................... 49

3.7 Earth-fault Backup Protection for Main Transformer ..................................... 49


3.7.1 Zero-sequence Overcurrent Protection ............................................................................... 49

3.7.2 Inverse-time Zero-sequence Overcurrent Protection .......................................................... 51

3.7.3 Gap Zero-sequence Protection ........................................................................................... 52

3.7.4 Zero-sequence Voltage Alarm at LV side of Main Transformer ........................................... 53

3.7.5 VT Circuit Supervision......................................................................................................... 53

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3.8 Generator Inter-turn Protection ....................................................................... 53


3.8.1 High-sensitive Transverse Differential Protection ................................................................ 53

3.8.2 Longitudinal Zero-sequence Voltage Protection.................................................................. 55

3.8.3 VT Circuit Failure Alarm and Blocking ................................................................................. 57

3.8.4 DPFC Inter-turn Protection.................................................................................................. 57

3.9 Phase-to-phase Backup Protection of Generator .......................................... 58


3.9.1 Voltage Controlled Overcurrent Protection .......................................................................... 58

3.9.2 Impedance Protection ......................................................................................................... 59

3.10 Stator Earth-fault Protection .......................................................................... 61


3.10.1 Fundamental Zero-sequence Overvoltage Protection ....................................................... 61

3.10.2 Third Harmonic Voltage Ratio Protection .......................................................................... 62

3.10.3 Third Harmonic Voltage Differential Protection.................................................................. 63

3.10.4 VT Circuit Failure Blocking ................................................................................................ 63

3.10.5 Logic Scheme ................................................................................................................... 64

3.11 Stator Earth-fault Protection with Voltage Injection ..................................... 66


3.11.1 Earthing Resistance Criterion ............................................................................................ 66

3.11.2 Earthing Current Criterion ................................................................................................. 67

3.11.3 External Voltage Circuit Monitoring ................................................................................... 67

3.11.4 Logic Scheme ................................................................................................................... 68

3.12 Rotor Earth-fault Protection with Ping-pang Type ....................................... 68


3.12.1 One-point Earth-fault Protection........................................................................................ 68

3.12.2 Two-points Earth fault Protection ...................................................................................... 69

3.13 Rotor Earth-fault Protection with Voltage Injection...................................... 70


3.13.1 One-point Earth-fault Protection........................................................................................ 70

3.13.2 Two-point Earth-fault Protection ........................................................................................ 71

3.14 Stator Overload Protection............................................................................. 72


3.14.1 Definite-time Stator Overload Protection ........................................................................... 72

3.14.2 Inverse-time Stator Overload Protection ........................................................................... 72

3.15 Negative-sequence Overload Protection ...................................................... 74


3.15.1 Definite-time Negative-sequence Overload Protection ..................................................... 74

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3.15.2 Inverse-time Negative-sequence Overload Protection ...................................................... 74

3.16 Loss-of-excitation Protection......................................................................... 76


3.16.1 Undervoltage Criterion ...................................................................................................... 76

3.16.2 Stator-side Impedance Criterion........................................................................................ 76

3.16.3 Rotor-side Criterion ........................................................................................................... 77

3.16.4 Logic Scheme ................................................................................................................... 78

3.17 Out-of-step Protection .................................................................................... 80


3.18 Overvoltage Protection ................................................................................... 81
3.19 Over-excitation Protection ............................................................................. 82
3.19.1 Definite-time Over-excitation Protection ............................................................................ 82

3.19.2 Inverse-time Over-excitation Protection ............................................................................ 83

3.20 Power Protection............................................................................................. 84


3.20.1 Reverse Power Protection ................................................................................................ 84

3.20.2 Sequence Tripping Reverse Power Protection.................................................................. 85

3.20.3 Low Power Protection ....................................................................................................... 85

3.21 Frequency Protection ..................................................................................... 86


3.21.1 Underfrequency Protection ............................................................................................... 86

3.21.2 Overfrequency Protection ................................................................................................. 86

3.21.3 Logic Scheme ................................................................................................................... 86

3.22 Inadvertent Energization Protection.............................................................. 86


3.23 Breaker Flashover Protection ........................................................................ 88
3.24 Startup and Shutdown Protection ................................................................. 89
3.25 Overload Protection of Excitation Windings ................................................ 90
3.25.1 Definite-time Excitation Winding Overload Protection ....................................................... 90

3.25.2 Inverse-time Excitation Winding Overload Protection ....................................................... 90

3.26 Excitation Transformer/Exciter Protection.................................................... 91


3.26.1 Excitation Transformer and Exciter Differential Protection ................................................ 91

3.26.2 Excitation Transformer and Exciter Overcurrent Protection .............................................. 92

3.27 Backup Protection of Step-down Transformer ............................................. 92


3.27.1 Backup Protection for HV side of Step-down Transformer ................................................ 92

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3.27.2 Backup Protection for LV side of Step-down Transformer ................................................. 93

3.27.3 Earth-fault Protection for LV side of Step-down Transformer ............................................ 94

3.27.4 Other Protection of Step-down Transformer ...................................................................... 95

3.28 Pole Disagreement Protection ....................................................................... 95


3.29 Breaker Failure Protection ............................................................................. 96
3.30 Restrict Earth-fault Protection (REF) of Main Transformer ......................... 97
3.30.1 Amplitude ratio compensation ........................................................................................... 97

3.30.2 Percentage Restricted Earth Fault Protection (PcntREF) ................................................. 98

3.30.3 Unrestrained Instantaneous Restricted Earth Fault Protection (UIREF) ........................... 99

3.30.4 Influence from CT Transient Characteristics ................................................................... 100

3.30.5 Zero-sequence Differential Current Abnormality Alarm ................................................... 100

3.30.6 Logic Scheme ................................................................................................................. 100

3.31 CT Circuit Supervision ................................................................................. 101


3.31.1 Three-phase Current Circuit Failure Alarm...................................................................... 101

3.31.2 Differential Current Alarm in Differential Protection Circuit .............................................. 101

3.31.3 Alarm or Blocking to Differential Protection by CT Circuit Failure.................................... 101

3.32 VT Circuit Supervision.................................................................................. 102


3.32.1 VT circuit of Any Side Failure Alarm ................................................................................ 102

3.32.2 Voltage Valance on Generator Terminals ........................................................................ 102

3.32.3 Three-phase Voltage Circuit Failure Supervision ............................................................ 103

3.33 Mechanical protection .................................................................................. 103

4 Supervision ..................................................................................... 105


4.1 Overview .......................................................................................................... 105
4.2 Startup Self-testing ......................................................................................... 105
4.2.1 System Boot...................................................................................................................... 105

4.2.2 Initialization Software ........................................................................................................ 106

4.2.3 Platform Software Initialization and Monitoring ................................................................. 106

4.3 Continuous Self-testing.................................................................................. 106


4.4 Alarm Messages .............................................................................................. 107

5 Measurement and Recording......................................................... 119


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5.1 Metering ........................................................................................................... 119


5.1.1 Measured Voltages and Currents ...................................................................................... 119

5.1.2 Sequence Voltages and Currents ..................................................................................... 119

5.1.3 RMS of Voltages and Currents .......................................................................................... 119

5.1.4 Differential Current and Relevant Quantities ..................................................................... 119

5.1.5 Phase Angles .................................................................................................................... 119

5.1.6 Measurement Display Quantities ...................................................................................... 119

5.1.7 All Metering Data ............................................................................................................... 119

5.2 Signaling .......................................................................................................... 126


5.3 Event and Fault Recorder ............................................................................... 130
5.3.1 Introduction ....................................................................................................................... 130

5.3.2 Event & Fault Records ...................................................................................................... 130

5.3.3 Type of Event .................................................................................................................... 130

5.3.4 State Change of Binary Inputs .......................................................................................... 130

5.3.5 Relay Alarm Signals .......................................................................................................... 130

5.3.6 Protection Element ............................................................................................................ 131

5.4 Disturbance Record ........................................................................................ 135

6 Hardware ......................................................................................... 137


6.1 Overview .......................................................................................................... 137
6.2 Plug-in Module Terminal Definition ............................................................... 140
6.2.1 PWR Plug-in Module (Power Supply) ............................................................................... 140

6.2.2 MON Plug-in Module (Monitor) ......................................................................................... 142

6.2.3 DSP Module 1 (Protection Calculation) ............................................................................. 144

6.2.4 DSP Module 2 (Fault Detector) ......................................................................................... 145

6.2.5 BI Module (Binary Input) ................................................................................................... 145

6.2.6 BO Module (Binary Output) ............................................................................................... 147

6.2.7 AI Module (Analog Input) .................................................................................................. 154

7 Settings ............................................................................................ 159


7.1 Communication Settings ................................................................................ 159
7.1.1 Setting Description ............................................................................................................ 160

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7.1.2 Access Path ...................................................................................................................... 163

7.2 Device Settings ............................................................................................... 163


7.2.1 Setting Description ............................................................................................................ 163

7.2.2 Access Path ...................................................................................................................... 164

7.3 Label Settings ................................................................................................. 164


7.3.2 Access Path ...................................................................................................................... 164

7.4 Display Control Settings ................................................................................ 164


7.4.2 Access Path ...................................................................................................................... 164

7.5 System Settings .............................................................................................. 165


7.5.1 Equipment Settings ........................................................................................................... 165

7.5.2 Logic Settings of Configuring Functions ............................................................................ 165

7.5.3 Main Transformer System Settings ................................................................................... 169

7.5.4 Generator System Settings ............................................................................................... 172

7.5.5 System Settings of Step-down Transformer 1&2............................................................... 174

7.5.6 System Settings of Excitation Transformer or Exciter ....................................................... 176

7.5.7 Implicit Configuration Settings........................................................................................... 178

7.6 Protection Settings ......................................................................................... 182


7.6.1 Settings of Differential Protection of Generator-transformer Unit (GTU) ........................... 182

7.6.2 Settings of Differential Protection of Main Transformer ..................................................... 184

7.6.3 Settings of Restricted Earth-fault Protection of Main Transformer .................................... 191

7.6.4 Settings of Phase-to-phase fault Protection of Main Transformer ..................................... 193

7.6.5 Settings of Earth-fault Protection of Main Transformer ..................................................... 198

7.6.6 Settings of Over-excitation Protection of Main Transformer .............................................. 203

7.6.7 Settings of Differential Protection of Generator ................................................................. 206

7.6.8 Settings of Turn-to-turn Fault Protection of Generator ...................................................... 209

7.6.9 Settings of Backup Protection of Generator ...................................................................... 211

7.6.10 Settings of Stator Earth-fault Protection .......................................................................... 216

7.6.11 Settings of Rotor Earth-fault Protection ........................................................................... 219

7.6.12 Settings of Thermal Overload Protection of Stator .......................................................... 221

7.6.13 Settings of Negative-sequence Overcurrent Protection .................................................. 223

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7.6.14 Settings of Loss-of-excitation Protection ......................................................................... 225

7.6.15 Settings of Out-of-step Protection ................................................................................... 230

7.6.16 Settings of Overvoltage Protection .................................................................................. 233

7.6.17 Settings of Overexcitation Protection of Generator ......................................................... 234

7.6.18 Settings of Power Protection of Generator ...................................................................... 237

7.6.19 Settings of Underfrequency and Overfrequency Protection ............................................ 239

7.6.20 Settings of Startup and Shutdown Protection of Generator ............................................. 241

7.6.21 Settings of Inadvertent Energization Protection of Generator ......................................... 243

7.6.22 Settings of Breaker Failure Protection of Generator ....................................................... 245

7.6.23 Settings of Differential Protection of Step-down Transformer 1&2 .................................. 246

7.6.24 Settings of Backup Protection at HVS of Step-down Transformer................................... 248

7.6.25 Settings of Backup Protection of Br1(2) of Step-down Transformer ................................ 252

7.6.26 Settings of Differential Protection of Excitation Transformer or Exciter ........................... 254

7.6.27 Settings of Backup Protection of Excitation Transformer or Exciter ................................ 255

7.6.28 Settings of Overload Protection of Excitation Transformer or Excitor .............................. 256

7.6.29 Settings of Mechanical Protection ................................................................................... 258

7.6.30 Settings of Pole Disagreement Protection of HVS of Main Transformer ......................... 259

7.7 Calculated Parameters ................................................................................... 261


7.7.1 Calculated Parameters of Secondary Rated Current ........................................................ 261

7.7.2 Calculated Parameters of Secondary Rated Voltage ........................................................ 263

7.7.3 Calculated Parameters of Differential Coefficient .............................................................. 264

8 Human Machine Interface .............................................................. 267


8.1 Overview .......................................................................................................... 267
8.1.1 Keypad Operation ............................................................................................................. 268

8.1.2 LED Indications ................................................................................................................. 269

8.1.3 Front Communication Port ................................................................................................ 270

8.1.4 Ethernet Port Setup .......................................................................................................... 270

8.2 Menu Tree ........................................................................................................ 271


8.2.1 Overview ........................................................................................................................... 271

8.2.2 Main Menus ...................................................................................................................... 272

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8.2.3 Sub Menus ........................................................................................................................ 274

8.3 LCD Display ..................................................................................................... 288


8.3.1 Overview ........................................................................................................................... 288

8.3.2 Normal Display.................................................................................................................. 288

8.3.3 Display Disturbance Records ............................................................................................ 289

8.3.4 Display Supervision Event ................................................................................................ 291

8.3.5 Display IO Events ............................................................................................................. 291

8.3.6 Display Device Logs ......................................................................................................... 292

8.4 Keypad Operation ........................................................................................... 293


8.4.1 View Device Measurements .............................................................................................. 293

8.4.2 View Device Status ........................................................................................................... 293

8.4.3 View Device Records ........................................................................................................ 293

8.4.4 Print Device Report ........................................................................................................... 294

8.4.5 View Device Setting .......................................................................................................... 295

8.4.6 Modify Device Setting ....................................................................................................... 295

8.4.7 Copy Device Setting ......................................................................................................... 298

8.4.8 Switch Setting Group ........................................................................................................ 298

8.4.9 Delete Device Records ..................................................................................................... 299

8.4.10 Modify Device Clock ....................................................................................................... 300

8.4.11 View Module Information ................................................................................................. 300

8.4.12 Check Software Version .................................................................................................. 301

8.4.13 Select Language ............................................................................................................. 301

9 Communication ............................................................................... 303


9.1 Overview .......................................................................................................... 303
9.2 Rear Communication Port Information ......................................................... 303
9.2.1 RS-485 Interface ............................................................................................................... 303

9.2.2 Ethernet Interface ............................................................................................................. 305

9.2.3 IEC60870-5-103 Communication ...................................................................................... 306

9.3 IEC60870-5-103 Interface over Serial Port .................................................... 306


9.3.1 Physical Connection and Link Layer ................................................................................. 307

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9.3.2 Initialization ....................................................................................................................... 307

9.3.3 Time Synchronization ........................................................................................................ 307

9.3.4 Spontaneous Events ......................................................................................................... 307

9.3.5 General Interrogation ........................................................................................................ 308

9.3.6 General Service ................................................................................................................ 308

9.3.7 Disturbance Records ........................................................................................................ 308

9.4 Modbus Protocol ............................................................................................. 308


9.4.1 Overview ........................................................................................................................... 308

9.4.2 Fetch Real-time Binary Status (Function Code: 02H) ....................................................... 309

9.4.3 Fetch Settings Value of Device (Function Code: 03H) ...................................................... 311

9.4.4 Fetch Relay Measurement Values of Device (Function Code: 04H) ................................. 311

9.4.5 Diagnostics (Function Code: 08H) .................................................................................... 311

9.4.6 Exception Responses ....................................................................................................... 311

9.5 Messages Description for IEC61850 Protocol .............................................. 311


9.5.1 Overview ........................................................................................................................... 311

9.5.2 Communication profiles .................................................................................................... 312

9.5.3 Server data organization ................................................................................................... 313

9.5.4 Server features and configuration ..................................................................................... 316

9.5.5 ACSI Conformance ........................................................................................................... 318

9.5.6 Logical Nodes ................................................................................................................... 321

9.6 DNP3.0 Interface ............................................................................................. 324


9.6.1 Overview ........................................................................................................................... 324

9.6.2 Link Layer Functions ......................................................................................................... 324

9.6.3 Transport Functions .......................................................................................................... 324

9.6.4 Application Layer Functions .............................................................................................. 324

10 Installation ..................................................................................... 327


10.1 Overview ........................................................................................................ 327
10.2 Safety Information......................................................................................... 327
10.3 Checking Shipment....................................................................................... 328
10.4 Material and Tools Required ........................................................................ 328

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10.5 Device Location and Ambient Conditions .................................................. 328


10.6 Mechanical Installation ................................................................................. 329
10.7 Electrical Installation and Wiring ................................................................. 330
10.7.1 Grounding Guidelines ..................................................................................................... 330

10.7.2 Cubicle Grounding .......................................................................................................... 330

10.7.3 Ground Connection on the Device .................................................................................. 331

10.7.4 Grounding Strips and their Installation ............................................................................ 332

10.7.5 Guidelines for Wiring ....................................................................................................... 332

10.7.6 Wiring for Electrical Cables ............................................................................................. 333

11 Commissioning ............................................................................. 335


11.1 Overview ........................................................................................................ 335
11.2 Safety Instructions ........................................................................................ 335
11.3 Commission Tools ........................................................................................ 336
11.4 Setting Familiarization .................................................................................. 336
11.5 Product Checks ............................................................................................. 337
11.5.1 With the Relay De-energized .......................................................................................... 337

11.5.2 With the Relay Energized ................................................................................................ 339

11.5.3 Print Fault Report ............................................................................................................ 342

11.5.4 On-load Checks .............................................................................................................. 342

11.6 Final Checks .................................................................................................. 343

12 Maintenance .................................................................................. 345


12.1 Appearance Check ........................................................................................ 345
12.2 Failure Tracing And Repair ........................................................................... 345
12.3 Replace Failed Modules ............................................................................... 345
12.4 Cleaning ......................................................................................................... 347
12.5 Storage ........................................................................................................... 347

13 Decommissioning and Disposal.................................................. 349


13.1 Decommissioning ......................................................................................... 349
13.2 Disposal ......................................................................................................... 349

14 Manual Version History ................................................................ 351


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1 Introduction

1 Introduction

1.1 Application
RCS-985 series generator-transformer unit protection have accumulated large field operation
experience, on this basis, combined with the latest computer technology and users′ requirement
and complex applications, and NR developed a new generation of PCS-985 series
generator-transformer unit protection. PCS-985 series inherits the benefits of RCS-985 series,
improves protection criterion, and provides more friendly human-machine interfaces.

PCS-985 supports conventional CT/VT and ECT/EVT. PCS-985 can be applied for large-scale
turbo-dynamo, gas-turbine generator and nuclear power generator with different connection
modes. It meets the requirements of power plant automation.

PCS-985B provides complete electric quantity protection of a generator-transformer unit which


usually comprises generator, main transformer, step-down transformer and exciter or excitation
transformer.

For a large-scale generator-transformer unit, two sets of PCS-985B can be used and then main
protection, abnormal operation condition protection and backup protection can be duplicated.
Control circuit and mechanical protection are installed on a separate panel. Two PCS-985B use
different CT groups and main and backup protection in one PCS-985B share one CT group. The
outputs correspond to various trip coils.

1.2 Function
Taking fully into account maximum configuration of large-scale generator-transformer unit,
PCS-985B suits the connection mode of two-windings main transformer (220kV, 500kV or above),
generator with capacity of 100MW or above, one or two step-down transformers (three windings or
split winding),excitation transformer or exciter.

1.2.1 Protection Function


PCS-985B can select to configure the following protection functions, and ―*‖ means that it is an
abnormality alarm function.

Table 1.2-1 Function configuration of generator

No. Function Stage Delay ANSI


1 Differential protection - - 87G
2 DPFC differential protection - - 87G
3 High sensitive transverse differential protection 2 - 87G
4 Longitudinal zero-sequence overvoltage protection for inter-turn fault 2 1 59N/60
5 DPFC directional protection for inter-turn fault 1 1 67
6 Voltage controlled overcurrent protection 2 1 50
7 Phase-to-phase impedance protection 2 1 21G

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8 Extreme current blocking function at generator terminal 1 1


9 Fundamental zero-sequence voltage protection for stator earth fault 2 1 64S
10 Third harmonic overvoltage ratio protection for stator earth fault 1 1 64S
11 Third harmonic overvoltage differential protection for stator earth fault 1 1 64S
12 100% stator earth-fault protection with voltage injection 2 1 64R
13 Rotor one-point earth-fault protection 2 1 64R1
14 Rotor two-point earth-fault protection 1 1 64R2
15 Definite-time stator overload protection 2 1 50S
16 Inverse-time stator overload protection - - 51S
17 Definite-time negative-sequence overload protection 2 1 50Q
18 Inverse-time negative-sequence overload protection - - 51Q
19 Loss-of-excitation protection 3 1 40
20 Out-of-step protection 2 1 78
21 Overvoltage protection 2 1 59
22 Definite-time over-excitation protection 2 1 24
23 Inverse-time over-excitation protection - - 24
24 Reverse-power protection 2 1 32R
25 Low-power protection 1 1 37G
26 Sequential tripping reverse-power protection 1 1 32R
27 Underfrequency protection 3 1 81U
28 Overfrequency protection 2 1 81O
29 Startup/shutdown protection of differential current 1 1
30 Startup/shutdown protection of zeros-equence voltage 1 1
31 Low-freuquency overcurrent protection 1 1 50
32 Inadvertent energization protection 1 1 50/27
33 Breaker failure protection 1 2 50BF
34 *Voltage balance function - - 60
35 *VT circuit supervision - - VTS
36 *CT circuit supervision - - CTS

Note!

Roter earth-fault protection can select voltage switchover pricinple or external voltage
injection principle.

Table 1.2-2 Function configuration of excitation transformer/excitor

No. Function Stage Delay ANSI


1 Differential protection - - 87ET
2 Overcurrent protection 2 1 50
3 Definite-time overload protection 1 1 50
4 Inverse-time overload protection - - 51

Table 1.2-3 Function configuration of main transformer

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No. Function Stage Delay ANSI


1 Generator-transformer unit differential protection - - 87GTU
2 Differential protection - - 87T
3 DPFC differential protection - - 87T
4 Restricted earth-fault protection - - 64REF
5 Phase-to-phase impedance protection at HV side 2 1 21P
6 Voltage controlled overcurrent protection at HV side 2 1 50
7 *Overload alarm 1 1 49
8 *Initiating cooling 2 1 49
9 Directional zero-sequence overcurrent protection at HV side 2 2 67G
10 Inverse-time zero-sequence overcurrent protection at HV side - - 51G
11 Gap zero-sequence voltage protection at HV side 1 2
12 Gap zero-sequence current protection at HV side 1 2
13 Zero-sequence voltage alarm at LV side 1 1
14 Definite-time over-excitation protection 2 1 24
15 Inverse-time over-excitation protection - - 24
16 Pole discrepancy protection at HV side 1 2 62PD
17 Breaker flashover protection 1 2
18 *VT circuit supervision - - VTS
19 *CT circuit supervision - - CTS

Table 1.2-4 Function configuration of step-down transformer

No. Function Stage Delay ANSI


1 Differential protection - - 87T
2 Voltage controlled overcurrent protection at HVside 2 1 50P
3 Voltage controlled overcurrent protection of branch 1 at LV side 2 1 50P
4 Voltage controlled overcurrent protection of branch 2 at LV side 2 1 50P
5 Zero-sequence overcurrent protection of branch 1 at LV side 2 1 50G
6 Zero-sequence overcurrent protection of branch 2 at LV side 2 1 50G
7 Overload alarm 1 1 49
8 Initiating cooling 1 1 49
9 Blocking on-load tap change (OLTC) 1 1
10 *VT circuit supervision - - VTS
11 *CT circuit supervision - - CTS

Table 1.2-5 mechanical function configuration

No. Function Stage Delay ANSI


1 Mechanical protection 1 1 1
2 Mechanical protection 2 1 1
3 Mechanical protection 3 1 1
4 Mechanical protection 4 1 1

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1 Introduction

Note!

The name of mechanical protection 1~4 can be modified.

1.2.2 Typical Applications


PCS-985B can be applied for four applications as shown in Figure 1.2-1~Figure 1.2-4. Connection
shown in the figure is that of panel A. However, connection of panel B including polarity mark of CT
is the same as panel A. The scheme is also adaptive to generator-transformer unit with the
capacity of 100MW and the same connection mode. Although exciter or excitation transformer is
drawn in these figures, either of them is applicable for any scheme.

1.2.2.1 Typical Application of PCS-985B

500kV

Panel A Panel B Panel C

Mechanical
PCS-985B PCS-985B
Protection

Main Transformer

Generator Step-down
Transformer

Excitor

Figure 1.2-1 Typical application 1

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1 Introduction

1.2.2.2 Typical Application 2 of PCS-985B

220kV
Busbar VT

Panel A Panel B Panel C


Mechanical
Main Protection
PCS-985B PCS-985B
Transformer Interposing
Relay Set

Generator Step-down
Transformer
Excitation
Transformer

Figure 1.2-2 Typical application 2

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1 Introduction

1.2.2.3 Typical Application 3 of PCS-985B

500kV

Panel A Panel B Panel C

Mechanical
PCS-985B PCS-985B
Protection

Main Transformer

Generator

Excitation Step-down
Transformer Transformer B

Step-down
Transformer A

Figure 1.2-3 Typical application 3

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1 Introduction

1.2.2.4 Typical Application 4 of PCS-985B

220kV
Busbar VT

Panel A Panel B Panel C


Mechanical
Main Protection
PCS-985B PCS-985B
Transformer Interposing
Relay Set

Generator

Step-down Step-down
Transformer A Transformer B
Excitor

Figure 1.2-4 Typical application 4

1.2.3 Congiruation Explanation

1.2.3.1 Differential Protection

1. For generator-transformer unit with the capacity of 300MW or above, panel A and B are both
equipped with generator-transformer unit differential protection, main transformer differential
protection, generator differential protection and step-down transformer differential protection.

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2. The scope of generator-transformer unit differential protection may cover generally LV side of
step-down transformer or its HV side if necessary.

3. For generator-transformer unit with capacity of 100MW~300MW, panel A and B are equipped
with main transformer differential protection, generator differential protection and step-down
transformer differential protection.

4. For generator-transformer unit differential protection, main transformer differential protection


and step-down transformer differential protection there are two kinds of discrimination
principle for inrush current: second harmonics discrimination and waveform discrimination. It
is recommended that one set of PCS-985B adopt second harmonics discrimination and the
other set adopt waveform discrimination.

5. For generator differential protection and main transformer differential protection, there are
also two kinds of percentage differential protection: variable Slope percentage differential
protection and DPFC percentage differential protection.

1.2.3.2 Backup Protection

1. Panel A and B are equipped with complete set of backup protection of generator-transformer
unit. Different CTs are used for them.

2. As to rotor earth-fault protection, two sets of such protection cannot work simultaneously
otherwise influence between them will appear. Only one set of rotor earth-fault protection can
be enabled during operation. If other set will be put into operation sometimes, this set shall be
quitted firstly.

1.2.3.3 Current Transformer

1. Panels A and B adopt different CT.

2. Main protection and backup protection share one group of CT.

3. The current of generator terminal is used by generator differential protection and main
transformer differential protection. These two kinds of differential protection can share one
group of CT without any influence. In fact two groups of CT input channel are provided in
PCS-985B. One of them is reserved for special case.

4. The current at HV side of step-down transformer is used by main transformer differential


protection and step-down transformer differential protection. Since capacities of these two
transformers are different to each other significantly, in order to ensure performance of
differential protection, it is better to adopt two groups of CT for them, one CT with large ratio is
prepared for main transformer differential protection, and the other with small ratio for
step-down transformer differential protection. However, if there is only one group of CT can be
used for them, it is also possible if make related configuration by software.

5. At 220kV side, there shall be one group of CT to be adopted dedicatedly for breaker failure
protection.

6. Generator reverse power protection can share one group of generator terminal CT with
generator differential protection, or adopt independent measurement CT.

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1 Introduction

1.2.3.4 Voltage Transformer

1. Panel A and B shall adopt different VT or its different windings if possible.

2. For generator inter-turnn protection, in order to prevent undesired operation due to VT circuit
failure at HV side used dedicatedly for this protection, one set of protection shall adopt two
groups of VT. However, if it is considered to adopt only independent VT windings, too much
VT will be installed at generator terminal and it is not reasonable. So it is recommended to
equip three windings of VT there, namely VT1, VT2 and VT3. Panel A adopts voltage from
VT1 and VT3 while panel B VT2 and VT3. During normal operation, panel A adopts VT1 and
panel B adopts VT2 while VT3 is backup to both of them. If circuit of VT1 or VT2 fails, VT3 will
be switched on automatically by software.

3. For zero-sequence voltage, there are two windings adopted by two sets of protection
equipments simultaneously in general.

1.3 Features
 High-performance general-purpose hardware and realtime calculations

Hardware structure of 32-bit microprocessors+dual DSP is adopted. A number of processors


operate in parallel. 32-bit microprocessors provide functions of MMI, communication, and printing
etc. The two DSPs provide protection operations and output logic. High performance hardware
ensures realtime calculation for all relays in each sampling interval of this relay. This relay adopts
32-bit high performance CPUs and DSPs, internal high-speed bus, and intelligent I/O. Both
hardware and software adopt modular design, which can be flexibly configured. Features include
versatility, easy expansion, and easy maintenance.

 Independent fault detector elements

The output mode of fault detector+protection operation eliminates the possibility of malfunction
and misjudgment caused by hardware fault of the device.

 Strong EM compatibility

Integral panel and fully enclosed chassis are adopted. Strong electricity and weak electricity are
strictly separated. Traditional rear board wiring mode is not used. At the same time, measures
against interference are taken in software design, greatly improving the immunity to disturbances.
EM radiation to outside satisfies relevant standards.

 Modular programs

Modular programs allow flexible protection configuration and easy functional adjustment.

 Variable slope percentage differential protection

Variable slope percentage characteristic is adopted for differential protection. Pickup slope and
maximum slope should be reasonably set, so that high sensitivity can be gained during internal
fault and transient unbalance current can be avoided during external fault. In order to prevent
undesired operation of differential protection due to CT saturation, measures to discriminate CT
saturation are provided for phase current at each side.

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1 Introduction

 DPFC percentage differential protection

DPFC percentage differential protection reflects only deviation components of differential current
and restraint current and is not effected by load current. It can detect light fault within transformer
and generator. Besides, it is insensitive to CT saturation since its restraint coefficient is set
comparatively high.

 Detect CT Saturation by asynchronous method

According to relation between DPFC restraint current and DPFC differential current of differential
protection, external or internal fault can be discriminated correctly. For external fault, waveform
discrimination of phase current and differential current is adopted. Undesired operation will not
occur if CT correct transfer time from primary to secondary side is not less than 5ms. As to internal
fault, the device will operate quickly.

 High-sensitive transverse differential protection

By adopting frequency tracking, digital filter and Fourier transformation, the filtration ratio of third
harmonic component can reach more than 100. All these countermeasure guarantees the
reliability of the protection in all occasions as mentioned as below:

The transverse differential protection can get reliable restraint effect because the faulty phase
current increases greatly while transverse differential current increases less in external fault
situation

The protection has very high operation sensitivity because transverse differential current
increases comparatively large whereas phase current change not too observably in slightly
inter-turn fault situation.

The high-setting stage of transverse differential protection will operate quickly and reliably when
severe inter-turn fault occurs in stator winding.

In case of phase-to-phase fault of stator winding, not only transverse differential current but also
phase current increase greatly, therefore just low percentage restraint by phase current
guarantees the reliable operation of transverse differential protection against the fault.

As for unbalanced transverse differential current increasing during normal operation condition,
transverse differential protection uses float threshold to avoid undesired operation.

 Percentage restraint interturn protection

By adopting frequency tracking, digital filter and Fourier transformation, the filtration ratio of third
harmonic component can reach more than 100. New criteria of generator current percentage
restraint technique:

Fault current increase greatly while longitudinal residual voltage increase less in external
three-phase fault, therefore the protection tends to be reliably restrained thanks to current
increment as restraint quantity.

If external asymmetric fault occurs, phase current increases greatly with negative-sequence
current, but the longitudinal residual voltage has a little bit increment, therefore the protection

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1 Introduction

tends to be reliably restrained by the mixing quantity of current increment and negative-sequence
component.

The protection has very high operation sensitivity because longitudinal residual voltage increases
comparatively large whereas phase current hardly changes in slightly inter-turn faulty situation.

The high-setting stage of longitudinal residual voltage protection will operate quickly and reliably
when severe inter-turn fault occurs in stator winding.

As for unbalanced longitudinal residual voltage increasing during normal operation condition, the
protection uses floating threshold to avoid undesired operation.

 Stator earth-fault protection

By adopting frequency tracking, digital filter and Fourier transformation, the filtration ratio of third
harmonic component can reach more than 100.

The sensitive stage of fundamental residual voltage protection operates and issues trip command
only if the dual criterias of residual voltages of generator terminal and neutral point are met at the
same time.

The ratio settings of third harmonic of generator terminal to that of neutral point used in third
harmonic ratio criteria will automatically suit to the change of ratio fore-and-aft incorporating in
power network third harmonic voltage of the plant unit. This automation adjustment function
ensures the correctness of signals generated and issued by the third harmonic voltage criteria
even during incorporation or isolation course of generator.

The ratio and phase-angle difference of third harmonic voltage of generator terminal to that of
neutral point keeps almost stable when the generator is in normal operation condition; also it is a
slow developing course. Through real time adjustment of coefficient of amplitude value and phase,
PCS-985 makes differential voltage between generator terminal and neutral point as 0 in normal
operation condition. When stator earth fault occurs, the criteria tend to operate reliably and
sensitively.

 Stator earth-fault protection with external voltage injection principle

The protection adopts digital technology to calculate earth fault resistance accurately.

Settings configured two stage are provided. One stage operates to alarm, and the other stage
operates to trip.

The residual current protection is free from impact of 20Hz power, which provides mainly
protection for comparatively severe stator earth fault.

The protection is adaptive for various operation conditions, such as stillness, no-load, shutdown,
startup and connected to power grid.

 Sampling-switch type rotor earth-fault protection

DC current is input by high-performance isolated amplifier. Via switching two different electronic
switch, PCS-985 solves four different ground-loop equations to compute rotor winding voltage,
rotor ground resistance and earthing position on real time and display these information on LCD.

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1 Introduction

 Rotor earth-fault with external voltage injection principle

Injecting a low-frequency square wave between positive terminal and negative terminal of rotor
windings or between one terminal of rotor windings and axis, the device acquires leakage current
of rotor, and calculates insulation resistance between rotor windings and ground in real-time. The
injected square wave voltage is generated by the device. The protection reflect the insulation
reduction between rotor windings and axis.

The calculation to rotor earth resistance is unrelated to fault location, and no dead zone.

The calculation accuracy of rotor earth resistance is high and is not affected by the capacitance
between rotor windings and ground.

The calculation to rotor earth resistance is unrelated to excitation voltage. It can still supervise
insulation situation of rotor windings when no excitation voltage is supplied.

It can be adaptive to various lead-out mode of rotor windings, and both single-end injection and
double-ends injection can be selected. The fault location can be measured if selecting
double-ends injection.

 Loss-of-excitation protection

Loss-of-excitation protection adopts optimizing protection scheme in which stator impedance


criteria, reactive power criteria, rotor voltage criteria and busbar voltage criteria, could be
optionally combined to meet various demands of different generator units.

 Out-of-step protection

Out-of-step protection adopts three-impedance element (gains from positive-sequence current


and positive sequence voltage of generator) to distinguish out-of-step from steady oscillation.
More than that, the protection can accurately locates the position of oscillation center and record
oscillation slid numbers of external and internal oscillation respectively in real-time.

 VT circuit failure supervision

Two groups of VT inputs are equipped at generator terminal. If one group fails, the device will
issue alarm and switch over to the healthy one automatically. It doesn‘t need to block protection
element relevant to voltage. For main transformer and step-down transformer, the protection
elements relevant to voltage are optional to blocked or not blocked according to the corresponding
logic setting. Based on percentage restraint characteristic, it can discriminate that neutral point of
VT circuit fails.

 CT circuit failure supervision

Reliable blocking function when CT circuit failure can prevent the device from undesired operation
due to CT circuit failure or AC sampled circuit failure.

 Powerful communication function

Flexible communication mode is provided. 2 independent Ethernet interfaces and 2 independent


RS-485 communication interfaces are provided. Power industry communication standard
IEC60870-5-103, Modbus protocol and new generation substation communication standard

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1 Introduction

IEC61850 are supported.

 Complete event recording function

64 faults and operation sequence, 64 fault waveforms, results of 256 self-supervision reports, and
1024 binary signal change reports can be recorded.

 Auxiliary PC software

PC software allows easy application of this device.

1.4 Order Information

 CT secondary rated value: 1A or 5A

 DC power supply for device: 110/125V, 220V/250V

 DC power supply for binary input: 24V/48, 110/125V, 220V/250V

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2 Technical Data

2 Technical Data

2.1 Electrical Specifications


2.1.1 AC Current Input
Standard IEC 60255-27:2005
Phase rotation ABC
Nominal frequency (fn) 50±5Hz, 60±5Hz
Rated Current (In) 1A 5A
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden < 0.15VA/phase @In < 0.25VA/phase @In
Accuracy ±0.5%In

2.1.2 AC Voltage Input


Standard IEC 60255-6, IEC60288
Phase rotation ABC
Nominal frequency (fn) 50±5Hz, 60±5Hz
Rated Voltage (Un) 100V~130V
Linear to 1V~170V
Thermal withstand
-continuously 200V
-10s 260V
-1s 300V
Burden at rated < 0.20VA/phase @Un
Accuracy ±0.5%Un

2.1.3 Power Supply


Standard IEC 60255-11:2008
Rated Voltage 110Vdc/125Vdc, 220Vdc/250Vdc
Operating Range 80%~120% of rated voltage
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <50W
Operating condition <70W

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2 Technical Data

2.1.4 Binary Input


Rated Voltage 24V 48V 110V 125V 220V 250V
Rated current drain 1.2mA 2.4mA 1.1mA 1.25mA 2.2mA 2.5mA
Pickup voltage 55%~70% of rated voltage
Dropoff voltage <55% of rated voltage
Maximum permissible voltage 120% of rated voltage
Withstand voltage
2000Vac, 2800Vdc
-continously
Response time for logic input <1ms

2.1.5 Binary Output


Contact Type Trip output Signal output
Output mode Potential free contact
5A@380Vac 8A@380Vac
Continuous carry
5A@250Vdc 8A@250Vdc
Pickup time <8ms (typical 3ms) <10ms
Dropoff time <5ms <8ms
0.6A@48Vdc 0.7A@48Vdc
Breaking capacity (L/R=40ms) 0.1A@110Vdc 0.3A@110Vdc
0.05A@220Vdc 0.2A@220Vdc
Burden 300mW 240mW
Making capacity 2000VA 3040VA
380Vac
Maximal system voltage
250Vdc
Test voltage across open contact 1000V RMS for 1min 1200V RMS for 1min
6A@3s 10A@3S
Short duration current
15A@0.5s 20A@0.5S

2.2 Mechanical Specifications


Enclosure dimensions (W×H×D) 482.6mm×354.0mm×291.0mm
Mounting Way Flush mounted
Trepanning dimensions (W×H) 450.0mm×354.0mm, M6 screw
Housing color Silver grey
Weight per device Approx. 30kg
Housing material Aluminum
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated frontplate
Protection class
Standard IEC 60225-1:2009
Front side IP40, up to IP51 (Flush mounted)
Other sides IP30
Rear side, connection terminals IP20

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2 Technical Data

2.3 Ambient Temperature and Humidity Range


Standard IEC 60225-1:2009
Operating temperature -40°C to +70°C
Transport and storage temperature
-40°C to +70°C
range
Permissible humidity 5%-95%, without condensation
Pollution degree 2
Altitude <3000m

2.4 Communication Port


2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Transmission distance <500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable

2.4.2 Ethernet Port


Connector type RJ-45
Transmission rate 100Mbits/s
Transmission standard 100Base-TX
Transmission distance <100m
Protocol IEC 60870-5-103:1997 or IEC 61850
Safety level Isolation to ELV level

2.4.3 Optical Fibre Port

2.4.3.1 For Station Level

Characteristic Glass optical fiber


Connector type ST, SC
Fibre type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB

2.4.3.2 For Process Level

Characteristic Glass optical fiber


Connector type LC

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2 Technical Data

Fibre type Multi mode


Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB

2.4.3.3 For Pilot Channel

Characteristic Glass optical fiber


Connector type FC
Fibre type Single mode
Transmission distance <40km (1310nm), <100km (1550nm)
Wave length 1310nm, 1550nm
Transmission power Min. -18.0dBm
Minimum receiving power Min. -38.0dBm
Margin Min +3.0dB

2.4.3.4 For Synchronization Port

Characteristic Glass optical fiber


Connector type ST
Fibre type Multi mode
Wave length 820nm
Minimum receiving power Min. -25.0dBm
Margin Min +3.0dB

2.4.4 Print Port


Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
Safety level Isolation to ELV level

2.4.5 Clock Synchronization Port


Type RS-485
Transmission distance <500m
Maximal capacity 32
Timing standard PPS, IRIG-B
Safety level Isolation to ELV level

2.5 Type Tests


2.5.1 Environmental Tests

Dry cold test IEC60068-2-1:2007


Dry heat test IEC60068-2-2:2007

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Damp heat test, cyclic IEC60068-2-30:2005

2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 Class I


Shock and bump IEC 60255-21-2:1988 Class I

2.5.3 Electrical Tests

Standard IEC 60255-27:2005


Dielectric tests Test voltage 2kV, 50Hz, 1min
Standard IEC 60255-5:2000
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ

Insulation resistance
Isolation resistance >100MΩ@500VDC
measurements

2.5.4 Electromagnetic Compatibility


IEC 60255-22-1:2007
1MHz burst disturbance test Common mode: class III 2.5kV
Differential mode: class III 1.0kV
IEC60255-22-2:2008 class IV
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-22-3:2007 class III
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008
Fast transient disturbance tests Power supply, I/O, Earth: class IV, 4kV, 2.5kHz, 5/50ns
Communication terminals: class IV, 2kV, 5kHz, 5/50ns
IEC 60255-22-5:2008
Power supply, AC input, I/O port: class IV, 1.2/50us
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-22-6:2001
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class III, 10Vrms, 150
Disturbance
kHz~80MHz
Power Frequency Magnetic Field IEC 61000-4-8:2001
Immunity class V, 100A/m for 1min, 1000A/m for 3s

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IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
class V, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2001
immunity class V, 100kHz & 1MHz–100A/m

Auxiliary power supply performance IEC60255-11: 2008


- Voltage dips Up to 500ms for dips to 40% of rated voltage without reset
-Voltage short interruptions 100ms for interruption without rebooting

2.6 Certifications
 ISO9001:2000

 ISO14001:2004

 OHSAS18001:1999

 ISO10012:2003

 CMMI L3

 EMC: 2004/108/EC, EN50263:1999

 Products safety(PS): 2006/95/EC, EN61010-1:2001

2.7 Protective Functions

Note !

Ie is secondary rated current of main transformer or generator

In is secondary rated current of CT

Un is secondary rated voltage of VT

Pn is rated active power of generator

2.7.1 Generator-transformer Unit/Main Transformer Differential Protection


Pickup setting range of percentage differential
0.1Ie~1.5Ie
element
Setting accuracy ≤5% or 0.01In whichever is greater
Setting range of unrestrained instantaneous
2Ie~14Ie
differential element
Setting accuracy ≤2.5%
Setting range of differential current alarm 0.05Ie~1.0Ie
Setting range of first slope of percentage differential
0~0.50
element

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Setting range of maximum slope of percentage


0.5~0.80
differential element
Operating time ≤30ms (2 times pickup current settings)

2.7.2 Restricted Earth Fault Protection of Main Transformer (REF)


Pickup setting range of percentage REF 0.1Ie~1.5In
Setting accuracy ≤5% or 0.01In whichever is greater
Setting range of unrestrained instantaneous REF 2In~14In
Setting accuracy ≤2.5%
Setting range of REF alarm 0.05In~1.0In
Setting range of slope 0.3~0.80
Operating time ≤30ms (2 times pickup current settings)

2.7.3 Generator/Excitor Differential Protection


Pickup setting range of percentage differential
0.1Ie~1.5Ie
element
Setting accuracy ≤5% or 0.01In whichever is greater
Setting range of unrestrained instantaneous
2Ie~14Ie
differential element
Setting accuracy ≤2.5%
Setting range of differential current alarm 0.05Ie~1.0Ie
Setting range of first slope of percentage differential
0~0.50
element
Setting range of maximum slope of percentage
0.3~0.80
differential element
Operating time ≤25ms (2 times pickup current settings)

2.7.4 Step-down Transformer/Excitation Transfomer Differential Protection


Pickup setting range of percentage differential
0.1Ie~1.5Ie
element
Setting accuracy ≤5% or 0.01In whichever is greater
Setting range of unrestrained instantaneous
2Ie~14Ie
differential element
Setting accuracy ≤2.5%
Setting range of differential current alarm 0.05Ie~1.0Ie
Setting range of first slope of percentage differential
0~0.50
element
Setting range of maximum slope of percentage
0.5~0.80
differential element
Operating time ≤35ms(2 times pickup current settings)

2.7.5 Generator Inter-turn Protection


Setting range of transverse differential element 0.1~50A

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Setting accuracy ≤2.5% or 0.01In whichever is greater


High setting range of transverse differential element 0.1~50A
Time delay of transverse differential element
0~10s
(one-point earth)
Setting range of longitudinal zero-sequence voltage
1~20V
element
High setting range of longitudinal zero-sequence
1~20V
voltage element
Setting accuracy ≤2.5% or 0.05V whichever is greater
Time delay of longitudinal zero-sequence voltage
0.1~10s
element
Setting accuracy ≤1%Setting + 40ms

2.7.6 Generator Stator Earth-fault Protection


Setting range of zero-sequence voltage blocking
1~100V
element
Setting range of zero-sequence voltage element 0.1~50V
High setting range of zero-sequence voltage element 0.1~50V
Setting accuracy ≤2.5% or 0.05V whichever is greater
Setting range of third harmonic voltage ratio element 0.5~10
Setting range of third harmonic voltage differential
0.05~2
element
Setting accuracy ≤5%
Time delay 0.~10s
Setting accuracy ≤1%Setting + 40ms

2.7.7 Stator Earth-fault Protection with External Inject Principle


Resistance setting range 10~1000Ω
Setting accuracy ≤5%
Zero-sequence current setting range 0.02~1.50A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0.1~10s
Setting accuracy ≤1%Setting + 40ms

2.7.8 Generator Rotor Earth-fault Protection


Resistance setting range of one-point earth 0.1~100kΩ
Setting range of large-power resistance injected 0.1~100kΩ
Setting accuracy ≤10% or 0.5kΩ whichever is greater
negative-sequence voltage setting range of 2nd
0.1~10V
harmonic
Setting range of switchover cycle 0.5~10s
Time delay 0~10s
Setting accuracy ≤1%Setting + 1s

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2.7.9 Generator Stator Overload Protection


Definite-time current setting range 0.1~50A
Inverse-time pickup current setting range 0.1~100A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0~10s
Setting accuracy ≤1%Seting + 40ms
Setting range of thermal capcity of stator windings 1~100
Setting range of heat emission factor 1.02~2.0

2.7.10 Generator Negative-sequence Overload Protection


Definite-time negative-sequence current setting range 0.1~20A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0~10s
Setting accuracy ≤1%Setting + 40ms
Inverse-time negative-sequence pickup current
0.05~5A
setting range
Setting range of rotor heat constant 1~100
Setting range of continuous tolerable
0.05~5A
negative-sequence current

2.7.11 Excitation Windings Overload Protection


Definite-time current setting range 0.1~100A
Inverse-time pickup current setting range 0.1~50A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0~25s
Setting accuracy ≤1%Setting + 40ms
Setting range of thermal capcity factor 1~100
Setting range of reference current 0.1~50A

2.7.12 Generator Loss-of-excitation Protection


Impedance setting range (Z1) 0 ~ 200Ω
Impedance setting range (Z2) 0 ~ 200Ω
Setting accuracy ≤2.5% or 0.1Ω whichever is greater
Reverse reactive power setting range 0 ~ 50%Pn
Setting accuracy ≤1% or 0.002Pn whichever is greater
Low-voltage setting range of rotor 0.1 ~ 500V
No-load voltage setting range of rotor 0.1 ~ 500V
Setting accuracy ≤5% or 0.1Un whichever is greater
Low-voltage setting range of bus or generator terminal 0.1 ~ 100V
Setting accuracy ≤2.5% or 0.05V whichever is greater
Setting range of rotor low-voltage factor 0 ~ 10
Time delay of loss-of-excitation 0.1 ~ 10s

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Time delay of stage 1 and stage 2 0.1 ~ 10s


Time delay of stage 3 0.1 ~ 3000s
Setting accuracy ≤1%Setting + 40ms

2.7.13 Generator Out-of-step Protection


Impedance setting A range 0 ~ 100Ω
Impedance setting B range 0 ~ 100Ω
Impedance setting C range 0 ~ 100Ω
Setting accuracy ≤2.5% or 0.1Ωwhichever is greater
Setting range of sensitive angle 0 ~ 90°
Setting range of len′s inner angle lens 0 ~ 150°
Setting accuracy ≤3°
Setting range of pole slipping number 1 ~ 1000
Setting range of permitted tripping current 0.1 ~ 100A
Setting accuracy ≤2.5% or 0.01In whichever is greater

2.7.14 Generator Overvoltage Protection


Voltage setting range 0.1 ~ 200V
Setting accuracy ≤2.5% or 0.05V whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1%Setting + 40ms

2.7.15 Generator/Main Transformer Over-excitation Protection


V/F setting range 1~2
Setting accuracy ≤2.5% or 0.1 whichever is greater
Time delay for tripping 0.1 ~ 3000s
Time delay for alarm 0.1 ~ 25s
Setting accuracy ≤1%Setting + 40ms

2.7.16 Generator Reverse Power Protection


Setting range of reverse power element 0.5 ~ 50%Pn
Setting range of reverse power sequential tripping
0.5 ~ 10%Pn
element
Setting accuracy ≤10% or 0.002Pn whichever is greater
Time delay of reverse power element 0.1 ~ 3000s
Time delay of reverse power sequential tripping
0.01~10s
element
Setting accuracy ≤1%Setting + 40ms

2.7.17 Generator Frequency Protection


Setting range of underfrequency protection (stage 45 ~ 51Hz (for 50Hz system)
1~3) 50 ~ 61Hz (for 60Hz system)

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50 ~ 60Hz (for 50Hz system)


Setting range of overfrequency protection (stage 1~2)
55 ~ 70Hz (for 60Hz system)
Setting accuracy ≤0.02Hz
Time delay of underfrequency protection (stage 1~3) 0.1 ~ 300min
Time delay of overfrequency protection (stage 1) 0.1 ~ 100min
Time delay of overfrequency protection (stage 2) 0.1 ~ 100s
Setting accuracy ≤1%Setting + 40ms

2.7.18 Generator Inadvertent Energization Protection


Current setting range of inadvertent energization
0.1 ~ 50A
protection
Negative-sequence current setting range of flashover
0.1~20A
protection
Setting accuracy ≤2.5% or 0.01In whichever is greater
40 ~ 50Hz (for 50Hz system)
Blocking frequency setting range
50 ~ 60Hz (for 60Hz system)
Time delay of inadvertent energization protection 0.01 ~ 1s
Time delay of flashover protection 0.01~2s
Setting accuracy ≤1%Setting + 40ms

2.7.19 Generator Startup/shutdown Protection


40 ~ 50Hz (for 50Hz system)
Blocking frequency setting range
50 ~ 60Hz (for 60Hz system)
Differential current setting range 0.1~14Ie
Setting accuracy ≤5% or 0.02In whichever is greater
Overcurrent setting range under low-frequency
0.1 ~ 100A
condition
Setting accuracy ≤5% or 0.02In whichever is greater
Zero-sequence voltage setting range 5 ~ 25V
Setting accuracy ≤5% or 0.02Un whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1%Setting + 40ms

2.7.20 Pole Discrepancy Protection


Phase current setting range 0.1 ~ 20A
Negative-sequence current setting range 0.1 ~ 20A
Zero-sequence current setting range 0.1 ~ 20A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1% + 40ms

2.7.21 Low-impedance Protection


Forward impedance setting range 0.1 ~ 100Ω

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Reverse impedance setting range 0.1 ~ 100Ω


Setting accuracy ≤2.5% or 0.1Ω whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1%Setting + 40ms

2.7.22 Voltage Controlled Overcurrent Protection


Negative-sequence voltage setting range 1 ~ 20V
Low voltage setting range 2 ~ 100V
Setting accuracy ≤2.5% or 0.05V whichever is greater
Current setting range 0.1 ~ 100A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1%Setting + 40ms

2.7.23 Main Transformer Zero-sequence Overcurrent Protection


Zero-sequence blocking voltage setting range 2 ~ 100V
Setting accuracy ≤2.5% or 0.05V whichever is greater
Zero-sequence overcurrent setting range 0.1 ~ 100A
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay 0 ~ 10s
Setting accuracy ≤1% + 40ms

2.7.24 Main Transformer Gap Zero-sequence Protection


Setting range of gap zero-sequence overvoltage
2 ~ 220V
protection
Setting accuracy ≤2.5% or 0.05V whichever is greater
Setting range of gap zero-sequence overcurrent
0.1 ~ 100A
protection
Setting accuracy ≤2.5% or 0.01In whichever is greater
Time delay accuracy ≤1%Setting + 40ms

2.7.25 Mechanical Protection


Time delay of mechanical repeater 1~3 0 ~ 300s
Time delay of mechanical repeater 4 0 ~ 6000s
Setting accuracy ≤1%Setting + 40ms

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3 Operation Theory

3.1 Overview
The device has 2 plug-in modules (i.e. protection DSP module and fault detector DSP module),
and the logic relation between them is ―AND‖. They have independent sample circuit and output
circuit. AC current and voltage is converted into small voltage signal and sent to protection
calculation module (also called DSP module 1) and fault detector calculation module (also called
DSP module 2) respectively. Protection DSP module is responsible for protection calculation and
fault detector DSP module is responsible for fault detector. Fault detectors on fault detector DSP
module picks up to connect positive pole of power supply of output relays. Real-time data
exchange between protection DSP module and fault detector DSP module is performed. Based on
strict mutual check and self-check, any of them fails will lead to block the device and issue alarm
signal. The device will not mal-operate due to hardware error.

Serial port Ethernet


CPU
Print Clock Synchronization

AC Opto-
Signal LPF A/D DSP coupler
External BI

Protection DSP module Output


Relay

QDJ

+E
LPF A/D DSP

Fault detector DSP module

Figure 3.1-1 Hardware structure

3.2 Fault Detector (FD)


The device provides dedicated fault detector elements for different protection elements. The
corresponding fault detector element will be enabled when the protection element is enabled. After
the fault detector element operates, the positive power supply will be provided to output relay and
pickup signal will keep 500ms even the fault detector element drops off. Tripping output is only
enabled if both corresponding fault detector element on fault detector DSP module and
corresponding protection element on protection DSP module operate, otherwise the device will

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issue alarm signal. The principle of each fault detector element is given below:

3.2.1 Generator-transformer Unit/Main Transformer Differential Protection


When the differential current of generator-transformer unit is greater than the setting
[I_Pkp_PcntDiff_GTU], the fault detector element of generato-transformer unit differential
protection will operate.

When the differential current of main transformer is greater than the setting [I_Pkp_PcntDiff_Tr],
the fault detector element of main transformer differential protection will operate.

When DPFC differential protection of main transformer meet the operation criteria, the fault
detector element of main transformer differential protection will operate.

When zero-sequence differential current of main transformer is greater than the setting
[I_Pkp_PcntREF_Tr], the fault detector element of restricted earth-fault protection (REF) of main
transformer will operate.

3.2.2 Phase-to-phase Backup Protection of Main Transformer


When the fundamental variation of phase current is greater than 0.2In, the fault detector element
of impedance protection of main transformer will operate.

When the maximum value of three phase currents is greater than the setting [I_OCn_Tr ], the fault
detector element of impedance protection of main transformer will operate.

3.2.3 Earth Backup Protection of Main Transformer


When zero-sequence current of main transformer is greater than the setting [I_ROCn_Tr], the fault
detector element of zero-sequence overcurrent protection of main transformer will operate.

When gap zero-sequence current of main transformer is greater than the setting
[I_ROC_Gap_HVS], the fault detector element of gap zero-sequence overcurrent protection of
main transformer will operate.

When gap zero-sequence voltage of main transformer is greater than the setting
[V_ROV_Gap_Tr], the fault detector element of gap zero-sequence voltage protection of main
transformer will operate.

3.2.4 Differential Protection of Step-down Transformer


When the differential current of step-down transformer is greater than the setting
[I_Pkp_PcntDiff_STx], the fault detector element of step-down transformer differential protection
will operate.

3.2.5 Backup Protection of Step-down Transformer


When the maximum value of three phase currents at HV side of step-dwown transformer is greater
than the setting [I_OCn_HVS_STx], the fault detector element of overcurrent protection of
step-down transformer will operate.

When the maximum value of three phase currents at LV side of step-dwown transformer is greater

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than the setting [I_OCn_Br1_STx] or [I_OCn_Br2_STx], the fault detector element of overcurrent
protection of step-down transformer will operate. (Branch 1 and branch 2 at LV side)

When zero-sequence current at LV side of step-dwown transformer is greater than the setting
[I_ROCn_Br1_STx] or [I_ROCn_Br2_STx], the fault detector element of zero-sequence
overcurrent protection of step-down transformer will operate. (Branch 1 and branch 2 at LV side)

3.2.6 Differential Protection of Generator


When the differential current of generator is greater than the setting [I_Pkp_PcntDiff_Gen], the
fault detector element of generator differential protection will operate.

When the fundamental variation of differential current is greater than the threshold value, the fault
detector element of generator differential protection will operate.

3.2.7 Differential Protection of Generator


When the transverse differential current of generator is greater than the setting
[I_SensTrvDiff_Gen], the fault detector element of generator transverse differential protection will
operate.

When the longitudinal zero-sequence voltage is greater than the setting


[V_SensROV_Longl_Gen], the fault detector element of longitudinal zero-sequence voltage
protection will operate.

When the fundamental variation of negative-sequence voltage, current and power are greater than
their threshold values, the fault detector element of DPFC inter-turn protection will operate.

3.2.8 Stator Earth-fault Protection of Generator


When zero-sequence voltage of generator terminal and neutral point are greater than the setting
[V_SensROV_Sta], the fault detector element of zero-sequence voltage protection will operate.

When third harmonic voltage ratio is greater than the setting [k_V3rdHRatio_PreSync_Sta] or
[k_V3rdHRatio_PostSync_Sta], the fault detector element of third harmonic voltage ratio
protection will operate.

When differential third harmonic voltage is greater than the setting [k_V3rdHDiff_Sta], the fault
detector element of third harmonic voltage differential protection will operate.

3.2.9 Rotor Earth-fault Protection of Generator


When grounded resistance of rotor windings is smaller than its setting [R_1PEF_RotWdg], the
fault detector element of rotor one-point earth-fault protection will operate.

When the change of rotor grounding location is greater than its internally fixed setting, the fault
detector element of rotor two-points earth-fault protection will operate.

3.2.10 Stator Overload Protection of Generator


When maximum value of three phase currents is greater than the setting [I_OvLd_Sta], the fault
detector element of definite-time overload protection will operate.

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When the inverse time accumulated value is greater than the setting [I_InvOvLd_Sta], the fault
detector element of inverse-time overload protection will operate.

3.2.11 Negative-sequence Overload Protection of Generator


When maximum value of negative sequence current is greater than the setting [I_NegOC_Gen],
the fault detector element of definite-time negative-sequence overload protection will operate.

When the inverse time accumulated value is greater than the setting [I_InvNegOC_Gen], the fault
detector element of inverse-time negative-sequence overload protection will operate.

3.2.12 Loss-of-excitation Protection of Generator


When the locus of calculated impedance enters into impedance circle, the fault detector of
loss-of-excitation protection will operate.

3.2.13 Out-of-step Protection of Generator


When the locus of calculated impedance leaves boundary of impedance operation zone, the fault
detector of out-of-step protection will operate.

3.2.14 Overvoltage Protection of Generator


When maximum value of three phase-to-phase voltage is greater than the setting [V_OVn_Gen],
the fault detector element of overvoltage protection will operate.

3.2.15 Over-excitation Protection of Generator


When the measured U/F is greater than the setting [k_OvExc1_Gen], the fault detector element of
definite-time over-excitation protection will operate.

When the accumulated value is greater than the setting [k0_InvOvExc_Gen], the fault detector
element of inverse-time over-excitation protection will operate.

3.2.16 Generator Power Protection


When reverse power is greater than setting [P_RevP_Gen], the fault detector of reverse power
protection will operate.

3.2.17 Generator Frequency Protection


When the frequency is smaller than the setting value for a specified time interval, the fault detector
element of low-frequency protection will operate.

When the frequency is greater than the setting value for a specified time interval, the fault detector
element of over-frequency protection will operate.

3.2.18 Generator Inadvertent Energization Protection


When the maximum value of three phase currents of generator is greater than the setting
[I_OC_AccEnerg_Gen], the fault detector element of generator inadvertent energization protection
will operate.

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When negative-sequence current at CB side is greater than the setting


[I_NegOC_Flash_CB_HVS_Tr], the faulte detector element of breaker flashover protection will
operate.

3.2.19 Generator Startup/shutdown Protection


When the differential current of generator is greater than the setting [I_GenDiff_StShut_Gen], the
fault detector element of generator startup/shutdown protection will operate.

When the zero-sequence voltage of generator is greater than the setting


[V_StaROV_StShut_Gen], the fault detector element of generator startup/shutdown protection will
operate.

When the low-frequency current of generator neutral point is greater than the setting
[I_StShut_Gen], the fault detector element of generator startup/shutdown protection will operate.

3.2.20 Differential Protection of Exciter/Excitation Transformer


When the maximum value of three phase differential currents is greater than the setting
[I_Pkp_PcntDiff_Exc], the fault detector element of differential protection will operate.

3.2.21 Overcurrent Protection/Overload Protection of Exciter/Excitation


Transformer
When the maximum value of three phase currents is greater than the setting [I_OCn_Exc], the
fault detector element of overcurrent protection will operate.

When the accumulated value is greater than the setting [I_InvOvLd_RotWdg], the fault detector
element of inverse-time overload protection will operate.

3.2.22 Pole Discrepancy Protection


When the binary input [BI_PD_CB] is energized, and phase current, negative-sequence current or
zero-sequence current is greater than the setting value, the fault detector element of pole
discrepancy protection will operate.

3.2.23 Breaker Failure Protection


When the binary input [BI_ExtTrpCtrl] is energized, and phase current or negative-sequence
current is greater than the setting value, the fault detector element of breaker failure protection will
operate.

3.2.24 Mechanical Protection


When the operation duration of mechanical protection is greater than its time delay, the fault
detector element of mechanical protection will operate.

Note!

These setting values of above fault detector elements are formed automatically by the
device, it need not to set manually.

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3.3 Differential Protection (GTU, MT, ST and ET)


GTU: Generator-transformer unit

MT: Main transformer

ST: Step-down transformer

ET: Excitation transformer

3.3.1 Operation Characteristic


Operation criterion of percentage differential protection is

 I d  K bl  I r  I cdqd ( I r  nI e )

 K bl  K bl1  K blr  ( I r / I e )

 I d  K bl 2  ( I r  nI e )  b  I cdqd ( I r  nI e )

 K blr  ( K bl 2  K bl1 ) /(2  n)
b  ( K bl1  K blr  n)  nI e
Equation 3.3-1

 I1  I 2  I 3  I 4  I 5
 I r 
2
     
I  I 1  I 2  I 3  I 4  I 5
 d

n is the multiple of restraint current at the second slope and is fixed at 6.

Figure 3.3-1 shows operation characteristic of differential protection.

Id

Operation area of unrestrained


instantaneous differential protection
Icdsd
Operation area of high-
setting percentage
io e
ro ce of
ct ag

differential protection
l p er a

n
te nt
ia p re
.0

nt te a

Kbl2
=1

re ta ion
K

ffe y s at
di d er
ea p
st O

1.2Ie
Kbl1
Icdqd
Ir
0 Ie nIe

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Figure 3.3-1 Operation characteristic of differential protection

Where:

Icdqd is pickup value of differential current fault detector.

Id is differential current.

Ir is restraint current.

Ie is rated current.

Icdsd is the setting of unrestrained instantaneous differential protection.

Kbl is percentage differential restraint factor and Kb1r is its increment.

Kbl1 is the first slope of percentage differential with setting range 0.05~0.15. 0.10 is applicable
usually.

Kbl2 is the second slope of percentage differential with setting range 0.50~0.80. 0.70 is applicable
usually.

Steady-state percentage differential protection element will not send tripping signal in case of CT
saturation, CT circuit failure (optional), inrush current and overexcitation condition. It can ensure
sensitivity of protection and avoid unwanted operation when CT is saturated during external fault.
Its operation area is tint shadow area.

High-setting percentage differential protection element (described in section 3.3.4) will not send
tripping signal only due to CT circuit failure (optional) and inrush current. It eliminates influence of
transient and steady saturation of CT during external fault and ensures reliable operation even if
CT is in saturation condition during internal fault by means of its percentage restraint characteristic.
Its operation area is deep shadow area.

Unrestrained instantaneous differential protection element (described in section 3.3.5) will send
tripping signal without any blocking if differential current of any phase reaches its setting. Its
operation area is over the above two areas with no shadow.

Note!

For differential current of generator-transformer unit and main transformer, the current
redefinition of each side in Equation 3.3-1 is different for different program versions and
can be found on individual project-specific document.

 Usually, for generator-transformer unit differential protection,

I1 represent currents of HV side of main transformer

I2 represents current of HV side of step-down transformer

I3 represents current of neutral point of generator

I4 and I5 are not defined

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 For differential protection of main transformer,

I1 represents current of HV side1 of main transformer

I2 represents current of HV side of step-down transformer

I3 represents current of LV side of main transformer

I4 and I5 are not defined

 For differential protection of step-down transformer

I1 represents current of HV side of step-down transformer

I2 represents current of branch 1 at LV side of step-down transformer

I3 represents current of branch 2 at LV side of step-down transformer

I4 and I5 are not defined

 For differential protection of excitation transformer

I1 represents current of HV side of excitation transformer

I2 represents current of LV side of excitation transformer

I3, I4 and I5 are not defined

3.3.2 Inrush Current Detection Element


1. Second harmonic restraint principle

In the device, the second harmonic of differential current can be used to distinguish inrush current.
Its operation criterion is:

I 2 nd  K 2 xb  I1st

Where:

I 2 nd is the second harmonic of each phase differential current.

I1st is the differential fundamental current of corresponding phase.

k 2 xb is the setting of restraint coefficient of second harmonic. (0.15 is recommended value)

2. Waveform distortion discrimination principle

During internal fault, differential currents of various sides transferred by CT are basically
fundamental sinusoidal wave. But when the transformer is energized, lots of harmonics occur. The
waveform is intermittent and unsymmetrical. A special algorithm can be used for discrimination of
the inrush current.

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During internal fault, following relation exists:

S  kb*S

S  St

Where:

S is the full cycle integral of differential current

S+ is full cycle integral of the sum of instantaneous value of differential current and that of half
cycle before.

Kb is a fixed constant.

St is a threshold value which can be represented as follows:

St   * I d  0.1* I e

Where:

Id is the full cycle integral of differential current.

α is a proportional constant.

Ie is the secondary rated current of transformer.

If any of three phases can not meet above equation, the differential current can be considered as
inrush current and percentage differential protection will be blocked.

In this device, logic setting is provided for user to select the restraint blocking principle. If the logic
setting is set as ―0‖, discrimination by harmonics is enabled. Otherwise, discrimination by
waveform distortion is enabled.

3.3.3 CT Saturation Detection Element


In order to prevent undesired operation of steady-state percentage differential protection caused
by transient or steady-state CT saturation during external fault, composite harmonics of secondary
differential current is used for the device to discriminate CT saturation. The expression is as
following:

I cop  K nxb  I1

Where:

I cop is the composite harmonics of phase differential current.

I1 is the fundamental component of corresponding phase differential current.

k nxb is proportional coefficient.

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For an internal fault, DPFC restraint current and DPFC differential current appear simultaneously.
If DPFC restraint current appears before DPFC differential current, it maybe an external fault. CT
saturation detection element shall be adopted in this case. It can prevent percentage differential
protection from undesired operation due to CT saturation.

3.3.4 High-setting Percentage Differential Protection Element (HSDP)


A percentage differential protection with high percentage and high setting is equipped with the
device to prevent delayed operation of percentage differential protection caused by CT saturation
and other factors during serious internal fault. This protection is blocked only by inrush current
criterion i.e. second harmonic of differential current or waveform discrimination. It can prevent
influence of steady state and transient CT saturation during external fault and can operate
correctly and quickly during internal fault even if CT is in saturation condition. Operation criterion of
this high setting percentage differential protection is:

I d  1.2  I e

I d  1.0  I r

Where:

Id is differential current as mentioned above.

Ir is restraint current as mentioned above.

Id

Instantaneous operation area


Icdsd

Operation area

K=1.0

1.2Ie

Ir
0

Figure 3.3-2 Operation characteristic of HSDP

When fault occurs, the operation criterion will be discriminated phase by phase and percentage
differential protection will operate if the criterion is met.

Note!

Parameters of this protection have been fixed in program and do not need to be configured
by user.

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3.3.5 Unrestrained Instantaneous Differential Protection Element (UIDP)


The aim of unrestrained instantaneous differential protection for transformer is to accelerate the
trip speed for transformer‘s inner fault. So the element does not need any block element, but the
setting should be greater than maximum inrush current.

Its operation criterion is:

Differential current of any phase is greater than the setting [I_InstDiff_x].

(x can be GTU, MT, ST or ET.)

3.3.6 Differential Current Abnormality Alarm and CT Circuit Failure Blocking


Differential current abnormality alarm with percentage restraint and instant CT circuit failure
blocking function are equipped with the device.

CT circuit failure blocking function can be configured by logic setting [Opt_CTS_Blk_PcntDiff_x].


When such failure occurs and is discriminated, issuing alarm signal only or blocking percentage
differential protection is optional. If the logic setting is set as ―1‖, percentage differential protection
will be blocked immediately.

(x can be GTU, MT, ST or ET.)

3.3.7 Overexcitation Detection Element


When a transformer is overexcited, the exciting current will increase sharply which may result in
unwanted operation of differential protection. Therefore the overexcitation shall be discriminated to
block the current differential protection. The fifth harmonic of differential current is used as criterion
of overexcitation discrimination.

I 5th  k5 xb * I1st

Where:

I1st is fundamental component of differential current.

I 5th is fifth harmonic of differential current.

k5 xb is the fifth harmonic restraint coefficient, it is fixed at 0.25.

Note!

High-setting percentage differential protection is not blocked by fifth harmonic of differential


current.

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3.3.8 Logic Scheme

Note!

All the settings mentioned below are from main transformer for example.

Flg_UIDP
&
[EBI_Diff_Tr] &
Op_InstDiff_Tr
[En_InstDiff_Tr]

FD_Diff_Tr

Flg_Inrush_Tr

Flg_HSDP_Tr
& &
[EBI_Diff_Tr]

[En_PcntDiff_Tr]

Flg_CTS
&

FD_Diff_Tr

Flg_CTsat &
Flg_Inrush
≥1
Flg_SPDP_Tr Op_PcntDiff_Tr
&
[EBI_Diff_Tr]

[En_PcntDiff_Tr]

Flg_CTS & &

Flg_OvExc_Tr

FD_Diff_Tr

Figure 3.3-3 Logic diagram of differential protection

The above logic diagram is also suit for differential protection of generator-transformer unit,
step-down transformer and excitation transformer.

Where:

FD_Diff_Tr: fault detector of differential protection of main transformer.

Flg_UIDP _Tr is the flag indicating whether or not the criterion of UIDP element is met.

Flg_HSDP _Tr is the flag indicating whether or not the criterion of HSDP element is met.

Flg_SPDP _Tr is the flag indicating whether or not the criterion of SPDP element is met.

Flg_CTS is the flag indicating whether or not the CT circuit fails.

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Flg_CTsat is the flag indicating whether or not the CT is in saturation state.

Flg_Inrush is the flag indicating whether or not the criterion of inrush current detection is met.

Flg_OvExc_Tr is the flag indicating whether or not the transformer is in overexcitation state.

3.4 Differential Protection (Gen and Exc)


Gen: Generator-transformer unit

Exc: Exciter

3.4.1 Percentage Differential Protection (SPDP)


Operation characteristic of percentage differential protection is as shown as following figure.

Id

Unrestraint operation area

Icdsd

Kbl2
Operation area

Restraint area

Kbl1
Icdqd
Ir
0
Ie nIe

Figure 3.4-1 Operation characteristic of percentage differential protection

Operation equation of this percentage differential protection is

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 I d  K bl  I r  I cdqd ( I r  nI e )

 K bl  K bl1  K blr  ( I r / I e )

 I d  K bl 2  ( I r  nI e )  b  I cdqd ( I r  nI e )

 K blr  ( K bl 2  K bl1 ) /(2  n)
b  ( K bl1  K blr  n)  nI e
Equation 3.4-1

  
I 1 I2

 Ir 
 2
  
I d  I 1  I 2

Where:

I d is differential current

I r is restraint current

I cdqd is pickup value of differential current

I e is rated current of generator

K bl is percentage differential restraint coefficient and K blr is its increment

K bl1 is the first slope of percentage differential with setting range 0.05~0.15. 0.05 is

recommended usually

K bl 2 is the second slope of percentage differential with setting range 0.30~0.70. 0.50 is

recommended usually

n is the multiple of restraint current at second percentage restraint coefficient and is fixed at 4.

For differential protection of generator and exciter, I1 and I 2 are currents of terminal and neutral

point respectively.

3.4.2 High Performance Blocking Technique in Case of CT Saturation


In order to prevent unwanted operation of steady-state percentage differential protection due to CT
transient or steady state saturation during external fault, discrimination of waveform of differential
current principle is adopted as criterion of CT saturation.

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When fault occurs, the equipment decides firstly whether it is internal or external fault. If it is
external fault, criterion of CT saturation is enabled. If any phase differential current of differential
protection meets the criterion, it is decided that this differential current comes from CT saturation
and the percentage differential protection will be blocked.

3.4.3 High-setting Percentage Differential Protection (HSDP)


A percentage differential protection with high percentage coefficient and high pick-up setting is
equipped with the equipment to prevent operation of percentage differential protection delayed by
CT saturation and other factors during serious internal fault. It can prevent influence of steady
state and transient CT saturation during external fault due to its percentage restraint characteristic
and can operate correctly and quickly during internal fault and CT being saturated. Operation
criterion of this high setting percentage differential protection is

I d  1.2  I e

I d  1.0  I r

Where:

Differential current I d and restraint current I r are the same as mentioned above.

When fault occurs, the operation criterion will be discriminated phase by phase and percentage
differential protection will operate if the criterion is met.

Parameters of this protection are configured during manufacturing and not need to be configured
in site.

3.4.4 Unrestrained Instantaneous Differential Protection (UIDP)


This protection will operate and trip immediately if differential current of any phase is higher than
its setting.

3.4.5 Differential Current Abnormality Alarm and CT Circuit Failure Blocking


Differential current abnormality alarm with percentage restraint and instant CT circuit failure
blocking function are equipped with the device.

CT circuit failure blocking function can be configured by logic setting [Opt_CTS_Blk_PcntDiff_x].


When such failure occurs and is discriminated, issuing alarm signal only or blocking percentage
differential protection is optional. If the logic setting is set as ―1‖, percentage differential protection
will be blocked immediately.

(x can be Gen or Exc.)

3.4.6 Logic Scheme

Note!

All the settings mentioned below are from generator for example.

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Flg_UIDP_Gen
&
[EBI_Diff_Gen]
&
[En_InstDiff_Gen] Op_InstDiff_Gen

FD_Diff_Gen

Flg_HSDP_Gen
&
[EBI_Diff_Gen]
&
[En_PcntDiff_Gen]

Flg_CTS
&

FD_Diff_Gen

Flg_CTsat
≥1
Flag_SPDP_Gen
& & Op_PcntDiff_Gen
[EBI_Diff_Gen]

[En_PcntDiff_Gen]

Flg_CTS
&

FD_Diff_Gen

Figure 3.4-2 Logic diagram of differential protection

The above logic diagram is also suit for exciter differential protection.

Where:

Flg_UIDP _Gen is the flag indicating whether or not the criterion of UIDP element is met.

Flg_HSDP _Gen is the flag indicating whether or not the criterion of HSDP element is met.

Flg_SPDP _Gen is the flag indicating whether or not the criterion of SPDP element is met.

FD_Diff_Gen: fault detector of differential protection of generator.

Flg_CTS is the flag indicating whether or not the CT circuit fails.

Flg_CTsat is the flag indicating whether or not the CT is in saturation state.

3.5 DPFC Differential Protection


If slight fault occurs in generator or transformer, steady-state differential protection may not
response sensitively due to influence of load current. DPFC percentage differential protection of
generator and main transformer is equipped with the device for that and it can significantly
improve sensitivity of the protection during small current internal fault of generator and
transformer.

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3.5.1 Operation Characteristic


The operation criteria of DPFC percentage differential are as follows:


I d  1.25I dt  I dth
I d  0.6I r I r  2 I e

I d  0.75I r  0.3I e I r  2 I e Equation 3.5-1
I  I 1  I 2  I 3  I 4
 r
I  I1  I2  I3  I4
 d
Where:

I dt is floating threshold which increases progressively along with DPFC increasing. Take its

multiple as 1.25 can ensure threshold voltage always a bit higher than imbalance current. So that
unwanted operation of the equipment can be avoided during power swing and frequency deviation
conditions.

Generally, for differential protection of main transformer, I1 , I 2 , I 3 and I 4 are DPFC

currents of branch 1 and 2 at HV side of main transformer, generator terminal and HV side of

step-down transformer respectively. But for some specific design, I1 can represents the current

at HV side of transformer derived from backup CT and I 2 has no definition.

For differential protection of generator, I1 and I 2 are currents at the generator terminal of

and the neutral point of generator respectively. I 3 and I 4 have not specified.

I d is DPFC differential current.

I r is DPFC restraint current whose maximum value is taken for actual restraint.

I dth is fixed threshold.

Note!

Calculation of restraint current of DPFC percentage differential protection is different from


steady-state percentage differential protection, it is difficult to test this function on site, so
we recommend only qualitative function test on site.

DPFC differential protection is equipped to each phase of generator, but the user should

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know that DPFC restraint quantity for each phase is the same maximum value among the
three phases.

The following figure shows operating characteristic of DPFC percentage differential protection.

ΔId
Differential current

0.75

0.6
Icdqd
ΔIr
2Ie Restraint current

Figure 3.5-1 Operating characteristic of DPFC percentage differential protection

When fault occurs, the operation criterion will be discriminated phase by phase and percentage
differential protection will operate if the criterion is met. For DPFC percentage differential
protection of main transformer, second harmonic or waveform inrush current blocking and fifth
harmonic over excitation blocking are adopted. It can prevent influence of steady-state and
transient CT saturation during external fault due to its percentage restraint characteristic.

This protection element has high ability to eliminate the effect of transient and steady-state CT
saturation during the external fault because the restraint coefficient is set at a higher value.

3.5.2 Differential Current Abnormality Alarm and CT Circuit Failure Blocking


Differential current abnormality alarm with percentage restraint and instant CT circuit failure
blocking function are equipped with the device.

3.5.3 Logic Scheme

Note!

All the settings mentioned below are from generator for example.

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Flg_CTsat

Flg_DPFC_Diff_Gen
& &
[EBI_Diff_Gen] 0ms 20ms

[En_DPFC_Diff_Gen]
&
Op_DPFC_Diff_Gen
Flg_InstanCTS

FD_DPFC_Diff_Gen 0ms 500ms

Figure 3.5-2 Logic diagram of DPFC percentage differential protection

The above logic diagram is also suit for main transformer differential protection.

Where:

Flg_DPFC_Diff_Gen is the flag indicating whether or not the criterion of DPFC differential element
is met.

FD_DPFC_Diff_Gen: fault detector of DPFC differential protection of generator.

Flg_CTsat is the flag indicating whether or not the CT is in saturation state.

Flg_IntanCTS is the internally generated flag indicating that CT supervision program detects
failure of CT circuit with no delay considered into account.

The corresponding parameters of DPFC differential protection is are fixed and need not to be set
on site.

3.6 Phase-to-phase Backup Protection of Main Transformer


3.6.1 Voltage Controlled Overcurrent Protection
Voltage controlled overcurrent protection is equipped with PCS-985B. This protection, consisting
of 2 stages and 2 time delays per stage, is used for phase-to-phase backup protection of main
transformer. Of which, voltage controlled element can be enabled or disabled by logic setting.

3.6.1.1 Voltage Controlled Element

The voltage controlled element is an element which will operate if phase-to-phase voltage is lower
than the setting [Vpp_VCE_Tr] or negative-sequence voltage is greater than its setting
[V_NegOV_VCE_ Tr].

Criteria:

Upp< [Vpp_UV_VCE_Tr] or U2> [V_NegOV_VCE_ Tr]

Where:

Upp is phase-to-phase voltage of local side.

U2 is negative sequence voltage of local side.

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[Upp_UV_VCE_Tr] is setting of undervoltage control element of local side.

[U_NegOV_VCE_Tr] is setting of negative-sequence overvoltage control element of local side.

All two stages of definite time overcurrent protection can be controlled by voltage element by
configuring related logic settings [En_VCE_Ctrl_OC1_Tr] and [En_VCE_Ctrl_OC2_Tr].

Meanwhile, User can decide by which side voltage overcurrent protection is controlled by
configuring related settings. For example, if the setting [En_LVS.VCE_Ctrl_OC_Tr] is set as ―1‖,
then the overcurrent protection is controlled not only by HV side voltage element but also by LV
side voltage element.

3.6.1.2 Current Memory

For self and parallel-excited generator, current will decrease so quick during fault that it may be
lower than overcurrent setting before tripping. So memorizing function for fault current is equipped
with this protection. Logic setting [En_Mem_Curr_Tr] is used for configure of this function.

Note!

When logic setting [En_Mem_Curr_Tr] is enabled, the overcurrent must be controlled by


voltage element.

3.6.1.3 Influence of VT Circuit Failure on Voltage Control Element

When VT on one side is under maintenance or bus-tie breaker is used for the transformer but its
VT has not been switched over to the device, VT circuit failure is detected. Logic setting
[Opt_VTS_Ctrl_OC_Tr] is used to configure performance of voltage controlled element during VT
circuit failure. When this logic setting is set as ―1‖, if VT circuit failure is detected, the voltage
controlled element cannot pick up and the protection will not operate. When this logic setting is set
as ―0‖, if VT circuit failure is detected on this side, voltage controlled element is forced to be
satisfied, then the voltage controlled directional overcurrent protection controlled by voltage will
becomes a pure overcurrent protection.

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3.6.1.4 Logic Scheme

Upp< [Vpp_VCE_Tr] ≥1
&
U2>[V_NegOV_VCE_ Tr] ≥1
Flg_VCE_Tr
Flg_VTS

&

[Opt_VTS_Ctrl_OC_Tr]

&
≥1
[En_Mem_Curr_Tr] &
Flg_OCn_Tr

Flg_VCE_Tr ≥1

[En_VCE_Ctrl_OCn_Tr]

[En_PPF_Tr] & &


[t_OCn_Gen] Op_OCn_Tr
[EBI_PPF_Tr]

FD_OCn_Tr

Figure 3.6-1 Logic diagram of overcurrent protection of main transformer

Where:

Flg_VTS is flag indicating whether or not the VT circuit fails.

Flg_OCn_Tr is flag indicating that stage n of overcurrent element is met.

Flg_VCE_Tr is flag indicating whether or not voltage controlled element is met.

FD_OCn_Tr is fault detector of overcurrent protection of main transformer.

(n can be 1 or 2)

3.6.2 Impedance Protection

3.6.2.1 Operation Characteristic

Impedance protection is used as backup protection of generator-transformer unit. Three kinds of


impedance characteristic can be selected, i.e., full impedance, directional impedance and shifted
impedance characteristics. Full impedance characteristic suits case of forward setting of a zone
being equal to its reverse setting. Directional impedance characteristic suits case of reverse
setting of a zone being set as 0. Shifted impedance characteristic suits case of forward setting of a
zone being higher than its reverse setting. Reach angle of impedance protection is 78°. Forward of
the impedance protection is configurable and generally points to transformer.

Figure 3.6-2 shows operation characteristic of impedance protection. In this figure, I is phase

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current, U is corresponding phase-to-phase voltage, Zn is reverse impedance setting, Zp is


forward impedance setting.

jX

I Zp
 
U I Zp
m 
U
R

 
 U  I Zn
 I Zn

Figure 3.6-2 Operation characteristic of impedance element

Operation criterion:

90  Arg
U  IZ   270 

U  IZ 
P

The fault detector of impedance protection adopts DPFC phase current and negative-sequence
current. Pickup signal will be lasted for 500 ms and will be kept if impedance protection operates
during this time interval. Operation criterion of the fault detector is

I  1.25I t  I th

Where:

I t is floating threshold which increases progressively along with DPFC increasing.

Take its multiple as 1.25 can ensure threshold current always a bit higher than imbalance current.
So that unwanted operation of the equipment can be avoided during system swing and frequency
deviation conditions.

I th is the fixed threshold. When DPFC phase-to-phase current is higher than 0.3 Ie, the fault

detector operates.

The impedance protection will be disabled automatically if VT circuit fails.

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3.6.2.2 Logic Scheme

Flg_VTS

Flg_Zn_Tr
&
& &
[En_PPF_Tr] [t_Zn_Tr ] Op_Zn_Tr

[EBI_PPF_Gen]

FD_PPF_Tr

Figure 3.6-3 Logic diagram of impedance protection

Where:

Flg_Zn_Tr is flag indicating whether or not zone n of impedance protection.

Flg_VTS is flag indicating whether or not the VT circuit fails.

FD_PPF_Tr: fault detector of phase-to-phase backup protection of main transformer.

(n can be 1 or 2)

3.6.3 Protection for Other Abnormality


Backup protections for HV side of main transformer also include overload alarm and initial cooling.
Overload alarm and initiating cooling (two stages) can be enabled or disabled by logic settings
[En_OvLd_Tr] and [En_InitCooln_OvLd_Tr]. Outputs of initiating cooling are two normally open
contacts.

3.7 Earth-fault Backup Protection for Main Transformer


3.7.1 Zero-sequence Overcurrent Protection
Zero-sequence overcurrent protection is mainly used as backup protection of earth fault for
transformer with neutral point earthed. Two stages and two time delays for each stage of
zero-sequence overcurrent protection is equipped with PCS-985B. Zero-sequence current is
usually adopted from neutral point CT.

By setting logic settings, following functions of any stages of this protection can be selected:

 Whether it will be controlled by direction element.

 Whether it will be controlled by zero-sequence voltage element.

 Whether it will be controlled by second harmonic element.

 Whether it will be enabled or disabled.

3.7.1.1 Direction Element

The direction element uses calculated zero-sequence current and calculated zero-sequence
voltage. The direction of zero-sequence overcurrent protection points to system definitely with the
reach angle 75º. If VT circuit failure at HV side occurs, the direction element will be out of service.

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Figure 3.7-1 shows operation characteristic of zero-sequence overcurrent protection in which the
hatched area is operation region.

3U0

Φlm= 75°

I0
Point to system

Figure 3.7-1 Operation characteristic of zero-sequence overcurrent protection

Note!

The voltage used by direction element is definitely the calculated voltage. The direction
mentioned above is based on CT polarity for calculated zero-sequence current being at
busbar side. Zero-sequence voltage element uses definitely broken-delta voltage of VT.

3.7.1.2 Logic Scheme

Figure 3.7-2 shows logic diagram of zero-sequence overcurrent protection of main transformer.

3U0>[V_ROV_VCE_Tr] ≥1

[En_VCE.ROV_Ctrl_ROC1/2_Tr]

Flg_Harm_Block_ROC1/2_Tr ≥1

En_Harm_Ctrl_ROC1/2_Tr

Flg_Dir_ROC_Tr ≥1 &

[En_Dir_Ctrl_ROC1/2_Tr]

Flg_ROCn_Tr
&
[En_EF_Tr]

[EBI_EF_Tr]
&
[t_ROCn_Tr] Op_ROCn_Tr
FD_EF_Tr

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Figure 3.7-2 Logic diagram of zero sequence overcurrent protection of main transformer

Where:

Flg_Harm_Block_ROC1/2_Tr is flag indicating the criterion of second harmonic restraint is met.

Flg_Dir_ROC_Tr is flag indicating that whether or not the criterion of directional element is met.

Flg_ROCn_Tr is flag indicating that the zero sequence current is above the setting.

FD_EF_Tr: fault detector of earth-fault backup protection of main transformer.

(n can be 11, 12, 21 or 22)

3.7.2 Inverse-time Zero-sequence Overcurrent Protection

3.7.2.1 Characteristic Curve

Inverse-time zero-sequence overcurrent protection criterion:

k  Tp
t 
 I  Equation 3.7-1
   1
 IP 
Where:

T p is a time constant (0.1s).

I p is current setting [Ip_InvROC_Tr].

K is a constant.

 is a constant.

The user can select the operating characteristic from various inverse-time characteristic curves by
setting [Opt_InvROC_Tr], and parameters of available characteristics for selection are shown in
the following table.

Table 3.7-1 Inverse-time curve parameters

Opt_InvROC_Tr Time Characteristic K α

0 IEC Normal inverse 0.14 0.02

1 IEC Very inverse 13.5 1.0

2 IEC Extremely inverse 80.0 2.0

3 IEC Long-time inverse 120.0 1.0

3.7.2.2 Logic Scheme

Figure 3.7-3 shows logic diagram of inverse-time zero-sequence overcurrent protection.

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[I0_NP_HVS_Tr]>[ Ip_InvROC_Tr] & IDMT &

[En_EF_Tr] [tmin_InvROC_Tr]

[TrpLog_InvOC_Tr].Bit0 & &


Op_InvROC_Tr
[EBI_EF_Tr]

FD_InvROCProt_Tr

Figure 3.7-3 Logic diagram of inverse-time zero-sequence overcurrent protection

Where:

FD_InvROCProt_Tr: fault detector of inverse-time zero-sequence overcurrent protection of main


transformer.

3.7.3 Gap Zero-sequence Protection


Gap zero-sequence overcurrent protection is used for backup protection of main transformer with
neutral point grounded through gap or small reactance. Gap zero-sequence overvoltage
protection is used for backup protection of main transformer with neutral point ungrounded or
grounded through gap or small reactance. Considering that ground overcurrent via air gap and
zero-sequence overvoltage may appear alternatively during air gap broken down process, once
zero-sequence overcurrent or zero-sequence overvoltage protection operates, the operations of
these two elements are ―OR‖ relation. Therefore operation of the ―gap‖ protection is reliable. One
stage ―gap‖ zero-sequence overcurrent protection and one stage zero-sequence overvoltage
protection are provided.

PCS-985B provides one stage gap zero-sequence overvoltage protection and gap zero-sequence
overcurent protection with two time delays for each stage.

Figure 3.7-4 shows logic diagram of gap zero-sequence protection of transformer.

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[EBI_Gap_HVS_Tr]
&
[En_EF_Tr] FD_ROVProt_Tr

[U0_DeltVT_HVS_Tr]>[V_ROV1_Gap_Tr]

[EBI_Gap_HVS_Tr]
&
[En_EF_Tr] FD_ROC_Gap_Tr

[I0_Gap_HVS_Tr]>[I_ROC1_Gap_Tr]

FD_ROVProt_Tr ≥1

FD_ROC_Gap_Tr
&
FD_ROVProt_Tr ≥1

t Op_ROVn_Tr

FD_ROVProt_Tr ≥1

FD_ROC_Gap_Tr
&
FD_ROC_Gap_Tr ≥1

t Op_ROCn_Gap_Tr

Figure 3.7-4 Logic diagram of gap zero-sequence protection of transformer

Where:

n can be 11 or 12

3.7.4 Zero-sequence Voltage Alarm at LV side of Main Transformer


According to the case that circuit breaker is equipped at the generator terminal, a zero-sequence
voltage alarm can be provided at LV side of main transformer as the supervision of earthing fault.
The voltage setting is usually set as 10V~15V. The alarm can be enabled or disabled by logic
setting [En_Alm_ROV_LVS_Tr]. The function outputs alarm signals.

3.7.5 VT Circuit Supervision


VT circuit failure supervision principle refers to section 3.32.

3.8 Generator Inter-turn Protection


3.8.1 High-sensitive Transverse Differential Protection
Transverse differential protection installed on connection between two neutral points of generator
is used as main protection of inter-turn fault of generator‘s stator winding, open circuit fault of
branches and short circuit fault between phases.

Since this protection adopts frequency tracing, digital filtering and full cycle Fourier algorithm, the

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third harmonic can be reduced to 1/100 within the frequency tracing range and the protection can
response the fundamental component only.

This protection comprises two stages: high-setting stage (insensitive stage) and sensitive stage.

3.8.1.1 High-setting Stage

This stage is equivalent to traditional transverse differential protection. When the transverse
differential current is in excess of the setting [I_InsensTrvDiff_Gen], high-setting stage of
yransverse differential protection operates.

3.8.1.2 Sensitive Stage

Phase current percentage restraint principle is used for this stage. The operation criterion is

I d  I hcZD when I MAX  I e


 I MAX  I e
I  (1  K
hcZD  )  I hcZD when I MAX  I e


d
I e

Where:

I d is the transverse differential current

I hcZD is the transverse differential current setting [I_SensTrvDiff_Gen]

I MAX is the maximum value of three phase current of generator

I d is the rated current of generator

K hcZD is the restraint coefficient.

Phase current percentage restraint transverse differential principle can ensure no unwanted
operation during external fault and sensitive operation during internal fault. As this principle is
adopted, current setting of the transverse differential protection shall be only higher than
unbalance current during normal operation and much less than that of traditional transverse
differential current protection. Sensitivity for interturn fault of generator can be enhanced then.

This protection has also a floating threshold for high transverse differential unbalance current
during other normal operation conditions.

Operation of the high sensitive transverse differential protection will lead a tripping immediately.
When rotor of generator is grounded at one point, a configurable time delay [t_TrvDiff_Gen] will be
inserted in the tripping course. Figure 3.8-1 shows logic diagram of this protection.

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3.8.1.3 Logic Scheme

Flg_1PEF_RotWdg &
&
[En_Alm_1PEF_RotWdg] [t_TrvDiff_Gen] ≥1

Flg_TransDiff_Gen
&
[En_SensTrvDiff_Gen]
&
&
Op_SensTrvDiff_Gen
[EBI_IntTurn_Gen]

FD_TransDiff_Gen

Figure 3.8-1 Logic diagram of transverse differential protection

Where:

Flg_1PEF_RotWdg is flag indicating the one-point earth fault protection of rotor operates.

Flg_TransDiff_Gen is flag indicating the criterion of transverse diffderential protection of generator


is met.

FD_TransDiff_Tr: fault detector of transverse diffderential protection of generator.

3.8.2 Longitudinal Zero-sequence Voltage Protection


Longitudinal zero sequence voltage protection is configured for inter-turn fault of stator winding of
generator. It uses open-delta voltage of dedicated VT at the generator terminal as the criterion.

Since this protection adopts frequency tracing, digital filtering and full cycle Fourier algorithm, the
third harmonic can be reduced to 1/100 within the frequency tracing range and the protection can
response the basic wave component only.

This protection comprises two stages: high-setting stage (insensitive stage) and sensitive stage.

3.8.2.1 High-setting Stage

Setting of this stage shall be higher than maximum unbalance voltage during external fault, whilst
directional flag indicating internal fault must be satisfied. When measured longitudinal zero
sequence voltage is in excess of the setting [V_InsensROV_Longl_Gen] and lasts for longer than
the delay setting [t_ROV_Longl_Gen], this protective element will trip breakers according to the
configuration of [TrpLog_IntTurn_Gen].

3.8.2.2 Sensitive Stage

Phase current percentage restraint principle is used for this stage. The operation criterion is

 I 
U z 0  1  K z 0  m   U z 0 zd
 Ie 

 3  I2 I max  I e
Im  
I max  I e   3  I 2 I max  I e

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Where:

U zozd is the zero sequence voltage setting [V_SensROV_Longl_Gen]

I MAX is the maximum value among three phase current of generator

I 2 is the negative sequence current of generator

I e is the rated current of generator

K z 0 is the restraint coefficient

Likely to transverse differential principle, this protective element can ensure no unwanted
operation during external fault and sensitive operation during internal fault. As for the percentage
restraint characteristic, zero sequence voltage setting of the zero sequence voltage protection
shall be only higher unbalance voltage during normal operation. Sensitivity for interturn fault of
generator can be enhanced then.

This protective element has also a floating threshold for high unbalance longitudinal zero
sequence voltage during other operation conditions.

Operation of this element is usually configured to be delayed shortly by 0.1s~0.2s.

3.8.2.3 Llogic Scheme

Flg_Dir_NegP
&
Flg_LongiROV_Gen

Flag_VTS
&
[En_InsensROV_Longl_Gen]

[EBI_IntTurn_Gen]
&
[t_ROV_Longl_Gen] Op_InsensROV_Longl_Gen
FD_IntTurn_Gen

Flg_LongiROV_Gen &

Flag_VTS
&
[En_SensROV_Longl_Gen]

[EBI_IntTurn_Gen]
&
[t_ROV_Longl_Gen] Op_SensROV_Longl_Gen
FD_IntTurn_Gen

Figure 3.8-2 Logic diagram of longitudinal zero sequence voltage protection

Where:

Flg_Dir_NegP is internally generated flag indicating whether or not the direction element

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calculated from negative-sequence voltage and current is meet the faulty condition.

Flg_LongiROV_Gen is internally generated flag indicating whether or not the longitudinal


zero-sequence overvoltage protection operates.

3.8.3 VT Circuit Failure Alarm and Blocking


Longitudinal zero-sequence voltage protection for inter-turn fault of stator shall be blocked when
the dedicated VT2 circuit at the generator terminal fails. There are two criteria to decide to whether
or not block the protection.

Criterion 1:

1. Negative-sequence voltage of VT1: 3U2<U2_set1 and broken-delta voltage of VT2: 3U0′>Uozd


(zero-sequence voltage setting)

2. Negative-sequence voltage of VT2: 3U2′<U2_set2 and broken-delta voltage of VT2:


3U0′>Uozd (zero-sequence voltage setting)

Criterion 2:

U AB  U ab  5V

U BC  U bc  5V

U CA  U ca  5V

Where:

U AB , U BC , U CA are phase-to-phase voltages of VT1

U ab , U bc , U ca are phase-to-phase voltages of VT2

That any one of these three sub-criteria is met means criterion 2 picks up.

When any of criterion 1 and criterion 2 operates, alarm of VT2 circuit failure will be issued with a
time delay of 40ms and longitudinal zero-sequence voltage protection will be blocked.

After VT circuit failure reverting to normal condition, blocking can be released by pressing the reset
button.

3.8.4 DPFC Inter-turn Protection


The operation criterion is:

 

ΔF=Re ΔU 2  Δ I 2  e jΦ   ε  1.25 dF
 

U 2  0.5V  1.25du

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I 2  0.02In  1.25di

If the three criterions are met simultaneity, the directional flag of protection is set. Under
negative-sequence voltage and negative-sequence current controlling, the protection operates
after 0.2~0.5s time delay.

AC current and voltage input of DPFC inter-turn protection are from the generator terminal directly.
When the VT1 at the generator terminal fails, DPFC inter-turn protection is blocked. The setting is
default setting. The sensitivity is about 3V of longitudinal zero-sequence voltage.

DPFC inter-turn protection can not response to inter-turn fault before the generator is connected
into the power system.

3.9 Phase-to-phase Backup Protection of Generator


3.9.1 Voltage Controlled Overcurrent Protection
This protection is used as a backup protection of generator, main transformer, HV busbar and
adjacent lines. There are two stages with their own delay settings respectively. Stage 1 is used to
trip bus coupler breaker or other circuit breaker and stage 2 to shut down the generator. Figure
3.9-1 shows its logic diagram.

3.9.1.1 Composite Voltage Element

Composite voltage element consists of phase-to-phase undervoltage element and


negative-sequence overvoltage element. These two elements are jointed together by OR gate. By
relevant logic setting, stage 1 and stage 2 of overcurrent protection can be configured to be
controlled by composite voltage element respectively.

3.9.1.2 Current Memory

For generators with self shunt excitation, current will decrease so quickly during fault that it may be
lower than overcurrent setting before tripping. So memorized function for remember fault current is
equipped with this protection. Logic setting [En_Mem_Curr_Gen] is used for configuration of this
function.

Note!

When logic setting [En_Mem_Curr_Gen] is enabled, overcurrent protection must be


controlled by voltage element.

3.9.1.3 Blocking by HV-side Composite Voltage

Overcurrent protection can be blocked not only by composite voltage at generator terminal but
also by composite voltage at HV side of main transformer. This function can be configured by
setting logic setting [En_HVS.VCE_Ctrl_OC_Gen] as ―1‖.

3.9.1.4 Influence on Protection Performance during VT Circuit Failure

A logic setting [Opt_VTS_Ctrl_OC_Gen] is used to configure composite voltage element during VT

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circuit failure. When this logic setting is set as ―1‖, if VT circuit failure at this side is detected, the
composite voltage element will not meet conditions to operate. When this logic setting is set as ―0‖,
if VT circuit failure at this side is detected, composite voltage element is disabled, overcurrent
protection will not be blocked and becomes a pure overcurrent protection.

3.9.1.5 Logic Scheme

Upp< [Vpp_UV_VCE_Gen] ≥1
&
U2>[V_NegOV_VCE_ Gen] ≥1
Flg_VCE_Gen
Flg_VTS

&

[Opt_VTS_Ctrl_OC_Gen]

&
≥1
[En_Mem_Curr_Gen] &
Flg_OCn_Gen

Flg_VCE_Gen ≥1

[En_VCE_Ctrl_OCn_Gen]

[En_PPF_Gen] & &


[t_OCn_Gen] Op_OCn_Gen
[EBI_PPF_Gen]

FD_OCn_Gen

Figure 3.9-1 Logic diagram of overcurrent protection

Where:

Upp represents any one of the three phase-to-phase voltage of generator.

U2 is negative sequence voltage of generator calculated by protection.

Flg_OCn_Gen is internally generated flag indicating stage n of overcurrent operates, which means
the measured current is in excess of its setting [I_OCn_Gen]. (n can be 1 or 2).

As for principle of discrimination of VT circuit failure, see section 3.32.

3.9.2 Impedance Protection


Two stages impedance protection is equipped at the generator terminal as its phase-to-phase
backup protection. Phase-to-phase current used in impedance protection is derived from CT at the
neutral point of generator. Full impedance, directional impedance or shifted impedance
characteristic can be selected to operate for these two stages. Full impedance characteristic suits
case of forward setting of a zone being equal to its reverse setting. Directional impedance
characteristic suits case of reverse setting of a zone being set as 0. Shifted impedance

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characteristic suits for case that forward setting of a zone is higher than its reverse setting. Reach
angle of impedance protection is 78°. Forward of the impedance protection is configurable and
generally points to generator.

jX

I Zp
 
U I Zp
m 
U
R

 
 U  I Zn
 I Zn

Figure 3.9-2 Operation characteristic of impedance protection

Figure 3.9-2 shows operation characteristic of impedance protection. In this figure, I is phase
current, U is corresponding phase-to-phase voltage, Zn is reverse impedance setting, Zp is
forward impedance setting.

Operation criterion:
 
(U  I Z P )
90  Arg

 
 270
(U  I Z n )

DPFC phase-to-phase current and negative-current current are adopted as fault detector of
impedance protection. Pickup signal will be maintain 500ms and will be kept if impedance
protection operates during this time interval. Operation criterion of the fault detector is:

I  1.25I t  I th

Where:

I t is floating threshold which increases gradually along with DPFC increasing. Take its multiple

as 1.25 can ensure threshold voltage always a bit higher than imbalance voltage.

Unwanted operation of the device can be avoided during conditions of power swing and frequency
deviation from nominal valuess.

I th is the fixed threshold. When DPFC phase-to-phase current is higher than 0.2Ie, the fault

detector operates.

The logic scheme of impedance protection is shown in Figure 3.9-3.

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Flg_VTS &
Flg_Zn_Gen
&
& [t_Zn_Gen] Op_Zn_Gen
[En_PPF_Gen]

[EBI_PPF_Gen]

FD_PPF_Gen

Figure 3.9-3 Logic diagram of impedance protection

Where:

Flag_Zn_Gen is internally generated indicating stage n of distance protection of generator is met.

Note!

If VT circuit failure occurs, impedance protection of generator will be blocked.

Note!

When stage 1 of phase-to-phase backup protection of generator operates to trip bus


coupler circuit breaker, The current blocking circuit breaker at HV side of main transformer
can be selected.

3.10 Stator Earth-fault Protection


3.10.1 Fundamental Zero-sequence Overvoltage Protection
Single-phase earth fault within 85%~95% ranges from terminal of stator winding can be protected
by fundamental zero-sequence overvoltage protection.

Fundamental zero-sequence overvoltage protection reacts to magnitude of zero sequence voltage


of generator. Since it adopts frequency tracing, digital filtering and full cycle Fourier algorithm, the
third harmonic can be reduced to 1/100 within the frequency tracing range and the protection can
response the basic wave component only.

This protection comprises two stages: sensitive stage and insensitive stage (high setting stage).

3.10.1.1 Sensitive Stage

Operation criterion:

U n0  U 0zd

Where:

U n 0 is zero-sequence voltage of neutral point of generator

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U 0zd is operation threshold setting of fundamental zero-sequence voltage [V_SensROV_Sta].

When the sensitive stage operates to trip, in order to prevent sensitive stage of fundamental
zero-sequence overvoltage protection from undesired trip due to external fault, it can be blocked
by zero-sequence voltage at HV side of main transformer, and the blocking setting of
zero-sequence voltage can settable.

When the sensitive stage operates to trip, it will be blocked by broken-delta zero-sequence voltage
of generator terminal, and the blocking setting need not be set. The device switched automatically
according to VT ratio of generator terminal and neutrol point of generator.

Zero-sequence voltage of generator terminal can be from broken-delta zero-sequence voltage of


VT1 or calculated zero-sequence voltage of VT1.

3.10.1.2 High-setting Stage

Operation criterion:

U n0  U 0hzd

Where:

U n0 is zero-sequence voltage of neutral point of generator

U 0hzd is zero-sequence voltage high setting [V_InsensROV_Sta]. 20V~25V is recommended

generally.

The high-setting stage can be independently set to trip.

3.10.2 Third Harmonic Voltage Ratio Protection


This protection is designed to cover only about 25% of earth fault of the stator winding away from
generator terminal. Third harmonic voltage of generator terminal is got from its broken-delta
zero-sequence voltage. Third harmonic voltage of neutral point side is got from neutral point VT of
the generator.

Operation criterion:

U 3T / U 3N  K 3wzd

Where:

U 3T and U 3N are third harmonic voltage of generator terminal and neutral point respectively.

K 3wzd is the third harmonic voltage percentage setting.

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During incorporation of generator to power system, the ratio U3T/U3N changes considerably owing
to variation of equivalent capacitive reactance at generator terminal. So two different settings are
designed for protection before and after connection of generator with system, and these two
settings can be switched over with alternation of contacts‘ position of the terminal breaker.

In addition, settings are provided for deciding whether the ratio protection of third harmonics
voltage is used for alarm or tripping or both.

Third harmonic voltage ratio protection can operates for alarm purpose or trip purpose.

3.10.3 Third Harmonic Voltage Differential Protection


Operation criterion:

  
U 3T  K t  U 3 N  Kre  U 3 N

Where:

 
U 3T and U 3 N are third harmonic vector voltage of generator terminal and neutral point

K t is automatic tracing regulation coefficient

K re is third harmonic differential percentage setting

This protection is enabled automatically when the generator has been connected with the system
and load current is higher than 0.2 Ie (generator rated current) and only issues alarms if operates.

Third harmonic voltage differential protection operates only for alarm purpose.

3.10.4 VT Circuit Failure Blocking


1. Broken-delta VT circuit failure alarm of generator terminal and neutral point of generator

Since broken-delta voltages of VT at neutral point and generator terminal are taken for
zero-sequence voltage protection of stator, failure of these VT circuits will make this protection fail
to operation. So alarm shall be issued during this case. Third harmonic voltage ratio criterion and
third harmonic voltage differential criterion shall be disabled during VT circuit failure at neutral
point of generator.

The operation criterion is:

Positive-sequence voltage of secondary winding of generator terminal is higher than 0.9Un and
third harmonic of zero-sequence voltage is lower than 0.1V.

VT circuit failure alarm will be issued by delay 10s and reverted automatically by delay 10s when
the failure vanishes.

If zero-sequence voltage of generator terminal is from calculated zero-sequence voltage,

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broken-delta circuit failure of VT1 at generator terminal is not discriminated.

The alarm function of broken-delta VT circuit failure of generator terminal and neutral point of
generator can be enabled or disabled by logic setting [En_Alm_DeltVTS1_Gen].

2. Primary circuit failure of VT1 at generator terminal

Secondary circuit failure of VT1 of generator terminal will not influence ground protection of stator.
Primary circuit failure of VT1 of generator terminal will cause basic wave component of zero
sequence voltage of generator terminal increasing and third harmonic component decreasing, and
will not cause unwanted operation of basic wave zero sequence voltage protection and third
harmonic voltage ratio protection. However, it will cause unwanted operation of third harmonic
voltage differential protection, so this protection shall be blocked during this failure. The operation
criterion is:

1. Negative-sequence voltage of VT2: 3U2′<3V

2. Negative-sequence voltage of VT1: 3U2 >8V

3. Calculated zero-sequence voltage of VT1: 3U0>8V

4. Open-delta zero-sequence voltage of VT1: 3U0>8V

When these criterions are met, VT1 primary circuit failure alarm will be sent by short delay and
third harmonic voltage differential protection and third harmonic voltage ratio protection will be
blocked.

If zero-sequence voltage of generator terminal is from calculated zero-sequence voltage, primary


circuit failure of VT1 is not discriminated.

3.10.5 Logic Scheme


Figure 3.10-1 show logic diagrams of stator earth-fault protection.

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[En_Alm_ROV_Sta] &
t Alm_ROV_Sta
Flg_SensROV_Sta

Flg_SensROV_Sta
&
Flg_VTS

[En_Trp_ROV_Sta]
&
[En_EF_Sta] &
[t_ROV_Sta] Op_Trp_ROV_Sta
[EBI_ROV_Sta]

FD_EF_Sta

Flg_InsensROV_Sta &

[En_Trp_InsensRov_Sta]
&
[En_EF_Sta] &
[t_InsensROV_Sta] Op_InsensROV_Sta
[EBI_ROV_Sta]

FD_EF_Sta

En_Alm_V3rdHRatio_Sta &
Flg_VTS
& t Alm_V3rdHRatio_Sta
Flg_V3rdHRatio_Sta

[En_EF_Sta]
&
[En_Trp_V3rdHRatio_Sta] &
t_V3rdH_Sta Op_V3rdHRatio_Sta
[EBI_V3rdH_Sta]

FD_EF_Sta

Figure 3.10-1 Logic diagram of stator earth-fault protection

Where:

Flg_SensROV_Sta is internally generated flag indicating sensitive stage of fundamental


zero-sequence overvoltage protection operates.

Flg_InsensROV_Sta is internally generated flag indicating insensitive stage of fundamental


zero-sequence overvoltage protection operates.

Flg_V3rdHRatio_Sta is internally generated flag indicating third harmonic voltage ratio protection
operates.

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3.11 Stator Earth-fault Protection with Voltage Injection

GND Earthing Generator Main Breaker Busbar


transformer transformer

Band-Pass Filter
B10

Load
Resistor
Voltage
Rn Divider Square-wave
power supply
A2
Inter-CT

ISEF USEF RCS-985U auxiliary power


Panel B
supply for stator earth fault
protection

PCS-985B Generator Relay

Figure 3.11-1 Circuit design of stator earth-fault protection with voltage injection

An external low-frequency alternating voltage source injects into neutral point of the generator via
secondary side of earthing transformer, or injects into secondary side of broken-delta VT at the
generator terminal.

3.11.1 Earthing Resistance Criterion


Earthing resistance criterion is not related ot the location of stator windings eart fault, and it can
protect 100% range of stator windings for single-phase earth-fault.

According to the erthing resistance of stator windings, PCS-985B provides two stages for alarm
purpose with high setting and for trip purpose with low setting respectively. The operation
criterions are:

RE  REsetL
(for trip purpose)

RE  REsetH
(for alarm purpose)

Where:

RE is calculated earth resistance .

REsetL is resistance setting for trip purpose.

REsetH is resistance setting for alarm purpose.

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3.11.2 Earthing Current Criterion


If an earth fault happens to stator windings near generator terminal during normal generator
operation, fundamental components will increase obviously and the sensitivity of detecting
low-frequency faulty components will be affected seriously. In order to improve the sensitivity,
earthing current criterion is equipped with the device. It can detect single-phase fault with the
range of 80%~90% stator windings away from generator terminal. The great advantage of this
criterion is that more close to the generator terminal the fault point locates, more high sensitivity
the criterion can get, which can realize 100% stator earth-fault protection cooperated with the
earthing resistance criterion.

The operation criterion is:

I G 0  I Eset

Where:

I G 0 is earthing current of stator without being subjected to digital filter.

I Eset is earthing current setting.

3.11.3 External Voltage Circuit Monitoring

When U LF 0 ( U G 0 is low-frequency voltage after Un0 is digital filtered) is smaller than the setting

value or I LF 0 ( I G 0 is low-frequency current after In0 is digital filtered) is smaller than the setting

value, it means that external injection circuit for stator earth-fault protection is abnormal. The
device will be blocked and issue an alarm signal.

The operation criterion is:

U LF 0  U LF 0 set

I LF 0  I LF 0 set

Where:

U LF 0 set is alarm setting of low-frequency voltage

I LF 0 set is alarm setting of low-frequency current

When the frequency of generator voltage deviate rated frequency seriously, the earthing
resistance criterion should be blocked, but the earthing current criterion is not affected.

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3.11.4 Logic Scheme

ULF0<ULF0.SET ≥1
0s 0.1s Alm_Pwr_Inj_EF_Sta
ILF0<ILF0.SET
&
Frequency blocking & &
t Alm_SensInjEF_Sta
[En_Freq_Blk_Inj_EF_Sta]

RE<RE.SET.H &
≥1
RE<RE.SET.L t Op_Inj_EF_Sta

IG0>IE.SET &

[EBI_Inj_EF_Sta]

Figure 3.11-2 Logic diagram of stator earth-fault protection with voltage injection

3.12 Rotor Earth-fault Protection with Ping-pang Type


3.12.1 One-point Earth-fault Protection
If one-point earth fault of rotor occurs, insulation resistance between rotor winding and the axis will
drop down. Rotor earth-fault protection adopts switch-over sampling principle (ping-pang type)

Rotor earth-fault protection measures earthing resistance Rg of the winding by an unbalance


bridge as shown in Figure 3.12-1. Corresponding equations can be got by switching over S1 and
S2 alternately, and earthing resistance Rg and location of the earthing point ―α‖ can be found by
calculation.

There are two stages equipped for one-point earth protection: sensitive stage and regular stage.
Sensitive stage is used for alarm and regular stage for tripping or alarm.

U
+ aU -

rotor
R Rg R

R S1 S2 R

Figure 3.12-1 Schematic diagram of measurement principle

Figure 3.12-2 show logic scheme of one-point earth fault protection.

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Rg<[R_Sens1PEF_RotWdg] &
Alm_Sens_1PEF_RotWdg
[En_Alm_Sens_1PEF_RotWdg]

[En_Alm_1PEF_RotWdg] &
t Alm_1PEF_RotWdg
Rg<[R_1PEF_RotWdg] &

[En_EF_RotWdg]
&
[En_Trp_1PEF_RotWdg] &
[t_1PEF_RotWdg] Op_Trp_1PEF_RotWdg
[EBI_EF_RotWdg]

FD_EF_RotWdg

Figure 3.12-2 Logic diagram of one-point earth fault protection

3.12.2 Two-points Earth fault Protection


If one-point earth protection is used for alarm only, when earth resistance Rg is less than setting of
its regular stage [R_1PEF_RotWdg], it will switch into two-points earth fault protection with a time
delay automatically. If the location of the earthing point varies and the variation reaches its setting
value, two-points earth fault protection will operate and issue a tripping command. In order to
improve the reliability, two-point earth fault protection can be blocked by second harmonic voltage
by setting logic setting [En_VCE_2PEF_RotWdg] as ―1‖.

Figure 3.12-3 show logic diagram of two-points earth fault protection.

Alm_1PEF_RotWdg t
&
Flg_2PEF_RotWdg &
[En_EF_RotWdg]

Flg_V2ndH_VCE_2PEF_RotWdg ≥1

[t_2PEF_RotWdg] Op_2PEF_RotWdg
[En_VCE_2PEF_RotWdg]

[En_2PEF_RotWdg]
&
[EBI_EF_RotWdg]

FD_EF_RotWdg

Figure 3.12-3 Logic diagram of two-points earth fault protection

Where:

Flag_2PEF_RotWdg is the flag indicating whether or not two-points earth-fault protection meet its
criteiron.

Flag_V2ndH_VCE_2PEF_RotWdg is the flag indicating whether or not the second harmonics


element used for control 2PEF operates.

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3.13 Rotor Earth-fault Protection with Voltage Injection


3.13.1 One-point Earth-fault Protection
Based on leading-out mode of rotor windings, rotor earth fault protection with injection principle of
double-ends or single-end can be selected. The injected power supply is connected to rotor
winding from between the positive/negative pole (or only negative pole) and shaft. The switching
cycle of injected power supply can be adjusted depended on in accordance with the capacitor
between rotor winding and ground. The rotor earth-fault protection with injection principle can
reflect a decline in insulation resistance between generator rotor and shaft by real-time calculating
one-point earth resistance of rotor.

The work circuit of voltage injection into the rotor winding at double-ends and single-end is shown
in Figure 3.13-1 and Figure 3.13-2 respectively.

Ur+

Usq
Rg
Rotor Axis

Ig Rx

Ur-
Ry

Figure 3.13-1 Measuring scheme of voltage injection into the rotor winding at single-end

Ry
Ur+

Usq
Rg
Rotor Axis

Rx Ig

Ur-
Ry

Figure 3.13-2 Measuring scheme of voltage injection into the rotor winding at double-ends

Where:

Ur: the rotor voltage

α: the percentage of earthing location

RX: the resistance of measure circuit

Ry: the injected external resistance

Usq: the injected square power supply

Rg: the insulation resistance between rotor windings and shaft

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Rotor one-point earth fault protection provides two stages: one stage is sensitive stage used to
issue alarm signal, and the other stage, regular stage, can operate to issue alarm signal or trip.

Figure 3.13-3 show logic diagram of one-point earth fault protection.

Rg<[R_Sens1PEF] &
Alm_Sens1PEF
[En_Alm_Sens1PEF]

[En_Alm_1PEF] &
[t_Alm_1PEF] Alm_1PEF
Rg<[R_1PEF]

&
[En_Trp_1PEF]

[EBI_1PEF_RotWdg]
&
[t_Trp_1PEF] Op_1PEF_RotWdg
FD_1PEF_RotWdg

Figure 3.13-3 Logic diagram of one-point earth-fault protection

3.13.2 Two-point Earth-fault Protection


If both positive and negative terminal of rotor windings are leaded out, rotor earth-fault protection
with voltage injection can measure the one-point earthing location, and then implement two-points
earth fault protection according to the variation of the earthing location.

If rotor one-point earth fault protection is used to issue alarm signal only, it is optional whether rotor
two-points earth fault protection is put into service or not. If it is selected to be in service, rotor
two-point earth fault protection will be enabled automatically with a time delay after regular stage
of rotor one-point earth fault protection operating to issue alarm signal. After that, if the location of
earthing point varies and the variation reaches its internal threshold value, the protective device
thinks it as two-point earth fault and rotor two-points earth fault protection will operate to trip.

Figure 3.13-4 show logic diagram of two-points earth fault protection.

[Alm_1PEF] t &
&
[En_2PEF] [t_Trp_2PEF] Op_2PEF_RotWdg

[EBI_2PEF_RotWdg] &

FD_2PEF_RotWdg

Figure 3.13-4 Logic diagram of two-points earth-fault protection

Note!

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The device only can enable any of rotor earth-fault protection with ping-pang type and rotor
earth-fault protection with voltage injection, the other is reserved.

3.14 Stator Overload Protection


Stator overload represents average heating of winding of the stator. This protection takes currents
from generator terminal and neutral point as its criterion.

3.14.1 Definite-time Stator Overload Protection


There are two stages equipped with definite-time stator overload protection: one for alarm and
another for tripping. Figure 3.14-1 shows its logic diagram.

I>[I_Alm_OvLd_Sta] &
t [Alm_OvLd_Sta]
[En_OvLd_Sta]

I>[I_OvLd_Sta] &

[En_OvLd_Sta]

[TrpLog_OvLd_Sta].Bit0 & &


t [Op_OvLd_Sta]
[EBI_Ovld_Sta]

FD_Ovld_Sta

Figure 3.14-1 Logic diagram of definite-time stator overload protection

3.14.2 Inverse-time Stator Overload Protection


Inverse-time stator overload protection consists of three parts: low-setting initiator, inverse-time
part and upper-limit definite-time part.

The upper-limit definite-time part has minimum operating time. When stator current reaches its low
setting (Iszd), inverse-time part initiates and the heat is accumulated. When the accumulated
value is greater than the setting, inverse-time stator overload protection operates to trip.

Inverse-time part can simulates generator-heating process including heat accumulation and
dissipation. When the stator current is lower than rated value, the heat accumulation will decrease
accordingly.

Figure 3.14-2 shows the inverse-time curve.

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I
Ih

Iszd

t min t max

Figure 3.14-2 Operation curve of inverse-time stator overload protection

Where:

tmin is time delay of upper limit

tmax is time delay of lower limit

Iszd is initiation setting of inverse-time part

Ih is upper-limit current value

Operation criterion of inverse-time stator overload protection:

[( I I ezd)  K srzd  ]  t  KS zd
2 2

Where:

KS zd is time constant of generator heating

K srzd is heat dissipation factor of generator

I ezd is rated secondary current of generator

Figure 3.14-3 shows logic diagram of inverse-time stator overload protection.

I > [I_InvOvLd_Sta] & IDMT &

[En_OvLd_Sta] t

[TrpLog_InvOvLd_Sta].Bit0 & &


Op_InvOvLd_Sta
[EBI_EF_Sta]

FD_InvOvLd_Sta

Figure 3.14-3 Logic diagram of inverse-time stator overload protection

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Note !

In order to prevent heat accumulation from not being dissipated, the dissipation coefficient
(the setting [K_Disppt_Sta])should be set as 1.02~1.05.

3.15 Negative-sequence Overload Protection


Negative-sequence overload reflects overheating on surface of the rotor and other abnormality
due to negative-sequence current. This protection takes negative-sequence current at generator
terminal and neutral point as its criterion.

3.15.1 Definite-time Negative-sequence Overload Protection


There are two stages equipped with definite-time negative-sequence overload protection: one for
alarm and the other for tripping. Figure 3.15-1 shows its logic diagram.

[En_NegOC_Gen] &
[t_Alm_NegOC_Gen] Alm_NegOC_Gen
I2>[I_Alm_NegOC_Gen]

I2>[I_NegOC_Gen] &

[En_NegOC_Gen]

[TrpLog_NegOC_Gen].Bit0 & &


[t_NegOCn_Gen] Op_NegOC_Gen
[EBI_NegOC_Gen]

FD_NegOC_Gen

Figure 3.15-1 Logic diagram of definite-time negative-sequence overload protection

3.15.2 Inverse-time Negative-sequence Overload Protection


Inverse time negative sequence protection consists of three parts: low-setting initiator,
inverse-time part and upper-limit definite-time part.

The upper-limit definite-time part has minimum operating time. When negative-sequence current
reaches its low setting [I_InvNegOC_Gen], inverse-time part initiates and the heat is accumulated.
When the accumulated value is greater than the setting, inverse-time negative-sequence overload
protection operates to trip.

Inverse-time part can simulate generator-heating process including heat accumulation and
dissipation. When the stator current is lower than permissive continuous negative-sequence
current [I_Neg_Perm_Gen], the heat accumulation will decrease accordingly.

Figure 3.15-2 shows the inverse-time curve.

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I2zd

t min t max

Figure 3.15-2 Operation curve of inverse-time negative-sequence overload protection

Operation criterion of inverse-time negative-sequence overload protection:

[( I 2 I ezd)  I 21  ]  t  A
2 2
Equation 3.15-1

Where:

I 2 is generator negative-sequence current

I ezd is generator rated current

I 2l is permissive continuous negative-sequence current (per unit value)

A is negative-sequence heating constant of rotor.

Inverse-time negative-sequence overload protection can be set to trip to separation and field
suppression or alarm. Figure 3.15-3 shows its logic diagram.

t>tmax
I2>[I_InvNegOC_Gen] & ≥1
IDMT &
[En_NegOC_Gen]
t>tmin

[TrpLog_InvNegOC_Gen].Bit0 & &


Op_InvNegOC_Gen
[EBI_NegOC_Gen]

FD_InvNegOC_Gen

Figure 3.15-3 Logic diagram of inverse-time negative-sequence overload protection

Note!

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The long time delay of lower limit should be smaller than the calculated operating time
using lower-limit pickup current according to Equation 3.15-1.

3.16 Loss-of-excitation Protection


Loss of excitation represents abnormal operation of generator due to excitation failure. There are 3
criterion used for loss-of-excitation protection: undervoltage criterion, stator-side impedance
criterion and rotor-side criterion.

3.16.1 Undervoltage Criterion


Three-phase voltages on busbar side generally and those at generator terminal sometimes are
taken as this criterion. Three-phase voltage should meet the criterion simultaneous.

U pp  U lezd

Where:

Upp is phase-to-phase voltage of busbar or of generator terminal.

Ulezd is undervoltage setting [V_BusUV_LossExc_Gen].

When bus voltage is taken as the criterion, if bus VT circuit fails, the protection will be blocked.
When generator terminal voltage is taken as the criterion, if one group of VT circuit fails, the other
group of VT will be switched over automatically.

3.16.2 Stator-side Impedance Criterion


This criterion is impedance circle including asynchronous impedance circle and steady-state
stabilization limit circle. The operation criterion is

Z  jX B
270  Arg  90
Z  jX A

Where:

XA: can be set as the system impedance Xs for steady-state stabilization limit circle and XA= 0.5
X'd for asynchronous impedance circle

XB: is taken as Xd+0.5 X'd for non-salient pole generator and 0.5(Xd+Xq)+0.5 X'd for salient pole
generator

The impedance criterion can be combined with reverse reactive power criterion, i.e.,
Q<[Q_RevQ_LossExc_Gen].

Using the same current and voltage to calculate inactive power and reverse power.

Figure 3.16-1 and Figure 3.16-2 show operation characteristics of steady-state stabilization
impedance circle and asynchronous impedance circle.

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jx
Z1

R
-Qzd

Z2

Figure 3.16-1 Operation characteristic of steady-state stabilization impedance circle

The hatched area is operating area, and the dotted line is operation limit of reverse reactive power.

jx

Z1
R
-Qzd

Z2

Figure 3.16-2 Operation characteristic of asynchronous impedance circle

Besides operation criterion mentioned above, there are also auxiliary operation criterion, namely:

1. Positive-sequence voltage is greater than or equal to 6V

2. Negative-sequence voltage U2 is lower than 0.1Un (rated voltage of generator)

3. Generator current is no less than 0.1Ie (rated current of generator)

3.16.3 Rotor-side Criterion


Rotor-side criterion comprises:

Rotor-side undervoltage criterion: Ur<Ur1zd

Where:

Ur is rotor voltage

Ur1zd is undervoltage setting [V_RotUV_LossExc_Gen]

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Variable excitation voltage criterion: Ur < Krel×Xdz×P×Uf0

Where:

Xdz=Xd+Xs, Xd is synchronous reactance of generator (per unit value)

Xs is equivalent reactance on system side connected with the generator (per unit value)

P is rated apparent power of generator (per unit value)

Uf0 is rated voltage of exciter during generator without load

Krel is reliability coefficient.

If Ur drops to zero or minus value suddenly during loss of excitation, the rotor under voltage
criterion will be met quickly before steady-state stability limit of the generator reaches. If Ur drops
to zero or reduces to a value gradually during loss of excitation, the variable excitation voltage
criterion will be reached. Excitation undervoltage or loss of excitation will cause out-of-step, and
then excitation voltage and output power of the generator will swing seriously. In this case, the
rotor under voltage criterion and the variable excitation voltage criterion will be met and withdrawn
periodically in general. So the excitation voltage element will revert with delay during out-of-step
condition while the impedance entering the steady state stability limit circle.

3.16.4 Logic Scheme


Three stages are equipped with loss-of-excitation protection: stage 1 is used to trip adopting
busbar-side undervoltage criterion, stage 2 is used to trip adopting generator terminal
undervoltage criterion, stage 3 is used to trip or alarm with long time delay.

Figure 3.16-3 shows logic diagram of stage 1 of loss-of-excitation protection.

Ur<[V_BusUV_LossExc_Gen] &
≥1
[En_RotUV_LossExc1_Gen] &
Ur<[V_RotUV_LossExc_Gen] ≥1
&
Ur<Krel×Xdz×P×Uf0 ≥1

[En_RotUV_LossExc1_Gen]
&
Flg_Z_LossExc1_Gen & & t Op_LossExc1_Gen

[En_Z_LossExc1_Gen]

& ≥1
Q>[Q_RevQ_LossExc_Gen] &
[En_RevQ_LossExc_Gen]

[En_LossExc_Gen]
&
[EBI_LossEXC_Gen]

FD_LossExc_Gen

Figure 3.16-3 Logic diagram of loss-of-excitation protection (stage 1)

Figure 3.16-4 shows logic diagram of stage 2 of loss-of-excitation protection. If excitation is lost

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and voltage at HVside of main transformer is lower than its setting, this stage will trip with a time
delay. In configuring this stage, considering of security, it is strongly recommended that impedance
criterion should be used as well as undervoltage criterion rather than that only undervoltage
(busbar or generator terminal) criterion and rotor undervoltage criterion are used.

Upp<[V_BusUV_LossExc_Gen &
≥1
[En_BusUV_LossExc2_Gen]

Ur<[V_RotUV_LossExc_Gen] ≥1
&
Ur<Krel×Xdz×P×Uf0 ≥1 &
t Op_LossExc2_Gen
[En_RotUV_LossExc2_Gen]

Flg_Z_LossExc2_Gen
&
&

[En_Z_LossExc2_Gen]

& ≥1
Q>[Q_RevQ_LossExc_Gen]

[En_RevQ_LossExc_Gen]

[En_LossExc_Gen]
&
[EBI_LossEXC_Gen]

FD_LossExc_Gen

Figure 3.16-4 Logic diagram of loss-of-excitation protection (stage 2)

Figure 3.16-5 shows logic diagram of stage 3 of loss-of-excitation protection. It is also used to trip
with a long time delay.

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[En_Alm_LossExc3_Gen]

Ur<[V_RotUV_LossExc_Gen] ≥1
&
Ur<Krel×Xdz×P×Uf0 ≥1
&
t Alm_LossExc_Gen
[En_RotUV_LossExc1_Gen]

Flg_Z_LossExc1_Gen
&
&

[En_Z_LossExc1_Gen]

Q>[Q_RevQ_LossExc_Gen] & ≥1

[En_RevQ_LossExc_Gen]

En_LossExc_Gen
&
& t Op_LossExc3_Gen
EBI_LossExc_Gen

FD_LossExc_Gen

Figure 3.16-5 Logic diagram of loss-of-excitation protection (stage 3)

3.17 Out-of-step Protection


Out-of-step protection represents asynchronous operation of generator due to out of step.
Out-of-step protection calculates impedance element by positive-sequence voltage and current,
and impedance locus can reflect any kinds of fault situation correctly.

Figure 3.17-1 shows operation characteristic of out-of-step protection that comprises three parts:
lens part, boundary part and reactance line part.

jx
Za
U

D
Zc
OL
IL 3
2
1 IR 1
OR
0 R

L R
Zb

Figure 3.17-1 Operation characteristic of out-of-step protection

1. Lens divides impedance plane into inside part I and outside part O

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2. Boundary divides the impedance plane into left part L and right part R

3. Reactance line divides the impedance plane into upper part U and lower part D

Considering lens and boundary comprehensively, the impedance plane is divided into four areas:
OL, IL, IR and OR. If the locus of impedance is passing through these four areas in sequence from
right to left or vice versa, and staying in each area for a moment longer than the setting, this case
is considered as power swing. The times of passing through are accumulated and the grand total
is considered as the times of pole sliding. When the grand total reaches its setting value,
out-of-step protection operates.

As to reactance line, if the impedance locus passes through the upper part U, the swing center is
considered outside the generator. If the locus passes through the lower part D, the swing center is
considered within the generator. Settings of times of pole sliding can be configured separately for
these two cases.

Out-of-step protection can be used either for alarm only or tripping. Minimum swing period which
can be identified by this protection is 120 ms.

Figure 3.17-2 shows logic diagram of out-of-step protection.

[En_Alm_Int_OOS_Gen] &
Accumulated Times Alm_Int_OOS_Gen

[En_Alm_Ext_OOS_Gen]

Flg_Blk_OOS
&
& Accumulated Times Alm_Ext_OOS_Gen
Flg_OOS_Gen

[En_OOS_Gen]
&
[TrpLog_OOS_Gen].Bit0

[EBI_OOS_Gen]
&
Accumulated Times Op_Ext_OOS_Gen
FD_OOS_Gen
Op_Int_OOS_Gen

Figure 3.17-2 Logic diagram of out-of-step protection

3.18 Overvoltage Protection


Overvoltage protection is used as protection against stator overvoltage occurring in various
operation conditions. It will issue tripping command when the maximum phase-to-phase voltage at
the generator terminal is in excess of the setting. Voltage calculation is independent of the
variation of frequency. Two stages of overvoltage protection are equipped with PCS-985B for
tripping. Figure 3.18-1 shows logic diagram of overvoltage protection.

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Upp>[V_OVn_Gen] &

[En_VoltProt_Gen]
&
[TrpLog_OVn_Gen].Bit0 &
[t_OVn_Gen] Op_OVn_Gen
[EBI_VoltProt_Gen]

FD_OV_Gen

Figure 3.18-1 Logic diagram of overvoltage protection

3.19 Over-excitation Protection


Over-excitation protection is used to prevent generator or transformer from damage due to over
excitation. It represents multiple of over excitation of generator (or LV side of main transformer)
and comprises two kinds of protection: generator over excitation protection and main transformer
over excitation protection. Besides, each kind of over excitation protection comprises definite-time
protection and inverse-time protection.

For generator, over-excitation protection calculates the voltage from generator terminal to
discriminate whether it is over excitation. For main transformer, over-excitation protection
calculates the voltage from HV side of main transformer to discriminate whether it is over
excitation. If no circuit breaker is equipped with generator terminal, only one set of over-excitation
protection needs be enabled. If there is a circuit breaker equipped with generator terminal, both
over-excitation protection of generator and over-excitation protection of main transformer should
be eneabled.

3.19.1 Definite-time Over-excitation Protection


One stage for tripping and one stage for alarm

Two stages are equipped for definite-time over-excitation protection, and one stage for alarm
purpose and one stage for trip purpose. Their time delays can be configured.

Multiple of over excitation n can be expressed as follows:

n  Upu / Fpu

Where:

Upu is per unit value of voltage

Fpu is per unit value of frequency

Figure 3.19-1 shows logic diagram of definite time over excitation protection.

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[En_OvExc_Gen] &
[t_Alm_OvExc_Gen] Alm_OvExc_Gen
U/F>[k_Alm_OvExc_Gen]

U/F>[k_OvExc n_Gen] &

[En_OvExc_Gen]

[TrpLog_OvExc n_Gen].Bit0 & &


[t_OvExcn_Gen] Op_OvExcn_Gen
[EBI_OvExc_Gen]

FD_OvExc_Gen

Figure 3.19-1 Logic diagram of definite-time over-excitation protection

3.19.2 Inverse-time Over-excitation Protection


Inverse-time over-excitation protection realizes inverse-time characteristic by linear processing on
given inverse time operation characteristic, obtaining multiple of over excitation by calculation, and
getting corresponding operation delay by sectional linear insertion. It reflects heat accumulation
and radiation.

Figure 3.19-1 shows inverse-time operation characteristics of over-excitation protection. It can be


specified by 8 over excitation multiple settings n0~n7.

U/F
n0
n1
n2
n3
n4
n5
n6
n7

t0 t1 t2 t3 t4 t5 t6 t(s) t7

Figure 3.19-2 Inverse-time characteristics

The over excitation multiple settings n (= U/F) are within range of 1.0~1.5 in general. Maximum
time delay t is considered as long as 3000s. Relation between various settings of n and t are:

n0 ≥ n1 ≥ n2 ≥ n3 ≥ n4 ≥ n5 ≥ n6 ≥ n7

t0 ≤ t1 ≤ t2 ≤ t3 ≤ t4 ≤ t5 ≤ t6 ≤ t7

Figure 3.19-3 shows logic diagram of inverse-time over-excitation protection.

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U/F>[k n_InvOvExc_Gen] &


IDMT
[En_OvExc_Gen]

[TrpLog_InvOvExc_Gen].Bit0 & &


Op_InvOvExc_Gen
[EBI_OvExc_Gen]

FD_OvExc_Gen

Figure 3.19-3 Logic diagram of inverse-time over-excitation protection

3.20 Power Protection


Power protection comprises reverse power protection, sequence tripping reverse power protection
and low power protection.

3.20.1 Reverse Power Protection


Reverse power protection can prevent turbine blades or gears from damage in the case that the
generator transforms into a motor mode and flows reverse power due to loss of its motive force.

Operation criterion of reverse power protection is

P<-[P_RevP_Gen]

Where:

P is the power calculated from three phase voltages and currents at generator terminal.

[P_RevP_Gen] is the reverse power setting.

One stage for tripping and another stage for alarm with independent delay setting respectively are
equipped with this protection.

The setting range of reverse power setting is 0.5%~10%Pn. (Pn is rated active power of the
generator)

The range of time delay is 0.1s~600s.

Figure 3.20-1 shows logic diagram of reverse power protection.

P≤-[P_RevP_Gen] &

[En_PwrProt_Gen]
&
[TrpLog_RevP_Gen].Bit0 &
[t_Trp_RevP_Gen] Op_RevP_Gen
[EBI_PwrProt_Gen]

FD_PwrProt_Gen

Figure 3.20-1 Logic diagram of reverse power protection

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3.20.2 Sequence Tripping Reverse Power Protection


Sometimes, when overload, over-excitation or loss-of-excitation protection of generator initiate
and tripping is needed, the steam valve of turbine has to be closed firstly. Sequence tripping
reverse power protection is used for this condition. Such protection is a reverse power protection
blocked by position contact of steam valve and circuit breaker of generator. It can trip relevant
circuit breaker with a certain delay since the steam valve being closed. Its setting range is
0.5%~10% Pn.

Figure 3.20-2 shows logic diagram of sequence tripping reverse power protection.

[BI_52b_GCB] &
[BI_Valve_Turbine]

P≤-[P_SeqTrp_RevP_Gen]

[En_PwrProt_Gen]
&
[TrpLog_SeqTrp_RevP_Gen].Bit0 &
[t_SeqTrpRevP_Gen] Op_SeqTrpRevP_Gen
[EBI_PwrProt_Gen]

FD_PwrProt_Gen

Figure 3.20-2 Logic diagram of sequence tripping reverse power protection

3.20.3 Low Power Protection


One stage of low power protection is equipped for tripping. It is blocked by the binary input for
emergency shutoff generator [BI_NotUrgBrake].

The setting range of low power protection is 0.5%~10% Pn. (Pn is rated active power of the
generator)

Figure 3.20-3 shows logic diagram of sequence tripping reverse power protection.

[BI_52b_GCB] &
[BI_NotUrgBrake]

P<[P_UP_Gen]

[En_PwrProt_Gen] &

&
t_UP_Gen Op_UP_Gen
[EBI_PwrProt_Gen]

FD_PwrProt_Gen

Figure 3.20-3 Logic diagram of low power protection

Where:

FD_PwrProt_Gen: fault detector of low power protection.

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3.21 Frequency Protection


Frequency protection of generator comprises underfrequency and overfrequency protection.

3.21.1 Underfrequency Protection


When frequency is lower than setting value, underfrequency protection will operate to issue alarm
or trip if the accumulated time or once duration of under frequency operation reaches time delay.
This protection is blocked by position contact of circuit breaker and no current flag.

Three stages of underfrequency protection are equipped for PCS-985B. Stage 1 is usually
configured as accumulating frequency protection, and can be reset to zero only after erasing
reports. Stage 2 and stage 3 can be configured as continuous frequency protection.

3.21.2 Overfrequency Protection


As to overfrequency protection, two stages are equipped for PCS-985B and they will issue alarm
or trip when operates.

3.21.3 Logic Scheme

[En_Alm_UFn_Gen]

[BI_52b_CB_HVS1(2)_Tr]
&
& t Alm_UF_Gen
f<[f_UFn_Gen]

[En_FreqProt_Gen]
&
[TrpLog_UF_Gen].Bit0 &
[t_UFn_Gen] Op_UFn_Gen
[EBI_FreqProt_Gen]

FD_FreqProt_Gen

Figure 3.21-1 Logic diagram of underfrequency protection

[En_Alm_OFn_Gen]
&
f<[f_OFn_Gen] & t Alm_OF_Gen

[En_FreqProt_Gen]
&
[TrpLog_OF_Gen].Bit0
&
[EBI_FreqProt_Gen] [t_OFn_Gen] Op_OFn_Gen

FD_FreqProt_Gen

Figure 3.21-2 Logic diagram of overfrequency protection

3.22 Inadvertent Energization Protection


Inadvertent energization protection is also called unwanted closing protection is used for following

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cases:

1. In the course of generator’s hand turning (low frequency condition), if it has not been excited,
breaker closure by accident may lead to asynchronous starting of the generator. The
protection is put into use automatically with time delay t1 when two groups of voltage derived
from two independent VTs are all less than undervoltage setting and exit with time delay t2
(designed to cooperate with low-frequency blocking criterion) when the two groups of voltage
revert to normal level.

2. In the case that generator breaker is closed by accident in excited condition but frequency is
under normal level which may occur in startup-and-shutdown process. The protection is put
into use automatically with time delay t3 while low-frequency criterion is met and returns with
time delay t4 after the frequency criteria releases. Here, t4 should be set as long as to ensure
the completion of tripping course.

3. In the case that generator breaker is closed by accident in excited condition but frequency is
greater than the setting which may occur in startup-and-shutdown process. The protection is
put into use with time delay t3 and returns with time delay t4, which can be enabled or
disabled by logic setting, and is also controlled by position contact of circuit breaker. Here, t3
should coordinate with open time of circuit breaker, and t4 should be set as long as to ensure
the completion of tripping course.

Considering security of the protection, both currents from generator terminal and neutral point are
used in the logic as criteria. In addition, the current at HV side of main transformer should be
greater 0.2Ie is also used as an auxiliary criterion.

Figure 3.22-1 shows logic diagram of inadvertent energization protection.

Flg_UF_Gen &
t3 t4 ≥1
Flg_UV_Gen ≥1
t1 t2
[BI_52b_CB]
&
Flg_NoCurr_CB_Gen t3 t4

[En_CB_Ctrl_AccEnerg_Gen]

Flg_OC_Term_Gen
& &
Flg_OC_NeuP_Gen & t3 t4 Op_AccEnerg_Gen

Flg_NoCurr_CB_Tr

[En_AccEnerg_Gen] &

[EBI_AccEnerg_Gen]

FD_AccEnerg_Gen

Figure 3.22-1 Logic diagram of inadvertent energization protection

Where:

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Flg_UF_Gen is the flag indicating whether or not low frequency element of generator operates.

Flg_UV_Gen is the flag indicating whether or not under voltage element of generator operates.

Flg_OC_Term_Gen is the flag indicating whether or not overcurrent current element of generator
terminal operates.

Flg_OC_NeuP_Gen is the flag indicating whether or not overcurrent current element of generator
neutral point operates.

3.23 Breaker Flashover Protection


During process of synchronization of generator, flashover in circuit breaker is possible when
difference of phase angle betwenn bus voltage and generator voltage is around 180°. Breaker
flashover protection is provided for this fault. One phase and two phases flashover is considered
by this protection but three phase flashover are ignored. Breaker flashover protection uses the
current of breaker-side CT at HV side of main transformer.

The criterion of breaker flashover protection is:

1. Three-phase position contacts of circuit breaker are open.

2. Negative-sequence current (phase current or zero-sequence current) is greater than the


setting.

3. Excitation has been applied to generator, and the voltage at generator terminal is greater than
a fixed setting.

Phase current criterion and zero-sequence current criterion can be enabled or disabled. The first
time delay of breaker flashover protection is used to filed suppression, and the second time delay
of breaker flashover protection is used to initiate breaker failure protection.

Due to that the voltage at generator terminal is lower than the voltage at HV side of main
transformer, if there is a circuit breaker equipped with generator terminal, maximum withstanding
voltage between two sides of the circuit breaker is small. Hence, breaker flashover protection for
the circuit breaker at generator terminal is not considered.

Figure 3.23-1 shows logic diagram of breaker flashover protection.

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I0>[I_ROC_Flash_CB_HVS_Tr] &

[En_ROC_Flash_CB_HVS_Tr]

Ip>[I_OC_Flash_CB_HVS_Tr] & ≥1

[En_OC_Flash_CB_HVS_Tr]

I2>[I_NegOC_Flash_CB_HVS_Tr]
&
Flag_On_CB=0

U>Uset.fix
&
[En_AccEnerg_Gen] & t_Flash1_CB_HVS_Tr Op_Flash1_CB_HVS_Tr

[EBI_Flash_CB]
&
t_Flash2_CB_HVS_Tr Op_Flash2_CB_HVS_Tr
FD_FlashCBProt_Tr

Figure 3.23-1 Logic diagram of breaker flashover protection

Where:

Uset.fix is an internal fixed voltage setting.

FD_FlashCBProt_Tr: fault detector of breaker flashover protection.

3.24 Startup and Shutdown Protection


Protections functions that can reflect phase-to-phase fault and stator earth-fault are provided
during startup and shutdown process of generator.

For stator earth-fault, zero-sequence overvoltage protection is provided.

For phase-to-phase fault of generator, overcurrent protections of differential circuit or


low-frequency overcurrent protection is provided.

Since frequency during startup and shutdown process is usually very low, algorithm independent
of frequency is used for this protection.

Whether the protection should be blocked or not by frequency element or auxiliary contact of
circuit breaker can be determined by logic setting.

F<[f_UF_StShut_Gen] t0
&
[Op_X_StShut_Gen]

[En_StShut_Gen]
&
[TrpLog_X_StShut_Gen].Bit0 &
[t_xx_StShut_Gen] Op_X_StShut_Gen
[EBI_StShut_Gen]

FD_StShut_Gen

Figure 3.24-1 Logic diagram of generator startup and shutdown protection

Where:

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―X‖ represent one of the three protective elements, ―TrDiff‖, ―GenDiff‖ and ―StaROV‖. Three
protection elements′ diagrams are so likely that they can be expressed in a figure instead of three
for them respectively.

3.25 Overload Protection of Excitation Windings


Excitation winding overload protection is equipped to reflect average heating condition of
excitation winding. Excitation transformer current, exciter current or rotor current of generator can
be taken as criterion of this protection.

Excitation winding protection comprises definite-time and inverse-time characteristics.

3.25.1 Definite-time Excitation Winding Overload Protection


Definite-time excitation winding overload protection provides one stage for alarm purpose.

Figure 3.25-1 shows logic diagram of definite-time excitation winding overload protection.

I>[I_Alm_OvLd_RotWdg] &
[t_Alm_OvLd_RotWdg] Alm_OvLd_RotWdg
[En_OvLd_Exc]

Figure 3.25-1 Logic diagram of definite time excitation winding overload protection

3.25.2 Inverse-time Excitation Winding Overload Protection


Inverse-time excitation winding overload protection consists of three parts: low-setting initiator,
inverse-time part and high setting definite-time part. Minimum operation time delay
([tmin_InvOvLd_RotWdg]) is provided for extreme overload condition.

When current in excitation circuit reaches the low setting [Ib_InvOvLd_RotWdg], the heating
accumulation starts. When the heating accumulation reaches its setting, alarm will be issued. The
inverse time protection can simulate heating accumulation and radiation process.

Il

Ilh

Ilszd

t min tmax t
Figure 3.25-2 Operation characteristic of inverse-time excitation winding overload protection

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Where:

t min is upper-limit time delay ([tmin_InvOvLd_RotWdg])

t max is lower-limit time delay

I 1szd is pickup setting ([Ib_InvOvLd_RotWdg])

I 1h :is the upper-limit current setting

Its operation criterion is:

[( I l I jzzd)  1]  t  KLzd
2

Where:

I l is the current in excitation circuit.

I jzzd is inverse-time reference current of excitation circuit.

KL zd is setting of heat capacity factor of excitation windings.

Figure 3.25-3 shows logic diagram of inverse time excitation winding overload protection.

I>[I_InvOvLd_RotWdg] &
IDMT &
[En_OvLd_Exc ]
tmin
[TrpLog_InvOvLd_RotWdg].Bit0 & &
Op_InvOvLd_RotWdg
[EBI_Bak_Exc]

FD_OvLd_RotWdg

Figure 3.25-3 Logic diagram of inverse-time excitation winding overload protection

3.26 Excitation Transformer/Exciter Protection


3.26.1 Excitation Transformer and Exciter Differential Protection
Operation criterion of excitation transformer or exciter differential protection is:

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 I d  K bl  I r  I cdqd ( I r  nI e )

 K bl  K bl1  K blr  ( I r / I e )

 I d  K bl 2  ( I r  nI e )  b  I cdqd ( I r  nI e )
 K  ( K  K ) /(2  n )
 blr bl 2 bl 1

b  ( K bl1  K blr  n )  nI e

 I1  I 2
 I r 
2
  
I  I 1  I 2
 d

For excitation transformer: I1 and I 2 are currents of HV side and LV side respectively.

For exciter: I1 and I 2 are currents of side 1 and side 2 respectively.

The differential protection of exciter can adopt the two kinds of frequency: 50Hz and 100Hz
according the setting [fn_Exciter].

3.26.2 Excitation Transformer and Exciter Overcurrent Protection


Excitation transformer or exciter overcurrent protection includes two stages used as backup
protection. These two stages will trip the circuit breaker with configurable delay. Figure 3.26-1
shows its logic diagram.

I>[I_OCn_Exc]

[En_Bak_Exc] & &


[t_OCn_Exc] Op_OCn_Exc
[EBI_Bak_Exc]

FD_Bak_Exc

Figure 3.26-1 Logic diagram of excitation transformer or exciter overcurrent protection

3.27 Backup Protection of Step-down Transformer


3.27.1 Backup Protection for HV side of Step-down Transformer
Voltage controlled overcurrent protection for step-down transformer is equipped with PCS-985B.
This protection, consisting of 2 stages and 1 time delay per stage, is used for phase-to-phase
backup protection of step-down transformer. Of which, composite voltage element can be enabled
or disabled by configuration of logic setting.

3.27.1.1 Voltage Control Element

It is same to the voltage control element in section 3.6.1.1.

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3.27.1.2 Current Memory

It is same to the function of current memory element in section 3.6.1.2.

3.27.1.3 Influence of VT Circuit Failure on Voltage Control Element

It is same to the influence of VT circuit failure in section 3.6.1.3.

3.27.1.4 Logic Scheme

Upp<[Vpp_UV_VCE_HVS_ST1] ≥1
&
U2>[V_NegOV_VCE_HVS_ST1] ≥1
Flg_VCE_HVS_ST1
Flg_VTS

&

[Opt_VTS_Ctrl_OC_HVS_ST1]

&
≥1
[En_Mem_Curr_HVS_ST1] &
Flg_OCn_HVS_ST1

Flg_VCE_HVS_ST1 ≥1

[En_VCE_Ctrl_OCn_HVS_ST1]

[En_Bak_HVS_ST1] & &


[t_OCn_HVS_ST1] Op_OCn_HVS_ST1
[EBI_Bak_HVS_ST1]

FD_Bak_HVS_ST1

Figure 3.27-1 Logic diagram of overcurrent protection of step-down transformer (HV side)

Where:

Flg_VTS is flag indicating whether or not the VT circuit fails.

Flg_OCn_HVS_ST1 is flag indicating that stage n of overcurrent element is met.

Flg_VCE_HVS_ST1 is flag indicating whether or not voltage controlled element is met.

FD_Bak_HVS_ST1 is fault detector of overcurrent protection of HV side of step-down transformer.

(n can be 1 or 2)

Only take step-down transformer 1 as an example, and logic scheme of step-down transformer 2
is the same.

3.27.2 Backup Protection for LV side of Step-down Transformer


This protection, consisting of 2 stages and 1 time delay per stage, is used for phase-to-phase
backup protection of step-down transformer. Of which, composite voltage element can be enabled

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or disabled by configuration of logic setting.

3.27.2.1 Voltage Control Element

It is same to the voltage control element in section 3.6.1.1.

3.27.2.2 Influence of VT Circuit Failure on Voltage Control Element

It is same to the influence of VT circuit failure in section 3.6.1.3.

3.27.2.3 Logic Scheme

Upp<[Vpp_UV_VCE_Br1_ST1] ≥1
&
U2>[V_NegOV_VCE_Br1_ST1] ≥1
Flg_VCE_Br1_ST1
Flg_VTS

&

[Opt_VTS_Ctrl_OC_Br1_ST1]

Flg_OCn_Br1_ST1 &
Flg_VCE_Br1_ST1 ≥1

[En_VCE_Ctrl_OC1_Br1_ST1]

[En_Bak_Br1_ST1] & &


[t_OCn_Br1_ST1] Op_OCn_Br1_ST2
[EBI_Bak_Br1_ST1]

FD_Bak_Br1_ST2

Figure 3.27-2 Logic diagram of overcurrent protection of step-down transformer (LV side)

Where:

Flg_VTS is flag indicating whether or not the VT circuit fails.

Flg_OCn_Br1_ST1 is flag indicating that stage n of overcurrent element is met.

Flg_VCE_Br1_ST1 is flag indicating whether or not voltage controlled element is met.

FD_Bak_Br1_ST1 is fault detector of overcurrent protection of LV side of step-down transformer.

(n can be 1 or 2)

Only take branch 1 at LV side of step-down transformer 1 as an example, and other logic schemes
are the same.

3.27.3 Earth-fault Protection for LV side of Step-down Transformer


Two stages zero-sequence overcurrent protection with time delay used for tripping is equipped for
each branch at LV side of step-down transformer.

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3.27.4 Other Protection of Step-down Transformer


Overload alarm and initial cooling are equipped for backup protection of step-down transformer.
These functions can be set by logic settings. One normally open contact is used for output of initial
cooling.

Blocking OLTC (on-load tap change) is also equipped with PCS-985B for step-down transformer.

3.28 Pole Disagreement Protection


Pole disagreement protection is used for protection of HV-side circuit breaker. The fault can be
detected by auxiliary position contact of breaker combined with zero-sequence current or
negative-sequence current. Whether zero or negative sequence current is used for detection can
be configured by corresponding logic setting. Two time delays are provided for pole disagreement
protection and logics with time delay 2 can be configured to be supervised by binary input from
protection tripping contact.

1. Logic scheme of pole disagreement protection (time delay 1)

3I0> [I_ROC_PD1_HVS_Tr] &

[En_ROC_PD_HVS_Tr] ≥1 ≥1
&
[t_PD11_HVS_Tr] OP_PD11
[En_NegOC_PD_HVS_Tr]
&

I2>[I_NegOC_PD1_HVS_Tr]

[BI_PD_CB] &

[EBI_PD_CB]

&
[En_PD_CB] &

FD_PD_CB

Figure 3.28-1 Logic diagram of pole disagreement protection (time delay 1)

2. Logic scheme of pole disagreement protection (time delay 2)

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[En_ExTrp_Ctrl_PD12_HVS_Tr] ≥1

[BI_ExtTrpCtrl]

≥1

Ip>[I_OC_PD1_HVS_Tr] &

[En_OC_PD12_HVS_Tr] ≥1 &
[t_PD12_HVS_Tr] OP_PD12
3I0>[I_ROC_PD1_HVS_Tr] &

[En_ROC_PD_HVS_Tr]
≥1
I2>[I_NegOC_PD1_HVS_Tr] &

[En_NegOC_PD_HVS_Tr]

[BI_PD_CB] &
&
[EBI_PD_CB]

[En_PD_CB] &

FD_PD_CB

Figure 3.28-2 Logic diagram of pole disagreement protection (time delay 2)

3.29 Breaker Failure Protection


When there is an internal fault of the generator, the protection operates to trip. If the circuit at
generator terminal or at HV side of main transformer fails, it need to initiate breaker failure
protection and trip adjacent circuit breaker in time. Breaker failure protection uses the current from
generator terminal CT as auxiliary criterion.

The current auxiliary criterion can be phase overcurrent element or negative-sequence current
element.

Figure 3.29-1 shows logic diagram of breaker failure protection.

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[BI_52b_GCB]

[BI_ExtTrpCtrl]

I>[I_OC_BFP_GCB] &
≥1 &
[En_OC_BFP_GCB] & [t_BFP11_GCB] OP_BFP11_GCB

I2>[I_NegOC_BFP_GCB] & [t_BFP12_GCB] OP_BFP12_GCB

[En_NegOC_BFP_GCB]

[En_BFP_GCB]
&
[EBI_BFP_GCB]

FD_BFP_GCB

Figure 3.29-1 Logic diagram of breaker failure protection

3.30 Restrict Earth-fault Protection (REF) of Main Transformer


Restricted earth fault protection (REF) is also called zero-sequence differential protection in this
manual, which includes zero-sequence percentage differential protection element and
unrestrained instantaneous zero-sequence differential protection element. REF is used to protect
the main transformer with neutral point earthed with/without resistance.

3.30.1 Amplitude ratio compensation


If CTs used for REF have different ratios, then the ratio compensation is needed. Here is the
method.

K TA
K ph   Kb
K TA_max

K TA max
K b  min( ,4)
K TA b

Where:

KTA is the CT ratio at calculated side

KTA_b is the CT ratio at the base side

KTA_max is the maximum CT ratio among all side

This method take the neutral point rated secondary current as the base of calculation and all other
sides will be considered as its multiples. The ratio of the maximum CT ratio to base CT ratio must
be less than 4. If ratio of the maximum CT ratio to base CT ratio is less than 4, the multiple of the
base rated current will be taken as 1, and other side will be calculated proportionally. Thus the
maximum setting range of current ration correction coefficient Kph of each side can be up to 4.

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The currents used in the following analyze are based on the assumption that they have been
adjusted, that means the currents are the products of original current of each side and its own
adjustment coefficient (Kph).

3.30.2 Percentage Restricted Earth Fault Protection (PcntREF)


REF is used for earth fault at HV side of main transformer (wye connection). Its operation criteria
are as follows:

I0d  I0cdqd
I  K  I
 0d 0bl 0r

I0r  max{ I01 , I02 , I03 , I0n }


    
I0d  I 01  I 02  I 03  I 0n


Where:

I01 is zero-sequence current of branches A1

I02 is zero-sequence current of branches A2

I03 is zero-sequence current of branches A3

For HV side of main transformer, there is only one branch I01 which is the sum of three-phase
currents derived from backup CT at HV side of main transformer, and other branches have no
definition.

I0n is zero-sequence current on neutral point side

I0cdqd is the pick up setting of zero-sequence percentage differential protection, i.e.


[I_Pkp_PcntREF_Tr]

I0d is zero-sequence differential current

I0r is zero-sequence restraint current

K0bl is the setting of percentage restraint coefficient of zero-sequence percentage differential


protection, i.e. [Slope_PcntREF_Tr]

For the restraint coefficient, 0.5 is recommended value.

When equation above is satisfied, the percentage REF will operate. Zero-sequence differential
currents on various sides except neutral point are gained from internal calculation, and the polarity
check of zero-sequence CT on various sides is not needed.

Warning!

Before restricted earth fault protection is put into operation on site, polarity of
zero-sequence current transformers (CT) on neutral point of the side must have been
checked right by an energizing test of the side of a transformer or a test of simulating an
external fault of the side in primary system.

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3.30.3 Unrestrained Instantaneous Restricted Earth Fault Protection (UIREF)


The aim of unrestrained instantaneous REF for main transformer is to accelerate clearing the
transformer‘s inner earth fault with high fault resistance. So the element does not need any block
element, but the setting should be greater than maximum inrush current.

This protection operates to trip all breakers at all sides of main transformer when any unrestrained
zero-sequence differential current is higher than its setting [I_InstREF_Tr]. Its operation criterion
is:

I0d  [I_InstREF _Tr]

Where:

I0d is the zero-sequence differential currents

[I_InstREF_Tr] is the setting of the unrestrained instantaneous REF.

Figure 3.30-1 shows operation characteristic of REF.

I0d

Operation area of UIREF


I0Inst

Operation area of PcntREF

K0bl

I0cdqd

I0r
Ith

Figure 3.30-1 Operating characteristic of restricted earth-fault protection

Where:

I0Inst: is the setting of the unrestrained instantaneous REF, i.e. [I_InstREF_Tr]

Ith will be automatically changed according to the pickup current [I_Pkp_PcntREF_Tr] and restrict
coefficient [Slope_PcntREF_Tr].

PcntREF: means percentage restricted earth fault protection

UIREF: means unrestrained instantaneous restricted earth fault protection

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3.30.4 Influence from CT Transient Characteristics


The difference of transient characteristic and CT saturation will increase zero-sequence current in
differential scheme during external three-phase short-circuit fault. In order to eliminate this effect,
positive-sequence current restraint criterion and CT saturation criterion are used.
Positive-sequence current restraint principle can be expressed as following:

I0  β0  I1

Where:

I0 is the calculated zero-sequence current from the three-phase current of CT at HV side of main
transformer

I1 is its corresponding positive-sequence current

β 0 is a proportional coefficient

PCS-985B also adopts second harmonic component to identify the CT saturation.

3.30.5 Zero-sequence Differential Current Abnormality Alarm


When the zero-sequence differential current is greater than the setting [I_Alm_REF_Tr] for 10s,
an abnormality alarm [Alm_REF_Tr] will be issued. But REF is still in service.

3.30.6 Logic Scheme


The logic scheme of REF for HV side of main transformer is shown in the following figure.

Flg_REF_Tr
&
[EBI_REF_Tr] &
OP_REF_Tr
[En_EF_Tr]

Flg_CTsat

FD_REF_Tr

Figure 3.30-2 Logic diagram of REF

Where:

Flag_REF_Tr is the flag indicating whether or not the criterion of REF element is met.

Flag_CTsat is the internally generated flag indicating that CT is not in saturation condition.

Caution!

Before REF is put into service, CT polarity used for this element must be carefully checked
to ensure it is suited for the requirement of REF to avoid undesired tripping.

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3.31 CT Circuit Supervision


3.31.1 Three-phase Current Circuit Failure Alarm
The operation criterion is:

3I0 > 0.04 In+ 0.25×Imax

Where:

3I0 is zero-sequence current

In is secondary rated current (1A or 5A)

Imax is maximum phase current

If this criterion is met, CT circuit failure alarm will be issued with a time delay of 10s. Once the
condition reverts normal condition, the alarm will be reset with a time delay of 10s.

3.31.2 Differential Current Alarm in Differential Protection Circuit


This function is enabled only when relevant differential protection logic setting is set as enabled. If
the criterion is met, the alarm will be sent by delay 10s and corresponding differential protection
will not be blocked. When the differential current eliminates, the alarm will be reset by delay 10s.

In order to increase sensitivity of this alarm, percentage restraint differential current alarm criterion
is adopted as shown as below.

dI > di_bjzd

dI > kbj ×Ires

If the differential current reaches its threshold and reaches differential alarm level of percentage
restraint factor multiplied by restraint current, the differential current alarm will be issued.

Where:

dI is differential current

di_bjzd is threshold value of differential current alarm

kbj is percentage coefficient of differential current alarm

Ires is restrained current

3.31.3 Alarm or Blocking to Differential Protection by CT Circuit Failure


Instantaneous CT circuit failure discrimination is equipped for differential protection. Only when
related logic setting and relevant enabling binary input of protection are set ―1‖, the alarm or
blocking to instantaneous CT circuit failure discrimination will be enabled.

If an internal fault occurs, at least one of following four conditions will be present:

1. Negative-sequence voltage at any side is greater than 2V

2. Any phase current of a certain side increases after fault detector operating

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3. Maximum phase current is greater than 1.2Ie after fault detector operating

4. At least three-phase currents increases after fault detector picks up

If none of above four conditions occurs within 40ms after differential protection′s fault detectors
picks up, the protection treats it as CT circuit failure. If the logic setting [Opt_CTS_Blk_PcntDiff_xx]
is set as ―1‖, the differential protection will be blocked and alarm will be issued. If this logic setting
is set as ―0‖, the differential protection will trip and alarm will be issued simultaneously.

If the alarm is issued, the signal can be removed only when the failure is removed and the device
is reset by manual.

Before the generator is connected to power grid, the blocking and alarm to CT circuit failure will be
disabled automatically.

3.32 VT Circuit Supervision


3.32.1 VT circuit of Any Side Failure Alarm
The operation criterion is:

1. Positive-sequence voltage is smaller than 18V and any phase current is greater than 0.04In

2. Negative-sequence voltage 3U2 is in excess of 8V

If any one condition occurs, VT circuit failure alarm will be issued with a time delay of 10s, and the
alarm will be removed automatically by delay 10s when the failure is removed.

3.32.2 Voltage Valance on Generator Terminals


When two groups of VT are equipped at generator terminal, VT circuit failure can be detected by
comparing phase voltage with positive sequence voltage of these two groups of VT.

Operation criterions are:

|UAB-Uab| >5V

|UBC-Ubc| >5V

|UCA-Uca| >5V

|U1 - U1′| >3V

Where:

UAB, UBC, UCA and U1 are phase-to-phase voltage and positive sequence voltage of VT group 1.

Uab, Ubc, Uca and U1′ are phase-to-phase voltage and positive sequence voltage of VT group 2.

If any condition mentioned above occurs, VT circuit failure alarm will be issued with delay 0.2s and
the VT group used will be switched.

When only a VT fails, it will not influence the function of related protection such as
loss-of-excitation, out-of-step, overvoltage, over-excitation, reverse power, frequency, impedance
protection and overcurrent protection.

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If only one group of VT is provided at generator′s terminal, user can disable this function.

3.32.3 Three-phase Voltage Circuit Failure Supervision


Operation criterions are:

1. Positive-sequence voltage (U1) is greater than 48V

2. Calculated third harmonic zero-sequence voltage(3U0_3ω) is greater than k*U1.

k is percentage coefficient, and takes 0.2~0.5.

When the above criterions are met, corresponding alarm signal of VT circuit failure will be issued
with a time delay of 20s. The alarm signal will be removed automatically with a time delay of 20s
after the abnormality disappears.

For VT2 and other VTs, their percentage coefficient can be settable respectively and their failure
criterions are also enabled or disabled respectively.

3.33 Mechanical protection


Interfaces of mechanical protection such as thermo-technical protection, interruption of water
protection, excitation system protection and one spare mechanical protection are equipped for the
equipment. External protection equipments send those signals to PCS-985B to make the event
record and send alarm and maybe tripping command to relevant circuit breaker with delay.
Enabling binary inputs are provided for those protections.

Their setting ranges are:

Mechanical protection 1: 0s~300.00s

Mechanical protection 1: 0s~300.00s

Mechanical protection 1: 0s~300.00s

Mechanical protection 1: 0s~6000.0s

Note!

The names of four mechanical protection can be user-defined by auxiliary software.

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4.1 Overview

If hardware failure of the equipment itself is detected, protection functions of the equipment will be
blocked and equipment blocking alarm will be issued. Hardware failure includes those on RAM,
EPROM, settings, power supply, DSP and tripping coil.

When following abnormal status is detected, abnormal warning will be issued: AC voltage or
current circuit failure, persist pickup, mismatch state of pickup between CPU and DSP and alarm
of protection element.

The relay includes a number of self-monitoring functions to check the operation of its hardware
and software when it is in service. These are included so that if an error or fault occurs within the
relay‘s hardware or software, the relay is able to detect and report the problem and attempt to
resolve it by performing a re-boot. This involves the relay being out of service for a short period of
time that is indicated by the ―HEALTHY‖ LED on the faceplate of the relay being extinguished and
the watchdog contact at the rear operating. If the restart fails to resolve the problem, then the relay
will take itself permanently out of service. Again this will be indicated by the ―ALARM‖ LED and
watchdog contact. If a problem is detected by the self-monitoring functions, the relay attempts to
store a maintenance record in battery backed-up SRAM to allow the nature of the problem to be
notified to the user.

The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is
performed when the relay is booted-up, e.g. at power-on, and secondly a continuous self-checking
operation which checks the operation of the relay‘s critical functions whilst it is in service.

4.2 Startup Self-testing

The self-testing which is carried out when the relay is started takes a few seconds to complete,
during which time the relay‘s protection is unavailable. This is signaled by the ―HEALTHY‖ LED on
the front of the relay which will illuminate when the relay has passed all of the tests and entered
operation. If the testing detects a problem, the relay will remain out of service until it is manually
restored to working order.

The operations that are performed at start-up are as follows:

4.2.1 System Boot


The integrity of the flash memory is verified using a checksum before the program code and data
stored in it is copied into SRAM to be used for execution by the processor. When the copy has
been completed the data then held in SRAM is compared to that in the flash to ensure that the two
are the same and that no errors have occurred in the transfer of data from flash to SRAM. The
entry point of the software code in SRAM is then called which is the relay initialization code.

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4.2.2 Initialization Software


The initialization process includes the operations of initializing the processor registers and
interrupts, starting the watchdog timers (used by the hardware to determine whether the software
is still running), starting the real-time operating system and creating and starting the supervisor
task. In the course of the initialization process the relay checks:

1. The integrity of the battery backed-up SRAM that is used to store event, fault and disturbance
records.

2. The integrity of the flash that is used to store program.

3. The correctness of the settings that ensures relay‘s proper response to fault.

4. The operation of DSP and CPU.

5. The voltage level of the field voltage supply which is used to drive the opto-isolated inputs.

6. The operation of the LCD controller.

7. The watchdog operation.

At the conclusion of the initialization software the supervisor task begins the process of starting the
platform software.

4.2.3 Platform Software Initialization and Monitoring


In starting the platform software, the relay checks the integrity of the data held in non-volatile
memory with a checksum. The final test that is made concerns the input and output of data, the
presence and healthy condition of the input board is checked and the analog data acquisition
system is checked through sampling the reference voltage.

At the successful conclusion of all of these tests the relay is entered into service and the protection
started-up.

4.3 Continuous Self-testing

When the relay is in service, it continually checks the operation of the critical parts of its hardware
and software. The checking is carried out by the system services software and the results reported
to the platform software. The functions that are checked are as follows:

1. The flash containing all program code, setting values and language text is verified by a
checksum

2. The code and constant data held in SRAM is checked against the corresponding data in flash
to check for data corruption

3. The SRAM containing all data other than the code and constant data is verified with a
checksum

4. The level of the field voltage

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5. The integrity of the digital signal I/O data from the opto-isolated inputs and the relay contacts
is checked by the data acquisition function every time it is executed. The operation of the
analog data acquisition system is continuously checked by the acquisition function every time
it is executed, by means of sampling the reference voltages.

In the unlikely event that one of the checks detects an error within the relay‘s subsystems, the
platform software is notified and it will attempt to log a maintenance record in battery backed-up
SRAM. If the problem is of no importance (no possibility of leading to maloperation), the relay will
continue in operation. However, for problems detected in any important area the relay will initiate a
shutdown and re-boot. This will result in a period of up to 5s when the protection is unavailable, but
the complete restart of the relay including all initializations should clear most problems that could
occur. As described above, an integral part of the start-up procedure is a thorough diagnostic
self-check. If this detects the same problem that caused the relay to restart, i.e. the restart has not
cleared the problem, and then the relay will take itself permanently out of service. This is indicated
by the ―HEALTHY‖ LED on the front of the relay, which will extinguish, and the watchdog contact
that will operate.

1. Voltage transformer supervision (VTS)

See Section 3.32 for detail.

2. Current transformer supervision (CTS)

See Section 3.31 for detail.

If the alarm is issued, the alarm signal can be reset only when the failure is removed and the
equipment is reset by pressing ―RESET‖ button on panel or re-power it up.

3. Overload Alarm

On condition that the relay does not picks up, adding current in excess of the setting of
overload protection, alarm messages are displayed and ―ALARM‖ LED is lit after the timer
stage duration has elapsed.

4. Binary input status monitoring

Any status of binary input changing will be monitored.

5. Tripping output circuit monitoring

Tripping output relay driving transistor is always monitored in normal program, and blocking
message will be issued when the equipment finds abnormality of the tripping output circuit.

4.4 Alarm Messages

All the alarm messages and relevant LED affections are listed in following table.

Table 4.4-1 Alarm messages and relevant LED affections

No. Alarm Reprot HEALTHY ALARM CT ALARM VT ALARM


1 Alm_Settings_ProtBrd ●

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2 Alm_Settings_FDBrd ●
3 Alm_DSP_FDBrd ●
4 Alm_DSP_ProtBrd ●
5 Alm_InnerComm ●
6 Alm_PersistFD_ProtBrd ● ●
7 Alm_PersistFD_FDBrd ● ●
8 Alm_InconsistFD ● ●
9 Alm_Sample_DSP ●
10 Alm_BI ● ●
11 Alm_ROV_LVS_Tr ● ●
12 Alm_SwOv_VTS1_Gen ● ● ●
13 Alm_SwOv_VTS2_Gen ● ● ●
14 Alm_BlkV3rdHDiff_VTS1 ● ● ●
15 Alm_BlkIntTurn_VTS2 ● ● ●
16 Alm_VTS_HVS_Tr ● ● ●
17 Alm_VTS_Term_Gen ● ● ●
18 Alm_VTS_NP_Gen ● ● ●
19 Alm_DeltVTS1_Term_Gen ● ● ●
20 Alm_DeltVTS2_Term_Gen ● ● ●
21 Alm_Pos_GCB ● ●
22 Alm_Pos_CB_HVS1 ● ●
23 Alm_Pos_CB_HVS2 ● ●
24 Alm_VTS_LossExc_RotWdg ● ● ●
25 Alm_DPFC_IntTurn_Gen ● ●
26 Alm_Diff_GTU ● ●
27 Alm_Diff_Tr ● ●
28 Alm_REF_Tr ● ●
29 Alm_Diff_Gen ● ●
30 Alm_Diff_Exc ● ●
31 Alm_Diff_ST1 ● ●
32 Alm_Diff_ST2 ● ●
33 Alm_MR1 ● ●
34 Alm_MR2 ● ●
35 Alm_MR3 ● ●
36 Alm_MR4 ● ●
37 Alm_PwrLoss_MR ● ●
38 Alm_Inconsist_MR ● ●
39 Alm_BO_OC_Term_Gen ● ●
40 Alm_On_2PEF_RotWdg ● ●
41 Alm_Sens1PEF_RotWdg ● ●
42 Alm_1PEF_RotWdg ● ●
43 Alm_LossExc_Gen ● ●
44 Alm_OvExc_Gen ● ●

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45 Alm_OvLd_Sta ● ●
46 Alm_NegOC_Gen ● ●
47 Alm_OvLd_RotWdg ● ●
48 Alm_ROV_Sta ● ●
49 Alm_V3rdHRatio_Sta ● ●
50 Alm_V3rdHDiff_Sta ● ●
51 Alm_UF1_Gen ● ●
52 Alm_UF2_Gen ● ●
53 Alm_UF3_Gen ● ●
54 Alm_OF1_Gen ● ●
55 Alm_OF2_Gen ● ●
56 Alm_RevP_Gen ● ●
57 Alm_OvLd_Tr ● ●
58 Alm_InitCool1_Tr ● ●
59 Alm_InitCool2_Tr ● ●
60 Alm_OvExc_Tr ● ●
61 Alm_Ext_OOS_Gen ● ●
62 Alm_Int_OOS_Gen ● ●
63 Alm_Accel_OOS_Gen ● ●
64 Alm_Decel_OOS_Gen ● ●
65 Alm_OvLd_ST1 ● ●
66 Alm_InitCool_ST1 ● ●
67 Alm_BO_OC_HVS_ST1 ● ●
68 Alm_OvLd_ST2 ● ●
69 Alm_InitCool_ST2 ● ●
70 Alm_BO_OC_HVS_ST2 ● ●
71 Alm_VTS_Br1_ST1 ● ● ●
72 Alm_VTS_Br2_ST1 ● ● ●
73 Alm_VTS_Br1_ST2 ● ● ●
74 Alm_VTS_Br2_ST2 ● ● ●
75 Alm_NeuVTS_TermVT1 ● ● ●
76 Alm_NeuVTS_TermVT2 ● ● ●
77 Alm_NeuVTS_HVS_Tr ● ● ●
78 Alm_CTS_Diff_GTU ● ● ●
79 Alm_CTS_Diff_Tr ● ● ●
80 Alm_CTS_Diff_Gen ● ● ●
81 Alm_CTS_Diff_Exc ● ● ●
82 Alm_CTS_Diff_ST1 ● ● ●
83 Alm_CTS_Diff_ST2 ● ● ●
84 Alm_CTS_HVS1_Tr ● ● ●
85 Alm_CTS_HVS2_Tr ● ● ●
86 Alm_CTS_LVS_Tr ● ● ●
87 Alm_CTS_HVS_Tr ● ● ●

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88 Alm_CTS_HVS_ST1 ● ● ●
89 Alm_CTS_Br1_ST1 ● ● ●
90 Alm_CTS_Br2_ST1 ● ● ●
91 Alm_CTS_HVS_ST2 ● ● ●
92 Alm_CTS_Br1_ST2 ● ● ●
93 Alm_CTS_Br2_ST2 ● ● ●
94 Alm_CTS_Term_Gen ● ● ●
95 Alm_CTS_NP_Gen ● ● ●
96 Alm_CTS_Bak_Gen ● ● ●
97 Alm_TestMode ● ●
98 Alm_dU_Inject ● ●
99 Alm_VTS_RotWdg ● ● ●
100 Alm_PoleDisagr_CB ● ●
101 Alm_PwrLoss_Opto1 ● ●
102 Alm_PwrLoss_Opto2 ● ●
103 Alm_TrpOut_B11 ● ●
104 Alm_TrpOut_B12 ● ●
105 Alm_TrpOut_B13 ● ●
106 Alm_TrpOut_B14 ● ●
107 Alm_BoardConfig ●
108 Alm_Version ●
109 Settings_Chgd ●
110 Alm_Setting_OvRange ●
111 Alm_TimeSync ● ●

The meaning and handing suggestions of these alarm messages are listed as below.

Table 4.4-2 Alarm message meaning and handing suggestions

No. Alarm Reprot Description Handling Suggestion


Error is found during checking settings Check the settings, if the
1 Alm_Settings_ProtBrd
on protection module. settings are configured
correctly and this alarm
Error is found during checking settings signal still exists, please
2 Alm_Settings_FDBrd
on fault detector module. Inform manufacturer for
maintenance.
DSP chip on fault detector module is
3 Alm_DSP_FDBrd
damaged.
DSP chip on protection module is
4 Alm_DSP_ProtBrd Inform manufacturer for
damaged.
maintenance.
Inner communication error between
5 Alm_InnerComm protection module and fault detector
module.

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Duration of pickup of any fault detector


6 Alm_PersistFD_ProtBrd in protection module is in excess of
Check the secondary circuit
10s.
and the corresponding
Duration of pickup of any fault detector
settings.
7 Alm_PersistFD_FDBrd in fault detector module is in excess of
10s.
Mismatch of pickup of same type fault Check the metering between
8 Alm_InconsistFD detectors in protection module and protection module and fault
fault detector module. detector module.
Sample values on fault detector
Inform manufacturer for
9 Alm_Sample_DSP module or protection module are
maintenance.
abnormal.
Any one of binary input sampled Check the binary input
10 Alm_BI directly does not match with that of between protection module
reorganization of protection itself. and fault detector module.
Alarm indicating operation of ROV
11 Alm_ROV_LVS_Tr protection of LV side of main
transformer.
Alarm indicating VT1 circuit failure and
12 Alm_SwOv_VTS1_Gen
start to switch over voltage circuit.
Alarm indicating VT2 circuit failure and
13 Alm_SwOv_VTS2_Gen
start to switch over voltage circuit.
Alarm indicating VT1 circuit failure and
14 Alm_BlkV3rdHDiff_VTS1 blocking third harmonics voltage
differential protection.
Alarm indicating VT2 circuit failure and
15 Alm_BlkIntTurn_VTS2
blocking interturn protection.
Alarm indicating secondary circuit Check the metering and
16 Alm_VTS_HVS_Tr failure of VT at HV side of main secondary circuit.
transformer.
Alarm indicating secondary circuit
17 Alm_VTS_Term_Gen
failure of VT at generator terminal.
Alarm indicating secondary circuit
18 Alm_VTS_NP_Gen failure of VT at the neutral point of
generator.
Alarm indicating secondary circuit
19 Alm_DeltVTS1_Term_Gen failure at open-delta side of VT1 at
generator terminal.
Alarm indicating secondary circuit
20 Alm_DeltVTS2_Term_Gen failure at open-delta side of VT2 at
generator terminal.
Alarm indicating the position of circuit
Check the corresponding
21 Alm_Pos_GCB breaker at generator terminal is
binary input.
abnormal.

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Alarm indicating the position of circuit


22 Alm_Pos_CB_HVS1 breaker of branch 1 at HV side of
step-down transformer is abnormal.
Alarm indicating the position of circuit
23 Alm_Pos_CB_HVS2 breaker of branch 2 at HV side of
step-down transformer is abnormal.
Alarm indicating rotor voltage circuit
Check the metering and
24 Alm_VTS_LossExc_RotWdg failure which used by loss-of-excitation
secondary circuit.
protection.
Alarm indicating operation of DPFC Treat according to specific
25 Alm_DPFC_IntTurn_Gen
interturn protective element. application requirement.
Alarm indicating the differential current
26 Alm_Diff_GTU is abnormal in differential protection of
generator-transformer unit.
Alarm indicating the differential current
27 Alm_Diff_Tr is abnormal in differential protection of
main transformer.
CT secondary circuit for restricted
28 Alm_REF_Tr earth fault protection of main
transformer is abnormal.
Alarm indicating differential current of
Check the metering and
29 Alm_Diff_Gen generator is in excess of normally
secondary circuit.
endurable level.
Alarm indicating differential current of
30 Alm_Diff_Exc excitation transformer or exciter is in
excess of normally endurable level.
Alarm indicating the differential current
31 Alm_Diff_ST1 is abnormal in differential protection of
step-down transformer1.
Alarm indicating the differential current
32 Alm_Diff_ST2 is abnormal in differential protection of
step-down transformer2.
Alarm indicating operation of
33 Alm_MR1
mechanical repeater 1.
Alarm indicating operation of
34 Alm_MR2
mechanical repeater 2. Treat according to specific
Alarm indicating operation of application requirement.
35 Alm_MR3
mechanical repeater 3.
Alarm indicating operation of
36 Alm_MR4
mechanical repeater 4.
Alarm indicating power loss of
37 Alm_PwrLoss_MR Check if the power circuit of
mechanical relay.
OPT module is connected
Alarm indicating circuit of mechanical
38 Alm_Inconsist_MR correctly with DC module.
is abnormal.

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Alarm indicating operation of


overcurrent element obtained from
39 Alm_BO_OC_Term_Gen
generator terminal used for driving a
set of contact to block other circuit.
Alarm indicating 2 points earth fault
protection has been put input
40 Alm_On_2PEF_RotWdg
operation after operation of 1 point
earth fault protection of rotor.
Alarm indicating operation of sensitive
41 Alm_Sens1PEF_RotWdg stage of 1 point earth fault protective
element of rotor.
Alarm indicating operation of normal
42 Alm_1PEF_RotWdg stage of 1 point earth fault protective
element of rotor.
Alarm indicating operation of
43 Alm_LossExc_Gen
loss-of-excitation protective element.
Alarm indicating operation of over
44 Alm_OvExc_Gen
excitation protective element.
Alarm indicating operation of overload
45 Alm_OvLd_Sta
element of stator.
Alarm indicating operation of negative
Treat according to specific
46 Alm_NegOC_Gen overcurrent protective element of
application requirement.
stator.
Alarm indicating operation of overload
47 Alm_OvLd_RotWdg
protective element of rotor winding.
Alarm indicating operation of sensitive
48 Alm_ROV_Sta stage of ROV protection of stator earth
fault.
Alarm indicating operation of 3rd
49 Alm_V3rdHRatio_Sta harmonics ratio earth fault protective
element of stator.
Alarm indicating operation of 3rd
50 Alm_V3rdHDiff_Sta harmonics differential earth fault
protective element of stator.
Alarm indicating operation of stage 1
51 Alm_UF1_Gen of under frequency protective element
of generator.
Alarm indicating operation of stage 2
52 Alm_UF2_Gen of under frequency protective element
of generator.
Alarm indicating operation of stage 3
53 Alm_UF3_Gen of under frequency protective element
of generator.

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Alarm indicating operation of stage 1


54 Alm_OF1_Gen of over frequency protective element
of generator.
Alarm indicating operation of stage 2
55 Alm_OF2_Gen of over frequency protective element
of generator.
Alarm indicating operation of reverse
56 Alm_RevP_Gen
power protection.
Alarm indicating overload of main
57 Alm_OvLd_Tr
transformer.
Alarm indicating stage 1 of initial
58 Alm_InitCool1_Tr
cooling of main transformer.
Alarm indicating stage 2 of initial
59 Alm_InitCool2_Tr
cooling of main transformer.
Alarm indicating over excitation of
60 Alm_OvExc_Tr
main transformer.
Alarm indicating out-of-step of system
61 Alm_Ext_OOS_Gen occurs while its oscillation center is
outside protective zone.
Alarm indicating out-of-step of system
62 Alm_Int_OOS_Gen occurs and its oscillation center is
inside protective zone.
Alarm indicating accelerate out-of-step
63 Alm_Accel_OOS_Gen
occurs.
Alarm indicating decelerate out-of-step
64 Alm_Decel_OOS_Gen
occurs.
Alarm indicating of initial cooling of
65 Alm_OvLd_ST1
step-down transformer 1.
Alarm indicating overload of
66 Alm_InitCool_ST1
step-down transformer 1.
Alarm indicating overcurrent status at
67 Alm_BO_OC_HVS_ST1
HV side of step-down transformer 1.
Alarm indicating of initial cooling of
68 Alm_OvLd_ST2
step-down transformer 2.
Alarm indicating overload of
69 Alm_InitCool_ST2
step-down transformer 2.
Alarm indicating overcurrent status at
70 Alm_BO_OC_HVS_ST2
HV side of step-down transformer 2.
Alarm indicating secondary circuit
71 Alm_VTS_Br1_ST1 failure of VT of Branch 1 at LV side of
step-down transformer 1. Check the metering and
Alarm indicating secondary circuit secondary circuit.
72 Alm_VTS_Br2_ST1 failure of VT of Branch 2 at LV side of
step-down transformer 1.

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Alarm indicating secondary circuit


73 Alm_VTS_Br1_ST2 failure of VT of Branch 1 at LV side of
step-down transformer 2.
Alarm indicating secondary circuit
74 Alm_VTS_Br2_ST2 failure of VT of Branch 2 at LV side of
step-down transformer 2.
Alarm indicating secondary circuit
75 Alm_NeuVTS_TermVT1 abnormality of VT1 at the neutral point
of generator.
Alarm indicating secondary circuit
76 Alm_NeuVTS_TermVT2 abnormality of VT2 at the neutral point
of generator.
Alarm indicating secondary circuit
77 Alm_NeuVTS_HVS_Tr abnormality of VT at the neutral point
of HV side of transformer.
Alarm indicating secondary circuit
78 Alm_CTS_Diff_GTU failure of CT in differential protection of
generator-transformer unit.
Alarm indicating secondary circuit
79 Alm_CTS_Diff_Tr failure of CT in differential protection of
main transformer.
Alarm indicating secondary circuit
80 Alm_CTS_Diff_Gen failure of CTs used for differential
Disable the link and check
protection of generator.
the secondary circuit. After
Alarm indicating secondary circuit
clear the error, reset the
failure of CT used in differential
81 Alm_CTS_Diff_Exc relay.
protection of excitation transformer or
exciter.
Alarm indicating secondary circuit
82 Alm_CTS_Diff_ST1 failure of CT in differential protection of
step-down transformer 1.
Alarm indicating secondary circuit
83 Alm_CTS_Diff_ST2 failure of CT in differential protection of
step-down transformer 2.
Alarm indicating secondary circuit
84 Alm_CTS_HVS1_Tr failure of CT at branch 1 of HV side of
main transformer.
Alarm indicating secondary circuit
Check the metering and
85 Alm_CTS_HVS2_Tr failure of CT at branch 2 of HV side of
secondary circuit.
main transformer.
Alarm indicating secondary circuit
86 Alm_CTS_LVS_Tr failure of CT in differential protection of
step-down transformer1.

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Alarm indicating secondary circuit


87 Alm_CTS_HVS_Tr failure of CT in differential protection of
step-down transformer1.
Alarm indicating secondary circuit
88 Alm_CTS_HVS_ST1 failure of HV side of step-down
transformer 1.
Alarm indicating secondary circuit
89 Alm_CTS_Br1_ST1 failure of branch 1 at LV side of
step-down transformer 1.
Alarm indicating secondary circuit
90 Alm_CTS_Br2_ST1 failure of branch 2 at LV side of
step-down transformer 1.
Alarm indicating secondary circuit
91 Alm_CTS_HVS_ST2 failure of HV side of step-down
transformer 2.
Alarm indicating secondary circuit
92 Alm_CTS_Br1_ST2 failure of branch 1 at LV side of
step-down transformer 2.
Alarm indicating secondary circuit
93 Alm_CTS_Br2_ST2 failure of branch 2 at LV side of
step-down transformer 2.
Alarm indicating secondary circuit
94 Alm_CTS_Term_Gen abnormality of CT at generator
terminal.
Alarm indicating secondary circuit
95 Alm_CTS_NP_Gen abnormality of CT at the neutral point
of generator.
Alarm indicating secondary circuit
abnormality of CT at generator
96 Alm_CTS_Bak_Gen
terminal for backup overcurrent
protection.
No special treatment is
needed. Just wait the
The device is in the binary output test
97 Alm_TestMode completion of
mode.
communication test or binary
output test., or exit the test.
Alarm indicating the DC power supply Check the metering and
98 Alm_dU_Inject
abnormity of the rotor. secondary circuit.
Alarm indicating voltage circuit failure Check the metering and
99 Alm_VTS_RotWdg
of rotor winding. secondary circuit.
Alarm indicating the binary input of Check the binary input of
100 Alm_PoleDisagr_CB
pole disagreement is in excess of 10s. pole disagreement.

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Loss of low voltage power supply of Check if the power circuit of


101 Alm_PwrLoss_Opto1 the optical couplers for binary inputs of OPT module is connected
the BI module on B04. correctly with DC module.
Loss of high voltage power supply of Check if the power circuit of
102 Alm_PwrLoss_Opto2 the optical couplers for binary inputs of OPT module is connected
the BI module on B05. correctly with DC module.
Driving circuits of binary output relays
103 Alm_TrpOut_B11
on the B11 module are damaged.
Driving circuits of binary output relays
104 Alm_TrpOut_B12
on the B12 module are damaged. Inform manufacturer for
Driving circuits of binary output relays maintenance.
105 Alm_TrpOut_B13
on the B13 module are damaged.
Driving circuits of binary output relays
106 Alm_TrpOut_B14
on the B14 module are damaged.

Module configuration is checked


automatically during equipment
initialization, if plug-in module
configuration is not consistent to the Check the module
107 Alm_BoardConfig
design drawing of an applied-specific, configuration.
the alarm signal [Alm_BoardConfig]
will be issued with the equipment
being blocked.

108 Alm_Version Device version abnormality alarm. Check the software version.
No special treatment is
The relay is in the proceeding of
109 Settings_Chgd needed. Just wait the
setting parameters.
completion of the process.
Please re-configure setting
values according to the
range described in the
instruction manual, then
110 Alm_Setting_OvRange Setting values are out of range. reboot the equipment and
the alarm message will
disappear and the
equipment will restore to
normal operation state.

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4 Supervision

Step1: check whether the


selected clock
synchronization mode
matches the clock
synchronization source;

Step 2: check whether the


wiring connection between
the equipment and the clock
synchronization source is
correct

Step 3: check whether the


Time synchronization abnormality setting for selecting clock
111 Alm_TimeSync
alarm. synchronization (i.e.
[Opt_TimeSyn]) is set
correctly. If there is no clock
synchronization, please set
the setting [Opt_TimeSyn]
as ‖No TimeSync‖.

After the abnormality is


removed, the ―ALARM‖ LED
will be extinguished and the
corresponding alarm
message will disappear and
the equipment will restore to
normal operation state.

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5 Measurement and Recording

5 Measurement and Recording

5.1 Metering

The relay produces a variety of both directly and calculated power system quantities. These
measurement values are updated on a per half second basis and can be viewed in the menu
―VALUES‖ of the relay or via relay communication.

This relay is able to measure and display the following quantities as summarized:

5.1.1 Measured Voltages and Currents


The relay produces both phase-to-ground and phase-to-phase voltage and current values. They
are produced directly from the DFT (Discrete Fourier Transform) used by the relay protection
functions and present both magnitude and phase angle measurement.

5.1.2 Sequence Voltages and Currents


Sequence quantities are produced by the relay from the measured Fourier values; these are
displayed as magnitude and phase angle values.

5.1.3 RMS of Voltages and Currents


Rms. phase voltage and current values are calculated by the relay using the sum of the samples
squared over a cycle of sampled data.

5.1.4 Differential Current and Relevant Quantities


Differential current and restrained current calculated in differential protection is displayed to user
for monitoring the correctness of operation or testing of the differential protection.

5.1.5 Phase Angles


Calculated phase angles are also displayed on LCD to help user to check the correctness of CT or
VT circuit.

5.1.6 Measurement Display Quantities

Here are ―VALUES‖ available in the relay for viewing of measurement quantities. All the
measurement quantities can be divided into CPU quantities or DSP quantities by their origin where
they are derived. These can also be viewed with PCSPC (see PCSPC User Manual).

5.1.7 All Metering Data


The quantities listed in following tables are to be displayed on LCD for PCS-985B, but for a certain
application, some of these quantities may be eliminated due of the scheme user required, so
please look up the devices on site for actual quantities displayed.

 Values of generator-transformer unit metering in CPU and MON

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5 Measurement and Recording

Phase A, B and C of per unit value of generator-transformer unit (GTU)


Id_Diff_GTU
differential current.
Ir_Diff_GTU Phase A, B and C of per unit value of GTU restraint current.
Icr_HVS1_GTU Corrected current of phase A, B and C at HV1 side of GTU.
Icr_HVS2_GTU Corrected current of phase A, B and C at HV2 side of GTU.
Icr_Gen_GTU Corrected current of phase A, B and C at generator side of GTU.
Icr_ST1_GTU Corrected current of phase A, B and C of ST1.
Icr_ST2_GTU Corrected current of phase A, B and C of ST2.

 Differential currents and related values in transformer metering in CPU and MON

Ie Secondary calculated rated current of generator.


Id_Diff_Tr Phase A, B and C of per unit value of transformer differential current.
Ir_Diff_Tr Phase A, B and C of per unit value of transformer restraint current.
Icr_HVS1_Tr Corrected current of phase A, B and C at branch1 of HV side of transformer.
Icr_HVS2_Tr Corrected current of phase A, B and C at branch2 of HV side of transformer.
Icr_LVS_Tr Corrected current of phase A, B and C at LV side of transformer.
Corrected current of phase A, B and C at HV side of step-down transformer1 for
Icr_ST1_Tr
differential protection of main transformer.
Corrected current of phase A, B and C at HV side of step-down transformer2 for
Icr_ST2_Tr
differential protection of main transformer.

 Currents in main transformer metering in CPU and MON

I_HVS1_Tr Currents of phase A, B and C of branch 1 at HV side of transformer.


I1_HVS1_Tr Positive sequence currents of branch 1 at HV side of transformer.
I2_HVS1_Tr Negative sequence currents of branch 1 at HV side of transformer.
I0_HVS1_Tr Zero sequence currents of branch 1 at HV side of transformer.
I_HVS2_Tr Currents of phase A, B and C of branch 2 at HV side of transformer.
I1_HVS2_Tr Positive sequence currents of branch 2 at HV side of transformer.
I2_HVS2_Tr Negative sequence currents of branch 2 at HV side of transformer.
I0_HVS2_Tr Zero sequence currents of branch 2 at HV side of transformer.
I_Bak_HVS_Tr Current sum of phase A, B and C of branch 1 and 2 at HV side of transformer.
I1_Bak_HVS_Tr Positive sequence current at HV side of transformer.
I2_Bak_HVS_Tr Negative sequence current at HV side of transformer.
I0_Bak_HVS_Tr Zero sequence current at HV side of transformer.
I0_NP_HVS_Tr Zero sequence current of neutral point at HV side of transformer.
I0_Gap_HVS_Tr Zero sequence current of GAP at HV side of transformer.
I_LVS_Tr Currents of phase A, B and C at LV side of transformer.
I1_LVS_Tr Positive sequence currents of at LV side of transformer.
I2_LVS_Tr Negative sequence currents of at LV side of transformer.
I0_LVS_Tr Zero sequence currents of at LV side of transformer.

 Voltages at HV side of main transformer metering in CPU and MON

U_HVS_Tr Phase voltages at HV side of transformer.

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5 Measurement and Recording

Upp_HVS_Tr Phase to phase voltages at HV side of transformer.


U1_HVS_Tr Positive sequence voltage at HV side of transformer.
U2_HVS_Tr Negative sequence voltage at HV side of transformer.
U0_HVS_Tr Zero sequence voltage at HV side of transformer.
U0_DeltVT_HVS_Tr Zero sequence voltage of delta VT at HV side of transformer.
U0_DeltVT_LVS_Tr Zero sequence voltage of delta VT at LV side of transformer.
U/F_OvExc_Tr Calculated ratio between voltage and frequency of transformer.

 Differential currents in step-down transformer A in CPU and MON

Phase A, B and C of per unit value of step-down transformer1 (ST1) differential


Id_Diff_ST1
current.
Ir_Diff_ST1 Phase A, B and C of per unit value of ST1 restraint current.
Icr_HVS_ST1 Corrected current of phase A, B and C at HV side of ST1
Corrected current of phase A, B and C at branch 1 of LV side of step-down
Icr_Br1_ST1
transformer.
Corrected current of phase A, B and C at branch 2 of LV side of step-down
Icr_Br2_ST1
transformer.

 Currents and voltages of ST1 metering in CPU and MON

I_CT_HVS_ST1 Currents of CT at HV side of ST1.


I1_CT_HVS_ST1 Positive sequence currents of CT at HV side of ST1.
I2_CT_HVS_ST1 Negative sequence currents of CT at HV side of ST1.
I0_CT_HVS_ST1 Zero sequence currents of CT at HV side of ST1.
I_CT#_HVS_ST1 Currents of CT at HV side of ST1 for main transformer differential protection.
Positive sequence currents of CT at HV side of ST1 for main transformer
I1_CT#_HVS_ST1
differential protection.
Negative sequence currents of CT at HV side of ST1 for main transformer
I2_CT#_HVS_ST1
differential protection.
Zero sequence currents of CT at HV side of ST1 for main transformer differential
I0_CT#_HVS_ST1
protection.
I_Br1_ST1 Currents of Br1 side of ST1.
I1_Br1_ST1 Positive sequence current of Br1 side of ST1.
I2_Br1_ST1 Negative sequence current of Br1 side of ST1.
I0_Br1_ST1 Zero sequence current of Br1 side of ST1.
I0_NP_Br1_ST1 Zero sequence current of neutral point of Br1 side of ST1.
Upp_Br1_ST1 Voltages at Br1 side of ST1.
U1_Br1_ST1 Positive sequence voltage at Br1 side of ST1.
U2_Br1_ST1 Negative sequence voltage at Br1 side of ST1.
I_Br2_ST1 Currents of Br2 side of ST1.
I1_Br2_ST1 Positive sequence current of Br2 side of ST1.
I2_Br2_ST1 Negative sequence current of Br2 side of ST1.
I0_Br2_ST1 Zero sequence current of Br2 side of ST1.
I0_NP_Br2_ST1 Zero sequence current of neutral point of Br2 side of ST1.

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Upp_Br2_ST1 Voltages at Br2 side of ST1.


U1_Br2_ST1 Positive sequence voltage at Br2 side of ST1.
U2_Br2_ST1 Negative sequence voltage at Br2 side of ST1.

 Differential currents in step-down transformer B in CPU and MON

Phase A, B and C of per unit value of step-down transformer1 (ST2) differential


Id_Diff_ST2
current.
Ir_Diff_ST2 Phase A, B and C of per unit value of ST2 restraint current.
Icr_HVS_ST2 Corrected current of phase A, B and C at HV side of ST2
Corrected current of phase A, B and C at branch 1 of LV side of step-down
Icr_Br1_ST2
transformer.
Corrected current of phase A, B and C at branch 2 of LV side of step-down
Icr_Br2_ST2
transformer.

 Currents and voltages of ST2 metering in CPU and MON

I_CT_HVS_ST2 Currents of CT at HV side of ST2.


I1_CT_HVS_ST2 Positive sequence currents of CT at HV side of ST2.
I2_CT_HVS_ST2 Negative sequence currents of CT at HV side of ST2.
I0_CT_HVS_ST2 Zero sequence currents of CT at HV side of ST2.
I_CT#_HVS_ST2 Currents of CT at HV side of ST2 for main transformer differential protection.
Positive sequence currents of CT at HV side of ST2 for main transformer
I1_CT#_HVS_ST2
differential protection.
Negative sequence currents of CT at HV side of ST2 for main transformer
I2_CT#_HVS_ST2
differential protection.
Zero sequence currents of CT at HV side of ST2 for main transformer differential
I0_CT#_HVS_ST2
protection.
I_Br1_ST2 Currents of Br1 side of ST2.
I1_Br1_ST2 Positive sequence current of Br1 side of ST2.
I2_Br1_ST2 Negative sequence current of Br1 side of ST2.
I0_Br1_ST2 Zero sequence current of Br1 side of ST2.
I0_NP_Br1_ST2 Zero sequence current of neutral point of Br1 side of ST2.
Upp_Br1_ST2 Voltages at Br1 side of ST2.
U1_Br1_ST2 Positive sequence voltage at Br1 side of ST2.
U2_Br1_ST2 Negative sequence voltage at Br1 side of ST2.
I_Br2_ST2 Currents of Br2 side of ST2.
I1_Br2_ST2 Positive sequence current of Br2 side of ST2.
I2_Br2_ST2 Negative sequence current of Br2 side of ST2.
I0_Br2_ST2 Zero sequence current of Br2 side of ST2.
I0_NP_Br2_ST2 Zero sequence current of neutral point of Br2 side of ST2.
Upp_Br2_ST2 Voltages at Br2 side of ST2.
U1_Br2_ST2 Positive sequence voltage at Br2 side of ST2.
U2_Br2_ST2 Negative sequence voltage at Br2 side of ST2.

 Differential currents in generator metering in CPU and MON

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Id_Diff_Gen Phase A, B and C of per unit value of generator differential current.


Ir_Diff_Gen Phase A, B and C of per unit value of generator restraint current.
I_Term_Gen Phase A, B and C of current derived from CT at generator‘ terminal.
I1_Term_Gen Positive sequence current of generator terminal.
I2_Term_Gen Negative sequence current of generator terminal.
I0_Term_Gen Calculated zero sequence current of generator terminal.
I_NP_Gen Phase A, B and C of current derived from CT at generator‘ neutral point.
I1_NP_Gen Positive sequence current of generator neutral point.
I2_NP_Gen Negative sequence current of generator neutral point.
I0_NP_Gen Calculated zero sequence current of generator neutral point.
I_Bak_Gen Phase A, B and C of current obtained from backup CT at generator‘ terminal.
I1_Bak_Gen Positive sequence current of backup CT.
I2_Bak_Gen Negative sequence current of backup CT.
I0_Bak_Gen Calculated zero sequence current of backup CT.

 Transverse differential currents of generator in CPU and MON (Optional)

Id_TrvDiff_Gen Transverse differential current of generator.


Id_3rdH_TrvDiff_Gen 3rd harmonics component of transverse differential current.

 Voltages of generator metering in CPU and MON

U_VT1_Term Phase A, B and C of voltage derived from VT1 at the generator‘s terminal.
U1_VT1_Term Calculated positive sequence voltage of VT1.
U2_VT1_Term Calculated negative sequence voltage of VT1.
U0_VT1_Term Calculated zero sequence voltage of VT1.
U_VT2_Term Phase A, B and C of voltage derived from VT2 at the generator‘s terminal.
U1_VT2_Term Calculated positive sequence voltage of VT2.
U2_VT2_Term Calculated negative sequence voltage of VT2.
U0_VT2_Term Calculated zero sequence voltage of VT2.
Upp_VT1_Term Phase-to-phase voltage of VT1—Uab, Ubc, Uca.
Upp_VT2_Term Phase-to-phase voltage of VT2—Uab, Ubc, Uca.
Zero sequence voltage derived from open-delta side of VT1 at the generator‘s
U0_DeltVT1_Term
terminal.
U0_NP_Gen Zero sequence voltage derived from VT at the neutral point of generator.
U0_3rdH_VT1_Term Calculated 3rd harmonics of VT1 at the generator‘s terminal.
U0_3rdH_NP_Gen Calculated 3rd harmonics of VT at the neutral point of generator.
3rd harmonics differential voltage between the terminal and the neutral point of
Ud_3rdH_Sta
generator.
U0_Longl_Gen Longitude zero sequence voltage of generator.
U0_3rdH_Longl_Gen 3rd harmonics voltage in longitude zero voltage.

 Misc metering quantities of generator in CPU and MON

P_Gen Active power of generator.


Q_Gen Reactive power of generator.

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Accu_InvOvLd_Sta Accumulation of thermal due to overload of stator.


Accumulation of thermal due to negative sequence current through stator result
Accu_InvNegOC_Gen
from interaction between rotor and stator.
U/F_OvExc_Gen Calculated ratio of per unit values of voltage and frequency.
Accu_InvOvExc_Gen Accumulation of thermal due to overexcitation of generator.
f_Gen Real time calculated frequency of generator.
Accumulation of underfrequency condition time of generator to decide
Accu_UF1_Gen
operation of state 1 of underfrequency protection.
Accumulation of underfrequency condition time of generator to decide
Accu_UF2_Gen
operation of state 1 of underfrequency protection.
Positive sequence voltage of 2nd harmonics voltage of stator derived from VT1
U1_2ndH_VT1_Term_Gen
at the generator‘s terminal.
Negative sequence voltage of 2nd harmonics voltage of stator derived from
U2_2ndH_VT1_Term_Gen
VT1 at the generator‘s terminal.
U_RotWdg Voltage of positive pole of rotor to negative pole.
Rg_RotWdg Calculated grounded resistance of rotor.
Location_EF_RotWdg Location of earth fault of rotor winding of generator.
I_RotWdg Excitation current through rotor winding.
I_Exc Alternative excitation current on the rectifier‘s AC side
Accu_InvOvld_RotWdg Accumulation of thermal of rotor winding.

 Differential currents in excitation metering in CPU and MON

Id_Diff_Exc Phase A, B and C of differential current of excitation transformer or exciter.


Ir_Diff_Exc Phase A, B and C of restraint current of excitation transformer or exciter.
Phase A, B and C of corrected current on the high voltage side of excitation
Icr_S1_Exc
transformer or terminal side of exciter (Side 1).
Phase A, B and C of corrected current on the low voltage side of excitation
Icr_S2_Exc
transformer or neutral point side of exciter (Side 2).

 AC metering in excitation metering in CPU and MON (Optional)

I_S1_Exc Phase A, B and C current on side 1 of excitation transformer or exciter.


I1_S1_Exc Positive sequence current of side 1 of excitation transformer or exciter.
I2_S1_Exc Negative sequence current of side 1 of excitation transformer or exciter.
I0_S1_Exc Zero sequence current of side 1 of excitation transformer or exciter.
I_S2_Exc Phase A, B and C current on side 2 of excitation transformer or exciter.
I1_S2_Exc Positive sequence current of side 2 of excitation transformer or exciter.
I2_S2_Exc Negative sequence current of side 2 of excitation transformer or exciter.
I0_S2_Exc Zero sequence current of side 2 of excitation transformer or exciter.

 Phase angles of main transformer metering

Phase angle between same-phase currents of HVS of main transformer and


φi_HVS_Tr&NP_Gen
neutral point of Generator.
φi_ST1&NP_Gen Phase angle between same-phase currents of HVS of step-down transformer 1

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and neutral point of generator.


Phase angle between same-phase currents of HVS of step-down transformer 2
φi_ST2&NP_Gen
and neutral point of generator.
Phase angle between same-phase currents between HVS1 of main transformer
φi_HVS1_Tr&Term_G
and terminal of generator.
Phase angle between same-phase currents between HVS2 of main transformer
φi_HVS2_Tr&Term_G
and terminal of generator.
Phase angle between same-phase currents of HVS of step-down transformer 1
φi_ST1&Term_Gen
and terminal of generator.
Phase angle between same-phase currents of HVS of step-down transformer 2
φi_ST2&Term_Gen
and terminal of generator.
Phase angle between phase A and B, B and C, C and A of currents of HVS1 side
φipp_HVS1_Tr
of main transformer.
Phase angle between phase A and B, B and C, C and A of currents of HVS2 side
φipp_HVS2_Tr
of main transformer.
Phase angle between phase A and B, B and C, C and A of currents obtained from
φipp_Bak_HVS_Tr
backup CT of HVS side of main transformer.
Phase angle between phase A and B, B and C, C and A of currents of LVS side of
φipp_LVS_Tr
main transformer.
Phase angle between phase A and B, B and C, C and A of voltages at HVS side
φvpp_Tr
of main transformer.
Phase angle between same-phase voltages and currents of HVS side of main
φvi_Tr
transformer.
Φvi0_Tr Phase angle between zero sequence voltage and current of main transformer.
Phase angle between same-phase voltages of HVS side of main transformer and
Φv_VT_Tr&VT1_Gen
generator terminal.

 Phase angles of step-down transformer1 metering

Phase angle between phase A and B, B and C, C and A of current derived from
φipp_CT_HVS_ST1
CT at HV side of step-down transformer1.
Phase angle between phase A and B, B and C, C and A of currents of Br1 side of
φipp_Br1_ST1
step-down transformer1.
Phase angle between phase A and B, B and C, C and A of currents of Br2 side of
φipp_Br2_ST1
step-down transformer1.
Phase angle between phase A and B, B and C, C and A of voltages of Br1 side of
φvpp_Br1_ST1
step-down transformer1.
Phase angle between phase A and B, B and C, C and A of voltages of Br2 side of
φvpp_Br2_ST1
step-down transformer1.

 Phase angles of step-down transformer2 metering

Phase angle between phase A and B, B and C, C and A of current derived from
φipp_CT_HVS_ST2
CT at HV side of step-down transformer2.
φipp_Br1_ST2 Phase angle between phase A and B, B and C, C and A of currents of Br1 side of

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step-down transformer2.
Phase angle between phase A and B, B and C, C and A of currents of Br2 side of
φipp_Br2_ST2
step-down transformer2.
Phase angle between phase A and B, B and C, C and A of voltages of Br1 side of
φvpp_Br1_ST2
step-down transformer2.
Phase angle between phase A and B, B and C, C and A of voltages of Br2 side of
φvpp_Br2_ST2
step-down transformer2.

 Phase angles of generator metering

Phase angle between same-phase currents derived from CT at generator‘s


φ_Term&NP_Gen
terminal and at generator‘s neutral point.
Phase angle between phase A and B, B and C, C and A of current derived from
φipp_Term_Gen
CT at generator‘s terminal.
Phase angle between phase A and B, B and C, C and A of current derived from
φipp_NP_Gen
CT at generator‘s neutral point.
Phase angle between phase A and B, B and C, C and A of voltage derived from
φvpp_VT1_Term_Gen
VT1 at generator‘s terminal.
Phase angle between phase A and B, B and C, C and A of voltage derived from
φvpp_VT2_Term_Gen
VT2 at generator‘s terminal.
Phase angle between same-phase voltage derived from VT1 and VT2 at
φv_VT1&VT2_Gen
generator‘s terminal.
Phase angle between phase A and B, B and C, C and A of 3rd harmonics voltage
φ_V3rdH_Gen
derived from VT1 at generator‘s terminal.
φvi_Term_Gen Phase angle between same-phase voltage and current of generator‘s terminal.

 Phase angle of excitation metering

Phase angle between same-phase currents derived from CT at side 1 and side 2
φi_S1&S2_Exc
of excitation transformer or exciter.
Phase angle between phase A and B, B and C, C and A of currents derived from
φipp_S1_Exc
CT at side 1 of excitation transformer or exciter.
Phase angle between phase A and B, B and C, C and A of currents derived from
φipp_S2_Exc
CT at side 2 of excitation transformer or exciter.

5.2 Signaling

Signals here mean changes of binary inputs. All these signals can be displayed on LCD, locally
printed or sent to automation system of substation via communication channel.

 Enabling binary inputs of transformer

EBI_Diff_GTU Enabling binary input of differential protection of generator-transformer unit.


EBI_Diff_Tr Enable binary input of differential protection of transformer.
EBI_PPF_Tr Enabling binary input of phase-to-phase backup protection of transformer.
EBI_EF_Tr Enabling binary input of earth fault protection of transformer.

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EBI_EF_Gap_Tr Enabling binary input of gap zero-sequence protection of main transformer.

 Enabling binary inputs of generator

EBI_Diff_Gen Enabling binary input of differential protection of generator.


EBI_PPF_Gen Enabling binary input of phase-to-phase backup protection of generator.
EBI_IntTurn_Gen Enabling binary input of interturn protection of generator.
EBI_ROV_Sta Enabling binary input of zero sequence overvoltage protection of stator.
EBI_V3rdH_Sta Enabling binary input of 3rd harmonics voltage protection of generator.
EBI_EF_RotWdg Enabling binary input of earth fault protection of rotor.
EBI_OvLd_Sta Enabling binary input of overload protection of stator.
EBI_NegOC_Gen Enabling binary input of negative overcurrent protection of stator.
EBI_LossExc_Gen Enabling binary input of loss-of-excitation protection of generator.
EBI_OOS_Gen Enabling binary input of out-of-step protection of generator.
EBI_VoltProt_Gen Enabling binary input of over-voltage and under-voltage protection of generator.
EBI_OvExc_GTU Enabling binary input of over-excitation protection of generator- transformer unit.
EBI_PwrProt_Gen Enabling binary input of power protection of generator.
Enabling binary input of over-frequency and under-frequency protection of
EBI_FreqProt_Gen
generator.
EBI_AccEnerg_Gen Enabling binary input of accidental energization protection of generator.
EBI_StShut_Gen Enabling binary input of startup and shutdown protection of generator.

 Enabling binary inputs of excitation and step-down transformer protection

EBI_Diff_ST1 Enabling binary input of differential protection of step-down transformer1.


EBI_Bak_HVS_ST1 Enabling binary input of backup protection of HV side of step-down transformer1.
Enabling binary input of backup protection of branch 1 of LV side of step-down
EBI_Bak_Br1_ST1
transformer1.
Enabling binary input of backup protection of branch 2 of LV side of step-down
EBI_Bak_Br2_ST1
transformer1.
EBI_Diff_ST2 Enabling binary input of differential protection of step-down transformer2.
EBI_Bak_HVS_ST2 Enabling binary input of backup protection of HV side of step-down transformer2.
Enabling binary input of backup protection of branch 1 of LV side of step-down
EBI_Bak_Br1_ST2
transformer2.
Enabling binary input of backup protection of branch 2 of LV side of step-down
EBI_Bak_Br2_ST2
transformer2.
EBI_Diff_Exc Enabling binary input of differential protection of excitation transformer or exciter.
EBI_Bak_Exc Enabling binary input of backup protection of excitation transformer or exciter.
EBI_Reserved Reserved binary input for protection function enabling

 Binary inputs of mechanical protection

Enabling binary input of mechanical protection to allow mechanical repeater x to


EBI_Trp_MechRly x
initial tripping.
BI_MechRly x Binary input indicating operation of mechanical repeater x.

 Auxiliary binary input

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Binary input of auxiliary contact of close position of circuit breaker at generator‘s


BI_52b_GCB
terminal.
Binary input of auxiliary contact of close position of circuit breaker at branch 1 of
BI_52b_CB_HVS1_Tr
HV side of transformer.
Binary input of auxiliary contact of close position of circuit breaker at branch 2 of
BI_52b_CB_HVS2_Tr
HV side of transformer.
BI_Valve_Turbine Binary input indicating the valve of steam turbine is in close position.
BI_Reserved Reserved binary input
Binary input indicating the generator is wording in synchronization condenser
BI_SyncCondenser
condition.
BI_Reserved1 Reserved binary input
BI_Reserved2 Reserved binary input
BI_Reserved3 Reserved binary input
Binary input indicating some binary input circuits (6B21 and 6B22) are working in
BI_Pwr_Superv
good condition.

 Fault detector flag generated internal by PROT

Internally generated binary input indicating operation of fault detector of


FD_DiffProt_GTU
differential protection of generator-transformer unit.
Internally generated binary input indicating operation of fault detector of
FD_IntTurn_Gen
generator interturn protection.
Internally generated binary input indicating operation of fault detector of
FD_NegOC_Gen
generator negative-sequence overcurrent protection.
Internally generated binary input indicating operation of phase-to-phase fault
FD_PPF_Gen
protection of generator.
Internally generated binary input indicating operation of differential protection of
FD_Diff_Gen
generator.
Internally generated binary input indicating operation of fault detector of earth
FD_EF_RotWdg
fault protection of rotor.
Internally generated binary input indicating operation of fault detector of
FD_InvOvLd_RotWdg
inverse-time overload protection of rotor.
Internally generated binary input indicating operation of backup protection of
FD_Bak_Br1_ST1
branch 1 at LV side of step-down transformer 1.
Internally generated binary input indicating operation of backup protection of
FD_Bak_Br2_ST1
branch 2 at LV side of step-down transformer 1.
Internally generated binary input indicating operation of differential protection of
FD_Diff_ST1
step-down transformer 1.
Internally generated binary input indicating operation of backup protection at HV
FD_Bak_HVS_ST1
side of step-down transformer 1.
Internally generated binary input indicating operation of backup protection of
FD_Bak_Br1_ST2
branch 1 at LV side of step-down transformer 2.
Internally generated binary input indicating operation of backup protection of
FD_Bak_Br2_ST2
branch 2 at LV side of step-down transformer 2.

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Internally generated binary input indicating operation of differential protection of


FD_Diff_ST2
step-down transformer 2.
Internally generated binary input indicating operation of backup protection at HV
FD_Bak_HVS_ST2
side of step-down transformer 2.
Internally generated binary input indicating operation of fault detector of earth
FD_StaEF_Gen
fault protection of stator.
Internally generated binary input indicating operation of fault detector of overload
FD_StaOvLd_Gen
protection of stator.
Internally generated binary input indicating operation of fault detector of
FD_Diff_Tr
differential protection of transformer.
Internally generated binary input indicating operation of fault detector of
FD_EF_Tr
earth-fault protection of main transformer.
Internally generated binary input indicating operation of fault detector of
FD_OvExct_Tr
overexcitation protection of main transformer.
Internally generated binary input indicating operation of fault detector of
FD_PPF_Tr
phase-to-phase fault protection of main transformer.
Internally generated binary input indicating operation of fault detector of
FD_REF_Tr
restricted earth-fault protection of main transformer.
Internally generated binary input indicating operation of fault detector of
FD_AccEnerg_Gen
accidental energization protection of generator.
Internally generated binary input indicating operation of fault detector of backup
FD_Bak_Exc
protection of excitation transformer.
Internally generated binary input indicating operation of fault detector of
FD_Diff_Exc
differential protection of excitation transformer.
Internally generated binary input indicating operation of fault detector of pole
FD_PD_HVS_Tr
discrepancy protection at HV side of main transformer.
Internally generated binary input indicating operation of fault detector of breaker
FD_BFPGCBProt
failure protection of generator terminal.
Internally generated binary input indicating operation of fault detector of voltage
FD_VoltProt_Gen
protection of generator.
Internally generated binary input indicating operation of fault detector of
FD_LossExc_Gen
loss-of-excitation protection of generator.
Internally generated binary input indicating operation of fault detector of
FD_Freq_Gen
frequency protection of generator.
Internally generated binary input indicating operation of fault detector of
FD_OOS_Gen
out-of-step protection of generator.
Internally generated binary input indicating operation of fault detector of
FD_OvExc_Gen
generator overexcitation protection.
Internally generated binary input indicating operation of fault detector of power
FD_PwrProt_Gen
protection of generator.
Internally generated binary input indicating operation of fault detector of startup
FD_StShut_Gen
and shutdown protection of generator.
Internally generated binary input indicating operation of fault detector of
FD_MechRly
mechanical protection of excitation transformer.

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 Other Binary Inputs

BI_Pwr_MechRly Binary input indicating the status of power supply for mechanical protection
BI_Pwr_Opto Binary input indicating the status of power supply for optical isolators
BI_Print Binary input used to initiate printer
BI_Pulse_GPS Binary input of GPS clock synchronous pulse
BI_RstTarg Binary input of signal reset

5.3 Event and Fault Recorder

5.3.1 Introduction
The PCS-985B is equipped with integral measurements, event, fault and disturbance recording
facilities suitable for analysis of complex system disturbances. The relay is flexible enough to allow
for the programming of these facilities to specific user application requirements and is discussed
below.

5.3.2 Event & Fault Records


The relay records and time tags up to 32 events and stores them in non-volatile (battery backed up)
memory. This enables the system operator to establish the sequence of events that occurred
within the relay following a particular power system condition, switching sequence etc. When the
available space is exhausted, the oldest event is automatically overwritten by the new one.

The real time clock within the relay provides the time tag to each event, to a resolution of 1ms. The
event records are available for viewing either via the front plate LCD or remotely, via the
communications ports (courier and MODBUS versions only).

Local viewing on the LCD is achieved in the menu column entitled ―REPORT‖. This column allows
viewing of event and fault records and is shown by setting sequence No. of the event or fault
report by user. Refer to section 8 for details of operation method.

5.3.3 Type of Event


An event may be a change of state of a control input or output relay, an alarm condition and
operation reports of protection etc.

5.3.4 State Change of Binary Inputs


If one or more of the opto inputs has changed state since the last time that the protection algorithm
ran, the new status is logged as an event.

Please see Section 5.2 for details about the binary input signals.

5.3.5 Relay Alarm Signals


Any alarm signal generated by the relays will also be logged as individual events.

Please see Section 4.4 for details about the alarm signals.

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5.3.6 Protection Element


Any operation of protection elements, (either a pickup or a trip condition) will be logged as an
event record, consisting of a text string indicating the operated element and an event sequence
number. Again, this number is intended not only for use by the event extraction software, such as
PCSPC, but also for the user.

All the protection element operation reports are listed as below. Please see Chapter 3 for details
about these operation reports.

Table 5.3-1 List of the protection elements

No. Protection Element Description


1 FD_Prot The fault detector element
Operation of instantaneous unrestrained differential protection of
2 Op_InstDiff_GTU
generator-transformer unit
Operation of percentage differential protection of generator-transformer
3 Op_PcntDiff_GTU
unit
Operation of instantaneous unrestrained differential protection of main
4 Op_InstDiff_Tr
transformer
5 Op_PcntDiff_Tr Operation of percentage differential protection of main transformer
6 Op_DPFC_Diff_Tr Operation of DPFC percentage differential protection of main transformer
Operation of instantaneous restricted earth fault protection of main
7 Op_InstREF_Tr
transformer
Operation of percentage restricted earth fault protection of main
8 Op_PcntREF_Tr
transformer
Operation of stage 2 of overcurrent protection at HV side of main
9 Op_OC1_Tr
transformer
Operation of stage 2 of overcurrent protection at HV side of main
10 Op_OC2_Tr
transformer
Operation of stage 1 of phase-to-phase impedance protection at HV side of
11 Op_Z1_Tr
main transformer
Operation of stage 2 of phase-to-phase impedance protection at HV side of
12 Op_Z2_Tr
main transformer
Operation of stage 1 with time delay 1 of zero sequence overcurrent
13 Op_ROC11_Tr
protection at HV side of main transformer
Operation of stage 1 with time delay 2 of zero sequence overcurrent
14 Op_ROC12_Tr
protection at HV side of main transformer
Operation of stage 2 with time delay 1 of zero sequence overcurrent
15 Op_ROC21_Tr
protection at HV side of main transformer
Operation of stage 2 with time delay 2 of zero sequence overcurrent
16 Op_ROC22_Tr
protection at HV side of main transformer
Operation of inverse time zero sequence overcurrent protection at HV side
17 Op_InvROC_Tr
of main transformer
18 Op_ROV1_Tr Operation of stage 1 residual overvoltage protection of main transformer

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19 Op_ROV2_Tr Operation of stage 2 residual overvoltage protection of main transformer


Operation of stage 1 residual overcurrent protection of air gap of main
20 Op_ROC1_Gap_Tr
transformer
Operation of stage 2 residual overcurrent protection of air gap of main
21 Op_ROC2_Gap_Tr
transformer
22 Op_OvExc_Tr Operation of over-excitation protection of main transformer
23 Op_InvOvExc_Tr Operation of inverse time over excitation protection of main transformer
Operation of stage 1 phase discrepancy protection at HV side of main
24 Op_PD11_HVS_Tr
transformer
Operation of stage 2 phase discrepancy protection at HV side of main
25 Op_PD12_HVS_Tr
transformer
26 Op_InstDiff_Gen Operation of instantaneous unrestraint differential protection of generator
27 Op_PcntDiff_Gen Operation of percentage differential protection of generator
Operation of DPFC (Deviation of Power Frequency Component) differential
28 Op_DPFC_Diff_Gen
protection of generator
29 Op_SensTrvDiff_Gen Operation of transverse differential protection of generator
Operation of insensitive stage of transverse differential protection of
30 Op_InsensTrvDiff_Gen
generator
31 Op_SensIntTurn_Gen Operation of any of the interturn protection of generator
32 Op_InsensIntTurn_Gen Operation of any of the insensitive stage of interturn protection of generator
33 Op_DPFC_IntTurn_Gen Operation of DPFC interturn protection of generator
34 Op_OC1_Gen Operation of stage 1 of overcurrent protection of generator
35 Op_OC2_Gen Operation of stage 2 of overcurrent protection of generator
36 Op_Z1_Gen Operation of stage 1 of distance protection of generator
37 Op_Z2_Gen Operation of stage 2 of distance protection of generator
Operation of sensitive stage zero sequence over voltage element of earth
38 Op_SensROV_Sta
fault protection of stator
Operation of insensitive stage zero sequence over voltage element of earth
39 Op_InsensROV_Sta
fault protection of stator
40 Op_V3rdHRatio_Sta Operation of 3rd harmonics ratio earth fault protection of stator
41 Op_1PEF_RotWdg Operation of 1 point earth fault protection of rotor
42 Op_2PEF_RotWdg Operation of 2 point earth fault protection of rotor
43 Op_OvLd_Sta Operation of definitive time overload protection of stator
44 Op_InvOvLd_Sta Operation of inverse time overload protection of stator
45 Op_NegOC_Gen Operation of negative sequence overcurrent protection of rotor
Operation of inverse time negative sequence overcurrent protection of
46 Op_InvNegOC_Gen
rotor
47 Op_LossExc1_Gen Operation of stage 1 of loss-of-excitation protection of generator
48 Op_LossExc2_Gen Operation of stage 2 of loss-of-excitation protection of generator
49 Op_LossExc3_Gen Operation of stage 3 of loss-of-excitation protection of generator
50 Op_Ext_OOS_Gen Operation of out-of-step protection outside zone of generator
51 Op_Int_OOS_Gen Operation of out-of-step protection inside zone of generator
52 Op_OV1_Gen Operation of stage 1 of overvoltage protection of generator

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53 Op_OV2_Gen Operation of stage 2 of overvoltage protection of generator


54 Op_OvExc_Gen Operation of overexcitation protection of generator
55 Op_InvOvExc_Gen Operation of inverse time stage of overexcitation protection of generator
56 Op_RevP_Gen Operation of reverse power protection of generator
Operation of sequence tripping with reverse power controlled protection of
57 Op_SeqTrpRevP_Gen
generator
58 Op_UP_Gen Operation of under power protection of generator
59 Op_UF1_Gen Operation of stage 1 of under-frequency protection of generator
60 Op_UF2_Gen Operation of stage 2 of under-frequency protection of generator
61 Op_UF3_Gen Operation of stage 3 of under-frequency protection of generator
62 Op_OF1_Gen Operation of stage 1 of over-frequency protection of generator
63 Op_OF2_Gen Operation of stage 2 of over-frequency protection of generator
Operation of differential current element of generator during startup and
64 Op_GenDiff_StShut_Gen
shutoff process
Operation of stator zero sequence overvoltage element of generator during
65 Op_ROV_Sta_StShut_Gen
startup and shutoff process
Operation of under-frequency overcurrent element of generator during
66 Op_GenCur_StShut_Gen
startup and shutoff process
67 Op_AccEnerg_Gen Operation of accidental energization protection of generator
68 Op_Flash1_CB_HVS_Tr Operation of stage 1 flashover protection of circuit breaker
69 Op_Flash2_CB_HVS_Tr Operation of stage 2 flashover protection of circuit breaker
70 Op_BFP11_GCB Operation of stage 1 breaker failure protection at generator terminal
71 Op_BFP12_GCB Operation of stage 2 breaker failure protection at generator terminal
Operation of instantaneous unrestrained differential protection of
72 Op_InstDiff_ST1
step-down transformer 1
73 Op_PcntDiff_ST1 Operation of percentage differential protection of step-down transformer 1
Operation of stage 1 of overcurrent protection at HV side of step-down
74 Op_OC1_HVS_ST1
transformer 1
Operation of stage 2 of overcurrent protection at HV side of step-down
75 Op_OC2_HVS_ST1
transformer 1
Operation of stage 1 overcurrent protection of branch 1 at LV side of
76 Op_OC1_Br1_ST1
step-down transformer 1
Operation of stage 2 overcurrent protection of branch 1 at LV side of
77 Op_OC2_Br1_ST1
step-down transformer 1
Operation of stage 1 residual overcurrent protection of branch 1 at LV side
78 Op_ROC1_Br1_ST1
of step-down transformer 1
Operation of stage 2 residual overcurrent protection of branch 1 at LV side
79 Op_ROC2_Br1_ST1
of step-down transformer 1
Operation of stage 1 overcurrent protection of branch 2 at LV side of
80 Op_OC1_Br2_ST1
step-down transformer 1
Operation of stage 2 overcurrent protection of branch 2 at LV side of
81 Op_OC2_Br2_ST1
step-down transformer 1

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Operation of stage 1 residual overcurrent protection of branch 2 at LV side


82 Op_ROC1_Br2_ST1
of step-down transformer 1
Operation of stage 2 residual overcurrent protection of branch 2 at LV side
83 Op_ROC2_Br2_ST1
of step-down transformer 1
Operation of instantaneous unrestrained differential protection of
84 Op_InstDiff_ST2
step-down transformer 2
85 Op_PcntDiff_ST2 Operation of percentage differential protection of step-down transformer 2
Operation of stage 1 of overcurrent protection at HV side of step-down
86 Op_OC1_HVS_ST2
transformer 2
Operation of stage 2 of overcurrent protection at HV side of step-down
87 Op_OC2_HVS_ST2
transformer 2
Operation of stage 1 overcurrent protection of branch 1 at LV side of
88 Op_OC1_Br1_ST2
step-down transformer 2
Operation of stage 2 overcurrent protection of branch 1 at LV side of
89 Op_OC2_Br1_ST2
step-down transformer 2
Operation of stage 1 residual overcurrent protection of branch 1 at LV side
90 Op_ROC1_Br1_ST2
of step-down transformer 2
Operation of stage 2 residual overcurrent protection of branch 1 at LV side
91 Op_ROC2_Br1_ST2
of step-down transformer 2
Operation of stage 1 overcurrent protection of branch 2 at LV side of
92 Op_OC1_Br2_ST2
step-down transformer 2
Operation of stage 2 overcurrent protection of branch 2 at LV side of
93 Op_OC2_Br2_ST2
step-down transformer 2
Operation of stage 1 residual overcurrent protection of branch 2 at LV side
94 Op_ROC1_Br2_ST2
of step-down transformer 2
Operation of stage 2 residual overcurrent protection of branch 2 at LV side
95 Op_ROC2_Br2_ST2
of step-down transformer 2
Operation of instantaneous differential protection of excitation transformer
96 Op_InstDiff_Exc
or excitor
Operation of percentage differential protection of excitation transformer or
97 Op_PcntDiff_Exc
excitor
Operation of stage 1 of overcurrent protection of excitation transformer or
98 Op_OC1_Exc
excitor
Operation of stage 2 of overcurrent protection of excitation transformer or
99 Op_OC2_Exc
excitor
100 Op_InvOvLd_RotWdg Operation of inverse time overload protection of rotor winding
101 Op_MechRly1 Operation of repeater of external mechanical input 1
102 Op_MechRly2 Operation of repeater of external mechanical input 2
103 Op_MechRly3 Operation of repeater of external mechanical input 3
104 Op_MechRly4 Operation of repeater of external mechanical input 4
105 TrpOutp1 Operation of the tripping output 1
106 TrpOutp2 Operation of the tripping output 2
107 TrpOutp3 Operation of the tripping output 3

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108 TrpOutp4 Operation of the tripping output 4


109 TrpOutp5 Operation of the tripping output 5
110 TrpOutp6 Operation of the tripping output 6
111 TrpOutp7 Operation of the tripping output 7
112 TrpOutp8 Operation of the tripping output 8
113 TrpOutp9 Operation of the tripping output 9
114 TrpOutp10 Operation of the tripping output 10
115 TrpOutp11 Operation of the tripping output 11
116 TrpOutp12 Operation of the tripping output 12
117 TrpOutp13 Operation of the tripping output 13
118 TrpOutp14 Operation of the tripping output 14
119 TrpOutp15 Operation of the tripping output 15
120 TrpOutp16 Operation of the tripping output 16
121 TrpOutp17 Operation of the tripping output 17
122 TrpOutp18 Operation of the tripping output 18
123 TrpOutp19 Operation of the tripping output 19
124 TrpOutp20 Operation of the tripping output 20
125 TrpOutp21 Operation of the tripping output 21
126 TrpOutp22 Operation of the tripping output 22
127 TrpOutp23 Operation of the tripping output 23
128 TrpOutp24 Operation of the tripping output 24
129 TrpOutp25 Operation of the tripping output 25
130 TrpOutp26 Operation of the tripping output 26
131 TrpOutp27 Operation of the tripping output 27
132 TrpOutp28 Operation of the tripping output 28
133 TrpOutp29 Operation of the tripping output 29

5.4 Disturbance Record

The integral disturbance recorder has an area of memory specifically set aside for record storage.
The number of records that may be stored by the relay is dependent upon the selected recording
duration. The recorder of CPU board can typically store a minimum of 32 records, among them 8
records with instantaneous waveform. The record is composed of tripping element, faulty phase,
operation time and the waveform content is composed of differential currents, corrected current of
each side of generator or transformer, three-phase current of each side, zero sequence current of
each side (if available), three-phase voltages, zero sequence voltage of each side, negative
sequence voltage and tripping pulse.

The MON board can store up to 4 seconds (24 sampling points per cycle) or 8 seconds (12
sampling points per cycle) continual waveform, which including all channels analog quantities
(sampled data, differential currents and so on), all the binary input changing state, binary output,
pick up flags of fault detectors, alarm signals, operation signals and tripping signals. Disturbance
records continue to be recorded until the available memory is exhausted, at which time the oldest

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record(s) are overwritten to make space for the newest one.

It is not possible to view the disturbance records locally via the LCD; they must be extracted using
suitable software such as PCSPC.

The CPU board can also record latest 8 cycles of waveform in normal operation condition, which is
composed of three phases current, corrected current of each side for differential protection, three
phases voltage and zero sequence voltage of each side. This function can help user to check the
pole‘s correctness of secondary circuit by comparing the phase of related quantities shown in
wave figure.

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6 Hardware

6.1 Overview

Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP

ECVT

Fault
A/D Detector Pickup
DSP Relay

ECVT
ETHERNET
LCD +E
GPS
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT

Figure 6.1-1 Hardware diagram

PCS-985 adopts 64-bit microchip processor CPU produced by FREESCALE as control core for
logic calculation and management function, meanwhile, adopts high-speed digital signal processor
DSP to be in charge of all the protection calculation. 24 points are sampled in every cycle and
parallel processing of sampled data can be realized in each sampling interval to ensure ultra-high
reliability and safety of protection equipment.

The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 64-bit CPU on MON module to be recorded.
Protection calculation DSP module carries out protection logic calculation, tripping output, and
MON module completes SOE (sequence of event) record, waveform recording, printing,
communication between protection and SAS and communication between HMI and CPU. The
work process of fault detector DSP module is similar to that of protection DSP module, and the
only difference is, when fault detector DSP module decides a fault detector picks up, only positive
power supply of output relay is switched on.

PCS-985 is comprised of intelligent modules, except that few particular modules‘ position cannot
be changed in the whole device (PWR module and DSP module), the others like AI (analog input)
module such as AC current, AC voltage and etc., and BI/BO module such as binary input, tripping

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output, signal output, and etc can be flexibly configured according to the remained slot positions.

Table 6.1-1 PCS-985 module configuration

No. Module description


1 Management module (MON module)
2 Protection calculation module (DSP module 1)

3 Fault detector calculation module (DSP module 2)

4 Analog input module ( AI module )


5 Binary input module (BI module)

6 Tripping output module (BO trip module )

7 Signal output module (BO signal module )


8 Power supply module (PWR module)

9 Human machine interface module (HMI module)

 MON module provides functions like management function, completed event record, setting
management, and etc.

 DSP modules are totally the same, to carry out filtering, sampling and protection calculation
and fault detector calculation respectively.

 AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.

 BI module provides binary input, and the binary is inputted via 24V, 48V, 110V/125V, or
220V/250V opto-coupler (configurable).

 BO trip module provides all tripping outputs.

 BO signal module provides all kinds of signal output contact, including annunciation signal,
remote signal, fault and disturbance signal, operation abnormal signal and etc.

 PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the equipment

 HMI module is comprised of LCD, keypad, LED indicator and test serial ports, and it is
convenient for user to perform human-machine interaction with equipment.

Following figures show front and rear views of PCS-985 respectively. Programmable LED
indicators (No.8-No.20) can be defined by users trough PCS-PC software.

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1
HEALTHY
11 PCS-985
2 12
ALARM
GENERATOR RELAY
3 13
TRIP

4 14

P
VT ALARM

GR
5 15
CT ALARM

6 16 ENT
STA EF ALARM

C
ES
7 17
ROT EF ALARM

8 18

9 19

10 20

Figure 6.1-2 Front view of PCS-985 (only for reference)

Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 00

NR1101E NR1151D NR1151D NR1502D NR1505A NR1533A NR1526A NR1526A NR1526A NR1526A NR1541C NR1541C NR1541C NR1541C NR1541D NR1301A
1 2 3 1 2 3
5V BJ

ETHER
NET
4 5 6 4 5 6
BJJ BSJ

ON

OFF

1 BO_COM1

2 BO_FAIL

3 BO_ALM
4 BO_COM2

5 BO_FAIL

6 BO_ALM

7 OPTO+
8 OPTO-

9
10 PWR+

11 PWR-

12 GND

NR1401 NR1401 NR1401 NR1401 NR1401 NR1401 NR1401 NR1418

DANGER DANGER DANGER DANGER DANGER DANGER DANGER

Slot No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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Figure 6.1-3 Typical rear view of PCS-985 (only for reference)

6.2 Plug-in Module Terminal Definition

The device consists of power supply module, MON module, DSP module, AI module, BI module,
tripping output module, signal output module, input and output signal for mechanical relay. The
definition and application of each module and its terminal is introduced as follows:

6.2.1 PWR Plug-in Module (Power Supply)


PWR module is a DC/DC or AC/DC converter with electrical insulation between input and output. It
has an input voltage range as described in ―0 Technical Data”. The standardized output voltages
are +3.3V, +5V, ±12V and +24V DC. The tolerances of the output voltages are continuously
monitored.

The +3.3V DC output provides power supply for the microchip processors, and the +5V DC output
provides power supply for all the electrical elements that need +5V DC power supply in this device.
The ±12V DC output provides power supply for A/D conversion circuits in this device, and the
+24V DC output provides power supply for the static relays of this device.

The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.

A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.

NR1301A

5V OK ALM

BO_ALM BO_FAIL

1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND

Figure 6.2-1 View of PWR plug-in module

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01
BO_FAIL
02
BO_ALM
03

04
BO_FAIL
05
BO_ALM
06

Figure 6.2-2 Output contacts of PWR plug-in module

Terminals′ definition and description is shown as follows:

Table 6.2-1 Terminals′ definition and description

Terminal No. Symbol Description

01 BO_COM1 Common terminal 1

02 BO_FAIL Device failure output 1 (01-02, NC)

03 BO_ALM Device abnormality alarm output 1 (01-03, NO)

04 BO_COM2 Common terminal 2

05 BO_FAIL Device failure output 2 (04-05, NC)

06 BO_ALM Device abnormality alarm output 2 (04-06, NO)

07 OPTO+ Positive power supply for BI module (24V)

08 OPTO- Negative power supply for BI module (24V)

09 Blank Not used

10 PWR+ Positive input of power supply for the device (250/220V/125/110V)

11 PWR- Negative input of power supply for the device (250/220V/125/110V)

12 GND Grounded connection of the device

Note!

The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. For
non-standard rated voltage power supply module please specify when place order, and
check if the rated voltage of power supply module is the same as the voltage of power
source before the device being put into service.

PWR module provides terminal 12 and grounding screw for device grounding. Terminal 12
shall be connected to grounding screw and then connected to the earth copper bar of
panel via dedicated grounding wire.

Effective grounding is the most important measure for a device to prevent EMI, so effective
grounding must be ensured before the device is put into service.

PCS-985, like almost all electronic relays, contains electrolytic capacitors. These

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capacitors are well known to be subject to deterioration over time if voltage is not applied
periodically. Deterioration can be avoided by powering the relays up once a year.

6.2.2 MON Plug-in Module (Monitor)


MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.

MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces, PPS/IRIG-B differential time synchronization
interface and RS-232 printing interface.

Modules with various combinations of memory and interface are available as shown in the table
below.

NR1102C NR1102D NR1102H NR1102I NR1101E

TX TX
ETHERNET ETHERNET ETHERNET
RX RX

TX TX

RX RX

ETHERNET ETHERNET

Figure 6.2-3 View of MON plug-in module

Module ID Interface Terminal No. Usage Physical Layer


2 RJ45 Ethernet To SCADA
01 SYN+
02 SYN-
RS-485 To clock synchronization
NR1102C 03 SGND Twisted pair wire
04
05 RXD
RS-232 To printer
06 TXD

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07 SGND
4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN-
RS-485 To clock synchronization
03 SGND
NR1102D Twisted pair wire
04
05 RXD
RS-232 06 TXD To printer
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To SCADA Optical fibre SC
01 SYN+
02 SYN-
RS-485 To clock synchronization
NR1102H 03 SGND
04 Twisted pair wire
05 RXD
RS-232 06 TXD To printer
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To SCADA Optical fibre ST
01 SYN+
02 SYN-
RS-485 To clock synchronization
NR1102I 03 SGND
04 Twisted pair wire
05 RXD
RS-232 06 TXD To printer
07 SGND
2 RJ45 Ethernet To SCADA
01 485-1A
02 485-1B
RS-485 To SCADA
03 SGND
04
05 485-1A
06 485-1B
RS-485 To SCADA
07 SGND
NR1101E Twisted pair wire
08
09 SYN+
10 SYN-
RS-485 To clock synchronization
11 SGND
12
13 RXD
RS-232 14 TXD To printer
15 SGND

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6 Hardware

16 FGND To earth

The correct connection is shown in Figure 6.2-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the ―+‖ and ―–‖ terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.

Twisted pair wire


485-1A 01

485-1B 02

COM
cable with single point earthing
To the screen of other coaxial

SGND 03

04

Twisted pair wire


SYN+ 01

Clock SYN
SYN- 02

SGND 03

04

Twisted pair wire


RTS 05

PRINT
TXD 06

SGND 07

Figure 6.2-4 Connection of communication terminal

6.2.3 DSP Module 1 (Protection Calculation)


The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, calculation of protection logic and tripping output
etc.

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NR1151D

1 2 3

4 5 6

Figure 6.2-5 Rear view of DSP module

6.2.4 DSP Module 2 (Fault Detector)


The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, calculation of fault detector elements and providing
positive power supply to output relay. (DSP module 1 and DSP module 2 have same hardware
configuration, see Figure 6.2-5.)

6.2.5 BI Module (Binary Input)


There are three kinds of BI modules available, NR1502D, NR1505A and NR1533A. The device
provides 13 HV binary signals (220V or 110V), including 4 binary signals of mechanical protection,
7 binary signals of auxiliary contact and 2 spare binary signals, and 38 LV binary signals (24V).

Four binary signals [BI_TimeSyn], [BI_Print], [BI_Pwr_Opto] and [BI_RstTarg] are fixed, they are
used to time synchronization, print, device maintenance and reset signal respectively. The power
supply for the device is independent with that of mechanical protection, and they are equipped
with the monitoring circuit of power supply.

Up to 3 BI modules can be equipped with the device. They are respectively NR1502D for LV
binary signal, NR1505A for HV and LV binary signal and NR1533A for binary signal of mechanical
protection. The terminal definition of BI module is described as below.

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B04 NR1502D B04

EBI_IntTurn_Gen BI02 02 01 BI01 EBI_Diff_Gen

EBI_V3rdH_Sta BI04 04 03 BI03 EBI_ROV_Sta

EBI_OvLd_Sta BI06 06 05 BI05 EBI_EF_RotWdg

EBI_LossExc_Gen BI08 08 07 BI07 EBI_NegOC_Gen

EBI_VoltProt_Gen BI10 10 09 BI09 EBI_OOS_Gen

EBI_PwrProt_Gen BI12 12 11 BI11 EBI_OvExc_GTU

BI_Pwr_Opto BI13 14 13
OPT-
16 15
(24V)
EBI_AccEnerg_Gen BI15 18 17 BI14 EBI_FreqProt_Gen

EBI_PPF_Gen BI17 20 19 BI16 EBI_StShut_Gen

EBI_Bak_Exc BI19 22 21 BI18 EBI_Diff_Exc

EBI_Trp_MechRly1 BI21 24 23 BI20 EBI_Flash_CB

EBI_Trp_MechRly3 BI23 26 25 BI22 EBI_Trp_MechRly2

EBI_Diff_Tr BI25 28 27 BI24 EBI_Trp_MechRly4

30 29 BI26 EBI_PPF_Tr

Figure 6.2-6 Terminal definition of NR1502D

B05 NR1505A B05

EBI_Gap_HVS_Tr BI02 02 01 BI01 EBI_EF_Tr

EBI_Biff_ST1 BI04 04 03 BI03 EBI_Diff_GTU

EBI_Bak_Br1_ST1 BI06 06 05 BI05 EBI_Bak_HVS_ST1

EBI_Biff_ST2 BI08 08 07 BI07 EBI_Bak_Br2_ST1

EBI_Bak_Br1_ST2 BI10 10 09 BI09 EBI_Bak_HVS_ST2

BI_TimeSyn BI12 12 11 BI11 EBI_Bak_Br2_ST2

BI_Print BI14 14 13 BI13 BI_RstTarg

EBI_BFP_GCB BI16 16 15 BI15 EBI_PD_CB


OPT-
18 17
(24V)
BI_52b_CB_HVS1_Tr BI02 20 19 BI01 BI_52b_GCB

BI_Valve_Turbine BI04 22 21 BI03 BI_52b_CB_HVS2_Tr

BI_PD_CB BI06 24 23 BI05 BI_ExtTrpCtrl

BI_NoneUrgentTrp BI08 26 25 BI07 BI_1PEF_RotWdg

BI_Pwr_Superv BI10 28 27 BI09 BI_Reserved2


OPT-
30 29
(220V)

Figure 6.2-7 Terminal definition of NR1505A

Note!

BI02 can be [EBI_Gap_HVS_Tr] or [EBI_REF_Tr].

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B06 NR1533A B06

Op_MR1 02 01 RESET Reset

Op_MR2 04 03 BI01 BI_MechRly1

Local Signal

Binary Input
Op_MR3 06 05 BI02 BI_MechRly2

Op_MR4 08 07 BI03 BI_MechRly3

Com 10 09 BI04 BI_MechRly4

Op_MR1 12 11 Op_MR1
Remote Signal

Op_MR2 14 13 Op_MR2

Trip
Op_MR3 16 15 Op_MR3

Op_MR4 18 17 Op_MR4

Com 20 19 Com

Op_MR1 22 21
Event Recorder

Op_MR2 24 23

Op_MR3 26 25 V+ Pwr+ (For MR)

Supply
Power
Op_MR4 28 27

Com 30 29 V- Pwr- (For MR)

Figure 6.2-8 Terminal definition of NR1533A

6.2.6 BO Module (Binary Output)


6.2.6.1 Signal Binary Output Module

Five BO modules are used to output alarm signals, trip signals and other abnormality signals. The
terminal definition of BO module is described as below.

NR1526A B07

02 01 BO_Alm_CTS

04 03 BO_Alm_VTS

06 05 BO_Alm_RevP

08 07 BO_Alm_OvExc

10 09 Com

12 11 BO_Alm_OvLd
Alarm Signal

14 13 BO_Alm_NegOC

16 15 BO_Alm_OvLd_RotWdg

18 17 BO_Alm_EF_Sta

20 19 Com

22 21 BO_EF_RotWdg

24 23 BO_Alm_LossExc

26 25 BO_Alm_OOS

28 27 BO_Alm_Freq

30 29 Com

Table 6.2-2 Alarm signals

No. Alarm Signal Description


1 BO_Alm_CTS CT circuit failure alarm
2 BO_Alm_VTS VT circuit failure alarm
3 BO_Alm_RevP Reverse power alarm

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4 BO_Alm_OvExc Overexcitation alarm


5 BO_Alm_OvLd Overload alarm
6 BO_Alm_NegOC Negative-sequence overload alarm
7 BO_Alm_OvLd_RotWdg Excitation overload alarm
8 BO_Alm_EF_Sta Stator earth fault alarm
9 BO_Alm_EF_RotWdg Rotor earth fault alarm
10 BO_Alm_LossExc Loss-of-excitation alarm
11 BO_Alm_OOS Out-of-step alarm
12 BO_Alm_LowFreq Low-frequency alarm

NR1526A B08

02 01 Spare

04 03 BO_Diff_Exc

06 05 BO_Bak_Exc

08 07 BO_MechRly

Trip Signal
10 09 Com

12 11 BO_AccEnerg_Gen

14 13 BO_RevP_Gen

16 15 BO_SeqTrpRevP_Gen

18 17 BO_StShut_Gen

20 19 Com

22 21 BO_Diff_Tr
Trip Signal

24 23 BO_PPF_Tr

26 25 BO_EF_Tr

28 27 BO_EF_Gap_Tr

30 29 Com

Table 6.2-3 Trip signals

No. Alarm Signal Description

1 Spare Spare trip signal

2 BO_Diff_Exc Excitation differential protection tripping

3 BO_Bak_Exc Excitation backup protection tripping

4 BO_MechRly Mechanical protection tripping

5 BO_AccEnerg_Gen Generator inadvertent energization protection tripping

6 BO_RevP_Gen Generator reverse power protection tripping


Generator sequential-tripping reverse power protection tripping. It also
7 BO_SeqTrpRevP_Gen
can be trip signal of forward low power protection (BO_LFP_Gen)
8 BO_StShut_Gen Generator startup and shutoff protection tripping

9 BO_Diff_Tr Main transformer differential protection tripping

10 BO_PPF_Tr Phase-to-phase fault protection of main transformer tripping

11 BO_EF_Tr Earth fault protection of main transformer tripping

12 BO_EF_Gap_Tr Gap zero-sequence protection of main transformer tripping. It also can be

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trip signal of restricted earth-fault protection of main transformer


(BO_REF_Tr)

NR1526A B09

02 01 BO_Diff_Gen

04 03 BO_EF_Sta

06 05 BO_IntTurn_Gen

08 07 BO_OvLd_Sta

10 09 Com

12 11 BO_VoltProt_Gen

14 13 BO_LossExc

Trip Signal
16 15 BO_OSS_Gen

18 17 BO_NegOC_Gen

20 19 Com

22 21 BO_EF_RotWdg

24 23 BO_OvExc_Gen

26 25 BO_FreqProt_Gen

28 27 BO_PPF_Gen

30 29 Com

Table 6.2-4 Trip signals

No. Alarm Signal Description

1 BO_Diff_Gen Generator differential protection tripping

2 BO_EF_Sta Stator earth fault protection tripping

3 BO_IntTurn_Gen Generator interturn fault protection tripping

4 BO_OvLd_Sta Stator overload protection tripping

5 BO_VoltProt_Gen Generator voltage protection tripping

6 BO_LossExc Generator loss-of-excitation protection tripping

7 BO_OSS_Gen Generator out-of-step protection tripping

8 BO_NegOC_Gen Generator negative sequence overload protection tripping

9 BO_EF_RotWdg Rotor earth fault protection tripping

10 BO_OvExc_Gen Generator over excitation protection tripping

11 BO_FreqProt_Gen Generator frequency protection tripping

12 BO_PPF_Gen Generator phase-to-phase backup protection tripping

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NR1526A B10

02 01 BO_Flash_CB

04 03 BO_PD_CB

06 05 BO_BFP_GCB

08 07 BO_Diff_GTU

10 09 com

12 11 BO_Diff_ST1

14 13 BO_Bak_HVS_ST1

Trip Signal
16 15 BO_Bak_Br1_ST1

18 17 BO_Bak_Br1_ST2

20 19 com

22 21 BO_Diff_ST2

24 23 BO_Bak_HVS_ST2

26 25 BO_Bak_Br1_ST2

28 27 BO_Bak_Br2_ST2

30 29 com

Table 6.2-5 Trip signals

No. Alarm Signal Description

1 BO_Flash_CB Breaker flashover protection tripping

2 BO_PD_CB Pole discrepancy protection tripping

3 BO_BFP_GCB Breaker failure protection tripping

4 BO_Diff_GTU Differential protection of generator-transformer unit tripping

5 BO_Diff_ST1 Step-down transformer1 differential protection tripping

6 BO_Bak_HVS_ST1 HV side of step-down transformer backup protection tripping

7 BO_Bak_Br1_ST1 Branch1 of LV side of step-down transformer1 backup protection tripping

8 BO_Bak_Br1_ST2 Branch1 of LV side of step-down transformer2 backup protection tripping

9 BO_Diff_ST1 Step-down transformer1 differential protection tripping

10 BO_Bak_HVS_ST1 HV side of step-down transformer1 backup protection tripping

11 BO_Bak_Br1_ST1 Branch1 of LV side of step-down transformer1 backup protection tripping

12 BO_Bak_Br1_ST2 Branch1 of LV side of step-down transformer2 backup protection tripping

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6 Hardware

NR1541D B15

02 01
RLY01 BO_OC_Term_Gen
04 03

06 05
RLY02 BO_BlkOLTC_ST1
08 07

10 09
RLY03 BO_BlkOLTC_ST2
12 11

RLY04 14 13

RLY05 16 15 BO_InitCool1_Tr

RLY06 18 17

RLY07 20 19

RLY08 22 21 BO_InitCool2_Tr

RLY09 24 23

RLY10 26 25 BO_InitCool_ST1

RLY11 28 27 BO_InitCool_ST2

RLY12 30 29 BO_1PEF_Gen

Table 6.2-6 Abnormality signals

No. Alarm Signal Description

1 BO_OC_Term_Gen Output contact of overcurrent element of generator terminal


Output contact of blocking on-load tap changer (OLTC) of step-down
2 BO_BlkOLTC_ST1
transformer 1
Output contact of blocking on-load tap changer (OLTC) of step-down
3 BO_BlkOLTC_ST2
transformer 2
Output contact 1 indicating operation of stage 1 of initial cooling of main
4 BO_InitCool1_Tr
transformer.
Output contact 2 indicating operation of stage 1 of initial cooling of main
5 BO_ InitCool2_Tr
transformer.
Output contact 1 indicating operation of initial cooling of step-down
6 BO_InitCool1_ST1
transformer1.
Output contact 2 indicating operation of initial cooling of step-down
7 BO_InitCool1_ST2
transformer2.
8 BO_1PEF_Gen Output contact indicating operation of one-point earth fault of rotor

Note!

Above output signals can be extended via a 4U device consisted of extend module, and 4
signal contacts and trip contacts can be available at most.

The type of extend module is NR1535A, the number of extend module is determined by
the number of signal contact.

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NR1535A Mechanical Repeater

Reset 02 CLR COM 01 COM

04 03 # BO_MechRly1-1

MR1
06 05 BO_MechRly1-2

08 07 BO_MechRly1-3

BO_MechRly2 10 DI2+ DI1+ 09 BO_MechRly1

12 11 # BO_MechRly2-1

MR2
14 13 BO_MechRly2-2

16 15 BO_MechRly2-3

18 17 # BO_MechRly3-1

20 19 BO_MechRly3-2

MR3
22 21 BO_MechRly3-3

BO_MechRly4 24 DI4+ DI3+ 23 BO_MechRly3

26 25 # BO_MechRly4-1

MR4
28 27 BO_MechRly4-2

30 29 BO_MechRly4-3

6.2.6.2 Trip Binary Output Module

PCS-985B provides four trip binary output module. An the definition of all trip output signal can be
user-defined by auxiliary software. The trip output signal can be set to be broadened, and the time
is settable, default value is 140ms. The instantaneous drop-off contacts can be used to initiate
breaker failure protection. The terminal definition of BO module is described as below.

NR1541C B11 NR1541C B12

02 01 02 01
RLY01 RLY01
04 03 04 03
BO_TrpOutp1 BO_TrpOutp5
06 05 06 05
RLY02 RLY02
08 07 TJ1 08 07 TJ5
10 09 10 09
RLY03 RLY03
12 11 12 11
BO_TrpOutp2 BO_TrpOutp6
RLY04 14 13 RLY04 14 13

RLY05 16 15 TJ2 RLY05 16 15 TJ6


RLY06 18 17 RLY06 18 17

RLY07 20 19 RLY07 20 19
BO_TrpOutp3 BO_TrpOutp7
RLY08 22 21 RLY08 22 21
TJ3 TJ7
RLY09 24 23 RLY09 24 23

RLY10 26 25 RLY10 26 25

RLY11 28 27 BO_TrpOutp4 RLY11 28 27 BO_TrpOutp8

RLY12 30 29 TJ4 RLY12 30 29


TJ8

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NR1541C B13 NR1541C B14

02 01 02 01
RLY01 BO_TrpOutp9 RLY01 BO_TrpOutp18
04 03 TJ9 04 03
TJ18
06 05 06 05
RLY02 BO_TrpOutp10 RLY02 BO_TrpOutp19
08 07 TJ10 08 07 TJ19
10 09 10 09
RLY03 BO_TrpOutp11 RLY03 BO_TrpOutp20
12 11 TJ11 12 11 TJ20
RLY04 14 13
BO_TrpOutp12
RLY04 14 13 BO_TrpOutp21
TJ21
RLY05 16 15 TJ12 RLY05 16 15 BO_TrpOutp22 TJ22
RLY06 18 17 BO_TrpOutp13 RLY06 18 17 BO_TrpOutp23
TJ13 TJ23
RLY07 20 19 BO_TrpOutp14 RLY07 20 19 BO_TrpOutp24
TJ14 TJ24
RLY08 22 21 BO_TrpOutp15
TJ15
RLY08 22 21 BO_TrpOutp25
TJ25
RLY09 24 23 BO_TrpOutp16 RLY09 24 23 BO_TrpOutp26
TJ16 TJ26
RLY10 26 25 RLY10 26 25 BO_TrpOutp27
TJ27
RLY11 28 27 BO_TrpOutp17 RLY11 28 27 BO_TrpOutp28 TJ28

RLY12 30 29 TJ17 RLY12 30 29 BO_TrpOutp29 TJ29

Figure 6.2-9 Trip output contact without latching

Note!

The trip output contact can be latching shown as below. # means that this contact is a
magnetic-latching contact

NR1541A B11 NR1541A B12

# 02 01 # 02 01
RLY01 RLY01
# 04 03 # 04 03
BO_TrpOutp1 BO_TrpOutp5
# 06 05 # 06 05
RLY02 RLY02
# 08 07 # 08 07

# 10 09 # 10 09
RLY03 RLY03
# 12 11 # 12 11
BO_TrpOutp2 BO_TrpOutp6
# RLY04 14 13 # RLY04 14 13

# RLY05 16 15 # RLY05 16 15

# RLY06 18 17 # RLY06 18 17

# RLY07 20 19 # RLY07 20 19
BO_TrpOutp3 BO_TrpOutp7
# RLY08 22 21 # RLY08 22 21

# RLY09 24 23 # RLY09 24 23

# RLY10 26 25 # RLY10 26 25

# RLY11 28 27 BO_TrpOutp4 # RLY11 28 27 BO_TrpOutp8

# RLY12 30 29 # RLY12 30 29

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6 Hardware

NR1541B B13 NR1541C B14

# 02 01 02 01
RLY01 BO_TrpOutp9 RLY01 BO_TrpOutp18
# 04 03 04 03

# 06 05 06 05
RLY02 BO_TrpOutp10 RLY02 BO_TrpOutp19
# 08 07 08 07

# 10 09 10 09
RLY03 BO_TrpOutp11 RLY03 BO_TrpOutp20
# 12 11 12 11

# RLY04 14 13 RLY04 14 13 BO_TrpOutp21


BO_TrpOutp12
# RLY05 16 15 RLY05 16 15 BO_TrpOutp22

RLY06 18 17 BO_TrpOutp13 RLY06 18 17 BO_TrpOutp23

RLY07 20 19 BO_TrpOutp14 RLY07 20 19 BO_TrpOutp24

RLY08 22 21 BO_TrpOutp15 RLY08 22 21 BO_TrpOutp25

RLY09 24 23 BO_TrpOutp16 RLY09 24 23 BO_TrpOutp26

RLY10 26 25 RLY10 26 25 BO_TrpOutp27

RLY11 28 27 BO_TrpOutp17 RLY11 28 27 BO_TrpOutp28

RLY12 30 29 RLY12 30 29 BO_TrpOutp29

Figure 6.2-10 Trip output contact with latching

6.2.7 AI Module (Analog Input)


PCS-985B can provide 84 analog input channels, and the terminal definition of analog current and
analog voltage input is described as below.

B16 NR1401X B18 NR1401X B20 NR1401X

A 01 02 A' A 01 02 A' A 01 02 A'


Current Current Current
B 03 04 B' B 03 04 B' B 03 04 B'
channel 1 channel 5 channel 9
C 05 06 C' C 05 06 C' C 05 06 C'

A 07 08 A' A 07 08 A' A 07 08 A'


Current
Current Current
B 09 10 B' B 09 10 B' channel B 09 10 B'
channel 2 channel 6
10
C 11 12 C' C 11 12 C' C 11 12 C'

A 13 14 A' A 13 14 A' A 13 14 A'


Current
Current Current
B 15 16 B' B 15 16 B' channel B 15 16 B'
channel 3 channel 7
11
C 17 18 C' C 17 18 C' C 17 18 C'

A 19 20 A' A 19 20 A' A 19 20 A'


Current
Current Current
B 21 22 B' B 21 22 B' channel B 21 22 B'
channel 4 channel 8
12
C 23 24 C' C 23 24 C' C 23 24 C'

12I 12I 12I

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B22 NR1401X B24 NR1401X


Zero-sequence current
A 01 02 A' L 01 02 N
1
Current
Zero-sequence current
channel B 03 04 B' L 03 04 N
2
13
Zero-sequence current
C 05 06 C' L 05 06 N
3
Zero-sequence current
A 07 08 A' L 07 08 N
4
Current
channel B 09 10 B' A 09 10 B
Branch 1 VT of step-
14
down transformer 1
C 11 12 C' B 11 12 C

A 13 14 A' A 13 14 B
Branch 2 VT of step-
Current
down transformer 1
channel B 15 16 B' B 15 16 C
15
C 17 18 C' A 17 18 B
Branch 1 VT of step-
down transformer 2
A 19 20 A' B 19 20 C
Current
channel B 21 22 B' A 21 22 B
Branch 2 VT of step-
16
down transformer 2
C 23 24 C' B 23 24 C

12I 4I8U

B26 NR1401X B28 NR1401X

A 01 02 N Zero-sequence current 5 L 01 02 N

B 03 04 N Zero-sequence current 6 L 03 04 N
VT1 of generator terminal
C 05 06 N Zero-sequence current 7 L 05 06 N

L 07 08 N Zero-sequence current 8 A 07 08 A'

A 09 10 N 09 10

B 11 12 N 11 12
VT2 of generator terminal
C 13 14 N 13 14

L 15 16 N 15 16

A 17 18 N Zero-sequence current 9 B 17 18 B'


VT at HV side of main Zero-sequence current 10 C 19 20 C'
B 19 20 N
transformer
Zero-sequence VT at
C 21 22 N L 21 22 N
neutral point
Zero-sequence VT at HV Zero-sequence VT at LV
L 23 24 N L 23 24 N
side of main transformer side of main transformer
12U 10I2U

Figure 6.2-11 AC current and voltage

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B30 NR1418 B30 NR1417

IR+ 01 IR+ 01

02 02
Spare input Spare input
IR- 03 IR- 03

04 04

UR2+ 05 UR2+ 05
Rotor voltage used Rotor voltage used
by loss-of-excitation 06 by loss-of-excitation 06
protection protection
UR2- 07 UR2- 07

08 08

09 09

UR1+ 10 UOUT 10

11 11

12 12

13 13

14 Rotor voltage used 14


Rotor voltage used
by rotor earth-fault
by rotor earth-fault
RGND 15 protection with RGND 15
protection with ping-
external voltage
pang principle
16 injection principle 16

TEST 17 TEST 17

18 18

19 UIN+ 19

UR1- 20 20

21 UIN- 21

22 22

Figure 6.2-12 Input of rotor earth-fault protection

Note!

1. Terminal 01~06 on NR1401 in slot 28 can be applied for either of the following two
functions:

 The zero-sequence current inputs 5~7.

 The 17th group three-phase current inputs. The 17th group three-phase current inputs
can be applied as the measurement CT inputs of reverse power protection.

2. Terminal 07~08 and 17~20 on NR1401 in slot 28 can be applied for either of the
following two functions:

 The zero-sequence current inputs 8~10.

 The 18th group three-phase current inputs.

Note!

For rotor earth-fault protection with voltage injection, NR1417 should be selected.

For rotor earth-fault protection with ping-pang type, NR1418 should be selected.

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In NR1417, UR2+ should be connected to positive pole of rotor winding, and UR2- should
be connected to negative pole of rotor winding. UR2+ and UR2- are applied to acquire the
rotor voltage for loss-of-excitation protection.

UOUT is applied as the input of injected external resistor (47kΩ is recommended).

RGND is applied to connect the shaft of rotor winding.

TEST is applied for test (18kΩ is recommended for the resistance in the test).

UIN+ and UIN- are applied to connect to the external power supply (110VDC or 220VDC,
predetermined when ordering).

In NR1418, UR2+ should be connected to positive pole of rotor winding, and UR2- should
be connected to negative pole of rotor winding. UR2+ and UR2- are applied to acquire the
rotor voltage for loss-of-excitation protection.

UR1+ and UR1- are applied as the inputs of injected external resistor (13.6kΩ is
recommended). UR1+ and UR1- should be connected to the positive/negative pole of rotor
winding via the injected external resistor.

RGND is applied to connect the shaft of rotor winding.

TEST is applied for test (18kΩ is recommended for the resistance in the test).

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7 Settings

7 Settings
The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active.

7.1 Communication Settings


Table 7.1-1 Communication settings

No. Settings item Range Description

000.000.000.000~
1 IP_LAN1 IP address of Ethernet port 1.
255.255.255.255

000.000.000.000~
2 Mask_LAN1 Subnet mask of Ethernet port1.
255.255.255.255

000.000.000.000~
3 IP_LAN2 IP address of Ethernet port 2.
255.255.255.255

000.000.000.000~
4 Mask_LAN2 Subnet mask of Ethernet port 2.
255.255.255.255

5 En_LAN2 0: disable, 1: enable Enable/disable the IP address of port 2.

6 IP_LAN3 0: disable, 1: enable IP address of Ethernet port 3.

000.000.000.000~
7 Mask_LAN3 Subnet mask of Ethernet port 3.
255.255.255.255

8 En_LAN3 0: disable, 1: enable Enable/disable the IP address of port 3.

9 IP_LAN4 0: disable, 1: enable IP address of Ethernet port 4.

000.000.000.000~
10 Mask_LAN4 Subnet mask of Ethernet port 4.
255.255.255.255

11 En_LAN4 0: disable, 1: enable Enable/disable the IP address of port 4.

000.000.000.000~
12 Gateway Gateway of router
255.255.255.255

Enable/disable sending message in broadcast


13 En_Broadcast 0: disable, 1: enable
mode via network. (IEC103).

Communication address between the protective


14 Addr_RS485A 0~255 device with the SCADA or RTU via RS-485 serial
port 1.

4800,9600,19200,
15 Baud_RS485A Baud rate of rear RS-485 serial port 1.
38400,57600,115200 bps

Communication protocol of rear RS-485 serial port


16 Protocol_RS485A 0, 2
1.

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No. Settings item Range Description

Communication address between the protective


17 Addr_RS485B 0~255 device with the SCADA or RTU via RS-485 serial
port 2.

4800,9600,19200,
18 Baud_RS485B Baud rate of rear RS-485 serial port 2.
38400,57600,115200 bps

Communication protocol of rear RS-485 serial port


19 Protocol_RS485B 0, 2
2.

Threshold value of sending measurement values to


20 Threshold_Measmt 0~100% SCADA through IEC103 or IEC61850 protocol.
Default value: ―1%‖.

The time period when the equipment sends


measurement data to SCADA through IEC103
21 Period_Measmt 0~65535s
protocol.
Default value:“60”.

Select the format of measurement data sent to


22 Format_Measmt 0, 1
SCADA through IEC103 protocol.

4800,9600,
23 Baud_Printer 19200,38400, 51600, Baud rate of printer port
115200 bps

0: disable
24 En_AutoPrint Enable/disable automatic printing function
1: enable

Conventional
SAS Select the mode of time synchronization of
25 Opt_TimeSyn
Advanced equipment.
NoTImeSyn

The address of the external SNTP clock


000.000.000.000~
26 IP_Server_SNTP synchronization server sending SNTP message to
255.255.255.255
the equipment.

The local time zone also refered to as the hour


27 OffsetHour_UTC -12~12hrs
offset hour from UTC.

28 OffsetMinute_UTC 0~60min The offset minute of local time from UTC.

7.1.1 Setting Description

1. En_LAN1, En_LAN2, En_LAN3, En_LAN4

Put Ethernet 1, Ethernet 2, Ethernet 3 and Ethernet 4 in service

They are used for Ethernet communication based on the 103 protocol. When the IEC 61850
protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.

2. [En_Broadcast]

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This setting is only used only for IEC 103 protocol. If NR network IEC103 protocol is used, the
setting must be set as ―1‖.

0: the device does not send UDP messages through network;

1: the device sends UDP messages through network.

3. Addr_RS485A, Addr_RS485B

They are the device′s communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).

4. Baud_RS485A, Baud_RS485B

Baud rate of rear RS-485 serial port A or B

5. Protocol_RS485A, Protocol_RS485B

Communication protocol of rear RS-485 serial port A or B

0: IEC 60870-5-103 protocol

2: Modbus Protocol

Note!

Above table listed all the communication settings, the device delivered to the user maybe
only show some settings of them according to the communication interface configuration.
If only the Ethernet ports are applied, the settings about the serial ports (port A and port B)
are not listed in this submenu. And the settings about the Ethernet ports only listed in this
submenu according to the actual number of Ethernet ports.

The standard arrangement of the Ethernet port is two, at most four (predetermined when
ordering). Set the IP address according to actual arrangement of Ethernet numbers and
the un-useful port/ports need not be configured. If the PCS-PC configuration tool auxiliary
software is connected with this device through the Ethernet, the IP address of the PCS-PC
must be set as one of the available IP address of this device.

6. Format_Measmt

The setting is used to select the format of measurement data sent to SCADA through IEC103
protocol.

0: GDD data type through IEC103 protocol is 12;

1: GDD data type through IEC103 protocol is 7, i.e. 754 shorth real number of IEEE standard.

7. Baud_Printer

Baud rate of printer port

8. En_AutoPrint

If automatic print is required for fault report after protection operating, it is set as ―1‖. Otherwise, it

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should be set to ―0‖.

9. En_FastPrint

It is set as ―0‖ for common printing with high definition, while it is set as ―1‖ for high-speed printing.

10. Opt_TimeSyn

There are four selectons for clock synchronization of device, each selection includs different time
clock synchronization signals shown in following table.

Item Description
PPS(RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B(RS-485): IRIG-B via RS-485 differential level.
Conventional
PPM(DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS(DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SAS SNTP(BC): Broadcast SNTP mode via Ethernet network.
Message (IEC103): Clock messages through IEC103 protocol.
IEEE1588: Clock message via IEEE1588.
Advanced IRIG-B(Fiber): IRIG-B via optical-fibre interface.
PPS(Fiber) PPS: Pulse per second (PPS) via optical-fibre interface.
When no time synchronization signal is connected to the equipment, please select
NoTimeSync
this option and the alarm message [Alm_TimeSync] will not be issued anymore.

―Conventional‖ mode and ―SAS‖ mode are always be supported by device, but ―Advanced‖ mdoe
is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn] may be
issued to remind user loss of time synchronization signals.

1) When ―SAS‖ is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When ―Conventional‖mode is slected, if there is
no conventional clock synchronization signal, ―SAS‖mode will be enabled automatically with
the alarm signal [Alm_TimeSyn] being issued simultaneously.

2) When ―Advanced‖ mode is selected, if there is no conventional clock synchronization signal


connected to NET-DSP moduel,―SAS‖mode is enabled automatically with the alarm signal
[Alm_TimeSyn] being issued simultaneously.

3) When ―NoTimeSyn‖ mode is selected, the device will not send alarm signals without

NOTE! The clock message via IEC103 protocol is invalid when the device receives the

IRIG-B signal through RC-485 port.

11. OffsetHour_UTC, OffsetMinute_UTC

If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.

The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT

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7 Settings

(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as ―8‖. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.

Time zone GMT zone East 1st East 2nd East 3rd East 4th East 5th
Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11th
Setting 6 7 8 9 10 11
th st nd rd th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5th
Setting -12/12 -1 -2 -3 -4 -5
th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11th
Setting -6 -7 -8 -9 -10 -11

7.1.2 Access Path


MainMenuSettingsDevice SetupComm Settings

7.2 Device Settings


Table 7.2-1 Device settings

No. Setting Item Range Description

Select encoding format of header (HDR) file


1 HDR_EncodeMode GB18030, UTF-8 COMTRADE recording file. Default value is
“UTF-8”.

Select the caption language sent to SAS via


2 Opt_Caption_103 0~1 IEC103 protocol. Default value is 0.
0: Local language; 1: Chinese

3 Un_BinaryInput 24V, 48V, 110V, 220V Voltage level of binary input

7.2.1 Setting Description

1. [HDR_EncodeMode], [Opt_Caption_103]

Two logic settings to select encoding format of header file and caption language of IEC103
protocol.

Default value of [HDR_EncodeMode] is 1((i.e. UTF-8 code) and please set it to 0(i.e. GB18030)
according to the special requirement.

Default value of [Opt_Caption_103] is 1(i.e. Chinese), and please set it to 0(i.e. local language) if
the SAS is supplied by China Manufacturer.

2. Un_BinaryInput

This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V or 220V can be set according to the actual requirement.

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7.2.2 Access Path


MainMenuSettingsDevice SetupDevice Settings

7.3 Label Settings


The settings in the following list can not be seen on LCD of equipment and only be viewed and
configured on PC through PCSPC software. Label settings will not affect protection logics and it
will only affect the displayed names of corresponding elements on LCD and in PCSPC software.

7.3.1.1 Settings List

Table 7.3-1 Label settings

No. Setting Item Description

1 Name_MRx (x=1~4) Label settings of external mechanical repeater x

2 Name_B05Pin02 Label settings of pin 02 of the module located in slot No.5

3 Name_Trpx (x=1~29) Label settings of tripping output x

7.3.2 Access Path


MainMenuSettingsDevice SetupLabel Settings

7.4 Display Control Settings


The settings in the following list can not be seen on LCD of equipment and only be viewed and
configured on PC through PCSPC software. Display controll settings will not affect protection
logics and it will only affect the displayed main connection system on LCD.

7.4.1.1 Settings List

Table 7.4-1 Display controll settings

No. Setting Item Range Description

0: The connection mode of main transformer is Yd mode


1 Yyd_Conn_Tr 0,1
1: The connection mode of main transformer is YYd mode

0: There is circuit breaker located at generator terminal


2 Opt_GCB 0,1
1: There is no circuit breaker located at generator terminal

0: Stepdown transformer 1 is two windings transformer


3 Opt_SLD_ST1 0,1
1: Stepdown transformer 1 is three windings transformer

0: Stepdown transformer 2 is not exist


4 Opt_SLD_ST2 0,1,2 1: Stepdown transformer 2 is two windings transformer
2: Stepdown transformer 2 is three windings transformer

7.4.2 Access Path


MainMenuSettingsDevice SetupDisplay Settings

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7.5 System Settings


7.5.1 Equipment Settings

7.5.1.1 Settings List

Table 7.5-1 List of equipment settings

No. Setting Item Range Step Default Description

1 Active_Grp 1~30 1 1 Current setting group.

Select system working frequency (0:50Hz,


2 Opt_SysFreq 0,1 0
1:60Hz).

Max 20 Name of the protected primary equipment,


3 PrimaryEquip_Name
characters such as transformer, line, etc.

7.5.1.2 Setting Description

1. [Active_Grp]

The current protection setting group number, and total 30 group settings are provided. The device
settings, communication settings and system settings, are common for all protection groups.

7.5.1.3 Access Path

Main Menu -> Settings -> System Settings -> Equip Settings

7.5.2 Logic Settings of Configuring Functions


If any of the following settings is set as ―1‖, corresponding protection function is enabled. If any of
the following settings is set as ―0‖, corresponding protection function is disabled and related
setting submenu and settings will be hidden.

7.5.2.1 Settings List

Table 7.5-2 List of protection configuration settings

No. Symbol Range Default


1 En_Diff_GTU 0/1 0
2 En_Diff_Tr 0/1 1
3 En_REF_Tr 0/1 0
4 En_PPF_Tr 0/1 1
5 En_EF_Tr 0/1 1
6 En_OvExc_Tr 0/1 0
7 En_Diff_Gen 0/1 1
8 En_IntTurn_Gen 0/1 1
9 En_PPF_Gen 0/1 1
10 En_EF_Sta 0/1 1
11 En_EF_RotWdg 0/1 1

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12 En_OvLd_Sta 0/1 1
13 En_NegOC_Gen 0/1 1
14 En_LossExc_Gen 0/1 1
15 En_OOS_Gen 0/1 1
16 En_VoltProt_Gen 0/1 1
17 En_OvExc_Gen 0/1 1
18 En_PwrProt_Gen 0/1 1
19 En_FreqProt_Gen 0/1 1
20 En_StShut_Gen 0/1 1
21 En_AccEnerg_Gen 0/1 1
22 En_BFP_GCB 0/1 1
23 En_Diff_ST1 0/1 1
24 En_Bak_HVS_ST1 0/1 1
25 En_Bak_Br1_ST1 0/1 1
26 En_Bak_Br2_ST1 0/1 1
27 En_Diff_ST2 0/1 1
28 En_Bak_HVS_ST2 0/1 1
29 En_Bak_Br1_ST2 0/1 1
30 En_Bak_Br2_ST2 0/1 1
31 En_Diff_Exc 0/1 0
32 En_Bak_Exc 0/1 1
33 En_OvLd_Exc 0/1 1
34 En_MechRly 0/1 1
35 En_PD_CB 0/1 0
36 En_VTComp_Term_Gen 0/1 0
37 En_NeuVTS_VT2 0/1 0
38 En_NeuVTS_OtherVT 0/1 0
39 En_TestMode 0/1 0

7.5.2.2 Setting Description

2. En_Diff_GTU

This logic setting is used to enable/disable differential protection of generator-transformer unit.

3. En_Diff_Tr

This logic setting is used to enable/disable differential protection of main transformer.

4. En_REF_Tr

This logic setting is used to enable/disable restricted earth-fault protection of main transformer.

5. En_PPF_Tr

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This logic setting is used to enable/disable phase to phase fault protection of main transformer.

6. En_EF_Tr

This logic setting is used to enable/disable earth fault protection of main transformer.

7. En_OvExc_Tr

This logic setting is used to enable/disable over excitation protection of main transformer.

8. En_Diff_Gen

This logic setting is used to enable/disable differential protection of generator.

9. En_IntTurn_Gen

This logic setting is used to enable/disable interturn fault protection of generator.

10. En_PPF_Gen

This logic setting is used to enable/disable phase to phase fault protection of generator

11. En_EF_Sta

This logic setting is used to enable/disable earth fault protection of stator of generator.

12. En_EF_RotWdg

This logic setting is used to enable/disable earth fault protection of rotor winding.

13. En_OvLd_Sta

This logic setting is used to enable/disable overload protection of stator.

14. En_NegOC_Gen

This logic setting is used to enable/disable negative sequence overcurrent protection of generator.

15. En_LossExc_Gen

This logic setting is used to enable/disable loss of excitation protection of generator.

16. En_OOS_Gen

This logic setting is used to enable/disable out-of-step protection of generator.

17. En_VoltProt_Gen

This logic setting is used to enable/disable overvoltage and undervoltage protection of generator.

18. En_OvExc_Gen

This logic setting is used to enable/disable overexcitation protection of generator.

19. En_PwrProt_Gen

This logic setting is used to enable/disable overpower and underpower protection of generator.

20. En_FreqProt_Gen

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This logic setting is used to enable/disable overfrequency and underfrequency protection of


generator.

21. En_StShut_Gen

This logic setting is used to enable/disable all relative protections in Startup/shutdown conditions
of generator.

22. En_AccEnerg_Gen

This logic setting is used to enable/disable relevant protection in case of accident energization of
generator.

23. En_BFP_GCB

This logic setting is used to enable/disable generator terminal circuit breaker failure protection.

24. En_Diff_ST1

This logic setting is used to enable/disable differential protection of step-down transformer1.

25. En_Bak_HVS_ST1

This logic setting is used to enable/disable backup protection at HV side of step-down


transformer1.

26. En_Bak_Br1_ST1

This logic setting is used to enable/disable backup protection at branch 1 of LV side of step-down
transformer1.

27. En_Bak_Br2_ST1

This logic setting is used to enable/disable backup protection at branch 2 of LV side of step-down
transformer1.

28. En_Diff_ST2

This logic setting is used to enable/disable differential protection of step-down transformer2.

29. En_Bak_HVS_ST2

This logic setting is used to enable/disable backup protection at HV side of step-down


transformer2.

30. En_Bak_Br1_ST2

This logic setting is used to enable/disable backup protection at branch 1 of LV side of step-down
transformer2.

31. En_Bak_Br2_ST2

This logic setting is used to enable/disable backup protection at branch 2 of LV side of step-down
transformer2.

32. En_Diff_Exc

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This logic setting is used to enable/disable differential protection of exciting transformer or exciter.

33. En_Bak_Exc

This logic setting is used to enable/disable backup protection of exciting transformer or exciter.

34. En_OvLd_Exc

This logic setting is used to enable/disable overload protection of exciting transformer or exciter.

35. En_MechRly

This logic setting is used to enable/disable mechanical protection.

36. En_VTComp_Term_Gen

This logic setting is used to enable/disable voltage balance function of VTs at the generator
terminal.

37. En_NeuVTS_VT2

This logic setting is used to enable/disable neutral line failure supervision of VT2 (i.e. interturn fault
protection used VT).

38. En_NeuVTS_OtherVT

This logic setting is used to enable/disable neutral line failure supervision of other VT (except for
VT2).

39. En_TestMode

This logic setting is configured for equipment debugging status. If it is set as ―1‖, debugging
window can be open by PCS-PC software. Under debugging window, corresponding protection
tripping signals and alarm signals can be issued, corresponding tripping contacts can be
energized without actual happening of corresponding fault. If it is set as ―0‖, debugging window
can not be open.

7.5.2.3 Access Path

Main Menu -> Settings ->System Settings ->Enable Settings

7.5.3 Main Transformer System Settings

7.5.3.1 Setting List

Table 7.5-3 List of main transformer system settings

No. Symbol Range Step Default


1 Sn_Tr 0.1-2000 MVA 0.1 MVA 370
2 U1n_HVS_Tr 0.01-2000 kV 0.01 kV 500
3 U1n_LVS_Tr 0.01-100 kV 0.01 kV 20
4 U1n_VT_HVS_Tr 0.01-2000 kV 0.01 kV 500
5 U2n_VT_HVS_Tr 0.01-200 V 0.01 V 100

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6 U2n_DeltVT_HVS_Tr 0.01-300 V 0.01 V 57.74


7 I1n_CT_HVS_Tr 0-60000 A 1A 1200
8 I2n_CT_HVS_Tr 1, 5 A 1A 5
9 I1n_CT_Bak_HVS_Tr 0-60000 A 1A 1200
10 I2n_CT_Bak_HVS_Tr 1, 5 A 1A 5
11 I1n_CT_LVS_Tr 0-60000 A 1A 12000
12 I2n_CT_LVS_Tr 1, 5 A 1A 5
13 I1n_CT#_HVS_ST1 0-60000 1A 12000
14 I2n_CT#_HVS_ST1 1, 5A 1A 5
15 I1n_CT#_HVS_ST2 0-60000A 1A 12000
16 I2n_CT#_HVS_ST2 1,5A 1A 5
17 I1n_CT_NP_Tr 0-60000A 1A 600
18 I2n_CT_NP_Tr 1,5A 1A 5
19 I1n_CT_Gap_Tr 0-60000A 1A 200
20 I2n_CT_Gap_Tr 1,5A 1A 5
Logic setting ―1‖ - enable, ―0‖ – disable
21 Yd11_Conn_Tr 0/1 1 1
22 Yyd11_Conn_Tr 0/1 1 0
23 Yd1_Conn_Tr 0/1 1 0
24 Yyd1_Conn_Tr 0/1 1 0
25 Opt_GCB 0/1 1 0

7.5.3.2 Setting Description

1. Sn_Tr

Transformer capacity shall be configured as its name plate stated.

2. U1n_HVS_Tr

System rated voltage at HV side of main transformer. This setting is used for calculating the rated
current of main transformer. It should be set according to the real operating voltage of the power
system.

3. U1n_LVS_Tr

System rated voltage at LV side of main transformer.

4. U1n_VT_HVS_Tr

Rated primary voltage of VT at HV side of main transformer.

5. U2n_VT_HVS_Tr

Rated secondary voltage of VT at HV side of main transformer.

6. U2n_DeltVT_HVS_Tr

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Rated secondary voltage of open-delta of VT at HV side of main transformer.

7. I1n_CT_HVS_Tr

Rated primary current of CT of HV side of main transformer.

8. I2n_CT_HVS_Tr

Rated secondary current of CT of HV side of main transformer.

9. I1n_CT_Bak_HVS_Tr

Rated primary current of backup CT of HV side of transformer.

10. I2n_CT_Bak_HVS_Tr

Rated secondary current of backup CT of HV side of transformer.

11. I1n_CT_LVS_Tr

Rated primary current of CT at LV side of transformer.

12. I2n_CT_LVS_Tr

Rated secondary current of CT at LV side of transformer.

13. I1n_CT#_HVS_ST1

Rated primary current of CT at HV side of step-down transformer1 for MT differential protection.

14. I2n_CT#_HVS_ST1

Rated secondary current of CT at HV side of step-down transformer1 for MT differential protection.

15. I1n_CT#_HVS_ST2

Rated primary current of CT at HV side of step-down transformer2 for MT differential protection.

16. I2n_CT#_HVS_ST2

Rated secondary current of CT at HV side of step-down transformer2 for MT differential protection.

17. I1n_CT_NP_Tr

Rated primary current of CT at neutral point of transformer.

18. I2n_CT_NP_Tr

Rated secondary current of CT at neutral point of transformer.

19. I1n_CT_Gap_Tr

Rated primary current of gap CT at HV side of transformer.

20. I2n_CT_Gap_Tr

Rated secondary current of gap CT at HV side of transformer.

21. Yd11_Conn_Tr

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The connection mode of main transformer is Yd-11 mode. The current input for HV side is only
one.

22. Yyd11_Conn_Tr

The connection mode of main transformer is Yd-11 mode. The currents input for HV side are two
CTs, such as 3/2 breakers of HV bus.

23. Yd1_Conn_Tr

The connection mode of main transformer is Yd-1 mode. The current input for HV side is only one.

24. Yyd1_Conn_Tr

The connection mode of main transformer is Yd-1 mode. The currents input for HV side are two
CTs, such as 3/2 breakers of HV bus.

25. Opt_GCB

Logic setting of circuit breaker at terminal of generator. ―1‖ means there is a circuit breaker at
terminal of generator. ―0‖ means there isn‘t a circuit breaker at terminal of generator.

7.5.3.3 Access Path

Main Menu -> Settings ->System Settings ->TrSys Settings

7.5.4 Generator System Settings

7.5.4.1 Setting List

Table 7.5-4 List of generator system settings

No. Symbol Range Step Default


1 Pn_Gen 0.1-2000.0 MW 0.1 MW 300
2 PF_Gen 0.01-1.00 0.01 0.85
3 U1n_Gen 0.01-100.00 kV 0.01 kV 20
4 U1n_VT_Term_Gen 0.01-100.00 kV 0.01 V 11.55
5 U2n_VT_Term_Gen 0.01-200.00 V 0.01 V 57.74
6 U2n_DeltVT_Term_Gen 0.01-300.00 V 0.01 V 33.33
7 U1n_VT_NP_Gen 0.01-100.00 kV 0.01 kV 11.55
8 U2n_VT_NP_Gen 0.01-300.00 V 0.01 V 57.74
9 I1n_CT_Term_Gen 0-60000 A 1A 12000
10 I2n_CT_Term_Gen 1A/5A 5
11 I1n_CT_NP_Gen 0-60000 A 1A 12000
12 I2n_CT_NP_Gen 1A/5A 5
13 I1n_CT_TrvDiff_Gen 0-60000 A 1A 12000
14 I2n_CT_TrvDiff_Gen 1A/5A 5
15 U1n_Exc 0-1000.00 V 0.01 V 200
16 K_U_RotWdg 0-2.000 0.001 1

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7.5.4.2 Setting Description

1. Pn_Gen

Capacity of active power of the generator shall be configured as its name plate stated.

2. PF_Gen

Rated power factor of generator.

3. U1n_Gen

System rated voltage at the terminal of generator. This setting is used for calculating the rated
current of generator. It should be set according to the real operating voltage of the power system.

4. U1n_VT_Term_Gen

Rated primary voltage of VT at the terminal of generator. This parameter can be configured as
either phase voltage or phase-to-phase voltage value. For example, if the terminal VT ratio is

20kV 100V 100V


, this parameter and the following two settings can be set as 11.55kV,
3 3 3
57.74V and 33.33V or can be set as 20kV, 100V and 57.74V. This is used for substation
automation system. From this setting and the next two ones, VT ratio can be got. Secondary
voltage and current recorded by the equipment will be transferred to primary value by multiplying
VT ratio when fault oscillogram is sent to the host.

5. U2n_VT_Term_Gen

Rated secondary voltage of VT at the terminal of generator.

6. U2n_DeltVT_Term_Gen

Rated secondary open-delta voltage at the terminal of generator.

7. U1n_VT_NP_Gen

Rated primary voltage of VT at the neutral point of generator.

8. U2n_VT_NP_Gen

Rated secondary voltage of VT at the neutral point of generator.

9. I1n_CT_Term_Gen

Rated primary current of CT at the terminal of the generator.

10. I2n_CT_Term_Gen

Rated secondary current of CT at the terminal of the generator.

11. I1n_CT_NP_Gen

Rated primary current of CT at the neutral point of the generator.

12. I2n_CT_NP_Gen

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Rated secondary current of CT at the neutral point of the generator.

13. I1n_CT_TrvDiff_Gen

Rated primary current of CT used for transverse differential protection.

14. I2n_CT_TrvDiff_Gen

Rated secondary current of CT used for transverse differential protection.

15. U1n_Exc

Rated primary voltage of exciter or excitation transformer.

16. k_U_RotWdg

Correction coefficient of voltage of rotor. For the occasion that partial rotor voltage is connected to
the device, rotor voltage need to be corrected by the setting. For example, if only one quarter of
rotor voltage is connected to the device, this setting should be set as ―4‖, if total rotor voltage is
connected to the device, this setting should be set as ―1‖.

7.5.4.3 Access Path

Main Menu -> Settings ->System Settings ->GenSys Settings

7.5.5 System Settings of Step-down Transformer 1&2

7.5.5.1 Setting List

Table 7.5-5 List of step-down transformer1&2 settings

No. Symbol Range Step Default


1 Sn_ST1(2) 0.01-100 MVA 0.01 MVA 30
2 U1n_HVS_ST1(2) 0.01-100 kV 0.01 kV 20
3 U1n_Br1_ST1(2) 0.01-100 kV 0.01 kV 6.3
4 U1n_Br2_ST1(2) 0.01-100 kV 0.01 kV 6.3
5 U1n_VT_Br1_ST1(2) 0.01-100 kV 0.01 kV 3.64
6 U2n_VT_Br1_ST1(2) 0.01-200 V 0.01 V 57.74
7 U1n_VT_Br2_ST1(2) 0.01-100 kV 0.01 kV 3.64
8 U2n_VT_Br2_ST1(2) 0.01-200 V 0.01 V 57.74
9 I1n_CT_HVS_ST1(2) 0-60000 A 1A 1000
10 I2n_CT_HVS_ST1(2) 1,5 A 1A 5
11 I1n_CT_Br1_ST1(2) 0-60000 A 1A 3000
12 I2n_CT_Br1_ST1(2) 1,5 A 1A 5
13 I1n_CT_Br2_ST1(2) 0-60000 A 1A 3000
14 I2n_CT_Br2_ST1(2) 1,5 A 1A 5
15 I1n_CT_NP_Br_ST1(2) 0-60000 A 1A 3000
16 I2n_CT_NP_Br_ST1(2) 1,5 A 1A 5
Logic setting ―1‖ - enable, ―0‖ – disable

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17 Yyy12_Conn_ST1(2) 0/1 0
18 Ddd12_Conn_ST1(2) 0/1 0
19 Dyy11_Conn_ST1(2) 0/1 1
20 Ydd11_Conn_ST1(2) 0/1 0
21 Dyy1_Conn_ST1(2) 0/1 0

7.5.5.2 Setting Description

1. Sn_ST1(2)

Capacity of step-down transformer, it shall be configured as its name plate stated.

2. U1n_HVS_ST1(2)

Rated primary voltage of HV side of step-down transformer.

3. U1n_Br1_ST1(2) or U1n_Br2_ST1(2)

Rated primary voltage of branch 1 or branch 2 of LV side of step-down transformer.

4. U1n_VT_Br1_ST1(2) or U1n_VT_Br2_ST1(2)

Rated primary voltage of VT at branch 1 or branch 2 of LV side of step-down transformer.

5. U2n_VT_Br1_ST1(2) or U2n_VT_Br2_ST1(2)

Rated secondary voltage of VT at branch 1 or branch 2 of LV side of step-down transformer.

6. 1n_CT_HVS_ST1(2)

Rated primary current of CT1 with small ratio at HV side of step-down transformer.

7. I2n_CT_HVS_ST1(2)

Rated secondary current of CT1 with small ratio at HV side of step-down transformer.

8. I1n_CT_Br1_ST1(2) or I1n_CT_Br2_ST1(2)

Rated primary current of CT at branch 1 or branch 2 of LV side of step-down transformer.

9. I2n_CT_Br1_ST1(2) or I2n_CT_Br2_ST1(2)

Rated secondary current of CT at branch 1 or branch 2 of LV side of step-down transformer.

10. I1n_CT_NP_Br_ST1(2)

Rated primary current of CT at neutral point of LV side of step-down transformer.

11. I2n_CT_NP_Br_ST1(2)

Rated secondary current of CT at neutral point of LV side of step-down transformer.

12. Yyy12_Conn_ST

The connection mode of step-down transformer is Yyy-12 mode.

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13. Ddd12_Conn_ST

The connection mode of step-down transformer is Ddd-12 mode.

14. Dyy11_Conn_ST

The connection mode of step-down transformer is Dyy-11 mode.

15. Ydd11_Conn_ST

The connection mode of step-down transformer is Ydd-11 mode.

16. Dyy1_Conn_ST

The connection mode of step-down transformer is Dyy-1 mode.

7.5.5.3 Access Path

Main Menu -> Settings ->System Settings ->ST1Sys Settings


Main Menu -> Settings ->System Settings ->ST2Sys Settings

7.5.6 System Settings of Excitation Transformer or Exciter

7.5.6.1 Setting List

Table 7.5-6 List of excitation transformer of exciter settings

No. Symbol Range Step Default


1. Sn_Exc 0.01-100.00 MVA 0.01 MVA 0.5
2. U1n_S1_Exc 0.01-100.00 kV 0.01 kV 20
3. U1n_S2_Exc 0.01-100.00 kV 0.01 kV 6.3
4. I1n_CT_S1_Exc 0-60000 A 1A 20
5. I2n_CT_S1_Exc 1A,5A 1A 5
6. I1n_CT_S2_Exc 0-60000 A 1A 60
7. I2n_CT_S2_Exc 1A,5A 1A 5
Logic setting “1” - enable, “0” – disable
8. Opt_Exc 0, 1 0
9. Yy12_Conn_ET 0, 1 0
10. Dd12_Conn_ET 0, 1 0
11. Dy11_Conn_ET 0, 1 0
12. Yd11_Conn_ET 0, 1 1
13. Dy1_Conn_ET 0, 1 0

7.5.6.2 Setting Description

1. Sn_Exc

Capacity of the exciter or excitation transformer, it shall be configured as its name plate stated.

2. U1n_S1_Exc

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System rated voltage on HV side of the excitation transformer. This setting is used to calculate the
correction coefficient of differential protection of excitation transformer.
If exciter is used, it shall be set as the rated voltage of exciter.

3. U1n_S2_Exc

System rated voltage on LV side of the excitation transformer. This setting is used to calculate the
correction coefficient of differential protection of excitation transformer.
If exciter is used, it shall be set as the rated voltage of exciter.

4. I1n_CT_S1_Exc

Primary rated current of the CT on HV side of the excitation transformer or CT at the terminal of
the exciter.

5. I2n_CT_S1_Exc

Secondary rated current of the CT on HV side of the excitation transformer or CT at the terminal of
the exciter.

6. I1n_CT_S2_Exc

Primary rated current of the CT on LV side of the excitation transformer or CT at the neutral point
of the exciter.

7. I2n_CT_S2_Exc

Secondary rated current of the CT on LV side of the excitation transformer or CT at the neutral
point of the exciter.

8. Opt_Exc

Exciter is used in the system. If this setting is set as ―1‖, that means exciter is used in the generator
system instead of excitation transformer. Otherwise means the contrary.

9. Yy12_Conn_ET

The connection mode of excitation transformer is Yy-12 mode.

Note:
In the symbol of ―Yy-12‖, the first letter ―Y‖ represents the connection mode of windings on HV side,
and the other ―y‖ represents the connection mode of windings on LV side, ―12‖ represents
connection group between HV and LV windings. The following four settings are similar to this one.

10. Dd12_Conn_ET

The connection mode of excitation transformer is Dd-12 mode.

11. Dy11_Conn_ET

The connection mode of excitation transformer is Dy-11 mode.

12. Yd11_Conn_ET

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The connection mode of excitation transformer is Yd-11 mode.

13. Dy1_Conn_ET

The connection mode of excitation transformer is Dy-1 mode.

7.5.6.3 Access Path

Main Menu -> Settings ->System Settings ->ExcSys Settings

7.5.7 Implicit Configuration Settings


The settings in the following list are associated with application-specific primary layout of
generator and exciter, tripping logics. These settings can not be seen on LCD of equipment and
only be viewed and configured on PC through PCSPC software. These settings are usually
configured in factory or configured by field commission engineer according to the design drawing
and project requirement.

7.5.7.1 Setting List

Table 7.5-7 List of implicit configuration settings

No. settings Range Default


1 Cfg_Polar_CT 0-7FFFF 0
2 Cfg_CT_HVS1_Tr Current channel 0-18 Channel 5
3 Cfg_CT_HVS2_Tr Current channel 0-18 Channel 6
4 Cfg_CT_HVS_Tr Current channel 0-18 Channel 7
5 Cfg_CT_LVS_Tr Current channel 0-18 Channel 8
6 Cfg_CT#_HVS_ST1 Current channel 0-18 Channel 10
7 Cfg_CT#_HVS_ST2 Current channel 0-18 Channel 14
8 Cfg_CT_Term_Gen Current channel 0-18 Channel 1
9 Cfg_CT_NP_Gen Current channel 0-18 Channel 2
10 Cfg_CT_Bak_Gen Current channel 0-18 Channel 1
11 Cfg_CT_PwrProt_Gen Current channel 0-18 Channel 1
12 Cfg_CT_S1_Exc Current channel 0-18 Channel 3
13 Cfg_CT_S2_Exc Current channel 0-18 Channel 4
14 Cfg_CT_HVS_ST1 Current channel 0-18 Channel 9
15 Cfg_CT_Br1_ST1 Current channel 0-18 Channel 11
16 Cfg_CT_Br2_ST1 Current channel 0-18 Channel 12
17 Cfg_CT_HVS_ST2 Current channel 0-18 Channel 13
18 Cfg_CT_Br1_ST2 Current channel 0-18 Channel 15
19 Cfg_CT_Br2_ST2 Current channel 0-18 Channel 16
20 Cfg_CT_TrvDiff_Gen Zero-sequence current channel Channel 10
0-10
21 Cfg_CT_NP_Tr Zero-sequence current channel Channel 1
0-10

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22 Cfg_CT_Gap_Tr Zero-sequence current channel Channel 2


0-10
23 Cfg_CT_NP_Br1_ST1 Zero-sequence current channel Channel 3
0-10
24 Cfg_CT_NP_Br2_ST1 Zero-sequence current channel Channel 4
0-10
25 Cfg_CT_NP_Br1_ST2 Zero-sequence current channel Channel 8
0-10
26 Cfg_CT_NP_Br2_ST2 Zero-sequence current channel Channel 9
0-10
27 Cfg_CT_Diff_GTU 00-3F 0017H
28 Cfg_CT_Diff_Tr 00-3F 0017H
29 Cfg_CT_PwrProt_Gen 0/1 0
30 Opt_InputMode_VT_ST 0/1 1
31 Opt_3U0_Gen 0/1 0
32 Cfg_Ext_TrpOutp 0-3FFFFFFF 1FE3FFFE
33 t_Ext_TrpOutp 0 – 0.45 S 0.14
34 kmax_V3rdHDiff_Sta 3-6
35 t_CurrMemory 1.00 – 30.00 S 10
36 K_NeuVTS_VT2 0.10-1.00 0.4
37 K_NeuVTS_OtherVT 0.10-1.00 0.2

7.5.7.2 Setting Description

1. Cfg_Polar_CT

Generally, CT polarity definition is shown as the below table. However if some CT polarity direction
is reversed by incorrect wiring connecting, there is still chance to correct it by configuring this logic
setting easily. Please set the corresponding digit of the logic setting. Bit.1-18 are corresponding to
18 three-phase current channels one by one. If any bit is set as ―0‖, the program will reverse the
current polarity of this channel before calculation.

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Three-phase channel 18

Three-phase channel 17

Three-phase channel 16

Three-phase channel 15

Three-phase channel 14

Three-phase channel 13

Three-phase channel 12

Three-phase channel 10
Three-phase channel 11

Three-phase channel 9

Three-phase channel 8

Three-phase channel 7

Three-phase channel 6

Three-phase channel 5

Three-phase channel 4

Three-phase channel 3

Three-phase channel 2

Three-phase channel 1

No definition

2. Cfg_CT_HVS1_Tr

Configurable setting for deciding which channel is chosen to input three-phase current of HVS1
side of main transformer.

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Following table gives all the choices that user can decide. Only one bit at most can be set as ―1‖
simultaneously.

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Three-phase channel 18

Three-phase channel 17

Three-phase channel 16

Three-phase channel 15

Three-phase channel 14

Three-phase channel 13

Three-phase channel 12

Three-phase channel 10
Three-phase channel 11

Three-phase channel 9

Three-phase channel 8

Three-phase channel 7

Three-phase channel 6

Three-phase channel 5

Three-phase channel 4

Three-phase channel 3

Three-phase channel 2

Three-phase channel 1

No definition
3. Cfg_CT_HVS2_Tr

Configurable setting for deciding which channel is chosen to input three-phase current of HVS2
side of main transformer. The definition is the same to the above table.

4. Cfg_CT_HVS_Tr

Configurable setting for deciding which channel is chosen to input three-phase current of HVS
side of main transformer. This current is specially used for backup protection of main transformer.
The definition is the same to the above table except for the bit0. In this setting, if the bit0 is set as
―1‖, the protection will recognize this directly input current as the whole current of HVS side of main
transformer, otherwise, the protection will automatically add HVS1 and HVS2 side currents
mentioned aboved to be the whole current of HVS side and ignoring the current input from this
channel.

5. Cfg_CT_LVS_Tr ~ Cfg_CT_NP_Br2_ST2

Configurable setting for deciding which channel is chosen to input each current. The definition of
each bit is the same to that of [Cfg_CT_HVS1_Tr]. The actual meaning of each setting is given in
the following table.

No. Settings Specific description

1. Cfg_CT_LVS_Tr Channel selection for LVS current of main transformer


Channel selection for HVS current via high ratio CT of step-down
2. Cfg_CT#_HVS_ST1
transformer1(ST1)
3. Cfg_CT#_HVS_ST2 Channel selection for HVS current via high ratio CT of ST2

4. Cfg_CT_Term_Gen Channel selection for terminal current of generator

5. Cfg_CT_NP_Gen Channel selection for neutral point current of generator

6. Cfg_CT_Bak_Gen Channel selection for backup current of generator

7. Cfg_CT_PwrProt_Gen Channel selection for reverse power metering

8. Cfg_CT_S1_Exc Channel selection for side 1 of excitation transformer or excitor

9. Cfg_CT_S2_Exc Channel selection for side 2 of excitation transformer or excitor

10. Cfg_CT_HVS_ST1 Channel selection for HVS current of ST1

11. Cfg_CT_Br1_ST1 Channel selection for branch 1 at LV side of ST1

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12. Cfg_CT_Br2_ST1 Channel selection for branch 2 at LV side of ST1

13. Cfg_CT_HVS_ST2 Channel selection for HVS current of ST1

14. Cfg_CT_Br1_ST2 Channel selection for branch 1 at LV side of ST1

15. Cfg_CT_Br2_ST2 Channel selection for branch 2 at LV side of ST1

16. Cfg_CT_TrvDiff_Gen Channel selection for transverse differential current


Channel selection for zero sequence current obtained for neutral point of
17. Cfg_CT_NP_Tr
main transformer
Channel selection for zero sequence current obtained for GAP of main
18. Cfg_CT_Gap_Tr
transformer
Channel selection for zero sequence current obtained for neutral point of
19. Cfg_CT_NP_Br1_ST1
branch 1 at LV side of ST1
Channel selection for zero sequence current obtained for neutral point of
20. Cfg_CT_NP_Br2_ST1
branch 2 at LV side of ST1.
Channel selection for zero sequence current obtained for neutral point of
21. Cfg_CT_NP_Br1_ST2
branch 1 at LV side of ST2
Channel selection for zero sequence current obtained for neutral point of
22. Cfg_CT_NP_Br2_ST2
branch 2 at LV side of ST2

6. Cfg_CT_Diff_GTU

Logic setting of selecting three-phase current channels for differential protection of generator
transformer unit. If any bit is set as ‖1‖, it means corresponding group is used in differential
protection of generator transformer unit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT#_HVS_ST

CT_HVS2_Tr

CT_HVS1_Tr
CT_HVS_ST

CT_NP_Gen
CT_LVS_ST

7. Cfg_CT_Diff_Tr

Logic setting of selecting three-phase current channels for differential protection of main
transformer. If the bit is set as ‖1‖, it means this group is used in the differential protection.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT#_HVS_ST

CT_HVS2_Tr

CT_HVS1_Tr
CT_HVS_ST
CT_LVS_ST

CT_LVS_Tr

8. Cfg_CT_PwrProt_Gen

Logic setting of selecting three-phase current CT for reverse power protection of generator.

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―0‖: CT of P level.

―1‖: CT of S level.

9. Opt_InputMode_VT_ST

Input mode of voltage of step-down transformer.

0: phase-to-ground voltage

1: phase-to-phase voltage

10. Opt_3U0_Gen

Whether generator terminal zero sequence voltage is calculated zero sequence voltage.

0: generator terminal zero sequence voltage is measured zero sequence voltage.

1: generator terminal zero sequence voltage is calculated zero sequence voltage.

11. Cfg_Ext_TrpOutp

Logic setting to configure which output relays will delay dropoff since corresponding tripping signal
dropoff. If any bit is set as ‖1‖, the corresponding output relay will delay dropoff since
corresponding tripping signal dropoff. DDO (delay dropoff) time is decided by [t_Ext_TrpOutp].

12. t_Ext_TrpOutp

DDO (delay dropoff) time of tripping output relays, its default value is 140ms.

13. kmax_V3rdHDiff_Sta

Differential current adjust coefficient for third harmonic differential current protection, 3.0 generally.

14. t_CurrMemory

Memory time of current, 10s generally.

15. K_NeuVTS_VT2

Ratio coefficient to judge whether neutral line failure of VT2 (interturn fault protection used VT)
happens, 0.4 generally.

16. K_NeuVTS_OtherVT

Ratio coefficient to judge whether neutral line failure of other VT (except for VT2) happens, 0.2
generally.

7.6 Protection Settings


7.6.1 Settings of Differential Protection of Generator-transformer Unit (GTU)

7.6.1.1 Settings List

Table 7.6-1 List of generator-transformer unit differential protection settings

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No. Symbol Range Step Default


1 I_Pkp_PcntDiff_GTU 0.10–1.50 (Ie) 0.01 (Ie) 0.3
2 I_InstDiff_GTU 2.00–14.00 (Ie) 0.01 (Ie) 6
3 I_AlmDiff_GTU 0.10–1.00 (Ie) 0.01 (Ie) 0.1
4 Slope1_PcntDiff_GTU 0.00–0.50 0.01 0.1
5 Slope2_PcntDiff_GTU 0.50–0.80 0.01 0.7
6 k_Harm_PcntDiff_GTU 0.10-0.35 0.01 0.15
7 TrpLog_Diff_GTU 00000000-3FFFFFFF 1 FFFF
Logic setting ―1‖ - enable, ―0‖ – disable
8 En_InstDiff_GTU 0, 1 1
9 En_PcntDiff_GTU 0, 1 1
10 Opt_Inrush_Ident_GTU 0, 1 0
11 Opt_CTS_Blk_PcntDiff_GTU 0, 1 0

7.6.1.2 Setting Description

1. I_Pkp_PcntDiff_GTU

This is pickup setting of percentage current differential protection, which is also the setting of fault
detector of percentage differential protection. It shall be higher than maximum unbalance
differential current when the generator-transformer unit operate on normal rated load.

2. I_InstDiff_GTU

Setting of unrestrained differential protection.

3. I_AlmDiff_GTU

Differential current alarm setting of generator-transformer unit. It shall be higher than normal
unbalance differential current and lower than [I_Pkp_PcntDiff_GTU].

4. Slope1_PcntDiff_GTU

Setting of the first slope of percentage differential protection.

5. Slope2_PcntDiff_GTU

Maximum value of restraint coefficient of the differential characteristic curve.

6. k_Harm_PcntDiff_GTU

The ratio setting of 2nd harmonic component in differential current. 0.15 is recommended.

7. TrpLog_Diff_GTU

Tripping output logic setting of differential protection is used to specify which breaker or breakers
will be tripped by this protection. This word comprises 30 binary bits as follows and is displayed as
a hexadecimal number from 00000000H to 3FFFFFFFH on LCD of equipment. The tripping output
logic settings is specified as follows:

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bit 29 … 12 11 10 9 8 7 6 5 4 3 2 1 0
rpOutput29

TrpOutp12

TrpOutp10
TrpOutp11

TrpOutp9

TrpOutp8

TrpOutp6

TrpOutp5

TrpOutp4

TrpOutp3

TrpOutp2

TrpOutp1
TrpOutp7
Function

En_Trp
……

Note:
―TrpOutp 1‖ just means to drive tripping output channel 1. Set bit0 as ―1‖ means this protection
element will trip breaker or breakers. The bit corresponding to the breaker to be tripped shall be
set as―1‖ and other bits shall be ―0‖. For example, if differential protection is defined to trip breaker
5 (tripping output channel 5), the bit0 and bit5 bit shall be set as ―1‖ and other bits ―0‖. Then a
hexadecimal number 00000021H is formed as the tripping output logic setting.
Please note that tripping output logic settings of the equipment have to be set on basis of
application-specific drawings.
All the tripping logic settings mentioned below is defined as same as this one.

8. En_InstDiff_GTU

Unrestrained instantaneous differential protection enabled. If this setting is set as ―1‖, it means this
protection is enabled. Otherwise it means the protection is disabled.

9. En_PcntDiff_GTU

Percentage differential protection enabled.

10. Opt_Inrush_Ident_GTU

The logic setting to select the method to identify inrush current of transformer.
―1‖ means to use the second harmonic restraint principle. ―0‖ means to use waveform distortion
discrimination principle.

11. Opt_CTS_Blk_PcntDiff_GTU

If this logic setting is set as ―1‖, it means percentage differential protection will be blocked when CT
circuit failure happens. Otherwise it means the function is disabled.

7.6.1.3 Access Path

Main Menu -> Settings -> GTUDiffProt Settings

7.6.2 Settings of Differential Protection of Main Transformer

7.6.2.1 Settings List

Table 7.6-2 List of main transformer differential protection settings

No. Symbol Range Step Default


1 I_Pkp_PcntDiff_Tr 0.10–1.50 (Ie) 0.01 (Ie) 0.3

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2 I_InstDiff_Tr 2.00–14.00 (Ie) 0.01 (Ie) 6


3 I_AlmDiff_Tr 0.05–1.00 (Ie) 0.01 (Ie) 0.1
4 Slope1_PcntDiff_Tr 0–0.50 0.01 0.1
5 Slope2_PcntDiff_Tr 0.50–0.80 0.01 0.7
6 k_Harm_PcntDiff_Tr 0.10-0.35 0.01 0.15
7 TrpLog_Diff_Tr 00000000-3FFFFFFF 1 FFFF
Logic setting ―1‖ - enable, ―0‖ – disable
8 En_InstDiff_Tr 0, 1 1
9 En_PcntDiff_Tr 0, 1 1
10 En_DPFC_Diff_Tr 0, 1 0
11 Opt_Inrush_Ident_Tr 0, 1 0
12 Opt_CTS_Blk_PcntDiff_Tr 0, 1 0

7.6.2.2 Preparation knowledge of transformer

1) Calculate rated secondary current at each side of transformer

Sn
I b1n  Equation 7.6-1
3U b1n

Where:

S n is the maximum rated capacity of all windings(i.e. [Sn_Tr]).

U b1n is the rated phase-to-phase voltage at the calculated side of the transformer (i.e.

[U1n_HVS_Tr] or [U1n_LVS_Tr].)

2) Calculate rated secondary current at each side of transformer

I b1n
Ib2n  Equation 7.6-2
nbLH

Where:

I b1n is the rated primary current at the calculated side of transformer.

nbLH is the ratio of CT at the calculated side of transformer.

3) Calculate the correction coefficient of each side of transformer

I b 2 nb
K ph  Equation 7.6-3
I b2n

Where:

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I b 2 n is the rated secondary current at the calculated side.

I b 2 nb is the rated secondary current of base side.

The currents used in the following analysis have been corrected, that means the currents are the
products of the original secondary current of each side multiplying its own correction coefficient

( K ph ).

7.6.2.3 Phase shift compensation

By defining which particular connection group the protected transformer belongs to, the proper
calculation routine will be applied.

The following transforming method is based on the assumptions listed here:

• CTs at each side of transformer are connected in star type.

• Secondary currents of each CT are connected to the equipment directly.

• The positive polarity of CT at HV and MV side is at busbar side and that at LV side is at branch
side or generator side.

•The secondary current phase shift compensation for all CTs are achieved by software, Y→Δ
transform method is used for this purpose. For connection Y/Δ-11, the correction equations are as
follows:

At side Y:

 '  

 I A  ( I A  I B)/ 3

 '  
I B  (I B  I C ) / 3 Equation 7.6-4
 '  
 I C  ( I C  I A) / 3

At side Δ:

' 
 I a  I a
' 
I b  I b Equation 7.6-5
 ' 
I c  Ic

Where:

  
I A , I B , I C are the secondary currents of CT at side Y.

  
I ' A , I ' B , I ' C are the corrected current of each phase at side Y.

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  
I a , I b , I c are the secondary currents of CT at side Δ.

  
I ' a , I ' b , I ' c are the corrected currents of each phase at side Δ;

For other connection type,the current can be calculated according to the equations listed above.
The connection type can be selected by some logic settings (refer to power system settings of
main transformer in Section 7.5.3).

Note:

If your actual transformer connection group is not included in above two groups, please let us
know before you make the order.

7.6.2.4 Setting Description

1. I_Pkp_PcntDiff_Tr

This is pickup setting of percentage current differential protection, which is also the setting of fault
detector of percentage differential protection. It shall be higher than maximum unbalanced current
of the transformer during normal rated load, i.e.

I cdqd  K rel ( K er  U  m) I e Equation 7.6-6

Where:

I cdqd represents the setting [I_Pkp_PcntDiff_Tr].

I e is secondary calculated rated current of transformer;

K rel is reliability coefficient (generally K rel = 1.3 - 1.5);

K er is the ratio error of CT (=0.032, for class 10P; =0.012, for class 5P and class TP);

U is the maximum deviation (in percentage of rated voltage) due to tap changing.
m is the error caused by the difference between ratios of CT at all side, 0.05 is recommended.
For practical engineering application, I cdqd =(0.2 - 0.5) I e is reasonable and unbalanced current

in differential circuit during maximum load of transformer shall be measured.

2. I_InstDiff_Tr

Setting of unrestrained instantaneous differential protection, which is used to clear serious internal

fault quickly and prevent operation delay caused by CT saturation. The setting I cdsd (i.e.

[I_InstDiff]) shall be greater than inrush current and maximum unbalanced current due to external
fault or asynchronous closing, generally

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I cdsd  K  I e Equation 7.6-7

Where:
K is a multiple depending on capacity of transformer and the system reactance, 6 – 8 is
recommended.

I e is secondary calculated rated current of transformer.

Sensitivity coefficient of unrestrained instantaneous differential protection K sen shall be calculated

according to the phase-to-phase solid short circuit fault in normal operation condition at installed

point of the relay. K sen ≥ 1.2 is required.

3. I_AlmDiff_Tr

Differential current alarm setting of main transformer. It shall be higher than normal unbalance
differential current and lower than [I_Pkp_PcntDiff_Tr].

4. Slope1_PcntDiff_Tr

Setting of the first slope of percentage differential protection, it shall be:

K bl1  K er  K rel Equation 7.6-8

Where:

K er is the error of current ratio of CT, takes 0.1.

K rel is reliability coefficient, (generally K rel = 1.0 – 2.0);

K bl1 is 0.10-0.20 generally.

Sensitivity check for percentage differential protection

The sensitivity coefficient K sen shall be calculated according to phase-to-phase short circuit on

outlet of transformer protected by the differential relay in minimum operation mode. From the

calculated minimum short circuit current I k . min and relevant restraint current I res , corresponding

pickup current I op will be found in the operation characteristic curve of percentage differential

relay, and then the sensitivity coefficient is:

K sen  I k . min / I op Equation 7.6-9

K sen ≥1.2 is required.

5. Slope2_PcntDiff_Tr

Setting of second slope of percentage differential protection.

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Calculation of secondary unbalanced current:


--- For two winding transformer

I unb. max  ( K ap K cc K er  U  m) I k . max Equation 7.6-10

Where:

Definition of K er , U and m have been mentioned above;

K cc is the ―same type coefficient‖ of CT, 1.0 is considered.

I k . max is the maximum value of fundamental component of external short circuit fault current

(secondary).

K ap is the coefficient of DC component. K ap = 1.0 if CT at both sides are class TP, or K ap = 1.5 -

2.0 if CT at both sides are class P.


--- For three winding transformer
Take external short circuit fault at LV side as example:

I unb. max  K ap K cc K er I k . max  U h I k .h. max  U m. I k .m. max  mI I k .I . max  mII I k .II . max Equation 7.6-11

Where:

Definition of K er , K cc and K ap have been mentioned above;

U h : maximum deviations (in percentage of rated voltage) on HV side due to tap changing.

U m : maximum deviations (in percentage of rated voltage) on MV side due to tap changing.

I k . max : is the maximum value of fundamental component of short circuit secondary current flowing

through CT at the fault side during external fault at LV side.

I k .h. max , I k .m. max : the maximum value of periodic component of short circuit secondary current

flowing through CT on tap changing sides during external fault at LV side.

I k .I . max I k .II . max


and are the periodic components of secondary currents flowing through CT at
other sides during external fault at LV side.

mI and mII are errors caused by difference between ratios of CT (auxiliary CT included if
any) at relevant sides.
Second slope of percentage differential protection is:

I unb. max*  I cdqd *  3k bl1


k bl 2  Equation 7.6-12
I k . max*  3

Where:

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Definition of I unb. max* , I cdqd * and I k . max* are almost same to I unb. max , I cdqd and

I k . max mentioned above, and the only difference is they are per unit values. I e (secondary

calculated rated current of transformer) is the base value of per unit.

k bl 2 =0.70 is recommended.

6. k_Harm_PcntDiff_Tr

Restraint coefficient of second harmonic. This parameter is the blocking threshold of second
harmonics involving in differential current to against inrush current when the transformer is
energized. The differential protection will be blocked when the percentage of second harmonics
reaches the threshold because the percentage of second harmonics is high in inrush current but
low in fault current. It is recommended that the parameter is set to be 15% -20%, 15% is
recommended.

7. TrpLog_DIff_Tr

Tripping output logic setting of differential protection is used to specify which breaker or breakers
will be tripped by this protection.

8. En_InstDiff_Tr

Unrestrained instantaneous differential protection is enabled or not. If this setting is set as ―1‖, it
means this protection is enabled. Otherwise, it means the protection is disabled.

9. En_PcntDiff_Tr

Percentage differential protection is enabled or not. If this setting is set as ―1‖, it means this
protection is enabled. Otherwise, it means the protection is disabled.

10. En_DPFC_Diff_Tr

DPFC percentage differential protection is enabled or not. If this setting is set as ―1‖, it means this
protection is enabled. Otherwise, it means the protection is disabled.

11. Opt_Inrush_Ident_Tr

Inrush current blocking principle selection:


―0‖, discrimination by harmonics.
―1‖, waveform distortion criteria is used.

12. Opt_CTS_Blk_PcntDiff_Tr

If this logic setting is set as ―1‖, it means percentage differential protection will be blocked when CT
circuit failure happens. Otherwise, it means the function is disabled.

7.6.2.5 Access Path

Main Menu -> Settings -> TrProt Settings -> TrDiffProt Settings

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7.6.3 Settings of Restricted Earth-fault Protection of Main Transformer

7.6.3.1 Settings List

Table 7.6-3 List of main transformer restricted earth-fault protection settings

No. Symbol Range Step Default


1 I_Pkp_PcntREF_Tr 0.10–1.50 (Ie) 0.01 (Ie) 0.3
2 I_InstREF_Tr 2.00–14.00 (Ie) 0.01 (Ie) 6
3 I_Alm_REF_Tr 0.05–1.00 (Ie) 0.01 (Ie) 0.2
4 Slope_REF_Tr 0.30–0.80 0.01 0.5
5 TrpLog_REF_Tr 00000000-3FFFFFFF 1 FFFF
Logic setting ―1‖ - enable, ―0‖ – disable
6 En_InstREF_Tr 0, 1 1
7 En_PcntREF_Tr 0, 1 1

7.6.3.2 Calculate the correction coefficient of each side of restricted earth-fault protection

K TA
K lph   K lb
K TA _ max
Equation 7.6-13
K TA max
K lb 
K TA min

Where:

K TA is the ratio of CT at the calculated side of restricted earth-fault protection.

KTA_ max is the maximum value of ratio of CT at each side of restricted earth-fault protection.

K TA _ min is the minimum value of ratio of CT at each side of restricted earth-fault protection.

The currents used in the following section have been corrected, that means the currents are the
products of the original zero sequence current of each side multiplying its own correction

coefficient ( K ph ). If K lb is bigger than 16, CT ratio will be judged unreasonable by the device.

7.6.3.3 Setting Description

1. I_Pkp_PcntREF_Tr

This is pickup setting of percentage restricted earth-fault protection of main transformer, which is
also the setting of fault detector of percentage restricted earth-fault protection. It shall be higher
than maximum unbalanced zero sequence current of the transformer during normal rated load, i.e.

I 0cdqd  K rel ( K er  m) I n Equation 7.6-14

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Where:

I 0cdqd represents the setting [I_Pkp_PcntREF_Tr].

I n is secondary rated current of main transformer;

K rel is reliability coefficient (generally K rel = 1.3 - 1.5);

K er is the ratio error of CT (=0.032, for class 10P; =0.012, for class 5P and class TP);

m is the error caused by the difference between ratios of CT at all side, 0.05 is recommended.
For practical engineering application, I cdqd =(0.3 - 0.5)I n is reasonable and unbalanced current

in zero sequence differential circuit during maximum load of transformer shall be measured. 0.3 I n

is recommended.

2. I_InstREF_Tr

Setting of unrestrained instantaneous restricted earth-fault protection of main transformer.

3. I_Alm_REF_Tr

Zero sequence differential current alarm setting of main transformer. It shall be higher than normal
unbalance differential zero sequence current and lower than [I_Pkp_PcntREF_Tr].

4. Slope_REF_Tr

Restraint coefficient of restricted earth-fault protection of main transformer.

5. TrpLog_REF_Tr

Tripping output logic setting of restricted earth-fault protection of main transformer. It is used to
specify which breaker or breakers will be tripped by this protection.

6. En_InstREF_Tr

Unrestrained instantaneous restricted earth-fault protection of main transformer is enabled or not.


If this setting is set as ―1‖, it means this protection is enabled. Otherwise, it means the protection is
disabled.

7. En_PcntREF_Tr

Percentage restricted earth-fault protection of main transformer is enabled or not. If this setting is
set as ―1‖, it means this protection is enabled. Otherwise, it means the protection is disabled.

7.6.3.4 Access Path

Main Menu -> Settings -> TrProt Settings -> TrREFProt Settings

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7.6.4 Settings of Phase-to-phase fault Protection of Main Transformer

7.6.4.1 Setting List

Table 7.6-4 Definition of phase to phase fault protection settings

No. Symbol Range Step Default


1 V_NegOV_VCE_Tr 1.00 V– 20.00 V 0.01 V 4
2 Vpp_UV_VCE_Tr 2.00V-100.00V 0.01 V 60
3 I_OC1_Tr 0.10 A – 100.00 A 0.01 A 15
4 t_OC1_Tr 0.00 s – 10.00 s 0.01 s 1
5 TrpLog_OC1_Tr 00000000-3FFFFFFF 1 FFFF
6 I_OC2_Tr 0.10 A – 100.00 A 0.01 A 10
7 t_OC2_Tr 0.00 s – 10.00 s 0.01 s 2
8 TrpLog_OC2_Tr 00000000-3FFFFFFF 1 FFFF
9 Z1_Fwd_Tr 0.00 – 100.00 Ohm 0.01Ohm 20
10 Z1_Rev_Tr 0.00 – 100.00 Ohm 0.01Ohm 20
11 t_Z1_Tr 0.00 – 10.00 s 0.01 s 1
12 TrpLog_Z1_Tr 00000000-3FFFFFFF 1 FFFF
13 Z2_Fwd_Tr 0.00 – 100.00 Ohm 0.01Ohm 20
14 Z2_Rev_Tr 0.00 – 100.00 Ohm 0.01Ohm 20
15 t_Z2_Tr 0.00 – 10.00 s 0.01 s 1
16 TrpLog_Z2_Tr 00000000-3FFFFFFF 1 FFFF
17 I_Alm_OvLd_Tr 0.10 – 100.00 A 0.01 A 6
18 t_Alm_OvLd_Tr 0.00 – 10.00 s 0.01 s 8
19 I_InitCool1_OvLd_Tr 0.10 – 100.00 A 0.01 A 5.5
20 t_InitCool1_OvLd_Tr 0.00 – 10.00 s 0.01 s 9
21 I_InitCool2_OvLd_Tr 0.10 – 100.00 A 0.01 A 5.5
22 t_InitCool2_OvLd_Tr 0.00 – 10.00 s 0.01 s 9
Logic setting ―1‖ - enable, ―0‖ – disable
23 En_VCE_Ctrl_OC1_Tr 0/1 0
24 En_VCE_Ctrl_OC2_Tr 0/1 0
25 En_LVS.VCE_Ctrl_OC_Tr 0/1 0
26 En_Mem_Curr_Tr 0/1 0
27 Opt_VTS_Ctrl_OC_Tr 0/1 0
28 En_OvLd_Tr 0/1 0
29 En_InitCool1_OvLd_Tr 0/1 0
30 En_InitCool2_OvLd_Tr 0/1 0

7.6.4.2 Setting Description

1. V_NegOV_VCE_Tr

This is setting of negative sequence voltage control element of main transformer. Setting and
displayed value of negative sequence voltage are U2.
Setting of this relay shall be higher than measured imbalance voltage during normal operation

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condition, generally

U op.2  (0.06  0.08)U n Equation 7.6-15

Where:

U n is secondary rated phase-to-phase voltage.

Sensitivity factor of negative sequence voltage relay shall be checked by

U k .2. min
K sen  Equation 7.6-16
U op.2

Where U k .2. min is minimum secondary negative sequence voltage at location of the relay during

phase-to-phase metallic short circuit fault at end of backup protected zone. K sen ≥2.0 is required

for near backup protection and K sen ≥1.5 for remote backup protection.

Note:
When sensitivity factor is checked for current relay and voltage relay, unfavorable normal system
operation condition and unfavorable type of short circuit fault shall be adopted. If sensitivity factor
of under voltage relay is not high enough, function of composite voltage on LV side initiation can
be enabled. Voltage is taken from LV side by configure logic setting [En_LVS.VCE_Ctrl_OC_Tr].

2. Vpp_UV_VCE_Tr

Voltage of voltage control element is taken from LV side usually (logic setting
[En_LVS.VCE_Ctrl_OC_Tr] is set as 1.). Undervoltage setting shall be higher than the lowest
voltage during starting process of the largest motor connected with the LV busbar.
Setting of phase-to-phase under voltage of composite voltage control element. It shall coordinate
with generator starting condition.
Setting shall be higher than possible minimum voltage during normal operation, namely

U min
U op  Equation 7.6-17
K rel K r

Where K rel is reliability factor, 1.10 – 1.20; K r is release factor, 1.05 – 1.25; U min is possible

minimum voltage during normal operation, 0.9 times of secondary rated line voltage generally.
When VT on HV side of the transformer is used for the under voltage relay

U op  0.7U n Equation 7.6-18

Where U n is secondary rated line voltage.

When step-up transformer is used in a power plant and VT on generator side is used for under
voltage relay, its setting shall be higher than under voltage during operation of generator without

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excitation,

U op  (0.5  0.6)U n Equation 7.6-19

Where U n is secondary rated line voltage.

Sensitivity factor of under voltage relay shall be checked by

U op
K sen  Equation 7.6-20
U c. max

Where U c. max is maximum secondary residual voltage at location of the relay when

phase-to-phase metallic short circuit fault occurs at the check point during operation condition for

calculation. K sen ≥1.5 is required for near backup protection and K sen ≥1.2 for remote backup

protection.

3. I_OC1_Tr

Setting of overcurrent protection stage 1.


Setting of overcurrent relay shall be higher than rated current of transformer,

K rel
I op  Ie Equation 7.6-21
Kr

where K rel is reliability factor, 1.2 generally; K r is release factor, 0.85 – 0.95; I e is secondary

rated current.
Sensitivity factor of overcurrent relay shall be checked by following:

I k( .2min
)
K sen  Equation 7.6-22
I op

( 2)
where I k . min is minimum fault current through location of the relay during phase-to-phase metallic

short circuit at end of backup protected section. K sen ≥ 1.3 is required for near backup protection

and K sen ≥ 1.2 for remote backup protection.

4. t_OC1_Tr

The time delay of stage 1 of overcurrent protection. It shall coordinate with main protection only
and oscillation period is not needed to be considered. It is set as 0.5 s generally.

5. TrpLog_OC1_Tr

Tripping output logic setting of the time delay of over current protection stage 1, please refer to
section 7.3.1.

6. I_OC2_Tr

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Setting of overcurrent protection stage 2.

7. t_OC2_Tr

The first time delay of overcurrent protection stage 2.

8. TrpLog_OC2_Tr

Tripping output logic setting of the first time delay of over current protection stage 2, please refer to
section 7.3.1

9. Z1_Fwd_Tr

Stage 1 of positive direction impedance setting of phase-to-phase impedance protection. Here


positive direction means the direction is pointing to the transformer instead of generator itself.
If the value of this setting is greater than the next one, then the characteristic of distance protection
is set as excursive impedance circle; if it is equal to the next one, the characteristic is whole
impedance circle; if the next one is set as ―0‖, the characteristic becomes directional impedance.
Generally, low impedance protection is considered as the backup protection of transformer in case
that voltage-controlled overcurrent protection cannot satisfy the sensitivity requirement of
transformer.
Setting of this impedance relay shall coordinate with that of HV side outlet, namely

Z op  K rel K inf Z Equation 7.6-23

Where K rel is reliability factor, 0.8 generally; K inf is enhanced factor, taking minimum value of

various operation conditions; Z is setting of impedance protection of coordinating HV side outlet;


Sensitivity shall be checked by phase-to-phase short circuit on end of designated protected zone,
namely

Z op
K sen  Equation 7.6-24
Z

Where Z is equivalent secondary impedance value of designated protected section. K sen ≥1.3

is required.
When this direction of impedance relay points to transformer.
The forward setting can be based on enough sensitivity for fault on terminal of generator and
referred to equation herein above. Reverse impedance equals to 5% - 10% of forward impedance.
Reverse setting shall be lower than setting of the shortest zone 1 of impedance protection of outlet
from this side busbar.

10. Z1_Rev_Tr

Stage 1 of negative direction impedance setting of distance protection. In general, this setting is
set as 5-10% of the positive direction impedance setting. Negative direction impedance setting
should be smaller than the impedance setting of stage 1 of impedance protection of the shortest
outline of local busbar.

11. t_Z1_Tr

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The first time delay of distance protection stage 1.

12. TrpLog_Z1_Tr

Tripping output logic setting of distance protection stage 1.

13. Z2_Fwd_Tr

Stage 2 of ppositive direction impedance setting of phase-to-phase impedance protection.

14. Z2_Rev_Tr

Stage 2 of negative direction impedance setting of distance protection.

15. t_Z2_Tr

The time delay of distance protection stage 2.

16. TrpLog_Z2_Tr

Tripping output logic setting of distance protection stage 2.

17. I_Alm_OvLd_Tr

Current setting of overload alarm.

18. t_Alm_OvLd_Tr

Time delay of overload alarm.

19. I_InitCool1_OvLd_Tr

Current setting of stage 1 of cooling initiation of main transformer.

20. t_InitCool1_OvLd_Tr

Time delay of stage 1 of cooling initiation of main transformer.

21. I_InitCool2_OvLd_Tr

Current setting of stage 2 of cooling initiation of main transformer.

22. t_InitCool2_OvLd_Tr

Time delay of stage 2 of cooling initiation of main transformer.

23. En_VCE_Ctrl_OC1_Tr

Logic setting of overcurrent protection stage 1 controlled by voltage element.


―1‖: the overcurrent protection stage 1 is controlled by voltage element.
―0‖: the protection is not controlled by voltage element.

24. En_VCE_Ctrl_OC2_Tr

Logic setting of overcurrent protection stage2 controlled by voltage element.

25. En_LVS.VCE_Ctrl_OC_Tr

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Logic setting of overcurrent protection controlled by LV side VCE.

26. En_Mem_Curr_Tr

Logic setting of memory function of current.

Note:
For generator with self parallel excitation system, the memory function of transformer is usually
disabled for phase to phase backup protection. But if it is enabled, the overcurrent protection must
be configured as voltage controlled overcurrent protection.

27. Opt_VTS_Ctrl_OC_Tr

Protection performance during VT circuit failure.


―1‖: when VT circuit failure at one side is detected, voltage control element at the same side will be
disabled but overcurrent relay on the same side can still be controlled by voltage control elements
of other side if corresponding logic setting is set as ―1‖.
―0‖: when VT circuit failure at one side is detected, the overcurrent relay will become an
overcurrent relay without voltage element control.

28. En_OvLd_Tr

Logic setting of enabling overload alarm of main transformer.

29. En_InitCool1_OvLd_Tr

Logic setting of enabling stage 1 of cooling initiation of main transformer.

30. En_InitCool1_OvLd_Tr

Logic setting of enabling stage 2 of cooling initiation of main transformer.

7.6.4.3 Access Path

Main Menu -> Settings -> TrProt Settings -> TrPPFBakProt Settings

7.6.5 Settings of Earth-fault Protection of Main Transformer

7.6.5.1 Setting list

Table 7.6-5 Definition of earth fault protection settings of main transformer

No. Symbol Range Step Default


1 V_ROV_VCE_Tr 2.00 –100.00V 0.01V 10
2 I_ROC1_Tr 0.10 –100.00A 0.01A 10
3 t_ROC11_Tr 0.00–10.00s 0.01s 1
4 TrpLog_ROC11_Tr 00000000-3FFFFFFF 1 0007
5 t_ROC12_Tr 0.00–10.00s 0.01s 1.5
6 TrpLog_ROC12_Tr 00000000-3FFFFFFF 1 0007
7 I_ROC2_Tr 0.10–100.00A 0.01A 10

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8 t_ROC21_Tr 0.00– 10.00s 0.01 s 2


9 TrpLog_ROC21_Tr 00000000-3FFFFFFF 1 0007
10 t_ROC22_Tr 0.00– 10.00s 0.01s 2.5
11 TrpLog_ROC22_Tr 00000000-3FFFFFFF 1 0007
12 Ip_InvROC_Tr 0.50-20.00 0.01 5
13 Tp_InvROC_Tr 0.05-10.00 0.01 0.1
14 tmin_InvROC_Tr 0.00– 10.00s 0.01s 0.1
15 Opt_InvROC_Tr 0-3 1 0
16 TrpLog_InvOC_Tr 00000000-3FFFFFFF 1 FFFE
17 V_ROV1_Gap_Tr 2.00 – 220.00 V 0.01 V 150
18 t_ROV11_Gap_Tr 0.00 – 10.00 s 0.01 s 0.5
19 TrpLog_ROV11_Gap_Tr 00000000-3FFFFFFF 1 0006
20 t_ROV12_Gap_Tr 0.00 – 10.00 s 0.01 s 1.5
21 TrpLog_ROV12_Gap_Tr 00000000-3FFFFFFF 1 0006
22 I_ROC1_Gap_Tr 0.10–100.00A 0.01A 4
23 t_ROC11_Gap_Tr 0.00 – 10.00 s 0.01 0.5
24 TrpLog_ROC11_Gap_Tr 00000000-3FFFFFFF 1 0006
25 t_ROC12_Gap_Tr 0.00 – 10.00 s 0.01 0.5
26 TrpLog_ROC12_Gap_Tr 00000000-3FFFFFFF 1 0006
27 V_Alm_ROV_LVS_Tr 5.00 – 100.00V 0.01 V 100
28 t_Alm_ROV_LVS_Tr 0.00 – 10.00s 0.01s 0.5
logic setting ―1‖ - enable, ―0‖ – disable
29 En_VCE.ROV_Ctrl_ROC1_Tr 0/1 0
30 En_VCE.ROV_Ctrl_ROC2_Tr 0/1 0
31 En_Dir_Ctrl_ROC1_Tr 0/1 0
32 En_Dir_Ctrl_ROC2_Tr 0/1 0
33 En_Harm_Ctrl_ROC1_Tr 0/1 0
34 En_Harm_Ctrl_ROC2_Tr 0/1 0
35 En_Alm_ROV_LVS_Tr 0/1 0

7.6.5.2 Setting Description

1. V_ROV_VCE_Tr

Setting (3U0) of zero-sequence voltage control element for zero-sequence overcurrent protection.

2. I_ROC1_Tr

Setting of stage 1 of zero-sequence overcurrent protection


This setting shall coordinate with unrestraint main protection or stage 1 or 2 of zero sequence
overcurrent relay of adjacent power line.

I op.o.I  K rel KbrI I op.o.1I Equation 7.6-25

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Where:

I op.o.I is setting of stage 1 of zero sequence overcurrent relay,

K brI is branch factor of zero sequence current which is ratio of zero sequence current passing

through the relay and passing through the faulty line during ground fault at end of protected zone
of stage 1 of power line zero sequence overcurrent protection, maximum value for various
operation conditions is taken;

K rel is reliability factor, 1.1 generally;

I op.o.1I is setting of relevant stage of coordinating line protection.

Sensitivity factor of zero sequence overcurrent relay shall be checked by

3I k .o. min
K sen  Equation 7.6-26
I op.o

Where:

3I k .o. min is minimum secondary zero sequence current passing through location of the relay

during ground fault at end of protected zone; I op.o is this setting. K sen ≥1.5 Is required.

3. t_ROC11_Tr

Time delay 1 of stage 1 of zero-sequence overcurrent protection


When earth fault occurs on near end of HV side outlet of startup/standby transformer, it is
protected by both this protection and zero-sequence overcurrent protection stage 2 on remote end,
so the time delay setting of this protection is

t  t II  t Equation 7.6-27

Where:
t is time delay [t_ROC11_Tr].
t II is time delay of zero-sequence overcurrent protection stage2 on remote end.
t is the step difference of delay.
4. TrpLog_ROC11_Tr

Tripping output logic setting of zero-sequence overcurrent protection stage 1 with time delay 1

5. t_ROC12_Tr

Time delay 2 of stage 1 of zero-sequence overcurrent protection

6. TrpLog_ROC12_Tr

Tripping output logic setting of zero-sequence overcurrent protection stage 1 with time delay 2

7. I_ROC2_Tr

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Setting of stage 2 of zero-sequence overcurrent protection


This setting shall coordinate with backup stage of zero sequence overcurrent relay of adjacent
power line.

I op.o.II  K rel K brII I op.o.1II Equation 7.6-28

Where:

I op.o.II is setting of stage 2 of zero sequence overcurrent relay,

K brII is branch factor of zero sequence current which is ratio of zero sequence current passing

through the relay and passing through the faulty line during ground fault at end of protected zone
of backup stage of power line zero sequence overcurrent protection, maximum value for various
operation conditions is taken;

K rel is reliability factor, 1.1 generally;

I op.o.1II is current setting of backup stage of zero sequence overcurrent protection of coordinating

line.

8. t_ROC21_Tr

Delay 1 of stage 2 of zero-sequence overcurrent protection.

9. TrpLog_ROC21_Tr

Tripping output logic setting of zero-sequence overcurrent protection stage 2 with time delay 1.

10. t_ROC22_Tr

Time delay 2 of stage 2 of zero-sequence overcurrent protection.

11. TrpLog_ROC22_Tr

Tripping output logic setting of zero-sequence overcurrent protection stage 2 with time delay 2

12. Ip_InvROC_Tr

Current setting of inverse-time overcurrent protection of main transformer.

13. Tp_InvROC_Tr

Time multiplier setting of inverse-time overcurrent protection of main transformer.

14. tmin_InvROC_Tr

Minimum time delay of inverse-time overcurrent protection of main transformer.

15. Opt_InvROC_Tr

Logic setting for selecting operating characteristic curve of inverse-time overcurrent protection of
main transformer.
0: normal inverse-time characteristic

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1: very inverse-time characteristic


2: extremely inverse-time characteristic
3: long-time inverse-time characteristic

16. TrpLog_InvOC_Tr

Tripping output logic setting of inverse-time overcurrent protection of main transformer.

17. V_ROV1_Gap_Tr

Voltage setting of gap zero-sequence overvoltage protection

18. t_ROV11_Gap_Tr

Time delay 1 of gap zero-sequence overvoltage protection

19. TrpLog_ROV11_Gap_Tr

Tripping output logic setting of gap zero-sequence overvoltage protection with time delay 1

20. t_ROV12_Gap_Tr

Time delay 2 of gap zero-sequence overvoltage protection

21. TrpLog_ROV12_Gap_Tr

Tripping output logic setting of gap zero-sequence overvoltage protection with time delay 2

22. I_ROC1_Gap_Tr

Current setting of gap zero-sequence overcurrent protection

23. t_ROC11_Gap_Tr

Time delay 1 of gap zero-sequence overcurrent protection

24. TrpLog_ROC11_Gap_Tr

Tripping output logic setting of gap zero-sequence overcurrent protection with time delay 1

25. t_ROC12_Gap_Tr

Time delay 2 of gap zero-sequence overcurrent protection

26. TrpLog_ROC12_Gap_Tr

Tripping output logic setting of gap zero-sequence overcurrent protection with time delay 2

27. V_Alm_ROV_LVS_Tr

Voltage setting of zero sequence overvoltage alarm at LV side, 10~15V generally.

28. t_Alm_ROV_LVS_Tr

Delay of zero sequence overvoltage alarm at LV side.

29. En_VCE.ROV_Ctrl_ROC1_Tr

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Stage 1 of zero-sequence overcurrent protection controlled by zero-sequence voltage element.

30. En_VCE.ROV_Ctrl_ROC2_Tr

Stage 2 of zero-sequence overcurrent protection controlled by zero-sequence voltage element.

31. En_Dir_Ctrl_ROC1_Tr

Stage 1 of zero-sequence overcurrent protection is controlled by direction element.

32. En_Dir_Ctrl_ROC2_Tr

Stage 2 of zero-sequence overcurrent protection is controlled by direction element.

33. En_Harm_Ctrl_ROC1_Tr

Stage 1 of zero-sequence overcurrent protection is controlled by secondary harmonic component


of zero-sequence current of main transformer.

34. En_Harm_Ctrl_ROC2_Tr

Stage 2 of zero-sequence overcurrent protection is controlled by secondary harmonic component


of zero-sequence current of main transformer.

35. En_Alm_ROV_LVS_Tr

Enable zero sequence overvoltage alarm on LV side.

7.6.5.3 Access path

Main Menu -> Settings -> TrProt Settings -> TrEFBakProt Settings

7.6.6 Settings of Over-excitation Protection of Main Transformer

7.6.6.1 Setting List

Table 7.6-6 List of over excitation protection settings of main transformer

No. Symbol Range Step Default


1 k_OvExc1_Tr 1.00 – 2.00 0.01 1.4
2 t_OvExc1_Tr 0.1 – 3000.0 s 0.1s 1
3 TrpLog_OvExc1_Tr 00000000 – 3FFFFFFF 1 0007
4 k_Alm_OvExc_Tr 1.00 – 2.00 0.01 1.1
5 t_Alm_OvExc_Tr 0.1 – 25.0s 0.1s 10
6 k0_InvOvExc_Tr 1.00 – 2.00 0.01 1.5
7 t0_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 1
8 k1_InvOvExc_Tr 1.00 – 2.00 0.01 1.45
9 t1_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 2
10 k2_InvOvExc_Tr 1.00 – 2.00 0.01 1.4
11 t2_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 5
12 k3_InvOvExc_Tr 1.00 – 2.00 0.01 1.3

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13 t3_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 15


14 k4_InvOvExc_Tr 1.00 – 2.00 0.01 1.25
15 t4_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 30
16 k5_InvOvExc_Tr 1.00 – 2.00 0.01 1.2
17 t5_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 100
18 k6_InvOvExc_Tr 1.00 – 2.00 0.01 1.15
19 t6_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 300
20 k7_InvOvExc_Tr 1.00 – 2.00 0.01 1.1
21 t7_InvOvExc_Tr 1.0 – 3000.0 s 0.1s 1000
22 TrpLog_InvOvExc_Tr 00000000– 3FFFFFFF 1 0007

7.6.6.2 Setting Description

1. k_OvExc1_Tr

Setting of stage 1 of definite time over excitation protection of main transformer.


U
B U gn
N    U  / f   1.3 or data provided by the factory
Bn f
f gn

2. t_OvExc1_Tr

Delay of stage 1 of definite time over excitation protection of main transformer.

3. TrpLog_OvExc1_Tr

Tripping output logic setting of stage 1 of definite time over excitation protection of main
transformer. The function of this protection is used for islanding, excitation shutting or
programming, excitation reducing etc.

4. k_Alm_OvExc_Tr

Setting of over excitation alarm of main transformer. Setting of alarm shall be lower than that of
over excitation protection. 1.1 is recommended.

5. t_Alm_OvExc_Tr

Delay of over excitation alarm of main transformer.

6. k0_InvOvExc_Tr

Upper limit of inverse time over excitation protection of main transformer—n0

7. t0_InvOvExc_Tr

Delay of upper limit of inverse time over excitation protection of main transformer.

8. k1_InvOvExc_Tr

Inverse time over excitation factor1—n1. Setting range of various inverse time over excitation

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coefficient s is 1.1 – 2.0. However setting of upper limit of over excitation factor n0 shall be higher
than that of over excitation factor1 n1, which of factor1 n1 shall be higher than that of factor2 n2,
etc.. Finally, setting of over excitation factor6 n6 shall be higher than that of lower limit.

9. t1_InvOvExc_Tr

Delay at the point n1 on inverse time over excitation curve—t1


The range of delay of various inverse time over excitation protection stage is 0s to 6000 s, ie.,0--50
min. Delay of upper limit of over excitation factor shall be shorter than that of over excitation
factor1, which of factor1 shall be shorter than that of factor2, etc.. Finally, delay of over excitation
factor6 shall be shorter than that of lower limit.

10. k2_InvOvExc_Tr

Inverse time over excitation factor n2.

11. t2_InvOvExc_Tr

Delay at the point n2 on inverse time over excitation curve—t2

12. k3_InvOvExc_Tr

Inverse time over excitation Ratio n3.

13. t3_InvOvExc_Tr

Delay at the point n3 on inverse time over excitation curve—t3.

14. k4_InvOvExc_Tr

Inverse time over excitation Ratio n4.

15. t4_InvOvExc_Tr

Delay at the point n4 on inverse time over excitation curve—t4.

16. k5_InvOvExc_Tr

Inverse time over excitation Ratio n5.

17. t5_InvOvExc_Tr

Delay at the point n5 on inverse time over excitation curve—t5.

18. k6_InvOvExc_Tr

Inverse time over excitation Ratio n6.

19. t6_InvOvExc_Tr

Delay at the point n6 on inverse time over excitation curve—t6.

20. k7_InvOvExc_Tr

Inverse time over excitation Ratio n7.

21. t7_InvOvExc_Tr

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Delay at the point n7 on inverse time over excitation curve—t7.

22. TrpLog_InvOvExc_Tr

Tripping output logic setting of inverse time over excitation protection of main transformer.

7.6.6.3 Access Path

Main Menu -> Settings -> TrProt Settings -> TrOvExcProt Settings

Note:
The over excitation protection of generator-transformer unit comprises two over excitation
protection: generator over excitation protection and transformer over excitation protection.
Configuration of the generator over excitation protection shall be higher than over excitation
capability of generator, while that of transformer shall be higher than over excitation capability of
transformer. If only one set of over excitation protection is used, configuration of the lower one
shall be adopted.

7.6.7 Settings of Differential Protection of Generator

7.6.7.1 Settings List

Table 7.6-7 List of generator differential protection settings

No. Symbol Range Step Default


1 I_Pkp_PcntDiff_Gen 0.10–1.50 (Ie) 0.01 (Ie) 0.1
2 I_InstDiff_Gen 2.00–14.00 (Ie) 0.01 (Ie) 6
3 I_AlmDiff_Gen 0.05–1.00 (Ie) 0.01 (Ie) 0.1
4 Slope1_PcntDiff_Gen 0.00–0.50 0.01 0.05
5 Slope2_PcntDiff_Gen 0.30–0.80 0.01 0.5
6 TrpLog_Diff_Gen 00000000–3FFFFFFF 1 FFFF
Logic setting ―1‖ - enable, ―0‖ – disable
7 En_InstDiff_Gen 0, 1 1
8 En_PcntDiff_Gen 0, 1 1
9 En_DPFC_Diff_Gen 0, 1 0
10 Opt_CTS_Blk_PcntDiff_Gen 0, 1 0

7.6.7.2 Setting Description

1. I_Pkp_PcntDiff_Gen

This is pickup setting of percentage current differential protection, which is also the setting of fault
detector of percentage differential protection. It shall be higher than maximum unbalance current
when the generator operates on normal rated load, i.e.

I cdqd  Krel  2 0.03I f 2n I cdqd  Krel  Iunb.0 Equation 7.6-29


or
Where:

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I f 2 n is secondary rated current of generator,

I f 1n
I f 2n 
n fLH

Where:

I f 1n is primary rated current of generator and n fLH is ratio of generator CT.

Pn / cos 
I f 1n 
3U f 1n

Where:

Pn is rated capacity of generator;

cos is power factor of generator and


U f 1n is rated voltage of generator terminal.

K rel is reliability factor, 1.5 in general;

I unb.0 is the measured actual unbalance current during rated load of generator, 0.2 I f 2 n -0.3

I f 2 n is recommended for reference.

Where:

I cdqd represents the setting [I_Pkp_PcntDiff_Gen].

2. I_InstDiff_Gen

Setting of unrestrained instantaneous differential protection.


Unrestraint instantaneous differential protection is a complementary part of differential protection.
Its current setting shall be higher than maximum unbalance current due to breaker‘s asynchronous
closure. For large unit, it can be set as 3 or 4 times of rated current. 4 times of rated current is
recommended.

3. I_AlmDiff_Gen

Differential current alarm setting of generator. It shall be higher than normal unbalance differential
current and lower than [I_Pkp_PcntDiff_Gen].

4. Slope1_PcntDiff_Gen

Setting of the first slope of percentage differential protection, it shall be:

K bl1  K rel  K cc  K er Equation 7.6-30

Where:

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K rel is reliability coefficient which is considered to be 1.0~2.0 in general;

K cc
is the type factor of CT, takes 0.5;

K er
is error factor of CT ratio, takes 0.1.

K bl1
represents [Slope1_PcntDiff_Gen] which is set as 0.05~0.1 in general.

5. Slope2_PcntDiff_Gen

Maximum value of restraint coefficient of the differential characteristic curve.


With type factor of CT not taken into account, the maximum unbalance current is, ,

I unb. max  K ap  K er  I k . max Equation 7.6-31

Where:

K ap
is non periodic component factor, usually no less than 2.0;

K er
is error factor of CT ratio, no more than 0.1;

I k . max
is periodic component of secondary value of external three phase short circuit current and it
can be taken as 4 times of rated current if it is less than 4 times of rated current.
Maximum slope of percentage differential protection is:

I unb. max*  I cdqd *  2k bl1


k bl 2  Equation 7.6-32
I k . max*  2

where:

I unb. max* I cdqd * I k . max*


, and are all per unit value of rated current of generator;

kbl 2 ([Slope2_PcntDiff_Gen] ) is taken as 0.50 generally.

If the percentage differential protection is configured based on rules mentioned above, when
phase-to-phase metallic short circuit fault occurs at the terminal of generator, sensitivity factor will

K sen
meet requirement ≥ 2 surely.

6. TrpLog_Diff_Gen

Tripping output logic setting of differential protection of generator.

7. En_InstDiff_Gen

Unrestrained instantaneous differential protection enabled. If this setting is set as ―1‖, it means this
protection is enabled. Otherwise it means the protection is disabled.

8. En_PcntDiff_Gen

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Percentage differential protection enabled.

9. En_DPFC_Diff_Gen

DPFC percentage differential protection enabled.

10. Opt_CTS_Blk_PcntDiff_Gen

If this logic setting is set as ―1‖, it means percentage differential protection will be blocked when CT
circuit failure take place. Otherwise it means the blocking function is disabled.

7.6.7.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenDiffProt Settings

7.6.8 Settings of Turn-to-turn Fault Protection of Generator

7.6.8.1 Setting List

Table 7.6-8 List of turn-to-turn fault protection settings

No. Symbol Range Step Default


1 I_SensTrvDiff_Gen 0.10 – 50.00 A 0.01 A 2.0
2 I_InsensTrvDiff_Gen 0.10 – 50.00 A 0.01 A 10
3 t_TrvDiff_Gen 0.00 – 10.00 S 0.01 S 0.2
4 V_SensROV_Longl_Gen 1 – 10.00 V 0.01 V 1
5 V_InsensROV_Longl_Gen 1 – 20.00 V 0.01 V 6
6 t_ROV_Longl_Gen 0.10 – 10.00 S 0.01 S 0.1
7 TrpLog_IntTurn_Gen 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
8 En_SensTrvDiff_Gen 0, 1 0
9 En_InsensTrvDiff_Gen 0, 1 0
10 En_SensROV_Longl_Gen 0, 1 1
11 En_InsensROV_Longl_Gen 0, 1 1
12 En_DPFC_IntTurn_Gen 0, 1 0

7.6.8.2 Setting Description

1. I_SensTrvDiff_Gen

Current setting of high sensitive transverse differential protection.


Setting of this protection shall be higher than maximum unbalance current during normal operation
condition. Reliability factor can be more than 2. The setting value is usually:

I op  0.05 I f ln / na Equation 7.6-33

Where:

I OP represents the setting [I_SensTrvDiff_Gen].

I f ln
is primary rated current of generator and

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na
is ratio of zero sequence CT of transverse differential protection.
Phase current restraint factor is a fixed coefficient in the program.

2. I_InsensTrvDiff_Gen

Current setting of high-setting transverse differential protection.


It is equivalent to traditional transverse differential protection. Setting of this protection is as follows
which shall be higher than maximum unbalance current during external short circuit fault.

I op (0.20 ~ 0.30)I f ln / na Equation 7.6-34

Where:

I OP represents the setting [I_SensTrvDiff_Gen].

I f ln
is primary rated current of generator and

na
is ratio of zero sequence CT of transverse differential protection.

3. t_TrvDiff_Gen

Delay of transverse differential protection (act on only after the occurrence of one-point ground of
rotor).
When one point earth fault occurs within rotor of generator and one point earth fault protection
operates, in order to prevent unwanted operation of transverse protection due to instantaneous
two points earth fault within the rotor, operation of this protection shall be delayed for 0.5 s – 1 s.

Note:
When a turn-to-turn fault occurs, the equipment will trip relevant breakers without delay according
to the tripping output logic setting, but a time delay decided by user will act on after occurrence of
one-point ground of rotor.

4. V_SensROV_Longl_Gen

Voltage setting of high sensitive longitudinal zero sequence overvoltage protection .


Setting of this protection shall be higher than maximum unbalance voltage during normal
operation condition, usually:

U op  0.5 - 3 V Equation 7.6-35

At beginning of configuration, 2 – 3 V is preferred. After fault waveform analysis, the setting can be
reduced properly and sensitivity of the protection can be improved than.
Phase current restraint factor is a fixed coefficient in the program.

5. V_InsensROV_Longl_Gen

Setting of this protection shall be higher than maximum unbalance voltage during external fault,
usually:

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U op  8 - 12 V Equation 7.6-36

6. t_ROV_Longl_Gen

Delay of longitudinal zero sequence overvoltage. Short delay 0.10 s – 0.20 s is recommended for
operation and output of this protection.

7. TrpLog_IntTurn_Gen

Tripping output logic setting of turn-to-turn fault protection of generator.

8. En_SensTrvDiff_Gen

Enable high sensitive transverse differential protection of generator.

9. En_InsensTrvDiff_Gen

Enable high-setting transverse differential protection of generator.

10. En_SensROV_Longl_Gen

Enable high sensitive longitude zero sequence overvoltage protection of generator.

11. En_InsensROV_Longl_Gen

Enable high-setting longitude zero sequence overvoltage protection of generator.

12. En_DPFC_IntTurn_Gen

Enable directional DPFC turn-to-turn fault protection of generator.

7.6.8.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenIntTurnProt Settings

7.6.9 Settings of Backup Protection of Generator

7.6.9.1 Setting List

Table 7.6-9 List of turn-to-turn fault protection settings

No. Symbol Range Step Default


1 V_NegOV_VCE_Gen 1.00 – 20.00 V 0.01 V 4
2 Vpp_UV_VCE_Gen 2.00 –100.00 V 0.01 V 60
3 I_OC1_Gen 0.10 –100.00 A 0.01 A 20
4 t_OC1_Gen 0.00 – 10.00 S 0.01 S 1
5 TrpLog_OC1_Gen 00000000 - 3FFFFFFF 1 0007
6 I_OC2_Gen 0.10 –100.00 A 0.01 A 20
7 t_OC2_Gen 0.00 – 10.00 S 0.01 S 1
8 TrpLog_OC2_Gen 00000000 - 3FFFFFFF 1 0007
9 Z1_Fwd_Gen 0.10 –100.00 Ω 0.01 Ω 20
10 Z1_Rev_Gen 0.10 –100.00 Ω 0.01 Ω 20

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11 t_Z1_Gen 0.00 – 10.00 S 0.01 S 1


12 TrpLog_Z1_Gen 00000000 - 3FFFFFFF 1 0006
13 Z2_Fwd_Gen 0.10 –100.00 Ω 0.01 Ω 20
14 Z2_Rev_Gen 0.10 –100.00 Ω 0.01 Ω 20
15 t_Z2_Gen 0.00 – 10.00 S 0.01 S 1
16 TrpLog_Z2_Gen 00000000 - 3FFFFFFF 1 0006
17 I_BO_OC_Term_Gen 0.10 –100.00 A 0.01 A 5.5
18 t_BO_OC_Term_Gen 0.00 – 10.00 S 0.01 S 9
Logic setting ―1‖ - enable, ―0‖ – disable
19 En_VCE_Ctrl_OC1_Gen 0, 1 1
20 En_VCE_Ctrl_OC2_Gen 0, 1 1
21 En_HVS.VCE_Ctrl_OC_Gen 0, 1 0
22 Opt_VTS_Ctrl_OC_Gen 0, 1 0
23 En_Mem_Curr_Gen 0, 1 0
24 En_BO_OC_Term_Gen 0, 1 0
25 En_HVSCurr_Ctrl_OC1_Gen 0, 1 0

7.6.9.2 Setting Description

1. V_NegOV_VCE_Gen

Negative sequence voltage setting of composite voltage control element. Setting and displayed
value of negative sequence voltage are U2.
Setting of negative sequence voltage relay shall be higher than unbalance voltage during normal
operation, generally

U op.2  (0.06 - -0.08 ) U n Equation 7.6-37

Where: U n is secondary rated voltage.

Sensitivity factor shall be checked by phase-to-phase short circuit fault on HV side bus of main
transformer:

U 2. min
K sen  Equation 7.6-38
U op 2
Where:

U 2. min is minimum negative sequence voltage at location of the equipment during phase-to-phase

short circuit fault on HV side bus of main transformer. K sen ≥ 1.5 is required.

2. Vpp_UV_VCE_Gen

Setting of phase-to-phase undervoltage of composite voltage control element.

Its operating voltage U op can be set as following:

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For turbine generator, U op  0.6U gn and for hydro-generator, U op  0.7U gn

U gn
Where is rated phase-to-phase voltage of generator.
Sensitivity factor shall be checked by three-phase short circuit fault on HV side bus of main
transformer:
U op
K sen  Equation 7.6-39
X t  I k(3. max
)

Where
I k( 3. max
)
is maximum secondary fault current during three-phase short circuit on HV side bus

Xt X t  Zt K sen
of main transformer; is reactance of main transformer, . ≥ 1.2 is required.

3. I_OC1_Gen

Setting of overcurrent protection stage 1.


Setting of overcurrent relay shall be higher than rated current of generator.

K rel
I op  I gn Equation 7.6-40
Kr

Where:

K rel
is reliability factor, 1.3 – 1.5;

K r is release factor, 0.85 – 0.95;

I gn
is secondary rated current of generator.
Sensitivity factor of overcurrent relay shall be checked by following:

I k( 2. min
)
K sen  Equation 7.6-41
I op

Where
I k( 2. min
)
is minimum fault current through location of the relay during phase-to-phase

K sen
metallic short circuit on HV side of main transformer. ≥ 1.2 is required.

4. t_OC1_Gen

Time delay of overcurrent protection stage 1. Delay of this protection shall be higher than that of
operation of backup protection of step-up transformer. This protection is used for islanding and
generator shutting off.

5. TrpLog_OC1_Gen

Tripping output logic setting of overcurrent protection stage 1.

6. I_OC2_Gen

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Setting of overcurrent protection stage 2. Setting of overcurrent relay shall be higher than rated
current of transformer.

7. t_OC2_Gen

Time delay of overcurrent protection stage2.

8. TrpLog_OC2_Gen

Tripping output logic setting of overcurrent protection stage2.

9. Z1_Fwd_Gen

Positive direction impedance setting of distance protection stage1. Here positive direction means
the direction is pointing to the transformer instead of generator itself.
If the value of this setting is greater than the next one, then the characteristic of distance protection
is set as excursive impedance circle; if it is equal to the next one, the characteristic is whole
impedance circle; if the next one is set as ―0‖, the characteristic becomes directional impedance.
Generally, low impedance protection is considered as the backup protection of generator in case
that voltage-controlled overcurrent protection can‘t satisfy the sensitivity requirement of generator.

10. Z1_Rev_Gen

Negative direction impedance setting of distance protection stage1. In general, this setting is set
as 5-10% of the positive direction impedance setting.

11. t_Z1_Gen

Delay of distance protection stage1.

12. TrpLog_Z1_Gen

Tripping output logic setting of distance protection stage 1.

13. Z2_Fwd_Gen

Positive direction impedance setting of distance protection stage2.

14. Z2_Rev_Gen

Negative direction impedance setting of distance protection stage2

15. t_Z2_Gen

Delay of distance protection stage2

16. TrpLog_Z2_Gen

Tripping output logic setting of distance protection stage1. Please refer to the tripping output logic
setting of differential protection of main transformer for details.

17. I_BO_OC_Term_Gen

Current setting of overcurrent element for controlling function of a set of contact.

18. t_BO_OC_Term_Gen

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Time delay setting of overcurrent element for controlling function of a set of contact.

19. En_VCE_Ctrl_OC1_Gen

Enable controlling function to stage 1 of overcurrent protection by Composite Voltage Element.

20. En_VCE_Ctrl_OC2_Gen

Enable controlling function to stage 2 of overcurrent protection by Composite Voltage Element.

21. En_HVS.VCE_Ctrl_OC_Gen

Enable controlling function to overcurrent protection by Composite Voltage Element from HVS of
transformer.

22. Opt_VTS_Ctrl_OC_Gen

Protection performance during VT circuit failure.


―1‖: when VT circuit failure at one side is detected, composite voltage element will be disabled if
corresponding logic setting is set as ―1‖.
―0‖: when VT circuit failure at one side is detected, the voltage-controlled overcurrent element will
become a pure overcurrent relay without composite voltage element controlling.

23. En_Mem_Curr_Gen

That the setting is set as ―1‖ indicates the excitation mode of generator is self shunt excitation
mode. In that case, the protection will remember the current value at the initiation of fault, and
operates based on it, no matter whether the current will decrease due to the descending excitation
voltage result from terminal voltage‘s getting down when external fault occurs. Once this setting is
set as ―1‖, the backup overcurrent protection of generator is always controlled by composite
voltage element.

24. En_BO_OC_Term_Gen

Enable blocking function of overcurrent element by outputting a set of contact.

25. En_HVSCurr_Ctrl_OC1_Gen

Enable stage 1 of overcurrent protection controlled by current of HVS of generator

Note:
In the above Table,current used in backup protection of generator comes from the backup current
input channel.

7.6.9.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenPPFBakProt Settings

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7.6.10 Settings of Stator Earth-fault Protection

7.6.10.1 Setting List

Table 7.6-10 List of stator earth fault protection settings

No. Symbol Range Step Default


1 V_ROV_VCE_Tr 1.00-100.00 V 0.01V 40
2 V_SensROV_Sta 0.10 – 50.00 V 0.01 V 10
3 V_InsensROV_Sta 0.10 – 50.00 V 0.01 V 20
4 t_ROV_Sta 0.00 – 10.00 S 0.01 S 2
5 t_InsensROV_Sta 0.00 – 10.00 S 0.01 S 1
6 k_V3rdHRatio_PreSync_Sta 0.50 – 10.00 0.01 1
7 k_V3rdHRatio_PostSync_Sta 0.50 – 10.00 0.01 1
8 k_V3rdHDiff_Sta 0.05 – 2.00 0.01 0.5
9 t_V3rdH_Sta 0.00 – 10.00S 0.01 S 3
10 TrpLog_EF_Sta 0000 – FFFF 1 7FFF
Logic setting ―1‖ - enable, ―0‖ – disable
11 En_Alm_ROV_Sta 0, 1 0
12 En_Trp_ROV_Sta 0, 1 1
13 En_Alm_V3rdHRatio_Sta 0, 1 1
14 En_Alm_V3rdHDiff_Sta 0, 1 0
15 En_Trp_V3rdHRatio_Sta 0, 1 0
16 En_Trp_InsensROV_Sta 0, 1 1
17 En_Alm_DeltVTS1_Gen 0, 1 1
18 En_Alm_VTS_NP_Gen 0, 1 1

7.6.10.2 Setting Description

1. V_ROV_VCE_Tr

fundamental zero sequence overvoltage protection of stator is controlled by zero sequence


voltage of HVS of main transformer. It is set as ―40V‖ generally.

2. V_SensROV_Sta

Setting of fundamental zero sequence overvoltage protection.

U op U unb. max
Setting of this protection shall be higher than maximum unbalance voltage of single
phase VT at neutral point during normal operation.

U op  K rel U unb. max Equation 7.6-42

K rel U unb. max


Where is reliability factor, 1.2 – 1.3 generally; is the maximum measured
fundamental unbalance zero sequence voltage derived from single VT at the neutral point of
generator.
To assure its security, user should check the transferred zero sequence voltage through coupling

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capacitance between HV side and LV side of transformer when external earth fault occurs on the
HV side of the transformer. Meanwhile, settings, including time delay and operation setting, should
be considered to cooperate with that of earth fault protection of the system.

Note:
The zero sequence voltage used in this protection comes from VT at the neutral point of generator.

3. V_InsensROV_Sta

Setting of high-setting fundamental zero sequence overvoltage protection.


Only zero sequence voltage at neutral point is taken for high setting zone of fundamental zero

U gn
sequence voltage protection. If ratio of VT on neutral point is nTVN  / 100V , this setting is
3
usually 20 V – 25 V.
Zero sequence voltage transferred by coupling capacitance per phase between HV and LV side
windings of step-up transformer shall be checked when external fault occurs at HV side of the
transformer. Coordination both on setting and delay between this protection and system earth fault
protection could be achieved then.

4. t_ROV_Sta

Delay of fundamental zero sequence overvoltage protection.

5. t_InsensROV_Sta

Delay of high-setting fundamental zero sequence overvoltage protection.

6. k_V3rdHRatio_PreSync_Sta

Ratio setting of 3rd harmonics before incorporation of generator in power network.


 
Let third harmonic voltage at the end and neutral point of generator be U t and U n , ratio setting of
third harmonic voltage percentage earth fault protection shall be
 
Ut Un   Equation 7.6-43

3  nTVN
and   K rel during pre-configuration,
nTV 0
Where:

K rel
is reliability factor, 1.3 – 1.5 in general;

nTV 0
is ratio of open-delta zero sequence voltage at the terminal of generator;

n TVN
is ratio of zero sequence VT on neutral point.

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U 3T / U 3N
During incorporation of generator to power system, the ratio changes considerably
owing to variation of equivalent capacitive reactance at generator terminal. So two different
settings are designed for protection before and after connection of generator with system, and
these two settings can be switched over with alternation of contacts‘ position of the terminal
breaker.

The setting shall be (1.3 – 1.5)× 1 before incorporation and (1.3 – 1.5)× 2 after that.

Where 1 and  2 are the maximum real-measured third harmonic voltage ratio before and
after incorporation respectively.

7. k_V3rdHRatio_PostSync_Sta

Ratio setting of 3rd harmonics after incorporation in power network.

8. k_V3rdHDiff_Sta

Restraint coefficient of percentage third harmonic voltage earth fault protection.


   
U t  k p U n  k zd U n Equation 7.6-44

Where:

kp
is vectorial automatic tracing regulation factor;

k zd
is restraint factor [3rdHarm Diff. Ratio], 0.3~0.5 is recommended.

U t is 3rd harmonics derived from the terminal of generator.

U n is 3rd harmonics derived from the neutral point of generator.

9. t_V3rdH_Sta

Delay of percentage third harmonic voltage earth fault protection. It shall be longer than that of
backup protection against external fault .

10. TrpLog_EF_Sta

Tripping output logic setting of stator earth fault protection.

11. En_Alm_ROV_Sta

Enable alarm function of zero sequence overvoltage.

12. En_Trp_ROV_Sta

Enable zero sequence overvoltage protection.

13. En_Alm_V3rdHRatio_Sta

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Enable alarm function of third harmonic voltage ratio element .

14. En_Alm_V3rdHDiff_Sta

Enable alarm function of third harmonics differential voltage.

15. En_Trp_V3rdHRatio_Sta

Enable tripping function of third harmonic voltage ratio element.

16. En_Trp_InsensROV_Sta

Enable tripping function of high-setting zero sequence overvoltage protection

17. En_Alm_DeltVTS1_Gen

Enable open-delta failure supervision of VT1 at generator terminal.

18. En_Alm_VTS_NP_Gen

Enable open-delta failure supervision of VT at neutral point of generator.

7.6.10.3 Access Path

Main Menu -> Settings -> GenProt Settings -> StaEFProt Settings

7.6.11 Settings of Rotor Earth-fault Protection

7.6.11.1 Setting List

Table 7.6-11 List of earth fault protection settings of rotor

No. Symbol Range Step Default


1 R_Sens1PEF_RotWdg 0.10 –100.00 kΩ 0.01 kΩ 20
2 R_1PEF_RotWdg 0.10 –100.00 kΩ 0.01 kΩ 10
3 t_Alm_1PEF_RotWdg 0.00 – 10.00 S 0.01 S 1
4 t_Trp_1PEF_RotWdg 0.00 – 10.00 S 0.01 S 2
5 t_2PEF_RotWdg 0.00 - 10.00 S 0.01 S 1
6 t_Switch 0.50-10.00 0.01s 1
7 R_Injected 0.10-100.00 0.01Ω 47
8 Opt_EF_RotWdg 0-2 1 0
9 TrpLog_EF_RotWdg 00000000 – 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
10 En_Alm_Sens1PEF_RotWdg 0, 1 1
11 En_Alm_1PEF_RotWdg 0, 1 1
12 En_Trp_1PEF_RotWdg 0, 1 0
13 En_2PEF_RotWdg 0, 1 0

7.6.11.2 Setting Description

1. R_Sens1PEF_RotWdg

Impedance setting of sensitive stage of one-point earth fault protection of rotor.

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General specification of generator specifies that insulation resistance of its excitation winding shall
be higher than 1 MΩ for air cooled and hydrogen-cooled turbine generator during cooling state,
and 2 kΩ for water cooled excitation winding. General specification of hydro-generator specifies
that insulation resistance of its excitation winding shall be higher than 0.5 MΩ in any case.
Sensitive stage of this protection is used for alarm. Its setting could be 20 kΩ – 80 kΩ generally.

2. R_1PEF_RotWdg

Impedance setting of one-point earth fault protection of rotor.


Setting of one point earth fault protection can be 20 kΩ for air cooled and hydrogen-cooled turbine
generator and 2.5 kΩ for water cooled excitation winding. This protection can be used for alarm or
generator shutting with delay.
Actual measured insulation resistance is used for this protection.

3. t_Alm_1PEF_RotWdg

Delay of one-point earth fault protection of rotor operates to alarm.

4. t_Trp_1PEF_RotWdg

Delay of one-point earth fault protection of rotor operates to trip.

5. t_2PEF_RotWdg

Delay of two-point earth fault protection of rotor.

6. t_Switch

For rotor earth fault protection with injection principle, it is switching cycle of square wave power.
For rotor earth fault protection with ping-pang principle, it is switching cycle of electronic switch.

7. R_Injected

The external connected heavy power resistance, it is 47kΩgenerally.

8. Opt_EF_RotWdg

Principle selection of earth fault protection of rotor


0: ping-pang principle
1: injection principle of double-ends
2: injection principle of single-end

9. TrpLog_EF_RotWdg

Tripping output logic setting of earth fault protection of rotor.

10. En_Alm_Sens1PEF_RotWdg

Enable alarm function of sensitive stage of one-point earth fault protection of rotor.

11. En_Alm_1PEF_RotWdg

Enable alarm function of one-point earth fault protection of rotor.

12. En_Trp_1PEF_RotWdg

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Enable tripping function of one-point earth fault protection of rotor.

13. En_2PEF_RotWdg

Enable two-point earth fault protection of rotor.

7.6.11.3 Access Path

Main Menu -> Settings -> GenProt Settings -> RotWdgEFProt Settings

7.6.12 Settings of Thermal Overload Protection of Stator

7.6.12.1 Setting List

Table 7.6-12 List of thermal overload protection settings of stator

No. Symbol Range Step Default


1 I_OvLd_Sta 0.10 – 50.00 A 0.01 A 10
2 t_OvLd_Sta 0.00 – 10.00 S 0.01 S 1
3 TrpLog_OvLd_Sta 00000000 - 3FFFFFFF 1 0007
4 I_Alm_OvLd_Sta 0.10 – 50.00 A 0.01 A 7
5 t_Alm_OvLd_Sta 0.00 – 10.00 S 0.01 S 2
6 I_InvOvLd_Sta 0.10 – 100.00 A 0.01 A 6
7 tmin_InvOvLd_Sta 0.10 – 10.00 S 0.01 S 1
8 A_Therm_Sta 1.00 –100.00 0.01 40
9 K_Disspt_Sta 1.02 – 2.00 0.01 1.03
10 TrpLog_InvOvLd_Sta 00000000 - 3FFFFFFF 1 0007

7.6.12.2 Setting Description

1. I_OvLd_Sta

Setting of definite time overcurrent protection.


Setting of this protection is determined by the requirement of reliable release during permissive
continuous load current of generator.

I gn
I OP  K rel Equation 7.6-45
Kr

Where:

K rel
is reliability factor, 1.05 generally;

K r is release factor, 0.85 – 0.95;

I gn
is secondary rated current of generator.
Delay of this protection shall be longer than maximum delay of backup protection. Alarm will be
issued or load will be reduced when it operates.

2. t_OvLd_Sta

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Delay of definite time overcurrent protection.

3. TrpLog_OvLd_Sta

Tripping output logic setting of definite time overcurrent protection.

4. I_Alm_OvLd_Sta

Setting of definite time overcurrent alarm.

5. t_Alm_OvLd_Sta

Delay of alarm issued by definite time overcurrent element.

6. I_InvOvLd_Sta

Pickup current of inverse time overcurrent protection.


Characteristic of this protection is indefinite time relationship between multiple of load current and
corresponding permissive duration which is determined by permissive overload capability of stator
provided by the factory.

K tc
t Equation 7.6-46
I *2  K sr2

Where:

K tc
is heat capacity factor of stator winding;

I * is per unit value of load current referred to rated current of stator;

K sr
is heat dissipation factor, 1.02 – 1.05 generally.
Minimum delay for upper limit of this protection shall coordinate with unrestraint protection.
Current setting of lower limit of this protection shall coordinate with definite time overload
protection mentioned above, namely

I gn
I OP. min  K c 0 K rel Equation 7.6-47
Kr

KC 0
Where: is coordination factor, 1.05 in general.

7. tmin_InvOvLd_Sta

Delay of upper limit of inverse time overcurrent protection.

8. A_Therm_Sta

Thermal capacity parameter of stator winding.

9. K_Disspt_Sta

Heat dissipation factor for inverse time overcurrent.

10. TrpLog_InvOvLd_Sta

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Tripping output logic setting of inverse time overcurrent protection.

7.6.12.3 Access Path

Main Menu -> Settings -> GenProt Settings -> StaOvLdProt Settings

7.6.13 Settings of Negative-sequence Overcurrent Protection

7.6.13.1 Setting List

Table 7.6-13 List of negative sequence overload protection

No. Symbol Range Step Default


1 I_NegOC_Gen 0.10 – 20.00 A 0.01 A 10
2 t_NegOC_Gen 0.00 – 10.00 S 0.01 S 1
3 TrpLog_NegOC_Gen 00000000 – 3FFFFFFF 1 0007
4 I_Alm_NegOC_Gen 0.05 – 20.00 A 0.01 A 1
5 t_Alm_NegOC_Gen 0.00 – 10.00 S 0.01 S 2
6 I_InvNegOC_Gen 0.05 – 5.00 A 0.01 A 0.5
7 I_Neg_Perm_Gen 0.05 – 5.00 A 0.01 A 0.4
8 tmin_InvNegOC_Gen 0.10 – 10.00 S 0.01 S 1
9 tmax_InvNegOC_Gen 0.1 – 5000.0 S 0.1 S 1000
10 A_Therm_RotBody 1.00 – 100.00 S 0.01 40
11 TrpLog_InvNegOC_Gen 00000000 – 3FFFFFFF 1 0007

7.6.13.2 Setting Description

1. I_NegOC_Gen

Setting of negative sequence overcurrent protection.


Setting of this protection is determined by the threshold under which this protection can release

reliably, that threshold value is continuously permissive negative sequence current I 2  . So,

I 2 I gn
I OP  K rel Equation 7.6-48
Kr
Where:

I OP is the setting [I_OvLd_Sta].

K rel
is reliability factor, 1.05;

K r is release factor, 0.85 – 0.95;

I 2  is per unit value of continuously permissive negative sequence current,

I gn
is secondary rated current of generator.

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2. t_NegOC_Gen

Delay of negative sequence overcurrent protection.


Delay of this protection shall be longer than maximum delay of backup protection. Alarm will be
issued when it operates.

3. TrpLog_NegOC_Gen

Tripping output logic setting of negative sequence overcurrent protection.

4. I_Alm_NegOC_Gen

Setting of alarm issued by negative sequence overcurrent element.

5. t_Alm_NegOC_Gen

Delay of alarm issued by negative sequence overcurrent element.

6. I_InvNegOC_Gen

Pickup current of inverse time negative sequence overcurrent protection.


Characteristic of this protection is determined by permissive negative sequence overload
capability of rotor surface provided by the manufacturer.

A
t Equation 7.6-49
I 22*  I 22

Where:
A is permissive negative sequence current factor of rotor surface;
I 2* is per unit value of negative sequence current of generator;

I 2  is per unit value of permissive continues negative sequence current.

Minimum delay for upper limit of this protection shall coordinate with unrestraint protection.

7. I_Neg_Perm_Gen

Permitted continuous currents of inverse time negative sequence overcurrent protection for lasting
operation.
Current setting of lower limit of this protection shall be the operating current corresponding to
delay 1000 s, namely

A
I OP. min   I 22 Equation 7.6-50
1000

This protection is used for islanding or program tripping.

8. tmin_InvNegOC_Gen

Delay of upper limit of inverse negative sequence overcurrent protection. Minimum delay for upper
limit of this protection shall coordinate with unrestraint protection.

9. tmax_InvNegOC_Gen

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Long delay of lower limit of inverse negative sequence overcurrent protection.

10. A_Therm_Rotbody

Heat dissipation factor for inverse time negative sequence overcurrent.

11. TrpLog_InvNegOC_Gen

Tripping output logic setting of inverse time negative sequence overcurrent protection.

7.6.13.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenNegOCProt Settings

7.6.14 Settings of Loss-of-excitation Protection

7.6.14.1 Setting List

No. Symbol Range Step Default


1 X1_LossExc_Gen 0.00 -200.00 Ω 0.01 Ω 5
2 X2_LossExc_Gen 0.00 -200.00 Ω 0.01 Ω 20
3 Q_RevQ_LossExc_Gen 0.00 – 50.00 % 0.01 % 10
4 V_RotUV_LossExc_Gen 0.1 – 500.00 V 0.01 V 30
5 Un_RotNoLoad_LossExc_Gen 0.1 – 500.00 V 0.01 V 50
6 k_RotUV_LossExc_Gen 0.00 – 10.00 (pu) 0.01 (pu) 2
7 V_TermUV_LossExc_Gen 0.10 – 100.00 V 0.01 V 85
8 V_BusUV_LossExc_Gen 0.10 – 100.00 V 0.01 V 90
9 t_LossExc1_Gen 0.10 – 10.00 S 0.01 S 0.5
10 t_LossExc2_Gen 0.10 – 10.00 S 0.01 S 1
11 t_LossExc3_Gen 0.10 – 3000.00 S 0.01 S 3
12 TrpLog_LossExc1_Gen 00000000- 3FFFFFFF 1 0007
13 TrpLog_LossExc2_Gen 00000000- 3FFFFFFF 1 0007
14 TrpLog_LossExc3_Gen 00000000- 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
15 En_Z_LossExc1_Gen 0, 1 1
16 En_RotUV_LossExc1_Gen 0, 1 0
17 En_BusUV_LossExc1_Gen 0, 1 0
18 En_TermUV_LossExc2_Gen 0, 1 0
19 En_Z_LossExc2_Gen 0, 1 1
20 En_RotUV_LossExc2_Gen 0, 1 0
21 En_Z_LossExc3_Gen 0, 1 1
22 En_RotUV_LossExc3_Gen 0, 1 0
23 En_Alm_LossExc3_Gen 0, 1 0
24 Opt_Z_LossExc_Gen 0, 1 0
25 En_RevQ_LossExc_Gen 0, 1 0

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7.6.14.2 Setting Description

1. X1_LossExc_Gen

Impedance setting1 of loss-of-excitation protection. In the following figure,


jx
Xc

R
Xa

Xb

Figure 7.6-1 Impedance circle of loss of excitation protection

Xa
For asynchronous impedance cycle, this setting represents for , and the next setting (NO.2) is

Xb
. Here

X d' U gn  n a
2
Xa    Equation 7.6-51
2 S gn  nv

X d'
2
U gn  na
X b  ( X d  ) Equation 7.6-52
2 S gn  nv

Where:
'
Xd Xd
and are unsaturated per unit value of transient reactance and synchronous reactance of
generator,

U gn S gn
and are rated voltage and rated apparent power of generator;

na nv
and are CT ratio and VT ratio.

XC Xb
For steady state stability limit circle, this setting represents for , and the next setting is ,
here
2
U gn  na
Xc  Xs  Equation 7.6-53
S gn  nv

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X d'
2
U gn  na
X b  ( X d  ) Equation 7.6-54
2 S gn  nv

Where:

Xs
is equivalent reactance on system side (including step-up transformer) connected with the
generator (per unit value, reference capacity is apparent power of the generator).
Asynchronous impedance circle and steady state stability limit circle can be selected by logic
setting [Opt_Z_LossExc_Gen].
For practical project, impedance between asynchronous impedance circle and steady state
stability limit circle can be selected for optimal combination of reliability and speed.

2. X2_LossExc_Gen

Impedance setting2 of loss-of-excitation protection

3. Q_RevQ_LossExc_Gen

Reverse power setting of reactive power


Reverse reactive power criterion:
Q jx
Q zd  K rel  Equation 7.6-55
Pgn

Where:

K rel
is reliability factor, 1 - 1.3;

Q jx
is permissive incoming reactive power to the generator;

Pgn
is rated active power of the generator.
Reverse reactive power criterion can be selected by logic setting [En_RevQ_LossExc_Gen] .

4. V_RotUV_LossExc_Gen

Low voltage setting of rotor. There are two low voltages setting of rotor, they are
a) Excitation undervoltage criterion

U fd .op  K rel  U fd 0 Equation 7.6-56

Where:

U fd .op
is this setting.

K rel
is reliability factor, 0.60 – 0.80;

U fd 0
is rated excitation voltage of the generator without load.
b) Variable excitation voltage criterion

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U fd 0
For a generator connecting with power system, there is a necessary excitation voltage for
keeping steady state stability.
Variable excitation voltage criterion is

P
U fd .op  K xs  U fd 0  Equation 7.6-57
Sn

K xs  K rel  ( X d  X S ) Equation 7.6-58

Where:

K xs
is rotor voltage criterion coefficient.

K rel is reliability factor, 0.70 – 0.85;

Xd Xs
and are per unit value of synchronous reactance of generator and equivalent reactance of
system connecting with the generator (referred to rated capacity of the generator);
P is current active power of the generator;
U fd 0
is rated excitation voltage of generator without load;

5. Un_RotNoLoad_LossExc_Gen

Rated excitation voltage of the generator without load.

6. k_RotUV_LossExc_Gen

Restrained coefficient of low voltage criterion of rotor.

7. V_TermUV_LossExc_Gen

Low voltage setting for generator terminal undervoltage criterion.


This criterion is used mainly to prevent generator terminal voltage lower than the permissible value
due to loss of excitation of generator.
Under voltage criterion for three phase simultaneously:

U op.3 ph  K rel  U gn Equation 7.6-59

Where:

K rel
is reliability factor, 0.85 – 0.90;

U gn rated voltage of generator.

8. V_BusUV_LossExc_Gen

Low voltage setting for busbar undervoltage criterion.


This criterion is used mainly to prevent voltage collapse due to loss of excitation of generator for a

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system without enough spare reactive power. Voltage on bus of system side is adopted for this
criterion.
Under voltage criterion for three phase simultaneously:

U op.3 ph  K rel  U h. min Equation 7.6-60

Where:

K rel
is reliability factor, 0.90 – 0.95;

U h. min
is minimum normal operation voltage of HV side of the system.
This criterion can also be configured as 0.90 – 0.95 times of terminal voltage of generator.

9. t_LossExc1_Gen

Delay of loss-of-excitation protection stage 1

10. t_LossExc2_Gen

Delay of loss-of-excitation protection stage 2

11. t_LossExc3_Gen

Delay of loss-of-excitation protection stage 3

12. TrpLog_LossExc1_Gen

Tripping output logic setting of loss-of-excitation protection stage 1

13. TrpLog_LossExc2_Gen

Tripping output logic setting of loss-of-excitation protection stage 2

14. TrpLog_LossExc3_Gen

Tripping output logic setting of loss-of-excitation protection stage 3

15. En_Z_LossExc1_Gen

Enable impedance criterion in loss-of-excitation protection stage 1

16. En_RotUV_LossExc1_Gen

Enable the criterion of rotor voltage in loss-of-excitation protection stage 1

17. En_BusUV_LossExc1_Gen

Enable the criterion of busbar voltage in loss-of-excitation protection stage 1

18. En_TermUV_LossExc2_Gen

Enable the criterion of generator terminal voltage in loss-of-excitation protection stage 2

19. En_Z_LossExc2_Gen

Enable impedance criterion in loss-of-excitation protection stage 2

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20. En_RotUV_LossExc2_Gen

Enable the criterion of rotor voltage in loss-of-excitation protection stage 2

21. En_Z_LossExc3_Gen

Enable impedance criterion in loss-of-excitation protection stage 3.

22. En_RotUV_LossExc3_Gen

Enable the criterion of rotor voltage in loss-of-excitation protection stage 3

23. En_Alm_LossExc3_Gen

Enable alarm function of loss-of-excitation protection stage 3

24. Opt_Z_LossExc_Gen

Impedance circle option.


―0‖, choose steady state stability circle.
―1‖, choose asynchronous impedance cycle.

25. En_RevQ_LossExc_Gen

Enable reverse power criterion

Note:
There must be one stage of loss-of-excitation protection, the criterion of busbar voltage is not
enabled and it will operate to reduce power output.

Following criterion are recommended for various stages of this protection:

Criterion Stage 1 Stage 2 Stage 3


Stator side impedance √ √ √ √
Busbar under voltage criterion √
Generator terminal under voltage criterion √
Rotor voltage criterion √ √ √ √
power output reduction √ √
switching over backup excitation √ √
Delay ( s ) 0.5–1s 0.5–1s 0.5–1s >1s

7.6.14.3 Access Path

Main Menu -> Settings -> GenProt Settings -> LossExcProt Settings

7.6.15 Settings of Out-of-step Protection

7.6.15.1 Setting List

Table 7.6-14 List of out-of-step protection

No. Symbol Range Step Default

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1 Za_OOS_Gen 0.00 –100.00 Ω 0.01 Ω 10


2 Zb_OOS_Gen 0.00 –100.00 Ω 0.01 Ω 5
3 Zc_OOS_Gen 0.00 –100.00 Ω 0.01 Ω 5
4 φ_Reach_OOS_Gen 0 – 90.00 ° 0.01 ° 85
5 φ_Inner_OOS_Gen 0 –150.00 ° 0.01 ° 120
6 n_Slip_Ext_OOS_Gen 1-1000 1 5
7 n_Slip_Int_OOS_Gen 1-1000 1 2
8 Ibrk_CB_HVS_Tr 0.10 – 100.00 A 0.01 A 10
9 TrpLog_OOS_Gen 00000000 – 3FFFFFFF 0.01 0007
Logic setting ―1‖ - enable, ―0‖ – disable
10 En_Alm_Ext_OOS_Gen 0, 1 1
11 En_Trp_Ext_OOS_Gen 0, 1 0
12 En_Alm_Int_OOS_Gen 0, 1 1
13 En_Trp_Int_OOS_Gen 0, 1 0

7.6.15.2 Setting Description

Explanation of the settings


Out-of-step protection operates only when out-of-step occurs in power system. Then, based on
situation at that time, the dispatching center will adopt islanding, generator shutting or restraint and
other necessary measures. Only if center of oscillation situates within the generator or near the
generator, or the oscillation lasts too long, and phase difference of electro-motive force between
two sides of the breaker less than 90°, this protection will trip.
Characteristic of this protection comprises three parts: lens part ②, boundary part ① and
reactance line part ③. See the following figure.
jx

Za
U

D
Zc 3
OL
IL
1  IR
 OR
0
R
1

Zb
2
L R

Figure 7.6-2 Impedance of out-of-step protection

1. Za_OOS_Gen

Impedance setting A of out-of-step protection.


Refer to Figure 7.6-2, this setting can be set by means of the following formula.
2
U gn  na
Za  ( X S  X C )  Equation 7.6-61
S gn  nv
Where:

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X C is per unit value of equivalent reactance of transformer connecting to the generator;

X S is equivalent reactance of power system network;

U gn S gn
and are rated voltage and rated apparent power of generator;

na nv
and are CT ratio and VT ratio.

2. Zb_OOS_Gen

Impedance setting B of out-of-step protection.


Refer to figure 7.3.2, this setting can be set by means of the following formula.
2
U gn  na
Z b   X d'  Equation 7.6-62
S gn  nv
Where:

X d' is transient reactance of generator;

3. Zc_OOS_Gen

Impedance setting C of out-of-step protection. Reactance line is the dividing line of oscillation
center. Refer to Figure 7.6-2, this setting can be set by means of the following formula. In practice,
0.9 times of transformer impedance is recommended.
2
U gn  na
Z c  0.9  X c  Equation 7.6-63
S gn  nv

4. φ_Reach_OOS_Gen

Reach angle of system impedance.

 = 80°- 85°according to the real angle of system.

5. φ_Inner_OOS_Gen

Internal angle of lens characteristic  , 120° is recommended. The following formula is for
reference,

2Z r
  180  2 arctan
Z a  Zb

1
Zr  RL. min Equation 7.6-64
1.3

RL. min
Where is minimum load impedance of generator.

6. n_Slip_Ext_OOS_Gen

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Pole sliding number setting for external fault of generator. When the oscillation center situates
outside the protected section, times of pole sliding shall be set as 2 – 15 for alarm and more than
15 for tripping.

7. n_Slip_Int_OOS_Gen

Pole sliding number setting for internal fault of generator. When the oscillation center situates
within the protected section, time of pole sliding shall be set as 1-2 in general.

8. Ibrk_CB_HVS_Tr

Tolerating current of breaker in tripping. This is an auxiliary criterion and is determined by


interruption capacity of the circuit breaker of main transformer.

9. TrpLog_OOS_Gen

Tripping output logic setting of out-of-step protection.

10. En_Alm_Ext_OOS_Gen

Enable alarm in out-of-step case outside the generator.

11. En_Trp_Ext_OOS_Gen

Enable tripping in out-of-step case outside the generator.

12. En_Alm_Int_OOS_Gen

Enable alarm in out-of-step case inside the generator.

13. En_Trp_Int_OOS_Gen

Enable tripping in out-of-step case inside the generator.

7.6.15.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenOOSProt Settings

7.6.16 Settings of Overvoltage Protection

7.6.16.1 Setting List

Table 7.6-15 List of overvoltage protection settings

No. Symbol Range Step Default


1 V_OV1_Gen 0.10 –200.00 V 0.01V 150
2 t_OV1_Gen 0.00 – 10.00 S 0.01S 0.3
3 TrpLog_OV1_Gen 00000000 – 3FFFFFFF 1 0007
4 V_OV2_Gen 0.10 –200.00 V 0.01V 130
5 t_OV2_Gen 0.00 – 10.00 S 0.01S 0.5
6 TrpLog_OV2_Gen 00000000 – 3FFFFFFF 1 0007

7.6.16.2 Setting Description

1. V_OV1_Gen

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Voltage setting of overvoltage protection stage 1.


Setting of overvoltage protection of stator shall base on permissive overvoltage capability provided
by the factory or insulation condition of the stator.
For turbo-generator with capacity more than 200 MW,

U op  1.3U gn Equation 7.6-65

Where:

U gn
is the secondary rated phase-to-phase voltage.
This is used for islanding and excitation shutting with delay 0.5 s.
For hydro-generator,

U op  1.5U gn Equation 7.6-66

This is used for islanding and excitation shutting with delay 0.5 s.
For hydro-generator with SCR excitation,

U op  1.3U gn Equation 7.6-67

This is used for islanding and excitation shutting with delay 0.3 s.

2. t_OV1_Gen

Delay of overvoltage protection stage1.

3. TrpLog_OV1_Gen

Tripping output logic setting of overvoltage protection stage1.

4. V_OV2_Gen

Voltage setting of overvoltage protection stage 2.

5. t_OV2_Gen

Delay of overvoltage protection stage2.

6. TrpLog_OV2_Gen

Tripping output logic setting of overvoltage protection stage2.

7.6.16.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenVoltProt Settings

7.6.17 Settings of Overexcitation Protection of Generator

7.6.17.1 Setting List

Table 7.6-16 List of over excitation protection settings of generator

No. Symbol Range Step Default


1 k_OvExc1_Gen 1.00 – 2.00 0.01 1.4
2 t_OvExc1_Gen 0.1 – 3000.0 S 0.1 S 1

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3 TrpLog_OvExc1_Gen 00000000 – 3FFFFFFF 1 0007


4 k_Alm_OvExc_Gen 1.00 – 2.00 0.01 1.1
5 t_Alm_OvExc_Gen 0.1 – 25.00 S 0.1 S 10
6 k0_InvOvExc_Gen 1.00 – 2.00 0.01 1.5
7 t0_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 1
8 k1_InvOvExc_Gen 1.00 – 2.00 0.01 1.45
9 t1_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 2
10 k2_InvOvExc_Gen 1.00 – 2.00 0.01 1.4
11 t2_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 5
12 k3_InvOvExc_Gen 1.00 – 2.00 0.01 1.3
13 t3_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 15
14 k4_InvOvExc_Gen 1.00 – 2.00 0.01 1.25
15 t4_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 30
16 k5_InvOvExc_Gen 1.00 – 2.00 0.01 1.2
17 t5_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 100
18 k6_InvOvExc_Gen 1.00 – 2.00 0.01 1.15
19 t6_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 300
20 k7_InvOvExc_Gen 1.00 – 2.00 0.01 1.1
21 t7_InvOvExc_Gen 1.0 – 3000.0 S 0.1 S 1000
22 TrpLog_InvOvExc_Gen 00000000 – 3FFFFFFF 1 0007

7.6.17.2 Setting Description

1. k_OvExc1_Gen

Setting of stage 1 of definite time over excitation protection.


U
B U gn
N    U  / f   1.3 or data provided by the factory
Bn f
f gn

2. t_OvExc1_Gen

Delay of stage 1 of definite time over excitation protection.

3. TrpLog_OvExc1_Gen

Tripping output logic setting of stage 1 of definite time over excitation protection. The function of
this protection is used for islanding, excitation shutting or programming, excitation reducing etc.

4. k_Alm_OvExc_Gen

Setting of over excitation alarm. Setting of alarm shall be lower than that of over excitation
protection. 1.1 is recommended.

5. t_Alm_OvExc_Gen

Delay of over excitation alarm.

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6. k0_InvOvExc_Gen

Upper limit of inverse time over excitation protection—n0

7. t0_InvOvExc_Gen

Delay of upper limit of inverse time over excitation protection.

8. k1_InvOvExc_Gen

Inverse time over excitation factor1—n1. Setting range of various inverse time over excitation
coefficient s is 1.0 – 2.0. However setting of upper limit of over excitation factor n0 shall be higher
than that of over excitation factor1 n1, that of factor1 n1 shall be higher than that of factor2 n2, etc.
Finally, setting of over excitation factor6 n6 shall be higher than that of lower limit.

9. t1_InvOvExc_Gen

Delay at the point n1 on inverse time over excitation curve—t1


The range of delay of various inverse time over excitation protection stage is 1s to 3000 s, ie.,0--50
min. Delay of upper limit of over excitation factor shall be shorter than that of over excitation
factor1, that of factor1 shall be shorter than that of factor2, etc.. Finally, delay of over excitation
factor6 shall be shorter than that of lower limit.

10. k2_InvOvExc_Gen

Inverse time over excitation factor n2.

11. t2_InvOvExc_Gen

Delay at the point n2 on inverse time over excitation curve—t2

12. k3_InvOvExc_Gen

Inverse time over excitation ratio n3.

13. t3_InvOvExc_Gen

Delay at the point n3 on inverse time over excitation curve—t3.

14. k4_InvOvExc_Gen

Inverse time over excitation ratio n4.

15. t4_InvOvExc_Gen

Delay at the point n4 on inverse time over excitation curve—t4.

16. k5_InvOvExc_Gen

Inverse time over excitation ratio n5.

17. t5_InvOvExc_Gen

Delay at the point n5 on inverse time over excitation curve—t5.

18. k6_InvOvExc_Gen

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Inverse time over excitation ratio n6.

19. t6_InvOvExc_Gen

Delay at the point n6 on inverse time over excitation curve—t6.

20. k7_InvOvExc_Gen

Inverse time over excitation ratio n7.

21. t7_InvOvExc_Gen

Delay at the point n7 on inverse time over excitation curve—t7.

22. TrpLog_InvOvExc_Gen

Tripping output logic setting of inverse time over excitation protection.

7.6.17.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenOvExcProt Settings

7.6.18 Settings of Power Protection of Generator

7.6.18.1 Setting List

Table 7.6-17 List of power protection settings of generator

No. Symbol Range Step Default


1 P_RevP_Gen 0.50 – 50.00 % 0.01% 2
2 t_Alm_RevP_Gen 0.10 – 3000.00 S 0.01 S 10
3 t_Trp_RevP_Gen 0.10 – 3000.00 S 0.01 S 10
4 TrpLog_RevP_Gen 00000000 – 3FFFFFFF 1 0007
5 P_SeqTrpRevP_Gen 0.50 – 10.00 % 0.01 % 2
6 t_SeqTrpRevP_Gen 0.01 – 10.00 S 0.01 S 1
7 TrpLog_SeqTrpRevP_Gen 00000000 – 3FFFFFFF 1 0007
8 P_UP_Gen 0.50 – 10.00 % 0.01 % 2
9 t_UP_Gen 0.01 – 10.00 M 0.01 M 1
10 TrpLog_UP_Gen 00000000 – 3FFFFFFF 1 0007

7.6.18.2 Setting Description

1. P_RevP_Gen

Power setting of reverse power protection.

Pop  K rel ( P1  P2 ) Equation 7.6-68

Where:

K rel
is reliability coefficient, 0.5 – 0.8 generally;

P1 is minimum loss of turbine during reverse power operation, 2% - 4% of rated power generally;

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P2 is minimum loss of generator during reverse power operation, P2  (1   ) Pgn generally, 


is efficiency factor of generator, 98.6% - 98.7%;

Pgn
is rated power of generator.

Pop
is set as 1% - 2% of rated active power generally, and 1% is recommended.

2. t_Alm_RevP_Gen

Delay of reverse power alarm. For reverse power protection without steam valve contact blocking,
delay 15 s for alarm.

3. t_Trp_RevP_Gen

Delay of reverse power protection. For reverse power protection without steam valve contact
blocking, according to permissive operation time of reverse power, delay 1 min – 3 min is set for
islanding in general.
For program reverse power protection with steam valve contact blocking, delay 0.5 s – 1.5 s is set
for islanding.

4. TrpLog_RevP_Gen

Tripping output logic setting of reverse power protection.

5. P_SeqTrpRevP_Gen

Power setting of sequent-tripping reverse power protection.

6. t_SeqTrpRevP_Gen

Delay of sequent-tripping reverse power protection.


For sequent-tripping reverse power protection with steam valve contact blocking, delay 0.5 s –
1.00 s for islanding.

7. TrpLog_SeqTrpRevP_Gen

Tripping output logic setting of sequent-tripping reverse power protection.

8. P_UP_Gen

Power setting of low power protection. 1%~2% of rated active power is recommended.

9. t_UP_Gen

Power setting of low power protection.


For low power protection controlled by un-emergency shutoff binary input, delay 0.5 s – 1.5 s is set
for islanding.

10. TrpLog_UP_Gen

Tripping output logic setting of low power protection.

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7.6.18.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenPwrProt Settings

7.6.19 Settings of Underfrequency and Overfrequency Protection

7.6.19.1 Setting List

Table 7.6-18 List of frequency protection settings

No. Symbol Range Step Default


45.00 – 51.00 Hz (for 50Hz system)
1 f_UF1_Gen 0.01 Hz 48.5
50.00 – 61.00 Hz (for 60Hz system)
2 t_Accu_UF1_Gen 0.10 –300.00 min 0.01min 10
45.00 – 51.00 Hz (for 50Hz system)
3 f_UF2_Gen 0.01 Hz 48
50.00 – 61.00 Hz (for 60Hz system)
4 t_UF2_Gen 0.10 –300.00 min 0.01min 10
45.00 – 51.00 Hz (for 50Hz system)
5 f_UF3_Gen 0.01 Hz 47.5
50.00 – 61.00 Hz (for 60Hz system)
6 t_UF3_Gen 0.10 –100.00 S 0.01 S 10
7 TrpLog_UF_Gen 00000000 – 3FFFFFFF 1 0007
50.00 – 60.00 Hz (for 50Hz system)
8 f_OF1_Gen 0.01 Hz 51.5
55.00 – 70.00 Hz (for 60Hz system)
9 t_OF1_Gen 0.10 –100.00 min 0.01min 10
50.00 – 60.00 Hz (for 50Hz system)
10 f_OF2_Gen 0.01 Hz 55
55.00 – 70.00 Hz (for 60Hz system)
11 t_OF2_Gen 0.10 –100.00 S 0.01 S 10
12 TrpLog_OF_Gen 00000000 – 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
13 En_Alm_UF1_Gen 0, 1 1
14 En_Trp_UF1_Gen 0, 1 0
15 En_Alm_UF2_Gen 0, 1 1
16 En_Trp_UF2_Gen 0, 1 0
17 En_Alm_UF3_Gen 0, 1 1
18 En_Trp_UF3_Gen 0, 1 0
19 En_Alm_OF1_Gen 0, 1 1
20 En_Trp_OF1_Gen 0, 1 0
21 En_Alm_OF2_Gen 0, 1 1
22 En_Trp_OF2_Gen 0, 1 0

7.6.19.2 Setting Description

1. f_UF1_Gen

Frequency setting of under frequency protection stage1.

2. t_UF1_Gen

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The sum of delay setting of under frequency protection stage1.

3. f_UF2_Gen

Frequency setting of under frequency protection stage2.

4. t_UF2_Gen

Delay of under frequency protection stage2.

5. f_UF3_Gen

Frequency setting of under frequency protection stage3.

6. t_UF3_Gen

Delay of under frequency protection stage3.

7. TrpLog_UF_Gen

Tripping output logic setting of under frequency protection.

8. f_OF1_Gen

Frequency setting of over frequency protection stage1.

9. t_OF1_Gen

Delay of over frequency protection stage1.

10. f_OF2_Gen

Frequency setting of over frequency protection stage2.

11. t_OF2_Gen

Delay of over frequency protection stage2.

12. TrpLog_OF_Gen

Tripping output logic setting of over frequency protection.

13. En_Alm_UF1_Gen

Enable alarm function of under frequency protection stage1.

14. En_Trp_UF1_Gen

Enable tripping function of under frequency protection stage1.

15. En_Alm_UF2_Gen

Enable alarm function of under frequency protection stage2.

16. En_Trp_UF2_Gen

Enable tripping function of under frequency protection stage2.

17. En_Alm_UF3_Gen

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Enable alarm function of under frequency protection stage3.

18. En_Trp_UF3_Gen

Enable tripping function of under frequency protection stage3.

19. En_Alm_OF1_Gen

Enable alarm function of over frequency protection stage1.

20. En_Trp_OF1_Gen

Enable tripping function of over frequency protection stage1.

21. En_Alm_OF2_Gen

Enable alarm function of over frequency protection stage2.

22. En_Trp_OF2_Gen

Enable tripping function of over frequency protection stage2.

7.6.19.3 Access Path

Main Menu -> Settings -> GenProt Settings -> GenFreqProt Settings

7.6.20 Settings of Startup and Shutdown Protection of Generator

7.6.20.1 Setting List

Table 7.6-19 List of startup and shutdown protection settings of generator

No. Symbol Range Step Default


40.0 – 50.0Hz (for 50Hz system)
1 f_UF_StShut_Gen 0.01 Hz 45
50.0 – 60.0Hz (for 60Hz system)
2 I_GenDiff_StShut_Gen 0.1 - 14.0 (Ie) 0.01 (Ie) 1
3 TrpLog_Diff_StShut_Gen 00000000 - 3FFFFFFF 1 0007
4 V_StaROV_StShut_Gen 5 – 25.0 V 0.01 V 10
5 t_StaROV_StShut_Gen 0.00 – 10.0 S 0.01 S 10
6 TrpLog_StaROV_StShut_Gen 00000000 - 3FFFFFFF 1 0007
7 I_OC_StShut_Gen 0.1 - 100.0 (Ie) 0.01 (Ie) 10
8 t_OC_StShut_Gen 0.00 – 10.0 S 0.01 S 10
9 TrpLog_OC_StShut_Gen 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
10 En_GenDiff_StShut_Gen 0, 1 1
11 En_StaROV_StShut_Gen 0, 1 1
12 En_GenCur_StShut_Gen 0, 1 1

7.6.20.2 Setting Description

1. f_UF_StShut_Gen

Frequency setting for blocking startup and shutdown protection of generator.

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Startup and shutdown protection is used for earth fault and phase-to-phase fault of stator during
low speed operation of the generator. Its algorithm is insensitive to variation of frequency.
This protection is auxiliary protection of generator during low frequency operation. Blocking setting
of this protection is 0.8 – 0.9 times of rated frequency.

2. I_GenDiff_StShut_Gen

Differential current setting for the differential protection of generator in startup and shutdown
condition. Setting of this protection shall be higher than unbalance differential current in full load
and rated frequency condition,

I op  K rel I unb Equation 7.6-69

Where:

K rel
is reliability factor, 1.30 – 1.50 generally;

I unb
is the unbalance differential current in full load and rated frequency condition.

3. TrpLog_Diff_StShut_Gen

Tripping output logic setting of low frequency differential protection of generator in startup and
shutdown condition.

4. V_StaROV_StShut_Gen

Zero sequence voltage setting of stator earth fault protection in startup and shutdown condition.
For earth fault, zero sequence voltage derived from neutral point is adopted as criterion with
setting 10 V in general.

5. t_StaROV_StShut_Gen

Delay of stator earth fault protection in startup and shutdown condition. It should be not shorter
than delay of fundamental zero sequence voltage earth fault protection for stator.

6. TrpLog_StaROV_StShut_Gen

Tripping output logic setting of stator earth fault protection in startup and shutdown condition.

7. I_OC_StShut_Gen

Current setting of overcurrent protection in startup and shutdown condition. 1.1~1.3 times of rated
current is recommended.

8. t_OC_StShut_Gen

Time delay of overcurrent protection in startup and shutdown condition.

9. TrpLog_OC_StShut_Gen

Tripping output logic setting of overcurrent protection in startup and shutdown condition.

10. En_GenDiff_StShut_Gen

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Enable differential current protective element of generator in startup and shutdown condition.

11. En_StaROV_StShut_Gen

Enable low frequency zero sequence voltage protective element of stator in startup and shutdown
condition.

12. En_GenCur_StShut_Gen

Enable low frequency overcurrent element in startup and shutdown condition.

7.6.20.3 Access Path

Main Menu -> Settings -> GenProt Settings -> StShutProt Settings

7.6.21 Settings of Inadvertent Energization Protection of Generator

7.6.21.1 Setting List

Table 7.6-20 List of accidental energaization protection settings of generator

No. Symbol Range Step Default


40.0 – 50.0Hz (for 50Hz system)
1 f_UF_AccEnerg_Gen 0.01 Hz 45
50.0 – 60.0Hz (for 60Hz system)
2 I_OC_AccEnerg_Gen 0.10 – 50.00 A 0.01 A 3
3 V_UV_AccEnerg_Gen 6.00-80.00V 0.01 V 12
4 t_AccEnerg_Gen 0.01 – 1.00 S 0.01 s 0.1
5 TrpLog_AccEnerg_Gen 00000000 - 3FFFFFFF 1 0007
6 I_NegOC_Flash_CB_HVS_Tr 0.10 – 20.00 A 0.01 A 3
7 I_ROC_Flash_CB_HVS_Tr 0.10 – 20.00 A 0.01 A 3
8 I_OC_Flash_CB_HVS_Tr 0.10 – 20.00 A 0.01 A 4
9 t_Flash1_CB_HVS_Tr 0.01 – 2.00 S 0.01 s 0.3
10 TrpLog_Flash1_CB_HVS_Tr 00000000 - 3FFFFFFF 1 0007
11 t_Flash2_CB_HVS_Tr 0.01 – 2.00 S 0.01 s 0.4
12 TrpLog_Flash2_CB_HVS_Tr 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
13 En_CB_Ctrl_AccEnerg_Gen 0, 1 0

7.6.21.2 Setting Description

1. f_UF_AccEnerg_Gen

Frequency setting for blocking accident energization protection of generator.


Frequency blocking setting shall be 80% - 90% of the rated frequency, i.e., 40 Hz – 45 Hz.

2. I_OC_AccEnerg_Gen

Current setting of accident energization overcurrent protection.


Current setting shall be 50% of minimum accidental closing current (generator terminal side)
during process of generator starting up but having not been excited. If accidental closing current of
circuit breaker on auxiliary transformer side shall be taken into account, current setting shall base

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on minimum accidental closing current during this condition. The current used for this setting is
derived from the CT at the terminal of generator.
In general, this setting shall be in excess of 1.3 times of rated current of generator.

3. V_UV_AccEnerg_Gen

Voltage setting of accident energization protection. 12V is recommended.

4. t_AccEnerg_Gen

Delay of accident energization overcurrent protection.

5. TrpLog_AccEnerg_Gen

Tripping output logic setting of accident energization overcurrent protection.

6. I_NegOC_Flash_CB_HVS_Tr

Negative sequence current setting of breaker flashover protection.


This setting shall be higher than possible unbalance current during normal operation. It must be
set according to the secondary current of the CT at the HV side of main transformer.

7. I_ROC_Flash_CB_HVS_Tr

Zero-sequence current setting of breaker flashover protection.

8. I_OC_Flash_CB_HVS_Tr

Phase current setting of breaker flashover protection.

9. t_Flash1_CB_HVS_Tr

Time delay 1 of breaker flashover protection.


This setting shall be longer than operation time of circuit breaker.

10. TrpLog_Flash1_CB_HVS_Tr

Tripping output logic setting of breaker flashover protection with time delay 1.
If impulse current may be higher than capacity of circuit breaker during asynchronous closing, the
protection shall shut off the excitation firstly. If current passing through circuit breaker is lower than
permissive value, the protection can trip the circuit breaker on outlet.
Permissive tripping current of circuit breaker shall be configured as that provided by factory.

11. t_Flash2_CB_HVS_Tr

Time delay 2 of breaker flashover protection.

12. TrpLog_Flash2_CB_HVS_Tr

Tripping output logic setting of breaker flashover protection with time delay 2.

13. En_CB_Ctrl_AccEnerg_Gen

Enable breaker position auxiliary contact blocking function.


If asynchronous unwanted closing is considered, breaker position contact blocking shall be

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selected.

7.6.21.3 Access Path

Main Menu -> Settings -> GenProt Settings -> AccEnergProt Settings

7.6.22 Settings of Breaker Failure Protection of Generator

7.6.22.1 Setting List

Table 7.6-21 List of breaker failure protection settings of generator

No. Symbol Range Step Default


1 I_OC_BFP_GCB 0.10 –20.00 (Ie) 0.01 (Ie) 0.3
2 I_NegOC_BFP_GCB 0.10 –20.00 (Ie) 0.01 (Ie) 6
3 t_BFP11_GCB 0.00– 10.00 s 0.01 s 0.1
4 TrpLog_BFP11_GCB 00000000 - 3FFFFFFF 1 FFFE
5 t_BFP12_GCB 0.00– 10.00 s 0.01s 0.7
6 TrpLog_BFP12_GCB 00000000 - 3FFFFFFF 1 FFFE
Logic setting ―1‖ – enable, ―0‖ – disable
7 En_NegOC_BFP_GCB 0, 1 0
8 En_OC_BFP_GCB 0, 1 0

7.6.22.2 Setting Description

1. I_OC_BFP_GCB

Phase current setting of generator breaker failure protection. It should be larger than rated current
of generator.

K rel
I op  I gn Equation 7.6-70
K r na

Where:

I OP is the setting [I_OC_BFP_GCB].

K rel
is reliability factor, takes 1.1~1.3;

K r is release factor, takes 0.90~0.95;

I gn
is secondary rated current of generator.

na
is CT ratio

2. I_NegOC_BFP_GCB

Negative-sequence current setting of generator breaker failure protection. It should be larger than
maximum unbalance negative sequence current under normal operating condition.

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I gn
I 2 op  (0.1 ~ 0.2) Equation 7.6-71
na

3. t_BFP11_GCB

Time delay 1 of generator breaker failure protection. It should be long than tripping time of the
breaker, takes 0.3~0.5s.

4. TrpLog_BFP11_GCB

Tripping output logic setting of generator breaker failure protection with time delay 1.

5. t_BFP12_GCB

Time delay 2 of generator breaker failure protection.

6. TrpLog_BFP12_GCB

Tripping output logic setting of generator breaker failure protection with time delay 2.

7. En_NegOC_BFP_GCB

Enable generator breaker failure protection being blocked by negative-sequence current element.

8. En_OC_BFP_GCB

Enable generator breaker failure protection being blocked by phase current element.

7.6.22.3 Access Path

Main Menu -> Settings -> GenProt Settings -> AccEnergProt Settings

7.6.23 Settings of Differential Protection of Step-down Transformer 1&2

7.6.23.1 Setting List

Table 7.6-22 List of differential protection settings of step-down transformer

No. Symbol Range Step Default


1 I_Pkp_PcntDiff_ST1(2) 0.10 –1.50 (Ie) 0.01 (Ie) 0.3
2 I_InstDiff_ST1(2) 2.00 – 14.00 (Ie) 0.01 (Ie) 6
3 I_AlmDiff_ST1(2) 0.05– 1.00 (Ie) 0.01 (Ie) 0.1
4 Slope1_PcntDiff_ST1(2) 0.00– 0.50 0.01 0.1
5 Slope2_PcntDiff_ST1(2) 0.50 – 0.80 0.01 0.7
6 k_Harm_PcntDiff_ST1(2) 0.10 – 0.35 0.01 0.15
7 TrpLog_Diff_ST1(2) 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ – enable, ―0‖ – disable
8 En_InstDiff_ST1(2) 0, 1 1
9 En_PcntDiff_ST1(2) 0, 1 1
10 Opt_Inrush_Ident_ST1(2) 0, 1 0
11 Opt_CTS_Blk_PcntDiff_ST1(2) 0, 1 0

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7.6.23.2 Setting Description

1. I_Pkp_PcntDiff_ST1(2)

Setting of pickup value of percentage differential current of step-down transformer.

2. I_InstDiff_ST1(2)

Setting of unrestrained instantaneous differential protection of step-down transformer.

3. I_AlmDiff_ST1(2)

Differential current alarm setting of step-down transformer. It shall be higher than normal
unbalance differential current and lower than [I_Pkp_PcntDiff_ST1(2)].

4. Slope1_PcntDiff_ST1(2)

Restraint coefficient of the first slope of the differential characteristic curve.

5. Slope2_PcntDiff_ST1(2)

Maximum value of restraint coefficient of the differential characteristic curve.

6. k_Harm_PcntDiff_ST1(2)

Restraint coefficient of second harmonics.

7. TrpLog_Diff_ST1(2)

Tripping output logic setting of differential protection of step-down transformer.

8. En_InstDiff_ST1(2)

Enable unrestrained instantaneous differential protection of step-down transformer.

9. En_PcntDiff_ST1(2)

Enable percentage differential protection of step-down transformer.

10. Opt_Inrush_Ident_ST1(2)

Inrush current blocking mode. Select criterion of Inrush current detection.


―0‖, discrimination by harmonics;
―1‖, waveform distortion criterion is used.

11. Opt_CTS_Blk_PcntDiff_ST1(2)

Enable differential protection blocked by CT circuit failure.


Setting ―0‖: Differential protection is not blocked by CT circuit failure.
Setting ―1‖: Differential protection is blocked by CT circuit failure

7.6.23.3 Access Path

Main Menu -> Settings -> ST1Prot Settings -> ST1DiffProt Settings
Main Menu -> Settings -> ST2Prot Settings -> ST2DiffProt Settings

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7.6.24 Settings of Backup Protection at HVS of Step-down Transformer

7.6.24.1 Setting List

Table 7.6-23 List of HVS backup protection settings of step-down transformer

No. Symbol Range Step Default


1 V_NegOV_VCE_HVS_ST1(2) 1.00 – 20.00 V 0.01 V 4
2 Vpp_UV_VCE_HVS_ST1(2) 2.00 – 100.00 V 0.01 V 60
3 I_OC1_HVS_ST1(2) 0.10 – 100.00 A 0.01 A 20
4 t_OC1_HVS_ST1(2) 0.00 – 10.00 S 0.01 S 1
5 TrpLog_OC1_HVS_ST1(2) 00000000 - 3FFFFFFF 1 0007
6 I_OC2_HVS_ST1(2) 0.10 – 100.00 A 0.01 A 17
7 t_OC2_HVS_ST1(2) 0.00 – 10.00 S 0.01 S 2
8 TrpLog_OC2_HVS_ST1(2) 00000000 - 3FFFFFFF 1 0007
9 I_Alm_OvLd_HVS_ST1(2) 0.10 – 50.00 A 0.01 A 6
10 t_Alm_OvLd_HVS_ST1(2) 0.00 – 10.00 S 0.01 S 8
11 I_InitCool_OvLd_HVS_ST1(2) 0.10 – 50.00 A 0.01 A 5.5
12 t_InitCool_OvLd_HVS_ST1(2) 0.00 – 10.00 S 0.01 S 9
13 I_BlkOLTC_OvLd_ST1(2) 0.10 – 200.00 A 0.01 A 5.5
14 t_BlkOLTC_OvLd_ST1(2) 0.00 – 10.00 S 0.01 S 9
Logic setting ―1‖ – enable, ―0‖ – disable
15 En_VCE_Ctrl_OC1_HVS_ST1(2) 0, 1 0
16 En_VCE_Ctrl_OC2_HVS_ST1(2) 0, 1 0
17 En_Mem_Curr_HVS_ST1(2) 0, 1 0
18 Opt_VTS_Ctrl_OC_HVS_ST1(2) 0, 1 0
19 En_Alm_OvLd_HVS_ST1(2) 0, 1 0
20 En_InitCool_OvLd_HVS_ST1(2) 0, 1 0
21 En_BlkOLTC_OvLd_ST1(2) 0, 1 0
22 Opt_Cur_OC1_HVS_ST1(2) 0, 1 0

7.6.24.2 Setting Description

1. V_NegOV_VCE_HVS_ST1(2)

Negative sequence voltage setting of composite voltage control element at HVS of step-down
transformer. It should be larger than the unbalance negative sequence voltage under normal
condition. Unbalance negative sequence voltage can be get by actual measurement. Generally,

U op.2  (0.06  0.08)U n Equation 7.6-72

Where:

U OP.2 is the setting [V_NegOV_VCE_HVS_ST1(2)].

U n is rated secondary phase-to-ground voltage of step-down transformer.

Sensitivity factor shall be checked as follow:

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U k .2. min
K sen  Equation 7.6-73
U op.2

Where:

U k .2. min is minimum negative sequence voltage at location of the equipment during

phase-to-phase metallic short circuit fault at end of backup protected zone. K sen ≥2.0 is required

for near backup protection and K sen ≥1.5 for remote backup protection.

2. Vpp_UV_VCE_HVS_ST1(2)

Setting of phase-to-phase under voltage of composite voltage control element.

0.65  U n
U op  Equation 7.6-74
K rel K r
Where:

U OP is the setting [Vpp_UV_VCE_HVS_ST1(2)].

K rel
is reliability factor, takes 1.1~1.2;

K r is release factor, takes 1.05~1.25;

U n is rated secondary phase-to-phase voltage of step-down transformer.

Sensitivity factor shall be checked as follow:


U op
K sen  Equation 7.6-75
U c. max

Where U c . max is maximum phase-to-phase voltage at location of the equipment during three

phases metallic short circuit fault at end of backup protected zone. K sen ≥1.5 is required for near

backup protection and K sen ≥1.2 for remote backup protection.

3. I_OC1_HVS_ST1(2)

Current setting of definite time overcurrent protection stage1.

K rel
I op  Ie Equation 7.6-76
Kr
Where:

I OP is current setting of definite time overcurrent protection.

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K rel
is reliability factor, takes 1.3;

K r is release factor, takes 0.85~0.95;

I e is rated secondary current.

Sensitivity factor shall be checked as follow:

I k( .2min
)
K sen  Equation 7.6-77
I op

( 2)
where I k . min is minimum fault current through location of the relay during phase-to-phase metallic

short circuit at LVS busbar under minimum operating mode.

4. t_OC1_HVS_ST1(2)

Delay of definite time overcurrent protection stage1.

5. TrpLog_OC1_HVS_ST1(2)

Tripping output logic setting of definite time overcurrent protection.

6. I_OC2_HVS_ST1(2)

Setting of definitive time overcurrent protection stage2.

7. t_OC2_HVS_ST1(2)

Delay of definite time overcurrent protection stage2.

8. TrpLog_OC2_HVS_ST1(2)

Tripping output logic setting of definite time overcurrent protection stage2.

9. I_Alm_OvLd_HVS_ST1(2)

Current setting of overload protection at HVS of step-down transformer.

10. t_Alm_OvLd_HVS_ST1(2)

Time setting of overload protection at HVS of step-down transformer.

11. I_InitCool_OvLd_HVS_ST1(2)

Current setting of overload to initial cooling system at HVS of step-down transformer.

12. t_InitCool_OvLd_HVS_ST1(2)

Time setting of overload to initial cooling system at HVS of step-down transformer.

13. I_BlkOLTC_OvLd_ST1(2)

Current setting of overload element of HV side of stepdown transformer for blocking OLTC
(on-load tap changing).

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14. t_BlkOLTC_OvLd_ST1(2)

Time delay of overload element of HV side of stepdown transformer for blocking OLTC (on-load
tap changing).

15. En_VCE_Ctrl_OC1_HVS_ST1(2)

Logic setting of overcurrent protection stage1 controlled by voltage element.

16. En_VCE_Ctrl_OC2_HVS_ST1(2)

Logic setting of overcurrent protection stage2 controlled by voltage element.

17. En_Mem_Curr_HVS_ST1(2)

Logic setting of memory function of current.

18. Opt_VTS_Ctrl_OC_HVS_ST1(2)

Protection performance during VT circuit failure.


―1‖: when VT circuit failure at one side is detected, voltage control element at the same side will be
disabled but overcurrent relay on the same side can still be controlled by voltage control elements
of other side if corresponding logic setting is set as ―1‖.
―0‖: when VT circuit failure at one side is detected, the overcurrent relay will become an
overcurrent relay without voltage element control.

19. En_Alm_OvLd_HVS_ST1(2)

Enable alarm for overload protection at HVS of step-down transformer.

20. En_InitCool_OvLd_HVS_ST1(2)

Enable overload to initial cooling system at HVS of step-down transformer.

21. En_BlkOLTC_OvLd_ST1(2)

Enable overload element of HV side of stepdown transformer to block OLTC (on-load tap
changing). If it is set as ―1‖, RCS-985A will output contact to block regulating voltage of stepdown
transformer with load with the time delay of [t_BlkOLTC_Ovld_ST1(2)] when the current is greater
than the setting [I_BlkOLTC_Ovld_ST1(2)].

22. Opt_Cur_OC1_HVS_ST1(2)

CT selection for stage 1 of overcurrent protection of HVS of step-down transformer.


0: big ratio CT
1: small ratio CT

7.6.24.3 Access Path

Main Menu -> Settings -> ST1Prot Settings -> ST1HVSBakProt Settings
Main Menu -> Settings -> ST2Prot Settings -> ST2HVSBakProt Settings

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7.6.25 Settings of Backup Protection of Br1(2) of Step-down Transformer

7.6.25.1 Setting List

Table 7.6-24 List of LVS backup protection settings of step-down transformer

No. Symbol Range Step Default


1 V_NegOV_VCE_Br1(2)_ST1(2) 1.00 – 20.00 V 0.01 V 4
2 Vpp_UV_VCE_Br1(2)_ST1(2) 2.00 – 100.00 V 0.01 V 60
3 I_OC1_Br1(2)_ST1(2) 0.10 – 100.00 A 0.01 A 20
4 t_OC1_Br1(2)_ST1(2) 0.00 – 10.00 S 0.01 S 1
5 TrpLog_OC1_Br1(2)_ST1(2) 00000000 - 3FFFFFFF 1 0007
6 I_OC2_Br1(2)_ST1(2) 0.10 – 100.00 A 0.01 A 17
7 t_OC2_Br1(2)_ST1(2) 0.00 – 10.00 S 0.01 S 2
8 TrpLog_OC2_Br1(2)_ST1(2) 00000000 - 3FFFFFFF 1 0007
9 I_ROC1_Br1(2)_ST1(2) 0.10 – 100.00 A 0.01 A 20
10 t_ROC1_Br1(2)_ST1(2) 0.00 – 10.00 S 0.01 S 1
11 TrpLog_ROC1_Br1(2)_ST1(2) 00000000 - 3FFFFFFF 1 0007
12 I_ROC2_Br1(2)_ST1(2) 0.10 – 100.00 A 0.01 A 17
13 t_ROC2_Br1(2)_ST1(2) 0.00 – 10.00 S 0.01 S 2
14 TrpLog_ROC2_Br1(2)_ST1(2) 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ – enable, ―0‖ – disable
15 En_VCE_Ctrl_OC1_Br1(2)_ST1(2) 0, 1 0
16 En_VCE_Ctrl_OC2_Br1(2)_ST1(2) 0, 1 0
17 Opt_VTS_Ctrl_OC_Br1(2)_ST1(2) 0, 1 0

7.6.25.2 Setting Description

1. V_NegOV_VCE_Br1(2)_ST1(2)

Negative sequence voltage setting of composite voltage control element of branch 1 or branch 2 of
step-down transformer.

2. Vpp_UV_VCE_Br1(2)_ST1(2)

Setting of phase-to-phase under voltage of composite voltage control element.

3. I_OC1_Br1(2)_ST1(2)

Setting of definite time overcurrent protection stage1.

4. t_OC1_Br1(2)_ST1(2)

Delay of definite time overcurrent protection stage1.

5. TrpLog_OC1_Br1(2)_ST1(2)

Tripping output logic setting of definite time overcurrent protection.

6. I_OC2_Br1(2)_ST1(2)

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Setting of definitive time overcurrent protection stage2.

7. t_OC2_Br1(2)_ST1(2)

Delay of definite time overcurrent protection stage2.

8. TrpLog_OC2_Br1(2)_ST1(2)

Tripping output logic setting of definite time overcurrent protection stage2.

9. I_ROC1_Br1(2)_ST1(2)

Setting of definitive time zero sequence overcurrent protection stage1.

10. t_ROC1_Br1(2)_ST1(2)

Delay of definite time zero sequence overcurrent protection stage1.

11. TrpLog_ROC1_Br1(2)_ST1(2)

Tripping output logic setting of definite time zero sequence overcurrent protection stage1.

12. I_ROC2_Br1(2)_ST1(2)

Setting of definitive time zero sequence overcurrent protection stage2.

13. t_ROC2_Br1(2)_ST1(2)

Delay of definite time zero sequence overcurrent protection stage2.

14. TrpLog_ROC2_Br1(2)_ST1(2)

Tripping output logic setting of definite time zero sequence overcurrent protection stage2.

15. En_VCE_Ctrl_OC1_Br1(2)_ST1(2)

Logic setting of overcurrent protection stage1 controlled by voltage element.

16. En_VCE_Ctrl_OC2_Br1(2)_ST1(2)

Logic setting of overcurrent protection stage2 controlled by voltage element.

17. Opt_VTS_Ctrl_OC_Br1(2)_ST1(2)

Protection performance during VT circuit failure.


―1‖: when VT circuit failure at one side is detected, voltage control element at the same side will be
disabled but overcurrent relay on the same side can still be controlled by voltage control elements
of other side if corresponding logic setting is set as ―1‖.
―0‖: when VT circuit failure at one side is detected, the overcurrent relay will become an
overcurrent relay without voltage element control.

7.6.25.3 Access Path

Main Menu -> Settings -> ST1Prot Settings -> ST1Br1Prot Settings
Main Menu -> Settings -> ST2Prot Settings -> ST2Br1Prot Settings
Main Menu -> Settings -> ST1Prot Settings -> ST1Br2Prot Settings

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Main Menu -> Settings -> ST2Prot Settings -> ST2Br2Prot Settings

7.6.26 Settings of Differential Protection of Excitation Transformer or Exciter

7.6.26.1 Setting List

Table 7.6-25 List of differential protection settings of excitation transformer or exciter

No. Symbol Range Step Default


1 I_Pkp_PcntDiff_Exc 0.10 –1.50 (Ie) 0.01 (Ie) 0.3
2 I_InstDiff_Exc 2.00 – 14.00 (Ie) 0.01 (Ie) 6
3 I_AlmDiff_Exc 0.05 – 1.00 (Ie) 0.01 (Ie) 0.1
4 Slope1_PcntDiff_Exc 0.00 – 0.50 0.01 0.1
5 Slope2_PcntDiff_Exc 0.50 – 0.80 0.01 0.7
6 k_Harm_PcntDiff_Exc 0.10 – 0.35 0.01 0.15
7 TrpLog_Diff_Exc 00000000 - 3FFFFFFF 1 FFFF
Logic setting ―1‖ - enable, ―0‖ – disable
8 En_InstDiff_Exc 0, 1 1
9 En_PcntDiff_Exc 0, 1 1
10 Opt_Inrush_Ident_Exc 0, 1 0
11 Opt_CTS_Blk_PcntDiff_Exc 0, 1 0

7.6.26.2 Setting Description

1. I_Pkp_PcntDiff_Exc

Setting of pickup value of percentage differential current of excitation transformer or exciter. In


practice, for excitation transformer, characteristic of CT on two sides may differ significantly and
the unbalance differential current may be larger than that of main transformer. So for pickup
setting, larger than 0.5 Ie is recommended.

2. I_InstDiff_Exc

Setting of unrestrained instantaneous differential protection.

3. I_AlmDiff_Exc

Differential current alarm setting of excitation transformer or exciter. It shall be higher than normal
unbalance differential current and lower than [I_Pkp_PcntDiff_Exc].

4. Slope1_PcntDiff_Exc

Restraint coefficient of the first slope of the differential characteristic curve.

5. Slope2_PcntDiff_Exc

Maximum value of restraint coefficient of the differential characteristic curve.

6. k_Harm_PcntDiff_Exc

Restraint coefficient of second harmonics.

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7. TrpLog_Diff_Exc

Tripping output logic setting of differential protection of excitation transformer of exciter.

8. En_InstDiff_Exc

Enable unrestrained instantaneous differential protection of excitation transformer or exciter.

9. En_PcntDiff_Exc

Enable percentage differential protection of excitation transformer or exciter.

10. Opt_Inrush_Ident_Exc

Inrush current blocking mode. Select criterion of Inrush current detection.


―0‖, discrimination by harmonics;
―1‖, waveform distortion criterion is used.

11. Opt_CTS_Blk_PcntDiff_Exc

Enable differential protection blocked by CT circuit failure.


Setting ―0‖: Differential protection is not blocked by CT circuit failure.
Setting ―1‖: Differential protection is blocked by CT circuit failure

7.6.26.3 Access Path

Main Menu -> Settings -> ExcProt Settings -> ExcDiffProt Settings

7.6.27 Settings of Backup Protection of Excitation Transformer or Exciter

7.6.27.1 Setting List

Table 7.6-26 List of backup protection settings of excitation transformer or exciter

No. Symbol Range Step Default


1 I_OC1_Exc 0.10 – 100.00 A 0.01 A 10
2 t_OC1_Exc 0.00 – 10.00 S 0.01 S 1
3 TrpLog_OC1_Exc 00000000 - 3FFFFFFF 1 0007
4 I_OC2_Exc 0.10 – 100.00 A 0.01 A 10
5 t_OC2_Exc 0.00 – 25.00 S 0.01 S 1
6 TrpLog_OC2_Exc 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
7 Opt_CT_OC_Exc 0, 1 0

7.6.27.2 Setting Description

1. I_OC1_Exc

Setting of definite time overcurrent protection stage1.

2. t_OC1_Exc

Delay of definite time overcurrent protection stage1.

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3. TrpLog_OC1_Exc

Tripping output logic setting of definite time overcurrent protection.

4. I_OC2_Exc

Setting of definitive time overcurrent protection stage2.

5. t_OC2_Exc

Delay of definite time overcurrent protection stage2.

6. TrpLog_OC2_Exc

Tripping output logic setting of definite time overcurrent protection stage2.

7. Opt_CT_OC_Exc

CT selection for overcurrent protection of excitation transformer or exciter


0: CT of HV side
1: CT of LV side

7.6.27.3 Access Path

Main Menu -> Settings -> ExcProt Settings -> ExcBakProt Settings

Note:
The current used in the overcurrent protection is derived from the CT at the HV side of excitation
transformer or the CT at the neutral point of exciter.

7.6.28 Settings of Overload Protection of Excitation Transformer or Excitor

7.6.28.1 Setting list

Table 7.6-27 List of overload protection settings of exciter

No. Symbol Range Step Default


1 I_Alm_OvLd_RotWdg 0.10 –100.00 A(kA) 0.01A(kA) 7
2 t_Alm_OvLd_RotWdg 0.00 – 25.00 S 0.01S 2
3 I_InvOvLd_RotWdg 0.10 – 50.00 A(kA) 0.01A(kA) 6
4 tmin_InvOvLd_RotWdg 0.10 – 10.00 S 0.01S 1
5 A_Therm_RotWdg 1.00 – 100.00 0.01 40
6 Ib_InvOvLd_RotWdg 0.10 – 50.00 A 0.01A 1
7 TrpLog_InvOvLd_RotWdg 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
8 Opt_CT_OvLd_RotWdg 0, 1 1

7.6.28.2 Setting Description

1. I_Alm_OvLd_RotWdg

Current setting of overload alarm.

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It should make inverse time overload protection dropoff reliably under normal rated excitation
current. If the protection is configured at AC side, the current setting will be (rated excitation

current I fd should be converted into RMS value of AC side, if bridge-type uncontrollable rectifier

is adopted, I grn  0.816I fd ):

I grn
I op   K rel Equation 7.6-78
Kr
Where:

K rel
is reliability factor, takes 1.05;

K r is release factor, takes 0.85~0.95;

I grn is secondary rated excitation current of generator

2. t_Alm_OvLd_RotWdg

Delay of overload alarm. It should be larger than the maximum delay of backup protection.

3. I_InvOvLd_RotWdg

Pickup current of inverse time overload protection. It should coordinate with definite time overload
protection.

I grn
I OP. min  K c 0 K rel
Kr
Where:

K co is coordination factor, takes 1.05;

4. tmin_InvOvLd_RotWdg

Delay of upper limit of inverse time overload protection. It is convenient for coordinating with fast
protection.

5. A_Therm_RotWdg

Thermal capacity parameter of excitation winding.

6. Ib_InvOvLd_RotWdg

Reference current setting of inverse time overload.

7. TrpLog_InvOvLd_RotWdg

Tripping output logic setting of inverse time overload protection.

8. Opt_CT_OvLd_RotWdg

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CT selection for overload protection of excitation transformer or excitor.


0: CT of side 1
1: CT of side 2

7.6.28.3 Access Path

Main Menu -> Settings -> ExcProt Settings -> RotWdgOvLdProt Settings

7.6.29 Settings of Mechanical Protection

7.6.29.1 Setting List

Table 7.6-28 List of mechanical protection settings

No. Symbol Range Step Default


1 t_MR1 0.00 – 300.0 S 0.01S 1
2 TrpLog_MR1 00000000 - 3FFFFFFF 1 0007
3 t_MR2 0.00 – 300.0 S 0.01S 1
4 TrpLog_MR2 00000000 - 3FFFFFFF 1 0007
5 t_MR3 0.00 – 300.0 S 0.01S 1
6 TrpLog_MR3 00000000 - 3FFFFFFF 1 0007
7 t_MR4 0.00 – 6000.0 S 0.1S 1
8 TrpLog_MR4 00000000 - 3FFFFFFF 1 0007

7.6.29.2 Setting Description

1. t_MR1

Time delay of output contact of external mechanical contact input1 repeater.

2. TrpLog_MR1

Tripping output logic setting of output contact of mechanical contact input1.

3. t_MR2

Time delay of output contact of external mechanical contact input1 repeater.

4. TrpLog_MR2

Tripping output logic setting of output contact of mechanical contact input2.

5. t_MR3

Time delay of output contact of external mechanical contact input1 repeater.

6. TrpLog_MR3

Tripping output logic setting of output contact of mechanical contact input3.

7. t_MR4

Time delay of output contact of external mechanical contact input1 repeater.

8. TrpLog_MR4

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Tripping output logic setting of output contact of mechanical contact input4.

7.6.29.3 Access Path

Main Menu -> Settings -> MiscProt Settings -> MechRlyProt Settings

7.6.30 Settings of Pole Disagreement Protection of HVS of Main Transformer

7.6.30.1 Setting List

Table 7.6-29 List of pole disagreement protection settings of HVS of main transformer

No. Symbol Range Step Default


1 I_OC_PD1_HVS_Tr 0.10 –20.00 A 0.01A 1
2 I_NegOC_PD1_HVS_Tr 0.10 –20.00 A 0.01A 1
3 I_ROC_PD1_HVS_Tr 0.10 –20.00 A 0.01A 3
4 t_PD11_HVS_Tr 0.00 – 10.00 S 0.01S 0.5
5 TrpLog_PD11_HVS_Tr 00000000 - 3FFFFFFF 1 0007
6 t_PD12_HVS_Tr 0.00 – 10.00 S 0.01S 1
7 TrpLog_PD12_HVS_Tr 00000000 - 3FFFFFFF 1 0007
Logic setting ―1‖ - enable, ―0‖ – disable
8 En_NegOC_PD_HVS_Tr 0, 1 0
9 En_ROC_PD_HVS_Tr 0, 1 0
10 En_ExTrp_Ctrl_PD12_HVS_Tr 0, 1 0
11 En_OC_PD12_HVS_Tr 0, 1 0

7.6.30.2 Setting Description

1. I_OC_PD1_HVS_Tr

Phase current setting of pole disagreement protection of HVS of main transformer.

I K . min 1
I op   Equation 7.6-79
K sen nTA
Where:

K sen is Sensitivity coefficient,takes 1.3

I op is the setting [I_OC_PD1_HVS_Tr], set it larger than transformer rated secondary current as

much as possible if sensitivity is met.

I K . min the minimum fault current flow through the protection for following three occasions (for

step-up transformer)
Phase-to-phase fault at LVS of transformer;
A fault at the end of line for generator-transformer-line unit (including expansion unit);
A fault at the end of line for one and a half breakers connection.

2. I_NegOC_PD1_HVS_Tr

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Negative sequence current setting should be larger than the maximum unbalance negative
sequence current under normal condition.

K rel 8% I N
I 2.op   Equation 7.6-80
Kr nTA
Where:

K rel
is reliability factor, takes 1.2;

K r is release factor, takes 0.90;

I N is primary rated current of HV side of main transformer.

nTA is ratio of CT of main transformer HV side


Generally,

I 2.op  0.1~0.15 
IN
nTA

3. I_ROC_PD1_HVS_Tr

Zero sequence current setting should be larger than the maximum unbalance zero sequence
current under normal condition, generally,

3I 0.op  0.1~0.15 
IN
Equation 7.6-81
nTA

4. t_PD11_HVS_Tr

Time delay 1 of pole disagreement protection of HVS of main transformer. It should be larger than
maximum inconsistent time of three phase interrupters when breaker is in the process of being
closed, 0.3s generally.

5. TrpLog_PD11_HVS_Tr

Tripping output logic setting of pole disagreement protection of HVS of main transformer with time
delay 1.

6. t_PD12_HVS_Tr

Time delay 2 of pole disagreement protection of HVS of main transformer

7. TrpLog_PD12_HVS_Tr

Tripping output logic setting of pole disagreement protection of HVS of main transformer with time
delay 2.

8. En_NegOC_PD_HVS_Tr

Enable pole disagreement protection of HVS of main transformer being controlled by negative

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7 Settings

sequence current element.

9. En_ROC_PD_HVS_Tr

Enable pole disagreement protection of HVS of main transformer being controlled by zero
sequence current element.

10. En_ExTrp_Ctrl_PD12_HVS_Tr

Enable pole disagreement protection of HVS of main transformer with time delay 2 being blocked
by tripping contact of other protection device.

11. En_OC_PD12_HVS_Tr

Enable pole disagreement protection of HVS of main transformer with time delay 2 being
controlled by phase current element.

7.6.30.3 Access Path

Main Menu -> Settings -> MiscProt Settings -> PDCBProt Settings

7.7 Calculated Parameters


The settings listed in the following tables calculated by the RCS-985A itself automatically, they
need not to be set by user. The settings are calculated according to the system parameters that
user input, include primary rated currents, secondary rated currents, secondary rated voltages and
correction coefficients used in all kinds of differential protection relays. Listing of the calculated
settings is only for reference of setting check or commission.

7.7.1 Calculated Parameters of Secondary Rated Current

7.7.1.1 Parameters List

Table 7.7-1 List of calculated parameters of secondary rated current

No. Symbol Range Note


1 I2b_SnTr_CT_HVS_Tr 0-600 A
2 I2b_SnTr_CT_LVS_Tr 0-600 A
3 I2b_SnTr_CT_ST1 0-600 A
4 I2b_SnTr_CT_ST2 0-600 A
5 I2b_SnTr_CT_Bak_HVS_Tr 0-600 A
6 I2b_SnTr_CT_Gen_GTU 0-600 A
7 I2b_SnTr_CT_ST1_GTU 0-600 A
8 I2b_SnTr_CT_ST2_GTU 0-600 A
9 I2b_SnGen_CT_Term_Gen 0-600 A
10 I2b_SnGen_CT_NP_Gen 0-600 A
11 I2b_SnST_CT_HVS_ST1 0-600 A
12 I2b_SnST_CT_Br1_ST1 0-600 A
13 I2b_SnST_CT_Br2_ST1 0-600 A
14 I2b_SnST_CT_HVS_ST2 0-600 A

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7 Settings

15 I2b_SnST_CT_Br1_ST2 0-600 A
16 I2b_SnST_CT_Br2_ST2 0-600 A
17 I2b_SnExc_CT_S1_Exc 0-600 A
18 I2b_SnExc_CT_S2_Exc 0-600 A

7.7.1.2 Setting Description

1. I2b_SnTr_CT_HVS_Tr

I b1n
Secondary rated current at HVS of main transformer. The equation is I b 2 n  .
nbLH

2. I2b_SnTr_CT_LVS_Tr

Secondary rated current at LVS of main transformer.

3. I2b_SnTr_CT_ST1

Secondary rated current at HVS of step-down transformer1.

4. I2b_SnTr_CT_ST2

Secondary rated current at HVS of step-down transformer2.

5. I2b_SnTr_CT_Bak_HVS_Tr

Secondary rated current of backup CT at HVS of step-down transformer of main transformer.

6. I2b_SnTr_CT_Gen_GTU

Secondary rated current at HVS of transformer. It is used for differential protection of


generator-transformer unit.

7. I2b_SnTr_CT_ST1_GTU

Secondary rated current at HVS of step-down transformer1. It is used for differential protection of
generator-transformer unit.

8. I2b_SnTr_CT_ST2_GTU

Secondary rated current at HVS of step-down transformer2. It is used for differential protection of
generator-transformer unit.

9. I2b_SnGen_CT_Term_Gen

Secondary rated current at terminal of generator.

10. I2b_SnGen_CT_NP_Gen

Secondary rated current at neutral point of generator.

11. I2b_SnST_CT_HVS_ST1

Secondary rated current of CT at HV side of step-down transformer1.

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7 Settings

12. I2b_SnST_CT_Br1_ST1

Secondary rated current of branch 1 at LV side of step-down transformer1.

13. I2b_SnST_CT_Br2_ST1

Secondary rated current of branch 2 at LV side of step-down transformer1.

14. I2b_SnST_CT_HVS_ST2

Secondary rated current of CT at HV side of step-down transformer2.

15. I2b_SnST_CT_Br1_ST2

Secondary rated current of branch 1 at LV side of step-down transformer2.

16. I2b_SnST_CT_Br2_ST2

Secondary rated current of branch 2 at LV side of step-down transformer2.

17. I2b_SnExc_CT_S1_Exc

Secondary rated current at HV side of excitation transformer or terminal side of exciter.

18. I2b_SnExc_CT_S2_Exc

Secondary rated current at LV side of excitation transformer or neutral point side of exciter.

7.7.1.3 Access Path

Main Menu -> Measurement -> Measurement2 -> Cal Settings -> Sec Rated Curr Values

7.7.2 Calculated Parameters of Secondary Rated Voltage

7.7.2.1 Parameters List

Table 7.7-2 List of calculated parameters of secondary rated voltage

No. Symbol Range Note


1 U2b_VT_HVS_Tr 0-600 V
2 U2b_DeltVT_HVS_Tr 0-600 V
3 U2b_VT_Term_Gen 0-600 V
4 U2b_DeltVT_Term_Gen 0-600 V
5 U2b_NP_Gen 0-600 V
6 k_DeltVT_Gen 0-600 V
7 U2b_VT_Br1_ST1 0-600 V
8 U2b_VT_Br2_ST1 0-600 V
9 U2b_VT_Br1_ST2 0-600 V
10 U2b_VT_Br2_ST2 0-600 V

7.7.2.2 Setting Description

1. V2b_VT_HVS_Tr

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7 Settings

Secondary rated voltage at HVS of main transformer.

2. U2b_DeltVT_HVS_Tr

Secondary rated voltage of delta VT at HVS of main transformer.

3. U2b_VT_Term_Gen

Secondary rated voltage at terminal VT of generator.

4. U2b_DeltVT_Term_Gen

Secondary rated voltage of delta VT at terminal of generator.

5. U2b_NP_Gen

Secondary rated voltage at neutral point VT of generator.

6. k_DeltVT_Gen

The ratio of zero sequence voltage between terminal and neutral point of generator. That is the
ratio between [U2b_DeltVT_Term_Gen] to [U2b_NP_Gen].

7. U2b_VT_Br1_ST1(2)

Secondary rated voltage of branch 1 at LVS of step-down transformer.

8. U2b_VT_Br2_ST1(2)

Secondary rated voltage at branch 2 at LVS of step-down transformer.

7.7.2.3 Access Path

Main Menu -> Measurement -> Measurement2 -> Cal Settings -> Sec Rated Volt Values

7.7.3 Calculated Parameters of Differential Coefficient

7.7.3.1 Parameters List

Table 7.7-3 List of calculated parameters of differential coefficient

No. Symbol Range Note


1 k_TrHVS_Diff_Tr 0-60
2 k_TrLVS_Diff_Tr 0-60
3 k_ST1_Diff_Tr 0-60
4 k_ST2_Diff_Tr 0-60
5 k_TrHVS_Diff_GTU 0-60
6 k_Gen_Diff_GTU 0-60
7 k_ST1_Diff_GTU 0-60
8 k_ST2_Diff_GTU 0-60
9 k_Term_Diff_Gen 0-60
10 k_NP_Diff_Gen 0-60
11 k_HVS_Diff_ST1 0-60

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7 Settings

12 k_Br1_Diff_ST1 0-60
13 k_Br2_Diff_ST1 0-60
14 k_HVS_Diff_ST2 0-60
15 k_Br1_Diff_ST2 0-60
16 k_Br2_Diff_ST2 0-60
17 k_S1_Diff_Exc 0-60
18 k_S2_Diff_Exc 0-60
19 k_Ref_Tr 0-60
20 k_NP_Ref_Tr 0-60

7.7.3.2 Setting Description

1. k_TrHVS_Diff_Tr

Differential coefficient of HV side for differential protection of main transformer.

2. k_TrLVS_Diff_Tr

Differential coefficient of LVS of main transformer. For differential protection of main transformer,
the base side is LV side.

3. k_ST1_Diff_Tr

Differential coefficient of HVS of step-down transformer1 for differential protection of main


transformer.

4. k_ST2_Diff_Tr

Differential coefficient of HVS of step-down transformer2 for differential protection of main


transformer.

5. k_TrHVS_Diff_GTU

Differential coefficient of HVS of main transformer for differential protection of generator and
transformer unit.

6. k_Gen_Diff_GTU

Differential coefficient of generator terminal side for differential protection of GTU.

7. k_ST1_Diff_GTU

Differential coefficient of step-down transformer1 side for differential protection of GTU.

8. k_ST2_Diff_GTU

Differential coefficient of step-down transformer2 side for differential protection of GTU.

9. k_Term_Diff_Gen

Differential coefficient of terminal of generator for differential protection of generator.

10. k_NP_Diff_Gen

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Differential coefficient of neutral point side of generator for differential protection of generator.

11. k_HVS_Diff_ST1

Differential coefficient of HVS for differential protection of step-down transformer1.

12. k_Br1_Diff_ST1

Differential coefficient of branch 1 at LVS for differential protection of step-down transformer1.

13. k_Br2_Diff_ST1

Differential coefficient of branch 2 at LVS for differential protection of step-down transformer1.

14. k_HVS_Diff_ST2

Differential coefficient of HVS for differential protection of step-down transformer2.

15. k_Br1_Diff_ST2

Differential coefficient of branch 1 at LVS for differential protection of step-down transformer2.

16. k_Br2_Diff_ST2

Differential coefficient of branch 2 at LVS for differential protection of step-down transformer2.

17. k_S1_Diff_Exc

Differential coefficient of side 1 of exciter for differential protection of exciter.

18. k_S2_Diff_Exc

Differential coefficient of side 2 of exciter for differential protection of exciter.

19. k_Ref_Tr

Differential coefficient of HVS of main transformer for restricted earth-fault protection of main
transformer.

20. k_NP_Ref_Tr

Differential coefficient of neutral point side of main transformer for restricted earth-fault protection
of main transformer.

7.7.3.3 Access Path

Main Menu -> Measurement -> Measurement2 -> Cal Settings -> Diff Corr Coef

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8 Human Machine Interface

8 Human Machine Interface

8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.

5
1 11 PCS-985
2 12
GENERATOR RELAY
3 13

4 14
P
GR
5 15

6 16 ENT
C

7 17
ES

8 18

9 19