UNIVERSITY OF SURREY

DEPARTMENT OF PHYSICS

Level 2: Modern Laboratory Experiment

THE DIGITAL TRAFFIC LIGHT CONTROLLER

Ben Murdin Aug 2009.

Objectives
You will learn about Boolean logic operations and how they may be implemented electronically
for useful tasks such as decoding signals of one form into another. You will see how Boolean
equations may be simplified for efficiency. Feedback of signals from the output of a logic
function back into its inputs produces memory and cyclic operations, and on completion of this
experiment you will be able to predict these cycles and apply them to a simple control circuit.

Introduction
Logical deduction is something we perform all the time, and everyone has encountered
situations where they would have liked to use and filter lots of information to leap straight to
the answer. Solving a Sudoku puzzle; finding the best travel route with multiple legs and modes
of transport; diagnosing a medical problem from a range of symptoms – all of these are
problems that can be described by a sequence of decisions, each of which is simple, but which
multiply up to make the problem complex. These kinds of problem all produce an output from
a range of inputs, and methods for rationalizing and simplifying the process are very useful. We
also regularly encounter problems where a system has a well-defined number of states and it
should perform a task that may depend on some inputs. Examples are lifts, washing machines,
alarm clocks etc. Understanding how they work can give insights into the concept of negative
feedback at its most general, since all systems that are stable or cyclic must involve negative
feedback. The techniques that will be developed in this experiment will be used for
implementation of electronic circuits, but are just as important for software where complicated
“if – else – then” statements and loop statements often occur. The experiments may appear to
students as being about “electronics”, but in reality they are about “information” generally.
All of the problems described above, indeed any logical deduction in any form (including
software programs, flow charts for medical diagnoses, etc etc) can be broken down into a small
number of basic building blocks in the form of the conditional decision. Decisions can all be
described by a small number of basic types. The simplest types are:

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 IF (condition A is true) THEN (perform task)
IF (condition A is NOT true) THEN (perform task)
An increasing level of sophistication is produced for multiple conditions:
IF (condition A is true AND condition B is true) THEN (perform task)
IF (condition A is true OR condition B is true) THEN (perform task)
These four decisions are represented by the following flow diagram symbols:

Electronic logic gates

We will investigate electronic logic gates that perform the decisions described above. The state “true”
or “1” will be represented by a voltage of 5V, and the state “false” or ”0” will be ground. You have been
given a “breadboard” which is a flexible set of sockets for integrated circuits. The three switches on the
left of the breadboard will act as three input points (like the A, B etc above). The LEDs on the right of
the breadboard can be used to represent the “task” and when connected to the output of the gate light
up if it is “true”. You have been give a range of chips (see appendix for the connections and
descriptions). Insert a 3-input NOR gate chip so that it straddles the middle row. Connect the +5V supply
to the top rail of the breadboard and the 0V to the bottom rail, and the positive supply Vdd of the chip to
the positive supply and the ground Vss of the chip to the negative supply. Set up the decision circuit
shown below: connect the three switches on the left of the breadboard to inputs the NOR gate, and
connect the output to the input of a NOT gate, and the output of that to one of the LEDs on the right of
the breadboard. NOR is just OR followed by NOT, and when we connect another NOT it gets us back to
OR again. Satisfy yourself that the circuit functions as you expect. Remove the NOT gate, and again,
satisfy yourself that the circuit functions as you expect.

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Preliminary Work
The following two-day lab is designed so that building the Traffic Light Controller is performed on the
second day, while the preliminary exercises are finished on the first day. This is likely to be possible only
if you have done the theory exercises (numbered) before starting the lab, and the corresponding
preparation for the traffic light controller as homework between the sessions. If you do theory work
outside the lab, be sure to write it in your diary, in pen, with dates. Your notes should show your
thought processes as well as the finished result and notes are not expected to be a perfect straight line
to the correct answer!

Boolean equations and the LED dice display

Let’s suppose we want to build an electronic display like a (single) die. We need to convert binary
numbers into signals that can be connected to each of seven LEDs that make up the face of the die.

Let’s label the LEDs:

We need to work out how to convert the binary signals of the input into the LED output signals. The
“truth table” for the inputs & outputs is as follows:
inputs outputs
Digital A B C S1 S2 S3 S4 S5 S6 S7
1 0 0 1 0 0
2 0 1 0 0 0
3 0 1 1 0 0
4 1 0 0 1 0
5 1 0 1 1 0
6 1 1 0 1 1
where for the outputs “on” has been represented by 1 and “off” by 0. The first two outputs have been
filled in for you. For example, the S1 LED is lit for the decimal 4,5 or 6, while for 1,2 and 3 it is off.
1. Fill in the remaining outputs.
The idea of this exercise is to create a logic circuit that will convert (i.e. “decode”) the input signals into
the required outputs signals. The example of S1 is trivial – one can see immediately that
Eqn (1)
and we simply need to directly wire A to the LED S1. LED S2 is on only if A and B are true and C is false, i.e
Eqn (2)
which is represented in logic gates by

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 2. Find the logic operations that produce each remaining output from the inputs
Arrange seven LEDs on the breadboard so that the negative leg of each (indicated by a flat side of the
LED and the short leg) is connected to the negative supply, and the positive leg to its own socket (the die
face will probably have to be slightly skewed relative to the board). On the positive side of each LED put
a current limiting resistor. (Calculate the necessary resistor value by checking the maximum current the
logic chips can supply in the Appendix, and taking the voltage output by the chips as 5V. If you don’t use
a resistor the chip’s output voltage will reduce to compensate and this will probably mess up your logic).
Experiment: Recreate the logic operations for each LED electronically. Use the switches on the left of
the breadboard to connect different combinations of the positive and negative supply (corresponding to
different binary numbers) to the three input points.
Note there is currently nothing to stop you from using an input which does not correspond to a decimal
number from 1-6, which will naturally produce a strange result.

The Karnaugh map

The logic operations we produced in Eqn 2 and Q2 are not the most efficient ones. We will now
examine methods for reducing the complexity of the logic operations based on the “Karnaugh map”.
The principle is simply to look for common factors. In some cases, as in this exercise, there are some
combinations of inputs that are not used so we don’t care about whether the output is 1 or 0, and this
makes it a bit harder to look for the best set of common factors, and that’s where the Karnaugh map can
help. The map shows the output for all possible combinations of the inputs. The inputs are arranged in
a special order, not the normal binary numerical order, but so that moving to an adjacent square
changes only one bit. The inputs are labelled around the outside, and to help you understand the order
of the inputs the following table contains the input combinations rather than the output:

inputs ABC C
000 001
010 011
B
110 111
A
101 011
Thus the Karnaugh map for S2 is:

S2 C
X 0
0 0
B
1 X
A
0 0
where “X” means “don’t care”, because that combination of inputs is not used. Since we can choose the
X’s to be either 1 or 0, we can choose them so that as far as possible 1’s are bunched with other 1’s and
0’s with other 0’s:

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 S2 C
0 0
0 0
B
1 1
A
0 0
One group of cells has been highlighted for which the output is 1. The fact that they are adjacent means
that one of the bits of the input (C in this case) can take either value (the other two bits are A=B=1). We
can therefore catch this input state with , and we don’t care what the value of C is. The minimum
logic equation for S1 is therefore:
Eqn (3)

We can arrive at the same conclusion without the Karnaugh map by noticing that will never be
true because the input state 111 is not used, and that false is the identity element for the OR operation,
i.e. R + FALSE = R. We may therefore replace Eqn 2 with:
Eqn (4)
which can be simplified:
Eqn (5)
The group of cells in the above example was a pair. Groups of 4 are even simpler, either in squares or
lines, and wrapping around from one side of the table to the other (or groups of 8 for larger tables of 4
inputs, etc etc). This is demonstrated by an alternative way of looking at the Karnaugh map for S2:

S2 C
X 0
0 0
B
1 X
A
0 0
There is a group of 4 0’s in the top half of the map defined by , and a group of 4 that wraps around the
top of the table defined by . The combination of these two groups is therefore . This map
shows groups of 0’s instead of 1’s (especially useful if there are fewer zeros on the map) so the final
result is
Eqn (6)
Equating (3) and (6) gives De Morgan’s theorem, that AND can be replaced by NOR and inverting all
inputs; similarly OR can be replaced by NAND and inverting all inputs.
3. Find the Karnaugh maps and draw the minimum logic gate arrangements for the other LEDs of
the display.
Experiment: Implement this set of operations experimentally.

S-R flip flops

So far we only considered logic that converts inputs instantaneously into outputs. It is often useful to
produce a memory, that will maintain its output even when the inputs are switched off. This requires
some kind of negative feedback (as does any stability or memory effect).

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The simplest kind of memory is the Set-Reset latch or “flip-flop”. You can build one with two NAND or
two NOR gates. Let us take the example of the one with two NORs.

The truth table for this flip-flop is

S R Q Q’
0 0 Q Q’
0 1 0
1 0 1
1 1 not used
The table indicates that when S and R are both 0, the outputs are left at whatever they were previously.
The “set” condition is when the S input is switched to 1, which causes Q to become 1 also. The “reset”
condition is when R is switched to 1, in which case Q becomes 0.
4. Find Q’ in the set and reset conditions, and convince yourself that in either of these two cases
reversion to S=R=0 does not change Q and Q’. See what happens when S=R=1 (and hence why
this state is not used).
Experiment: Build an SR flip-flop and test it.
5. An SR flip flop can be built using two NAND gates in the same arrangement. Of course the
operation is a little different. Produce the truth table and (if time allows) demonstrate
experimentally.

D-type flip-flop.
The SR flip-flop changes its output state as soon as the inputs change. It is often important to ensure
that states change in a time-controlled manner so than signals propagate down a chain of gates in the
correct sequence. The D-type flip-flop is designed to become set if the input is set to 1 and reset if the
input is 0, but only when a “clock” pulse triggers it.

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 6. Draw out the circuit and show (by filling in the states of P, P’, R and R’) that if C=0 then Q’ is the
inverse of Q, whatever Q and whatever D.
7. Show that if D=1 at the moment that C changes from 0 to 1 (the “rising edge” of the clock pulse)
then Q=1, and if D=0 on the rising edge of C then Q=0. Reassure yourself by looking at the
previous question that on the trailing edge of C that Q doesn’t change.
Experiment: Implement the D-type flip-flop experimentally and test it. Use the push button switch for
the clock pulses

Counters
The D-type flip-flop can be made to toggle its output (i.e. swap from 0 to 1 or from 1 to 0) by connecting
to D. The swap occurs on the rising edge the clock. An important application is the binary counter:

This example is produces a 3-bit counter, or 4-bits if the clock is included as the lowest bit.
8. Sketch the waveform of the clock signal, assuming it is a square wave alternating between “0”
and “1” (i.e. ground and Vcc). Sketch underneath the waveform of Q1 and its inverse, assuming
Q1 starts off at 0. Sketch underneath Q2 and Q3 and their inverses.
The circuit can easily be implemented experimentally, but not with the integrated D-types you have
been given. This is because each of the 4 flip-flops on the chip have their clock inputs hard-wired
together.

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Finite state machines.
The counter that was used above can also be made with a “finite state machine”. Such machines can be
more efficient and much more complex, with more inputs (i.e. more than just the clock input used
above). We will see an example of this in the traffic-light-controller exercise below. In the die display
example the machine has six states (a finite number), and there is a rather trivial sequence that gets you
from one state to the next.

We label each of these states with a binary representation. There are several ways to do this:
State label binary Gray code “one hot” output
representation representation representation representation
1 001 000 000001 00-----
2 010 001 000010 00-----
3 011 011 000100 00-----
4 100 010 001000 10-----
5 101 110 010000 10-----
6 110 111 100000 11-----
In the last column for the “output representation”, one bit has been used for each LED in the display so
that decoding the state of the machine into the display is trivial: the first bit is wired directly to S1, etc
(NB “-“ has been used where you were asked to fill in 1s and 0s in the first exercise). The “one-hot”
representation can be more efficient with power consumption, and often makes decoding easy (not
quite so easy as the output representation in this die display example). However, one flip-flop will be
required for each bit in the state representation, so these two representations are more costly in
hardware than the other two. In this example the state machine sequence is very simple, and the most
efficient for what follows is the Gray code (which, like the ordering chosen for the Karnaugh map,
changes only one bit from one state to the next, apart from when it jumps from 6 back to 1). However,
as we already produced the decoding circuit at the start of this lab using the binary representation, we
will stick with that. This representation requires 3 bits, for which we will use 3 D-type flip flops. The
“state table” for the three bit binary representation is:
current state next state
representation representation
AnBnCn An+1Bn+1Cn+1
001 010
010 011
011 100
100 101
101 110
110 001

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Remember from earlier that the output of a D-type becomes equal to its input when the clock pulse is
applied. Thus, if we have some logic circuit that can take the flip-flop outputs and calculate the desired
next state, and if we feed this back into the inputs, then each successive clock pulse will shift the output
into the next state and so on around the cycle. First let’s find An+1 from An, Bn and Cn (which we can then
feed back into the input of A). The Karnaugh map for An+1 is

An+1 Cn
X 0
0 1
Bn
0 X
An
1 1
whence
Eqn (6)
9. Find the other two inputs Bn+1 and Cn+1.
Experiment: Implement the state machine using three D-type flip flops. Connect the clock to each one.
Take the outputs (and their inverses) and construct logic operations to produce the flip-flop inputs.
Connect the outputs to the die display decoder, and use the push-button switch as the clock input to
demonstrate that the outputs cycle correctly.
10. Examine theoretically what are the next states if, when you switch on the power, the machine
starts in one of the unused states (000 or 111). We may have accidentally created a situation
such that the system remains in a cycle of undesired states forever (e.g. 000 is followed by
itself). To fix this problem (if it has arisen) all that is needed is to fill in the missing rows on the
state table and force one of the unused states in the cycle to go to a used state (if done cleverly,
this might only require changing one bit on one Karnaugh map and hence change only one
gate).

The traffic light controller

Your task is now to design and build a traffic light controller for a cross-road. Each approach has a
simple traffic light with the standard sequence of red, red/amber, green, amber (and back to red) with
no left or right turn filter lights. The North and South approach lights are in phase (i.e. both green
together, and similarly for the East-West road. There is a set of pedestrian lights that do not interrupt
the road traffic sequence unless they are triggered by a push button. The pedestrian lights do not come
on until the end of the complete road traffic cycle (when all traffic is halted and all pedestrian lights
come on). It is beyond the scope of this experiment to vary the duration of each state, so assume all
states are to last one clock cycle. Choose a representation for each state and follow the procedure you
used for the die sequence machine above. Implement the controller electronically. Use a 1Hz clock
cycle from a square-wave generator. Start by using a switch to indicate whether the request has been
pushed, but if time allows use a push button switch to simulate the pedestrian light request, and
incorporate an SR flip-flop so that the request is held until the light comes on, and connect the SR reset
so that the request is cleared after the light has come on.

Hints.
There are many possible representations. Different choices will mostly decrease the number of gates
required for decoding the state value into the light output, while increasing the number of gates
required for the state machine sequence, or vice versa. In the end, the important thing is whether or
not the controller works, and the importance of an efficient (i.e. small) set of logic operations is only

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that you are less likely to make mistakes experimentally. You should not spend too much time worrying
about the choice – it will never be perfect. Having said that, a few tricks can save a lot of effort.
As already mentioned, it is helpful for the state machine sequence logic if the sequence follows as far as
possible the Gray code, i.e. that adjacent states in the sequence differ by inverting only one bit. Write
out the traffic light sequence in order, starting from the state with the pedestrian light on, with a Gray
code sequence. The sequence logic will have to decide at the end of the normal traffic light sequence
whether to go back to the pedestrian state or skip to the second state (based on whether or not the
request has been made). The sequence logic will be much easier if these first two states differ by only
one bit (so only one flip-flop needs to take the request into account). This is why it was suggested that
you write the states down in order stating with the pedestrian state.
There are also some tricks when choosing the representation that will help decoding of the state value
into the traffic light outputs. [NB It is, of course, impossible to always ensure that the sequence follows
a Gray code while following the suggestions below, but on balance, so long as the last suggestion about
the pedestrian and next states differing by only one bit is maintained, keeping the rest of the Gray code
sequence is less important.] Note that the amber lights come on twice per sequence – it will be helpful
for the decoding if these two states differ by only one bit. A judicious swap of state values will therefore
help ensure they can be grouped on the Karnaugh map for this light output. Note also that each red
light is off only twice per sequence – again it helps the decoding logic if these two states differ by only
one bit (these two states were consecutive to start with so if the swap you just made for the amber
lights messed this up, better go back and choose a different swap). Finally, note that for a three-bit
representation there is one unused state, and the last decoding trick is to ensure that the two green
states both differ by only one bit from the unused state. Again, this can be achieved by judicious swaps
or shuffling along, without messing up the other achievements.
Of course even more efficient decoding logic is possible if we allow more bits. A very simple decoder is
achieved with 4 bits chosen so that one bit directly represents each of the red and amber lights (so
those ones do not require any decoding), from which it is also a very simple matter to find when the
green is on (when both the respective red and amber are off). The disadvantage is that the state-
machine sequence logic is less efficient (simply because there is more information to manipulate, and
you need to produce the next state of 4 inputs rather than 3), and working it out is a little more difficult
too.
Once you have decided a sequence: a simple 3-bit Gray code, or a modified and swapped around 3-bit
code, or even some other 4-bit code etc, we need to find the logical operations to decode the state into
the light output and for triggering the next state of the state-machine. Just as you did for the die-
display, for each light of the traffic system you need to make a Karnaugh map to find the minimum
decoding logic. [NB, there is hardly any point in the Karnaugh maps for the 4-bit representation
described above since the decoding is so simple, but you might like to produce them just to be sure!].
For the state-machine sequence, we also need to follow the procedure as for the die-display with one
important sophistication, which is that we need to add the effect of the pedestrian request. If the state
of this request is represented by an input P (say “1” means the request button has been pushed), and
say we have already chosen a 3-bit state representation (with 3 flip-flops), there are now a total of 4
inputs to the state machine logic. We need to create a Karnaugh map for each next state, An+1, Bn+1 and
Cn+1, just as before. The 4-bit Karnaugh map has its inputs (PAnBnCn) in the following pattern:
Bn
0000 0001 0011 0010
0100 0101 0111 0110 An

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 1100 1101 1111 1110
P
1000 1001 1011 1010
Cn
In our problem the value of P only affects one state so the top and bottom halves of the map for the An+1
etc are almost mirror images apart from that one state. Furthermore, if the suggestion above was
followed, P only affects one bit of that one state (just Cn+1), so for the other two bits there really will be
mirror images (and so we didn’t even really need to use a 4-bit map for those bits – a 3-bit map without
P would have been sufficient). Watch out for groups of outputs that wrap around the edges of the map
(e.g. connecting 2 corners or all 4).
If you chose a 4-bit state machine representation (with 4 flip-flops) there are now 5 inputs, and
unfortunately it is not possible to draw a simple Karnaugh map for 5 inputs – you need to draw two 4-bit
maps side-by-side one for P and one for and imagine them stacked one on top of the other. You need
to watch out for vertically connected groups. Hopefully, again, this will only be necessary for one of the
bits. [My best 3-bit controller requires 8 ANDs, 4 ORs and 2 NOTs, while the 4-bit controller requires 9
ANDs and 4 ORs].
For consideration of errors, why not think about the unused states and whether or not they produce
closed loops?

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Appendix 1. Chip layouts
You have been give some integrated circuit chips, each of which has several logic gates. The writing on
the chip is a code number that is usually something like “MC1” followed by the standard family name
and some further letters on the end (sometimes there are some extra letters added in the middle too,
just to confuse you!). These are: a quadruple D-type flip-flop (Standard family name: 4175); quadruple
2-input AND (No 7408 or 4081); quadruple 2-input NOR (No 4001); quadruple 2-input NAND (No 4011);
Triple 3-input NOR (No 4025); hex inverter (i.e. 6 NOT gates) (No 4069). You have also been given a
number of LEDs and resisistors. These chips and their internal connections are described in more detail
below. They can be fitted across the middle of the breadboard provided. The internal connections
between the sockets of the breadboard are illustrated in the figure below by the thin lines. There are
two rails running the length of the board at top and bottom for the power supply, and rows of 5 holes
that can be used to make connections to your chips as shown (pins 7 and 14 – counting anti-clockwise
around from the notch at the end of the chip - are usually the power supply for 14-pin chips).

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