2013 IEEE Eighth International Conference on Networking, Architecture and Storage
An FPGA-based Random Functional Verification Method for Cache
Li Tiejun Zhang Jianmin
School of Computer Science School of Computer Science
National University of Defense National University of Defense
Technology Technology
Changsha, China Changsha, China
tjli@nudt.edu.cn jmzhang@nudt.edu.cn
Abstract—Functional verification is the most difficult and time-
consuming step in VLSI design flow, owing to the complexity
and scale of chips rapidly increasing. The key problem of VLSI
functional verification is improving the efficiency and
coverage. For the important component-Cache in the
microprocessors, an FPGA-based pseudo-random functional
verification method is proposed in this paper. The testbench of
this method is synthesizable, and the field programmable gate
array (FPGA) emulation process is integrated to improve the
efficiency of verification. The functional verification coverage
is increased by automatically generating the constraints
directed pseudo-random test stimuli. The method is applied in
the real chips, and is compared with the pseudo-random
software simulation method. The results show that our method
is faster by about three orders of magnitude, and find more
bugs in the designs.
Keywords-Cache; functional verification; pseudo-random;
field programmable gate array
I. INTRODUCTION
Functional verification remains one of the largest
challenges in modern VLSI design flows taking up to 70%
[1] of the total design time, owing to the dramatically
increasing complexity and the number of transistors for a
single silicon chip. Functional verification is the register
transfer level (RTL) code or gate level netlist should
conform to the specification of the VLSI chip. The aim of
functional verification is to find and locate the bugs in the
circuits. In recent years, new methods have been developed
to cope with the verification challenge. Software simulation
method and hardware emulation method are the most
popular functional verification techniques. The main
advantage of software simulation method is that localization
of errors in the design is easy. However, since the software
simulation method is slow, its runtime is too long, and its
functional coverage generally is not very high, with typical
design sizes exceeding the half-million synthesized gates
mark. The most popular hardware emulation technique is
FPGA-based emulation method. It is generally faster than
software simulation method for about a few orders of
magnitude. Further, it generally can arrive at the high
coverage rate. However its debug process is difficult and its
testbench should be synthesizable. Therefore, the hardware
emulation method is generally applied in functional
978-0-7695-5034-3/13 $26.00 © 2013 IEEE 277
DOI 10.1109/NAS.2013.44
Li Sikun
School of Computer Science
National University of Defense
Technology
Changsha, China
sikunli@nudt.edu.cn
verification flow of the chips, when improving the efficiency
and coverage rate of functional verification is necessary.
Cache is the very important component in the
microprocessors. The main function of Cache is to bridge the
gap between the main memory and processor cores.
According the types of stimulus, the functional verification
method of Cache can be divided into two categories: directed
verification method and random verification method.
Broadly speaking, functional verification for Cache faces
three problems. Firstly, the huge verification space is the
main bottleneck of functional verification for Cache. In
general, the functional complexity and design scale of Cache
is very large. If using directed verification method, it is very
difficult for verification team to finish so much testbench.
Secondly, the automatic correctness check for verification
results is very necessary. The complex function of Cache and
large scale of testbench bring much trouble to check the
results correctness for Cache verification. Therefore the
correctness check for verification results is difficult, time-
consuming and error-prone. Thirdly, the high efficiency and
coverage rate is the main goal for functional verification of
Cache. When the directed verification method is adopted, the
verification team should write testbench for each functional
point of Cache. It consumes much time in verification flow.
Furthermore, some unpredictable combinational condition
and corner cases are very difficult to be covered by the
directed testbench. The random verification method can
solve the three problems during the verification flow of
Cache. The random verification method generates the
flexible scale of testbench, and easily covers many
unexpected functional corner cases. Therefore, it can arrive
at higher verification coverage rate. However, completely
random test stimuli always cover the same function points
more than once. Consequently these unnecessary repeatedly
testbench reduce the efficiency of verification.
For the above problems for the verification flow of
Cache, a synthesizable pseudo-random functional
verification method is proposed in this paper. Firstly, to
improve the functional coverage rate, the pseudo-random
stimulus generation technique is adopted. Secondly, all of the
testbench are synthesizable. Thus the FPGA-based hardware
emulation approach is applied in this method, to achieve
substantial improvement in verification efficiency. Thirdly,
constraint-directed random test generation technique is
introduced to reduce the unnecessary repeated test. The
pseudo-random stimuli are generated constrained by specific
functional specification. The specific constraints include
unreachable states of FSM, impossible assignment for input
signals, etc, according to the functional specification. The
synthesizable pseudo-random functional verification method
is applied in the real chips, and is compared with the random
verification method on software simulation. The results show
that our method is faster by about three orders of magnitude,
and find more deep bugs in the Cache designs.
The paper is organized as follows. The next section
surveys the relevant existing research work on random
verification technique. Section 3 introduces the synthesizable
pseudo-random functional verification method for Cache.
Section 4 shows and analyzes the comparison results on the
real chips. Finally, Section 5 concludes the paper and
outlines future research work.
II. RELATED WORK
There have been many different contributions to research
on random test generation approach in the last few years,
owing to the increasing importance in numerous practical
applications of VLSI design flow. Patrick Girard et al. [2]
compared the random and pseudo-random test generation
method for BIST of delay, stuck-at and bridging faults. In
[3], an efficient dynamic instruction and stimulus generator
and its associated methodology were proposed. The
generator was used to generate random stimuli with one of
the five random modes. It has been applied in the functional
verification of a high performance low-power embedded
processor, and was proved to have significantly reduced
verification cycle, improved test coverage.
Mike Bartley et al. [4] have compared three verification
techniques: directed testing, pseudo-random testing and
property checking by verifying two versions of a bridge
between two on-chip buses. The results show that the
property checking method found 18 bugs, and the directed
testing method found 14 bugs, and the pseudo-random
testing method found 22 bugs. In [5], the authors proposed
an efficient test generation technique, which can be used to
achieve full state and transition coverage in simulation based
verification for a wide variety of cache coherence protocols.
Based on effective analysis of the state space structure, this
method can generate more efficient test sequences (50%
shorter) compared with tests generated by breadth first
search.
The above verification methods have adopted the pseudo-
random test technique. Further, all of the pseudo-random test
techniques are based on software simulation. The main
advantage of software simulation method is easy to
localization of the errors in the designs. However, the
software simulation method is very slow, and its functional
coverage and efficiency is generally quite limited. Therefore,
how to improve the coverage and efficiency is the main
bottleneck for functional verification of Cache.
III. RANDOM VERIFICATION METHOD FOR CACHE
First of all, the overview of the pseudo-random
functional verification method is introduced in this section.
The architecture of the proposed FPGA-based pseudo-
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random functional verification method is sketched in Fig. 1.
This test approach consists of four components: data mirror
image, constraints directed test stimuli generator, automatic
error checker, pseudo-random number generator. Next each
of four modules will be detailedly described.
Pseudo-random Number
Generator
Constraints
Data Mirror Directed Pseudo-
Image random Test
Stimuli Generator
Automatic Error Checker
Figure 1. Architecture of the synthesizable pseudo-random functional
verification method
The data mirror image stores the writing data sent to
Cache. For each writing data operation to Cache, the data are
simultaneously stored in the same address of mirror image
memory, to keep the data consistency. When the data are
read back from Cache, the corresponding data will be read
from the same address in mirror image memory to
automatically check the correctness of reading operation.
The data mirror image is composed of the memories, and its
reading and writing logic. The capacity of the memories is
limited by the memory resource in FPGA chips. After reset
operation, all the memories in data mirror image will be
initialized. The detailed initialization flow is showed as
follow. The writing enable signal is keep the value of 1, and
the writing data signals are assigned to 0, and the writing
address signals are increased by 1 from 0 to the maximum
address of the memories. After all of the items in the
memories are initialized by 0, the writing enable signal is set
to 0. It indicates the initialization operation is finished. In
next step, the testbench generator will start to produce the
pseudo-random test stimuli.
The constraints directed pseudo-random test stimuli
generator mainly includes a finite state machine (FSM)
which generates and sends the accessing signals to Cache.
During the process of testbench generating, this module will
exclude some impossible combinational condition for the
logic of Cache, such as unreachable states of FSM,
impossible assignment for input signals, etc, according to the
functional specification of Cache. Then verification state
space can be reduced and the efficiency can be improved
through these useful constraints. As showed in Fig. 2, the
FSM contains 5 states: IDLE, BUILD, IDGEN, SEND,
UPDATE. The workflow and transition between these states
are described as follows.
1ˊIDLE˖The initial state of this FSM is called IDLE.
If the initialization of mirror image is finished, the enable
signal of generating pseudo-random number is set to 1, and
is sent to random number generator. Then the next state goes
to BUILD. Otherwise, the next state stays at current state
IDLE.
2ˊBUILD ˖ In this state, the constraints directed
pseudo-random signals, such as the address, writing data and
so on, are build. When received the pseudo-random number,
this module extracts the lowest n bits as the writing data to
be sent to Cache. The next m bits of random number are
treated as the accessing address to Cache. The value of m is
determined by the depth d of mirror image memory, more
precisely m=ªlog2dº. The highest bit is denoted as the type
of operation. It indicates the current operation to Cache is
reading or writing operation. If it is reading operation, the
next state is transmitted to IDGEN. Otherwise, the next state
is jumped to SEND.
3ˊIDGEN˖In this state, the module detects whether
there exits any idle reading ID number or not. If the set of
idle IDs are empty, the FSM stays at the current state.
Otherwise, the module selects an idle reading ID. This ID is
added into the used ID set, and removed from idle ID set. A
matching list between the used ID and address is updated at
the same time. Then the next state goes to SEND.
4ˊSEND˖The main function is sending control and
data signals to Cache. The sending valid signal is set to 1. At
the same time, all other signals, such as the generated
address, writing data, operation type, reading ID, are sent to
Cache. Then the next state will arrive at UPDATE.
5ˊUPDATE˖In this state, the writing data to Cache
are updated to the mirror image memory. When this current
operation is writing operation, the writing data are
simultaneously stored in the same address of mirror image
memory. Then the next state will return back to IDLE.
IDLE
Update Over
Constraints
Directed
Pseudo- UPDATE
random Test
Stimuli
Generator Write Op
Send Packets
SEND
ID Generation
Figure 2. The finite state machine
The automatic error checker is composed of error
judgment module and timeout reporting module. The error
judgment module mainly collects and judges three types of
errors. The first type of faults is the reading data error. When
the checker receives the reading data, it will compare the
reading date and the data at the same address in mirror image
memory. If they are unequal, it is indicated there exits a fault
for the reading date from Cache. The second fault type is
called reading ID error. In general, the double data rate
(DDR) SDRAM is employed in the main memory of CPU.
Whereas, the reading data returned from DDR SRAM may
be out of order. Therefore, the test stimuli generator always
allocates a read ID in company with the address for each
reading operation. As above mentioned, it also maintenances
a used ID set. When reading data and ID are returned from
Cache, the error checker will determine whether this ID
belongs to the used ID set. The third fault type is the error
correcting code (ECC) check error. Currently ECC technique
is generally applied in DDR SDRAM and Cache. While the
reading data are received from Cache, the error checker will
compute ECC parity, and judge there exits one bit fault or
two bits faults.
The timeout reporting module judges whether the reading
date can be return from Cache within a time limit after the
reading operation is started. In this module, a 64-bit counter
is added for each reading ID. When a idle reading ID is used,
the corresponding counter begins to increase by 1 from 0.
While that reading ID and data are received from Cache, the
counter will stop and set to 0. Otherwise, the counter will
continue accumulating, until the counter reaches the preset
timeout value. If timeout encountered, this module will
report the error signal to the system.
prbs_gen_64bit(clk,rst_n,enable,seed_data,prbs_o)
always @(posedge clk) begin
if (!rst_n) begin
lfsr_q <= seed_data;
end
else if (enable) begin
lfsr_q[64] <= lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= lfsr_q[62];
lfsr_q[62] <= lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= lfsr_q[64] ^ lfsr_q[60];
Initialization
lfsr_q[60:2] <= lfsr_q[59:1];
lfsr_q[1] <= lfsr_q[64];
end
BUILD end
assign prbs_o = lfsr_q[64:1];
Read Op
IDGEN Figure 3. 64-bit PRBS pseudo-random Number Generating Algorithm
The pseudo-random number generator is used to produce
the random number. It adopts a typical 64-bit PRBS pseudo-
random number generating algorithm. This algorithm is
illustrated in Fig. 3. If a 64-bit random number is not enough
for all the signals, the generator changes different seeds to
build multiple random numbers. The input signals of this
algorithm include the clock signal clk, and the reset signal
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rst_n, the enable signal enable, the 64-bit seed signal reading data is returned or the counter reaches the preset
seed_data. The output signal is a 64-bit pseudo-random value. The other branch fulfills the receiving data from
number called prbs_o. Cache. While the reading data and ID is arrived, the address
In Fig. 3, while reset signal is valid, the initial value of is obtained from the matching list between used ID and
the 64-bit register signal lfsr_q is assigned by the seed data. address, according to the ID. Then the data are read from the
When the reset signal is invalid, the algorithm is waiting for corresponding address of the mirror image memory, and
the enable signal. If the enable signal is 1, the linear compared with the reading data from Cache. At the same
feedback shift mode is adopted to generate the pseudo- time, the reading ID error and ECC parity error are checked
random number. In other words, the current clock cycle of and reported.
64-bit lfsr_q is obtained by ring shift of the last clock cycle
of lfsr_q. However, there is mutation on some bits. The 64th IV. EVALUATION RESULTS AND ANALYSIS
bit is generated by exclusive or operation of the 63rd and To evaluate the effectiveness and efficiency of the
64th of last cycle lfsr_q. Similarly, the 62nd bit is exclusive method, the three capacities of Cache, including 128KB,
or of the 61st and 64th of last cycle lfsr_q. The 61st bit is 256KB and 512KB, are implemented. The pseudo-random
exclusive or of the sixtieth and 64th of last cycle lfsr_q. This software simulation method is very popular verification
algorithm has two advantages. The first is all of the codes in technique for Cache. Therefore the proposed FPGA-based
this algorithm are synthesizable, and can be applied in FPGA pseudo-random verification method is compared with
verification. The second is the algorithm can generate pseudo-random software simulation method. The designs
different pseudo-random number by changing seed data, to under test (DUT) are 128KB Cache, 256KB Cache and
obtain more stimuli and improve the test coverage. 512KB Cache.
The software simulation environment is Cadence NC-
Verilog simulator. The experiments were conducted on a 2.9
Mirror image initialization
GHz Intel Xeon machine having 64 GB memory and running
the Linux operating system. The platform of the
synthesizable pseudo-random verification method is an
FPGA board based on Xilinx Virtex-6 565T FPGA device.
Pseudo-random Receive
number generation reading data The synthesizable pseudo-random verification method is
implemented in RTL verilog. The ISE tool is used to perform
synthesis, layout and routing. Finally, the bit stream of the
Build the control Obtain address DUT and testbench is generated, and is downloaded to the
and data signal by read ID FPGA verification board. The FPGA device works on
60MHz.
Allocate read
The evaluation results of the software simulation method
ID Read data and and pseudo-random verification method on FPGA are list in
compare Table 1. Table 1 shows the number of requests sent by
testbench within 10 seconds (Reqs no) and the number of
Send signals to bugs found by pseudo-random software simulation method.
Cache Errors check The last two columns provide the number of requests sent by
testbench within 10 seconds (Reqs no) and the number of
Update mirror bugs found by pseudo-random verification method on
image FPGA. The columns called Reqs no. are to evaluate
efficiency of the two verification methods.
Timeout report
TABLE I. VERIFICATION RESULTS OF TWO METHODS ON CACHE

Figure 4. Workflow of pseudo-random verification method Software simulation FPGA-based method

DUT
Reqs no. Bugs no. Reqs no. Bugs no.
The workflow of FPGA-based pseudo-random 128KB 22147 0 18134321 3
verification method is depicted in Fig. 4. First of all, the data 256KB 21320 2 16165842 5
512KB 20531 2 15271273 5
mirror image is initialized, and then the method branches.
One branch is controlled by the FSM, and generates the
constraints directed pseudo-random test stimuli. After From Table 1, we may observe the following. The
initialization, the first step is producing 64-bit pseudo- FPGA-based pseudo-random verification method strongly
random number. Then all the signals to be sent to Cache, outperforms the popular software simulation method by
such as the address, the operation type and the writing data, about three orders of magnitude. The 128KB Cache is fully
are built. If the current operation is reading operation, an idle test by the designer. Therefore software simulation method
reading ID is allocated and sent to Cache in company with cannot find any fault in this design. However the FPGA-
other control and data signals. Next the mirror image is based pseudo-random verification method has found 3 bugs.
updated by storing data into the same address of the memory. One of three bugs is the writing after reading error of LRU
Simultaneously, the timeout counter is started until the array. The cycle interval error between fill buffer requests

280
and miss buffer requests leads to another bug. The last one is
the address conflict problem of input queue and miss buffer
requests. The three bugs are deeply faults in the design, and
dug very difficultly.
The 256KB and 512KB Cache are modified based on
128KB Cache. Therefore the software has found 2 bugs
introduced by modification. The two bugs of 256KB Cache
are identical as the two bugs of 512KB Cache. However,
FPGA-based pseudo-random verification method has found
5 bugs. The two bugs are the same as the faults found by
software simulation method. The other three bugs are similar
as the bugs found in 128KB Cache. In summary, the FPGA-
based pseudo-random verification method achieves
substantial improvement on coverage, and can cover more
corner cases and combinational conditions. This method can
help to find more faults in the designs, and improve the
efficiency of verification, and shorten the time to market of
chips.
V. CONCLUSIONS
For the functional verification of Cache, we propose an
FPGA-based pseudo-random verification method. This
method has two features: one is the testbench is
synthesizable, and the FPGA emulation process is introduced
to improve the efficiency of verification; the second is the
pseudo-random stimuli are generated automatically, and then
the functional verification coverage is increased. This
method is compared with the pseudo-random software
simulation method. The results show that our method is
faster by about three orders of magnitude, and find more
bugs in the designs. One of the future works is to explore
281
more aggressive techniques to improve the efficiency of
locating the bugs. The other future work is to apply our
method to more designs.
ACKNOWLEDGMENT
The authors would like to thank all peer reviewers for
their valuable comments and suggestions. This work is
supported by the National Natural Science Foundation of
China under grant No. 61103083 and 61133007, and
National High Technology Research and Development
Program of China (863 Program) under grant No.
2012AA01A301.
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