CS2420 – Introduction to Digital Logic Design

2017/18 Tentative Lecture schedule

DATE JANUARY February MARCH APRIL

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1 Sunday
nd
2 Class Test 1 Arithmetic ccts 2 Easter Monday
rd
3 Introduction Saturday Saturday No Lab
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4 Introduction Sunday Sunday Registers 2
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5 Introduction Programmable logic devs 1 SHORT BREAK
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6 Saturday Tutorial 2 SHORT BREAK Counters (sync)
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7 Sunday Programmable logic devs 2 SHORT BREAK Saturday
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8 Binary Numbers SHORT BREAK Sunday
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9 No Lab Programmable logic devs 3 SHORT BREAK Counter design 1
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10 Logic gates and networks Saturday Saturday Lab 4
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11 Sunday Sunday Counter design 2
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12 Boolean Algebra intro Karnaugh Map 1 variable Combinational ccts
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13 Saturday Lab 1 Lab 3 Circuit design task
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14 Sunday Karnaugh Map 2 & 3 variable Multiplexers Saturday
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15 The Venn Diagram Sunday
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16 No Lab Karnaugh maps multiple vars Multiplexers Revision
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17 Synthesis using gates Saturday Saturday Lab 4 demo
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18 Sunday Sunday Revision
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19 Sums-of-products form Multiple output circuits Decoders
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20 Saturday Lab 2 Class Test 2 Lectures End
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21 Sunday Multilevel circuits Latches Saturday
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22 Product-of-sums form Sunday
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23 Tutorial 1 Unsigned integers Flip-flops (D-Type) SWOT WEEK
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24 Product-of-sums cont. Saturday Saturday SWOT WEEK
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25 Sunday Sunday SWOT WEEK
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26 NAND and NOR circuits Arithmetic circuits 1 Flip-flops (JK) SWOT WEEK
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27 Saturday Tutorial 3 SWOT WEEK
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28 Sunday Signed numbers Registers 1 Saturday
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29 NAND and NOR circuits Sunday
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30 Class Test 1 Good Friday
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31 Design Example MUX ccts Saturday

EXAMINATIONS PERIOD: Monday, 7th May 2018 to Sunday, 20th May 2018