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SECTION 2: SEQUENTIAL CIRCUITS

EXPERIMENT NO. 1

Aim: To design clocked SR flip flop.

Software: Xilinx ISE Design Suit.

Theory:

The outputs of a basic SR flip-flop change whenever its R or S inputs change appropriately.
A clocked SR flip-flop has an extra clock input which enables or disables the other two inputs.

If we connect two clocked SR flip-flops so that the Q and /Q outputs of the first, "master"
flip-flop drive the S and R inputs of the second, "slave" flip-flop, and we drive the slave's clock
input with an inverted version of the master's clock, then we have an edge-triggered RS flip-flop.
The external R and S inputs of this device are latched on one edge (transition) of the clock (e.g. the
falling edge) and the outputs will only change on the next opposite (rising) edge.

If both R and S inputs are active (when enabled), a race condition occurs and the outputs
will be in an indeterminate state. A JK flip-flop avoids this possibility.

Fig: Clocked SR Flip-Flop using NAND Gate

Fig: Truth Table of Clocked SR Flip-Flop

VHDL Code:
-- Create Date: 15:19:13 03/21/2017
-- Module Name: flipflop - Behavioral
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity flipflop is
Port (
clk : in STD_LOGIC;
s : in STD_LOGIC;
r : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC
);
end flipflop;

architecture Sequential of flipflop is


begin
process(s,r,clk)
variable temp : STD_LOGIC := '0';
begin

if (rising_edge(clk)) then
if s='0' and r='0' then
temp := temp;
elsif s='0' and r='1' then
temp := '0';
elsif s='1' and r='0' then
temp := '1' ;
elsif s='1' and r='1' then
temp := 'X';
end if ;
end if;
qbar <= not temp ;
q <= temp;
end process;
end Sequential;

Test Bench Code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY srfftt IS
END srfftt;

ARCHITECTURE behavior OF srfftt IS

COMPONENT flipflop
PORT(
clk : IN std_logic;
s : IN std_logic;
r : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal s : std_logic := '0';
signal r : std_logic := '0';
--Outputs
signal q : std_logic;
signal qbar : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN
uut: flipflop PORT MAP (
clk => clk,
s => s,
r => r,
q => q,
qbar => qbar
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
s<='0';
r<='0';
wait for clk_period*10;
wait for 100 ns;
s<='0';
r<='1';
wait for clk_period*10;
wait for 100 ns;
s<='1';
r<='0';
wait for clk_period*10;
wait for 100 ns;
s<='1';
r<='1';
wait for clk_period*10;
wait;
end process;
END;
RTL Schematic:

Output Waveform:

Conclusion: