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dU 2 cs 2 ⋅ Pr _ peak (2)
= sin 2ωt
dt Cs
Pr _ peak (3)
U cs = Const − cos 2ωt
C sω
(a) Charging phase
Pr _ peak sin 2ωt (4)
ics =
P
Const − r _ peak cos 2ωt
Csω
Pr _ peak
where: Const = k × ( k ≥ 1 ). If we consider total
Csω
Pr _ peak
charge and discharge, Const = is desired.
C sω
(b) Discharging phase
Fig.3. Charging and discharging phases duty-cycle generation strategy
The inductor current in Fig.3 (a) shows the charging
phase for one switching period, and Fig.3 (b) shows the
discharging phase for one switching period. The aim is to
control the average inductor current (the inductor and
capacitor currents are same) to match the reference which is
derived in (4). Defining the boost and buck slopes as (5)
and (6):
U (5)
Boost _ slope = cs
L
(a). Low-frequency capacitive voltage U d − U cs
Buck _ slope = (6)
L
For the charging phase, the time interval relationship
between t1 and t2 can be expressed as:
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Buck _ slope back into the dc link.
t2 = × t1 (7)
Boost _ slope The auxiliary capacitor mean voltage control loop is
required to prevent the Cs from over charging or under
According to the control objective, the average current charging. The PLL block is designed as shown in [4].
within one switching cycle should be equal to the current
reference, that is:
1 Buck _ slope ⋅ t1 (8)
(t1 + ) ⋅ Buck _ slope ⋅ t1 = ics ⋅ Ts
2 Boost _ slope
Then, the duty cycle for the charging and discharging
phases can be derived as (9) and (10). By using these
equations, the second-order ripple energy can be accurately
filtered out from the H-bridge.
2 ⋅ ics ⋅ f s (9)
D1 =
Buck _ slope
(1 + ) ⋅ Buck _ slope
Boost _ slope
2 ⋅ ics ⋅ f s (10)
D1 =
Boost _ slope
(1 + ) ⋅ Boost _ slope
Buck _ slope
Equations (9) and (10) determine the duty cycle control
laws for the charging and discharging operating modes. For
a practical implementation, it is not easy to determine the
auxiliary capacitor current reference in (4). A more
straightforward, but similar current filter method, is shown
in Fig.4. The compensation current is used to regulate the
low frequency ripple current. In Fig.3, the triangular shaded
area is the current waveform of the compensation current.
Using the previous method, the average compensation
current within one switching period should be equal to the Fig.5. Control schematic figure for the system
low frequency ripple current, then the duty cycle for the
charging and discharging phases are derived as (11) and
(12). IV. DESIGN CONSIDERATIONS
For single phase H-bridge rectifier, the modulation
method is specified to achieve both the minimum loss and
balanced temperature distribution. For the auxiliary circuit,
the auxiliary capacitor is selected according to the ripple
energy requirements and the auxiliary inductor is designed
as below.
A. Modulation method
Fig.4. Auxiliary circuit working as a parallel active ripple current filters
Fig.6 shows the single phase discontinuous PWM
2 ⋅ icomp ⋅ f s modulation method [5]. One phase leg will not switch within
D1 = (11) half of the supply frequency. It can lead to the minimum
Buck _ slope switching loss.
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Fig.7 shows the simulation results of modulation method
V. SIMULATION AND EXPERIMENT RESULTS
in [5]. During the discontinuous current period, switch 2 is
always conducted. Then, the loss distribution is not equal Fig.10. shows the simulation result. After 0.6 s, the
for the top and bottom switches. auxiliary circuit is inactive. A large dc-link voltage ripple
can be observed due to the small dc-link capacitor Cd.
Before 0.6 s, the auxiliary circuit is active. Most of the
ripple energy is stored in the auxiliary energy storage
capacitor. As such, the dc-link voltage ripple is within the
required 2% limit even with a 140 µF auxiliary energy
(a). Asymmetrical zero vector (b). Symmetrical zero vector storage capacitance Cs compared with 1.6 mF needed to
meet the same requirement using the conventional method.
Fig.8. Terminal voltages and voltage vectors
The voltage range of the auxiliary capacitor is between 320
The reason for the unequal loss distribution is shown in V and 520 V.
Fig.8 (a). The only zero vector (0,0) is inserted and causes
this asymmetrical problem. To prevent this, symmetrical
zero vectors are required as shown in Fig.8 (b). Zero
vectors (0,0) and (1,1) are inserted alternatively. This will
leads to the balanced thermal performance.
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over-voltage protection.
ACKNOWLEDGMENT
The authors would like to thank Rolls-Royce
Corporation and Dr. Kaushik Rajashekara for providing
(b). Auxiliary circuit is active
support for the project.
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REFERENCES
[1] G. Jack, B. C. Mecrow, and J. A. Haylock, “A
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Ertl, T. Friedli, and S. D. Round, “PWM Converter
Power Density Barriers”. Power Conversion Conference
Nagoya, 2007. PCC '07
[3] Ruxi Wang, Fred Wang, Puqi Ning, Rixin Lai, Rolando
Burgos, Dushan Boroyevich. “Study of Energy Storage
Capacitor Reduction for Single Phase PWM Rectifier” .
IEEE Applied Power Electronics Conference. 2008
[4] Timothy Thacker, Ruxi Wang, Dong Dong, Rolando
Burgos, Fred Wang, Dushan Boroyevich.
“Phase-Locked Loops using State Variable Feedback
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[5] D.Grahame Holmes, Thomas A. Lipo “Pulse Width
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[6] Venkatachalam, K. Sullivan, C.R. Abdallah, T. Tacca,
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