PD - 95092C

IRLR7833PbF
IRLU7833PbF
HEXFET® Power MOSFET
Applications
l High Frequency Synchronous Buck
VDSS RDS(on) max Qg
Converters for Computer Processor Power 30V 4.5m: 33nC
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance D-Pak I-Pak
IRLR7833PbF IRLU7833PbF
l Fully Characterized Avalanche Voltage
and Current

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 140 f
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 99 f A
IDM Pulsed Drain Current c 560
PD @TC = 25°C Maximum Power Dissipation g 140 W
PD @TC = 100°C Maximum Power Dissipation g 71
Linear Derating Factor 0.95 W/°C
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case)
Mounting torque, 6-32 or M3 screw x
10 lbf in (1.1N m) x
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.05
RθJA Junction-to-Ambient (PCB Mount) g ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110

Notes  through … are on page 11

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IRLR/U7833PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 19 ––– mV/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 3.6 4.5 VGS = 10V, ID = 15A f
––– 4.4 5.5
mΩ
VGS = 4.5V, ID = 12A f
VGS(th) Gate Threshold Voltage 1.4 ––– 2.3 V VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -6.0 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 VDS = 24V, VGS = 0V
µA
––– ––– 150 VDS = 24V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 66 ––– ––– S VDS = 15V, ID = 12A
Qg Total Gate Charge ––– 33 50
Qgs1 Pre-Vth Gate-to-Source Charge ––– 8.7 ––– VDS = 16V
Qgs2 Post-Vth Gate-to-Source Charge ––– 2.1 ––– VGS = 4.5V
nC
Qgd Gate-to-Drain Charge ––– 13 ––– ID = 12A
Qgodr Gate Charge Overdrive ––– 9.9 ––– See Fig. 16
Qsw Switch Charge (Qgs2 + Qgd) ––– 15 –––
Qoss Output Charge ––– 22 ––– nC VDS = 16V, VGS = 0V
td(on) Turn-On Delay Time ––– 14 ––– VDD = 15V, VGS = 4.5V f
tr Rise Time ––– 6.9 ––– ID = 12A
ns
td(off) Turn-Off Delay Time ––– 23 ––– Clamped Inductive Load
tf Fall Time ––– 15 –––
Ciss Input Capacitance ––– 4010 ––– VGS = 0V
Coss Output Capacitance ––– 950 ––– pF VDS = 15V
Crss Reverse Transfer Capacitance ––– 470 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy d ––– 530 mJ
IAR Avalanche Current c ––– 20 A
EAR Repetitive Avalanche Energy c ––– 14 mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 140 f MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 560 integral reverse G

(Body Diode)ch p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 12A, VGS = 0V f
trr Reverse Recovery Time ––– 39 58 ns TJ = 25°C, IF = 12A, VDD = 15V
Qrr Reverse Recovery Charge ––– 37 55 nC di/dt = 100A/µs f
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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 IRLR/U7833PbF

1000 1000
VGS VGS
TOP 10V TOP 10V
5.0V 5.0V
4.5V 4.5V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

4.0V 4.0V
3.5V 3.5V
3.0V 3.0V
100 2.8V 100 2.8V
BOTTOM 2.7V BOTTOM 2.7V

2.7V
2.7V

10 10

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
ID = 30A
RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

100 1.5
(Normalized)

T J = 175°C

T J = 25°C
10 1.0

VDS = 25V
≤60µs PULSE WIDTH
1.0 0.5
1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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100000 6.0
VGS = 0V, f = 1 MHZ
ID= 12A
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd 5.0 VDS= 24V

VGS , Gate-to-Source Voltage (V)

Coss = Cds + Cgd VDS= 15V
C, Capacitance(pF)

10000 4.0

Ciss
3.0
Coss
1000 2.0
Crss

1.0

100 0.0
1 10 100 0 10 20 30 40 50
VDS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 10000

OPERATION IN THIS AREA

LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.00 T J = 175°C 1000

10.00 100
100µsec

T J = 25°C
1.00 10 1msec
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse 10msec
0.10 1
0.0 0.5 1.0 1.5 2.0 2.5 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRLR/U7833PbF

150 2.5
LIMITED BY PACKAGE

VGS(th) Gate threshold Voltage (V)

125
2.0

100 ID = 250µA
ID , Drain Current (A)

1.5

75

1.0
50

0.5
25

0.0
0
25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
TC, Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Case Temperature

10
(Z thJC)

D = 0.50
Thermal Response

0.20

P DM
0.10
0.1
0.05 t1
SINGLE PULSE
0.02 t2
0.01 (THERMAL RESPONSE)

Notes:
1. Duty factor D = t1/ t 2
2. Peak T J = P DM x Z thJC +TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1

t1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U7833PbF
15V 15000
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 8.2A
L DRIVER 12500
VDS 14A
BOTTOM 20A
10000
RG D.U.T +
V
- DD
IAS A
20V
VGS 7500
tp 0.01Ω

Fig 12a. Unclamped Inductive Test Circuit 5000

2500
V(BR)DSS
tp
0
25 50 75 100 125 150
Starting T J , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
I AS
RD
VDS
Fig 12b. Unclamped Inductive Waveforms
VGS
D.U.T.
RG
+
-V DD

Current Regulator
V GS
Same Type as D.U.T.
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

50KΩ

12V .2µF
.3µF
Fig 14a. Switching Time Test Circuit
+ VDS
V
D.U.T. - DS 90%

VGS

3mA
10%
IG ID VGS
Current Sampling Resistors td(on) tr t d(off) tf

Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms

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 IRLR/U7833PbF

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by R G V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRLR/U7833PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛ Qgd ⎞ ⎛ Qgs 2
+⎜I × × Vin × f⎟ + ⎜ I × × Vin × f ⎟
⎝ ig ⎠ ⎝ ig
+ (Qg × Vg × f )
⎛ Qoss
+ × Vin × f ⎞
⎝ 2 ⎠ are transfered to Q1 and increase the dissipation in
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
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Synchronous FET
The power loss equation for Q2 is approximated
by;
Ploss = Pconduction + Pdrive + Poutput
*
( 2
Ploss = Irms × Rds(on) )
+ (Qg × Vg × f )
⎛Q ⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2 ⎠
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
⎞ portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
⎠ it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
 IRLR/U7833PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

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IRLR/U7833PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

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 IRLR/U7833PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 2.6mH, RG = 25Ω,
IAS = 20A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
… When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/2009
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