PLATE No.

1
Application of Combinational Circuits

Submitted to
ENGR. RODRIGO S. PANGANTIHON, JR., MIT
Professor in EE 538/L

In Partial Fulfilment of the Course Requirements

in EE 538/L – Logic Circuits and Switching Theory
03:30PM – 05:30PM

Submitted by
EXZELL KWYN ARACENA CALOYLOY
Student

January 2018
I – INTRODUCTION

Logic circuits for digital systems may be combinational or sequential. A

combinational circuit consists of logic gates whose outputs at any time are determined
directly from the present combination of inputs without regard to previous input. A
combinational circuit performs a specific information-processing operation fully specified
logically by a set of Boolean functions that consists input variables, logic gates and
output variable.

Appling combinational circuit, this report will illustrate how to design a 2-bit
comparator circuit without using special integrated circuit such as built-in decoder,
multiplexer, etc. This circuit only utilizes basic IC specifically AND, OR and universal
gates XOR. This will display the sum of two digits when less than, difference when
greater than and an equals sign when equal.

II – OBJECTIVES

The objectives of this project are as follows:

1.) To design a 4-bit decoder using basic logic gates only
2.) To make use of Karnaugh map in simplifying Boolean expressions in
designing 4-bit decoder
3.) To formulate truth table in analyzing the design of a 4-bit decoder and apply
concepts about sum of minterms or product of maxterms, or product of sums (POS) or
sum of products (SOP).
4.) To apply switching technique

III – LIST OF MATERIALS

Materials used in this laboratory exercise are listed below:
No. Material Quantity Specification
1. 7-segment display 3 pieces Common cathode
2. HD74LS32P 5 pieces Quad-Output, Two-
Input OR gate
3. HD74LS04P 3 pieces Quad-Output, Two-
Input NOT gate
4. HD74LS08P 5 pieces Quad-Output, Two-
Input AND gate
5. HD74LS86P 3 pieces Quad-Output, Two-
Input XOR gate
6. Resistor 4 pieces 470 Ohms
7. Breadboard 1 piece 4 pads

IV – EXPERIMENTAL PROCEDURES

To actualize this design, the following laboratory procedures were taken:

1. It is advisable to use Proteus for easy simulation and testing.

2. To display X digit, make a truth table for 2-bit displaying only 0,1,2 and 3 digits on
the 7-segment display with inputs X0 and X1 and formulate the equation for
corresponding pins of the 7-segment display which are for a, b, c, d, e, f, g.
Simplify using Karnaugh Map.
3. Repeat step 2 for Y digit with inputs Y0 and Y1; and outputs are a, b, c, d, e, f, g.

Comparator
4. Using 2-bit binary, compare digits X and Y whether equal, greater than, and less
than from each other by putting it in a table.
5. The inputs are X0, X1, Y0, Y1. Let equals, greater than and less than be the
output. Then, formulate the equation and simplify using Karnuagh Map.
 Adder/Subtractor
6. By research, there is a 4-bit adder/subtractor circuit.

7. I cut the circuit into 2-bit adder/subtractor circuit to compute (X+Y) or (X-Y) that
depends upon a mode input which controls the operation. I used two full-adders
with a 2-bit input X and a 2-bit input Y whose bits may be XOR’d based on the
mode triggered. The mode will be decided by bit M in the circuit.

For subtraction M = 1. 1 is chosen because M acts as the carry-in. For addition,

M = 0. Therefore, carry-in is set to zero as desired.

XOR Truth Table FULL ADDER Truth Table

Final Result

8. Setting the equals as the first input(MSB), last XOR output from the step 7 be the
second input, output of S1/D1 be the third input and output of S0/D0 be the fourth
input(LSB).

9. Connect logic probes(Proteus) on the inputs from step 8.

10. Manipulate the main switch in the X and Y digit. MSB’s probe will only turn on
when it’s equal.

11. Decode what is given by the main switch to the logic probes in the step 8.
V – PROBLEM ANALYSIS
2-bit for X digit

K-map for X digit

2-bit for Y digit

K-map for Y digit

Comparator

K-map for Comparator

or (X0’ xor Y0)(X1’ xor Y1)

Final result

K-map for Final result

VI – LOGIC CIRCUIT / DIAGRAM

Displaying 3 and 3 results to equals sign

VII – PHOTOS OF ACTUAL IMPLEMENTATION

This picture illustrates that 0 as X and 0 as Y are equals.

VIII – CONCLUSIONS

In light of this design, the following conclusions were drawn:

1.) Therefore, K-mapping is more advisable to use in simplifying equations rather than
Boolean algebra because K-map gives the simplest function when grouped properly.
2.) Therefore, knowledge in knowing how to use simulator is very essential to easily
test if the circuit performs accordingly.
3.) Therefore, using basic or universal gates is more complicated than special IC’s
because of its complexity.
4.) Therefore, only FA or Full Adder is being used in the Adder/Subtractor part of the
plate because of its function and that it only differs when ‘m’ is triggered that makes the
operation perform addition or subtraction.

IX – RECOMMENDATIONS

After the implementation of this project, the following recommendations were

offered:

1) Use simulation software like Proteus and Logisim for faster and effective
analysis
2) Simplify the equation by using Boolean Algebra or Karnaugh Map for
Construct the circuit in a manner that errors can be detected easily
3) Always do research for efficient circuit construction
4) Always foresee the number of IC’s to be used in bread boarding by referring
from the simulator
5) Always focus and never let your eyes off of your work because you might
jumble up

X – REFERENCES

Mano, Morris et. al. (2007). Digital design. 4th Edition. New Jersey : Pearson/Prentice
Hall.