PARK COLLEGE OF ENGINEERING AND

TECHNOLOGY
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PAPER PRESENTED TOPIC OF

VLSI DESIGN

HEARTLY SUBMITTED BY

M.VIDHYALAKSHMI
3 rd ECE
vidhyavkl@yahoo.co.in
G.SARANYA
3 rd ECE
saranece84@yahoo.com
 ABSTRACT

 MOORE’S LAW

 VLSI DESIGN STYLES

 FPGA DESIGN

 GATE ARRAY DESIGN

 FULL CUSTOM DESIGN

 CONCULSIONS

 REFERFENCES
 Very-large-scale integration (VLSI) of systems of transistor-based circuits into integrated
circuits on a single chip first occurred in the 1980s as part of the semiconductor and communication
technologies that were being developed.

FPGAs have their historical roots in complex programmable logic devices (CPLDs) of the early
to mid 1980s. CPLDs and FPGAs include a relatively large number of programmable logic elements.
CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic
gates, while FPGAs typically range from tens of thousands to several million.

The primary differences between CPLDs and FPGAs are architectural. A CPLD has a somewhat
restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a
relatively small number of clocked registers. The result of this is a general lack of design flexibility, with
the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. FPGA
architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in
terms of the range of designs that are practical for implementation within them) but also far more
complex to design for.

In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the
design of high-volume products such as memory chips, high- performance microprocessors and FPGA masters
Here, one can identify four different design styles on one chip: Memory banks (RAM cache), data-path units
consisting of bit-slice cells, control circuitry mainly consisting of standard cells and PLA blocks.

 Few engineers will design custom chips

 Some engineers will design ASICs & SOCs
 Many engineers will design FPGA systems
 MODERN TRENDS IN VLSI DESIGN

INTRODUCTION

VLSI TRENDS: MOORE’S LAW

In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing:
o Doubled transistor density every 18-24 months
o Doubled performance every 18-24 months
History has proven Moore right
But, is the end is in sight?
o Physical limitations
o Economic limitations

In graph it advances in manufacturing capability by charting the introduction dates of key products that pushed the
state of the manufacturing art. The circles shows various logic circuits, primary CPU and DSP, while the black
dots shows RAM primarily dynamic RAM or DRAM at any time memory chip have more transistors per unit area
than logic chips, but both obeyed Moore’s law

IN FUTURE

Moore’s Law is likely to hold for quite some time to come. In a short amount of time from this writing, we will be
able to design and fabricate in large quantities circuits with several hundred million transistors. We are already in
the age of deep-submicron VLSI-the typical fabrication process constructs transistors that are much smaller than
one micron in size. As we move toward even smaller transistors and even more transistors per chip, several types
of challenges must be faced.

Gordon Moore
 VLSI DESIGN STYLES

Several design styles can be considered for chip implementation of specified algorithms or logic
functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by
designers in order to provide the functionality at low cost.

FIELD-PROGRAMMABLE GATE ARRAY OR FPGA

A field-programmable gate array or FPGA is a semiconductor device containing programmable logic

components and programmable interconnects. The programmable logic components can be programmed to
duplicate the functionality of basic logic gates (such as AND, OR, XOR, INVERT) or more complex
combinatorial functions such as decoders or simple math functions. In most FPGAs, these programmable logic
components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or
more complete blocks of memories.

A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as

needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and
interconnects can be programmed after the manufacturing process by the customer/designer (hence the term
"field-programmable") so that the FPGA can perform whatever logical function is needed.

FPGAs are generally slower than their application-specific integrated circuit (ASIC) counterparts, can't
handle as complex of a design, and draw more power. However, they have several advantages such as a shorter
time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors
may offer less flexible versions of their FPGAs that are cheaper. The development of these designs is made on
regular FPGAs and then migrated into a fixed version that more resembles an ASIC due to lack of ability to
modify the design once it is committed.

ARCHITECTURE

The typical basic architecture consists of an array of logic blocks and routing channels. Multiple I/O pads
may fit into the height of one row or the width of one column. Generally, all the routing channels have the same
width (number of wires).
FPGA STRUCTURE

An application circuit must be mapped into an FPGA with adequate resources.

The typical FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop, as shown at below.

LOGIC BLOCK

There is only one output, which can be either the registered or the unregistered LUT output. The logic
block has four inputs for the LUT and a clock input. Since clock signals (and often other high-fanout signals) are
normally routed via special-purpose dedicated routing networks in commercial FPGAs, they are accounted for
separately from other signals.

For this example architecture, the locations of the FPGA logic block pins are shown below.

Logic Block Pin Locations

Each input is accessible from one side of the logic block, while the output pin can connect to routing wires
in both the channel to the right and the channel below the logic block.
 Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. The
figure below should make the situation clear.

Logic block pin to routing channel interconnect

Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For
example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the
horizontal channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block
before it terminates in a switch box. By turning on some of the programmable switches within a switch box,
longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines
that span multiple logic blocks.

Unsegmented FPGA routing

Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a
wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in
adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-
based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track
number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2
and so on. The figure below illustrates the connections in a switch box.

Switch box topology

Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into
the silicon. Having these common function embedded into the silicon reduces the area required and gives those
functions increased speed compared to building them from primitives. Example of these include multipliers,
generic DSP blocks, embedded processors, high speed IO logic and embedded memories.

FPGA DESIGN AND PROGRAMMING

To define the behavior of the FPGA the user provides a hardware description language (HDL) or a
schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a
technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a
process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software.
The user will validate the map, place and route results via timing analysis, simulation, and other verification
methodologies. Once the design and validation process is complete, the binary file generated (also using the
FPGA company's proprietary software) is used to (re)configure the FPGA device. Approaches based on
standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the
Catapult C tools from Mentor Graphics, and in the Impulse C tools from Impulse Accelerated
Technologies. Languages such as SystemVerilog, SystemVHDL, and Handel-C (from Celoxica) seek to
accomplish the same goal, but are aimed at making existing hardware engineers more productive vs
making FPGAs more accessible to existing software engineers.

Applications

Applications of FPGAs include DSP, software-defined radio, aerospace and defense systems,
ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics,
and a growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a
similar space, that of glue logic for PCBs. As their size, capabilities and speed increased they began to
take over larger and larger functions to the state where they are now marketed as competitors for full
systems on chips. They now find applications in any area or algorithm that can make use of the massive
parallelism offered by their architecture.

GATE ARRAY DESIGN

In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. While the
design implementation of the FPGA chip is done with user programming, that of the gate array is done
with metal mask design and processing. Gate array implementation requires a two-step manufacturing
process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted
transistors on each GA chip. These uncommitted chips can be stored for later customization, which is
completed by defining the metal interconnects between the transistors of the array (Fig.). Since the
patterning of metallic interconnects is done at the end of the chip fabrication, the turn-around time can be
still short, a few days to a few weeks. Figure shows a corner of a gate array chip which contains bonding
pads on its left and bottom edges, diodes for I/O protection, nMOS transistors and pMOS transistors for
chip output driver circuits in the neighboring areas of bonding pads, arrays of nMOS transistors and
pMOS transistors, underpass wire segments, and power and ground buses along with contact windows.

FULL
CUSTOM
DESIGN

Although the standard-cells based design is often called full custom design, in a strict sense, it is
somewhat less than fully custom since the cells are pre-designed for general use and the same cells are utilized in
many different chip designs. In a fuller custom design, the entire mask design is done anew without use of any
library. However, the development cost of such a design style is becoming prohibitively high. Thus, the concept of
design reuse is becoming popular in order to reduce design cycle time and development cost. The most rigorous
full custom design can be the design of a memory cell, be it static or dynamic. Since the same layout design is
replicated, there would not be any alternative to high density memory chip design. For logic chip design, a good
compromise can be achieved by using a combination of different design styles on the same chip, such as standard
cells, data-path cells and PLAs. In real full-custom layout in which the geometry, orientation and placement of
every transistor is done individually by the designer, design productivity is usually very low - typically 10 to 20
transistors per day, per designer.

In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this
include the design of high-volume products such as memory chips, high- performance microprocessors and FPGA
masters. Figure shows the full layout of the Intel 486 microprocessor chip, which is a good example of a hybrid
full-custom design. Here, one can identify four different design styles on one chip: Memory banks (RAM cache),
data-path units consisting of bit-slice cells, control circuitry mainly consisting of standard cells

Thus we concluded this paper in this paper we discussed about the current leading-edge
technologies (such as low bit-rate video and cellular communications) already provide the end-users a
certain amount of processing power and portability. This trend is expected to continue, with very
important implications on VLSI and systems design. One of the most important characteristics of
information services is their increasing need for very high processing power and bandwidth (in order to
handle real-time video, for example). The other important characteristic is that the information services
tend to become more and more personalized (as opposed to collective services such as broadcasting),
which means that the devices must be more intelligent to answer individual demands, and at the same
time they must be portable to allow more flexibility/mobility..

• Mead, C. and Conway, L. (1980). Introduction to VLSI Systems. Addison-Wesley.

• Kang, S. and Leblebici, Y. (2002). CMOS Digital Integrated Circuits Analysis & Design.
McGraw-Hill. Weste,
• Neil H.E. and Harris, David (2004). CMOS VLSI Design : A Circuits and Systems Perspective.
Addison Wesley.
• Hodges, D.A., Jackson H.G. and Saleh, R. (2003). Analysis and Design of Digital Integrated
Circuits. McGraw-Hill.
• Uyemura, John P. (2001). Introduction to VLSI Circuits and Systems. Wiley.

 http://www.systemc.org/.
 Accelerator homepage. http://www.accelera.org/.
 www.intel.com