Beruflich Dokumente
Kultur Dokumente
Lecture 1
[Moore65]
Electronics Magazine
AT&T Archives.
Reprinted with
permission.
Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
[Moore65]
VLSI: > 10k gates
Electronics Magazine
A
B
C
D
Y
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON
0
0
1
1
0
1
1
b b b b b
(b) ON OFF OFF OFF
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)
A
B
C D
Y
D
A B C
s d g=1
g=0
s d 1 strong 1
g g g
a b a b a b
gb gb gb
EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y
EN
EN
A Y
EN
1: Circuits & Layout CMOS VLSI Design 4th Ed. 23
Tristate Inverter
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
D0
S Y
D1
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
CLK CLK
D
Latch
D Q
Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
CLK
CLK = 1 CLK = 0
CLK
CLK
CLK
D
Flop
D Q
Q
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
CLK = 0
QM
D Q
CLK = 1
CLK
CLK1
CLK1 CLK2 CLK2
Q1
Flop
Flop
Q1 Q2
D
Q2
2 2 1 1
2 1
1
2
GND GND
INV NAND3
40 l
32 l
6 tracks =
48 l
Y
GND
5 tracks =
40 l