EC6504 MICROPROCESSOR AND MICROCONTROLLER LTPC

3003
OBJECTIVES:

The student should be made to:

 Study the Architecture of 8086 microprocessor.
 Learn the design aspects of I/O and Memory Interfacing circuits.
 Study about communication and bus interfacing.
 Study the Architecture of 8051 microcontroller.
UNIT I THE 8086 MICROPROCESSOR (9)

Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and assembler directives –
Assembly language programming – Modular Programming - Linking and Relocation - Stacks - Procedures – Macros –
Interrupts and interrupt service routines – Byte and String Manipulation.
UNIT II 8086 SYSTEM BUS STRUCTURE (9)

8086 signals – Basic configurations – System bus timing –System design using 8086 – IO programming – Introduction to
Multiprogramming – System Bus Structure – Multiprocessor configurations – Coprocessor, Closely coupled and loosely
Coupled configurations – Introduction to advanced processors.
UNIT III I/O INTERFACING (9)

Memory Interfacing and I/O interfacing - Parallel communication interface – Serial communication interface – D/A and
A/D Interface - Timer – Keyboard /display controller – Interrupt controller – DMA controller – Programming and
applications Case studies: Traffic Light control, LED display , LCD display, Keyboard display interface and Alarm
Controller.
UNIT IV MICROCONTROLLER (9)

Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and Circuits - Instruction set - Addressing
modes - Assembly language programming.
UNIT V INTERFACING MICROCONTROLLER (9)

Programming 8051 Timers - Serial Port Programming - Interrupts Programming – LCD & Keyboard Interfacing - ADC,
DAC & Sensor Interfacing - External Memory Interface- Stepper Motor and Waveform generation.
TOTAL: 45 PERIODS
OUTCOMES:
At the end of the course, the student should be able to:
 Design and implement programs on 8086 microprocessor.
 Design I/O circuits.
 Design Memory Interfacing circuits.
 Design and implement 8051 microcontroller based systems.
TEXT BOOKS:
1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088 Family -Architecture, Programming and
Design”, Second Edition, Prentice Hall of India, 2007.
2. Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, “The 8051 Microcontroller and Embedded Systems:
Using Assembly and C”, Second Edition, Pearson Education, 2011
REFERENCE:
1. Doughlas V.Hall, “Microprocessors and Interfacing, Programming and Hardware:,TMH, 2012
 UNIT-1 THE 8086 MICROPROCESSOR
Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and assembler directives
– Assembly language programming – Modular Programming - Linking and Relocation - Stacks - Procedures – Macros –
Interrupts and interrupt service routines – Byte and String Manipulation.

1.1 INTRODUCTION TO MICROPROCESSOR

Microprocessor is an electronic circuit that functions as the central processing unit (CPU) of a
computer, providing computational control. The microprocessor is one of the most important components of a
digital computer. It acts as the brain of the computer system. As technology has progressed, microprocessors
have become faster, smaller and capable of doing more work per clock cycle. Sometimes, microprocessor is
written as µP.
Microprocessor is a computer Central Processing Unit (CPU) on a single chip. It contains millions of
transistors connected by wires Microprocessor is the controlling unit or CPU of a micro-computer, fabricated
on a very small chip capable of performing ALU operations and communicating with the external devices
connected to it.
Typical microprocessors incorporate arithmetic and logic functional units as well as the associated
control logic, instruction processing circuitry, and a portion of the memory hierarchy. Portions of the interface
logic for the input/output (I/O) and memory subsystems may also be infused, allowing cheaper overall
systems. While many microprocessors and single chip designs, some high-performance designs rely on a few
chips to provide multiple functional units and relatively large caches.
Microprocessors have been described in many different ways. They have been compared with the brain
and the heart of humans. Their operation has been likened to a switched board, and to the nervous system in
an animal. They have often been called microcomputers.
The original purpose of the microprocessor was to control memory. That is what they were originally
designed to do, and that is what they do today. A microprocessor can do any information-processing task that
can be expressed, precisely, as a plan. It is totally uncommitted as to what its plan will be. It is a truly general-
purpose information-processing device. The plan is stored electronically. This is the principle of “stored
program control”. Without a program the microprocessor can do nothing. With one, it can do anything.
Furthermore, microprocessors can only perform information-processing tasks. To take action on the
outside world, or to receive signals from it, a connection must be provided between the microprocessor’s
representation of information (as digital electronic signals) and the real world representation.
 The input unit consists of the devices which accept the data and instructions from the user and
communicates it to the CPU. The output unit provides the result of the various operations performed by the
CPU to the user. The CPU is the heart and nerve centre of the computer. It fetches the instruction and data
from the peripheral devices and performs all the arithmetic operations, takes logical decision and control the
operation of all other units. In Microprocessor based system , the CPU is nothing but a Microprocessor
Various sub-blocks of the central processing unit are:
 Arithmetic and Logic Unit (ALU)
 Timing & Control Unit
 Registers
ARITHMETIC AND LOGIC UNIT (ALU)
 This unit performs all the logical and arithmetic operations.
 Various arithmetic operations are: addition, subtraction, increment and decrement etc.
 Various logical operations are: AND, OR, NOT, XOR, etc.
TIMING AND CONTROL UNIT
 This unit controls the entire operations being performed by the system.
 It controls the operations of ALU, input/output devices and memory unit.
 This unit interprets the instructions and generates various timing and control signals.
REGISTERS
A register is a very small amount of very fast memory that is built into the CPU in order to store the
current data and instructions which are being executed by the CPU.
MULTIPROCESSOR SYSTEM
 A computer whose CPU contains more than one microprocessor is called Multiprocessor System.
 The CPU of a large powerful digital computer contains more than one microprocessor.
 High-end powerful servers, mainframe computers supercomputers, etc. contain more than one
microprocessor to act as CPU

1.1.1 HISTORY OF MICROPROCESSOR DEVEELOPMENT

Developed during the 1970s, the microprocessor became most visible as the central processor of the
personal computer. Microprocessors also play supporting roles within larger computers as smart controllers
for graphics displays, storage devices, and high-speed printers. However, the vast majority of
microprocessors are used to control everything from consumer appliances to smart weapons.
The microprocessor has made possible the inexpensive hand-held electronic calculator, the digital
wristwatch, and the electronic game. Microprocessors are used to control consumer electronic devices, such
as the programmable microwave oven and videocassette recorder; to regulate gasoline consumption and
antilock brakes in automobiles; to monitor alarm systems; and to operate automatic tracking and targeting
systems in aircraft, tanks, and missiles and to control radar arrays that track and identify aircraft, among other
defense applications.
 The first microprocessor was the Intel 4004, produced in 1971. Originally developed for a calculator,
and revolutionary for its time, it contained 2,300 transistors on a 4-bit microprocessor that could perform only
60,000 operations per second.
The first 8-bit microprocessor was the Intel 8008, developed in 1972 to run computer terminals. The
Intel 8008 contained 3,300 transistors. The first truly general-purpose microprocessor, developed in 1974,
was the 8-bit Intel 8080, which contained 4,500 transistors and could execute 200,000 instructions per
second. By 1989, 32-bit microprocessors containing 1.2 million transistors and capable of executing 20 million
instructions per second had been introduced.
Reductions in both device size and power dissipation are essential in achieving these high densities.
Smaller device sizes also allow faster switching speeds, which in turn permit higher processor clock rates.
Increased density also lets designers add circuitry to increase the amount of work performed within a cycle.
Microprocessors are fabricated using techniques similar to those used for other integrated circuits, such
as memory chips.
Microprocessors generally have a more complex structure than do other chips, and their manufacture
requires extremely precise techniques.(VLSI DESIGN TECHNIQUES)
1.1.2 WORKING OF A MICROPROCESSOR
A basic difference between a microprocessor and other logic chips is the functional flexibility afforded
by the microprocessor’s programmable nature. Its instruction set comprises the group of available low-level
operations. Each instruction has a specific binary pattern, or operation code (OP-CODE).
This operation code specifies the operation as well as the location of the operands. A programmer uses
sequences of these low-level instructions to create a desired higher-level function.
Therefore the personality of a microprocessor-based system can be readily modified without the
hardware modifications usually associated with non-programmable logic systems.
A typical microprocessor chip set includes an instruction control unit, one or more functional units, a set
of register, and one or more caches. Conceptually, the instruction control unit fetches an instruction from main
memory, interprets the operation code, and then dispatches the instruction to a functional unite.
The functional unit may again interpret the operation code, read the required operands from the register
or memory perform the specified operation and store the result in either the register set or memory.
Then the process repeats, with the instruction control unite fetching the next instruction. A powerful
aspect of programmability arises from the ability to specify which instruction will be executed next; selection is
often based on the outcome of a test involving computed results.
1.1.3 GENERAL CHARACTERISTICS OF A MICROPROCESSOR
Instruction Set:
 The set of instructions that a microprocessor can understand.
Bandwidth:
 The number of bits processed in a single instruction.
Capability:
 It depends upon the number of instructions and capability of each instruction.
Clock Speed:
 The clock speed determines how many operations per second the processor can perform. It is
also called Clock Rate. Every computer contains an internal clock that regulates the rate at
which instructions are executed and synchronizes the various computer components.
 The faster the clock, the more instructions the CPU can execute per second.
 Clock speeds are expressed in megahertz (MHz) or gigahertz (GHz).
 The microprocessors of personal computers have clock speeds of anywhere from 300 MHz to
over 3.8 GHz.
Word Length:
 It depends upon the width of internal data bus, registers, ALU etc.
 An 8-bit microprocessor can process 8 bit data at a time.
 A processor with longer word length is more powerful and can process data at a faster speed
as compared to processor with shorter word length.
 The word length ranges from 4 bits for small microprocessor, to 64 bits for high-end
microcomputers.
Width of Data Bus:
 This is the size of the data bus. It defines the number of bits that can be transferred through
data bus.
Width of Address Bus:
 This parameter decides the memory addressing capability of the microprocessor. The maximum
size of the memory unit is decided by this parameter.
Input /Output Addressing Capability:
 The maximum number of the input/output ports accessed by the microprocessor depends upon
the width of the input/output address provided in the input/output instruction.
Data Types:
 The microprocessor handles various types of data formats like binary, BCD, ASCII, signed and
unsigned numbers.
Interrupt Capability:
 Interrupts are used to handle unpredictable and random events in the microcomputer.
 It is used to halt the microprocessor temporarily during its execution
 Interrupt driven input/output improves the throughput of a system.
Cost:
 The most important feature of a microcomputer is its low cost. Because of the widespread use
of microprocessors, the volume of production is very high.
 That is why, microprocessor chips are available at fairly low prices.
Size:
 The second important feature of a microprocessor is its small size.
 As a result of improvement in fabrication technology, VLSI, electronic circuitry has become so
dense that a minute silicon chip can contain hundred and thousands of transistors.
Power Consumption:
 Another important feature is its low power consumption.
 Microprocessors are normally manufactured by Metal-Oxide semiconductor technology, which
has the feature of low power consumption.
Versatility:
 The microprocessors are versatile.
 Keeping the same basic hardware, a microprocessor-based system can be configured for a
number of applications by simply altering the software program.
Reliability:
 Another important property of microprocessors is its extreme reliability.
 It has been established that the failure rate of an IC is fairly uniform at the package level,
regardless of its complexity.
1.1.4 LIST OF INTEL MICROPROCESSORS

1.2 THE 8086 MICROPROCESSOR

The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978, when it
was released. The Intel 8088, released in 1979, was a slightly modified chip with an external 8-bit data
bus (allowing the use of cheaper and fewer supporting ICs, and is notable as the processor used in the
original IBM PC design, The 8086 gave rise to the x86 architecture which eventually turned out as Intel's
most successful line of processors.
1.2.1 FEATURES OF THE 8086
 The 8086 is a 16 bit microprocessorwhich means its data handling capacity is 16 bits per
clock.(i.e) at any time any resources of 8086 system can handle up to 16 bit of data for processing.
 It has 16 bit address bus
 It has 20 bit data bus
 Direct addressing capability 1MB of memory. (1MB=220 Bytes)
 It has fourteen 16 bit registers
 24 operand addressing modes
 Supports Bit, Byte, Word and Block level operations
 8 and 16 bit signed and unsigned arithmetic operations including multiply and divide.( previously the
multiply and divide operations were carried out using the iterative looping of addition and subtraction
operations respectively)
 Four general purpose registers, each of 16 bit wide. AX,BX,CX and DX
 These can be used as 8-bit as well as 16 bit registers
o AX(16 bit register)AL &AH (2 x 8 bit registers)
o BX(16 bit register)BL&BH (2 x 8 bit registers)
o CX(16 bit register)CL&CH (2 x 8 bit registers)
o DX(16 bit register)DL&DH (2 x 8 bit registers)
  Two pointer group registers available. Stack pointer SP and Base Pointer BP
 Two Index group registers available Source Index SI and destination index DI
 There are four Segment registers in 80x86 Code Segment (CS),Data Segment (DS), Stack Segment
(SS), Extra Segment (ES)
 Six Status flags and three control flags
 Memory is Byte addressable-each stores and 8-bit value
 Addresses can be up to 32-bits long , resulting up to 4GB of memory (232 Bytes=4GB)
 Ranges of clock rates : 5MHz for 8086, 8 MHz for 8086-1 and 10 MHz for 8086-2
 Multi-bus system compatible interface
 Available as a 40 pin Plastic-DIP and Lead Cer-DIP

1.3 THE 8086 ARCHITECTURE

1.3.1 MAIN UNITS
The internal functions of the 8086 processor are partitioned logically as two functional units as shown in
the figure. They are
1. Bus Interface Unit –BIU
2. Execution Unit- EU

The BIU and EU function independently. The BIU interfaces the 8086 to the outside world. It fetches the
instructions, Reads data from memory and ports, and writes data to memory and I/O ports.
The EU receives the program instruction codes (OP-codes) and Data from the BIU, executes these
instructions and stores the results in general registers/memory or send them out as outputs through ports using
BIU. The EU has no connections to the system buses. It receives and outputs all its data through the BIU.
BIU contains
1. Segment Registers
2. Instruction Pointer
3. Instruction queue
EU contains
1. Arithmetic and Logic Unit ALU
2. General Purpose Registers
3. Index Registers
4. Pointers
5. Flag registers
1.3.2 BUS INTERFACE UNIT (BIU)
The function of BIU is to:
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
1.3.3 INSTRUCTION QUEUE
The use of this queue is to hold next six instructions to be executed in FIFO manner.
 To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from
memory.
 All six bytes are then held in first in first out 6 byte register called instruction queue.
 Then all bytes have to be given to EU one by one.
 This pre fetching operation of BIU may be in parallel with execution operation of EU, which improves
the speed execution of the instruction.
1.3.4 EXECUTION UNIT (EU)
The functions of execution unit are:
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
The EU contains the control circuitry to perform various internal operations. A decoder in EU decodes the
instruction fetched memory to generate different internal or external control signals required to perform the
operation. EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit.
1.3.5 GENERAL PURPOSE REGISTERS OF 8086
These registers can be used as 8-bit registers individually as AL-AH,BL-BH,CL-CH and DL-DH or can
be used as 16-bit in pair to have AX, BX, CX, and DX.
Note : Any Register RX can be 16 bit register, which can be used as 2 eight bit registers RL
and RH, where RL contains lower order byte of that 16 bit word and RH contains the higher order byte
of the word
AX Register: AX register is also known as accumulator register that stores operands for arithmetic operation
like divided, rotate. I/O operations and String Manipulation
BX Register: This register is mainly used as a base register. It holds the starting base location of a memory
region within a data segment. Contains a data pointer used for Based, Base indexed or Register indirect
addressing modes
CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter. Mainly
used as counter in string manipulation and shift and rotate operations
DX Register: DX register is used to contain I/O port address for I/O instruction.
It can be used as a port number in I/O operations. In 32-bit integer multiplication and division Dx contains the
higher order word of initial or resulting 64 bit number.

1.3.6 SEGMENT REGISTERS

Additional registers called segment registers generate memory address when combined with other in
the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow:

1. Code Segment (CS): It is a 16-bit register containing the address of 64KB segment with processor
instructions. The CS register is used for addressing a memory location in the Code Segment of the memory,
where the executable program is stored. The processor uses CS register for all accesses to instructions
referenced by instruction pointer (IP register). The CS register cannot be changed directly. The CS register is
automatically updated during FAR JUMP, FAR CALL and FAR RET instructions.
2. Stack Segment (SS): It is a 16-bit register containing the address of 64KB segment with program
stack. SS defined the area of memory used for the stack. By default the processor assumes that all data are
referenced by stack Pointer SP and Base pointer BP, located in stack segment. It can be directly changed by
POP instruction
3. Data Segment (DS): It is a 16-bit register containing the address of 64KB segment program data. By
default the processor assumes that all data referenced by general registers (A,B,C,D) and Index registers,
located in data segment. The DS contains most data used by program. Data are accessed in the Data
Segment by an offset address or the content of other register that holds the offset address.DS can be changed
directly using POP and LDS instructions.
4. Extra Segment (ES): It is a 16-bit register containing the address of 64KB segment with program
data. .ES is additional data segment that is used by some of the string to hold the destination data. By default
the processor assumes that DI register references the ES segment in string manipulation instructions. ES
register can be changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by prefixing instructions
with a CS,SS,DS and ES prefix

1.3.7 POINTER REGISTERS

1. Stack Pointer SP
It is a 16 bit register pointing to program stack. That is, the address in SP register corresponds to the
top of program stack.
2. Base Pointer BP
It is a 16-bit register pointing to the data in stack segment. BP register is usually used for based, based
indexed or register indirect addressing. The address in BP corresponding to the address location where the
data for program is beginning.
1.3.8 INDEX REGISTERS
1. Source Index SI
It is a 16 bit register. SI is used for indexed, based indexed and register indirect addressing modes, as
well as a source data address in string manipulation instructions.
2. Destination Index DI
It is a 16 bit register. DI is used for indexed, based indexed and register indirect addressing modes, as
well as a destination data address in string manipulation instructions.
1.3.9 INSTRUCTION POINTER (PROGRAM COUNTER)
It is a 16-bit register. The address in IP register corresponds to the physical address of the instruction
that is to be executed next. The IP register is updated by the BIU to point to the address of the next instruction.
Programs do not have direct access to IP, but during execution of a program the IP can be modified or saved
and restored from the stack.
1.3.10 FLAG REGISTER
The flag register expresses the state of the microprocessor. The register is updated automatically after
each execution cycle based on the results obtained due to processing. This allows to determine the type of the
result, and to determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they
are divided into two categories:
1. Conditional Flags
2. Control Flags

Six status flags and three conditional flags are available in flag register. Each flag is of 1 bit length. Based on
the binary value that it possess the status of MuP is assumed,
Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags
are as follows:
Overflow Flag (OF):
It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the
capacity of machine
Carry Flag (CF):
This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-
precision arithmetic.
Auxiliary Flag (AF):
If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper
nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose
flag, it is used internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF):
This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number
of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.
Zero Flag (ZF):
It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF):
In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is
negative, sign flag is set.
.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit. Control flags
are as follows:
Trap Flag (TP):
It is used for single step control. It allows user to execute one instruction of a program at a time for
debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF):
It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is
reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI
Instruction.
Direction Flag (DF):
It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower
memory address. When it is reset, the string bytes are accessed from lower memory address to higher
memory address.

1.3.11 INSTRUCTION QUEUE

It is an FIFO data structure, which contains a group of registers where 6 bytes of instruction code is
pre-fetched from the memory ahead of time. It is being done to speed up the program execution by overlapping
instruction fetch and execution. This mechanism is sometimes called PIPELINING.
If the queue is full, the BIU does not perform any bus cycle. If the BIU is not full and can store at least 2
bytes and EU does not request it to access memory, the BIU may pre-fetch instructions. If the BIU is
interrupted by EU for memory access while prefetching, the BIU first completes the fetching and then services
the EU. In case of JMP instruction, the BIU will reset the queue and begin refilling after passing new instruction
to EU.
1.3.12 ARITHMETIC AND LOGIC UNIT (ALU)
It is a 16 bit register. An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that
carries out arithmetic and logic operations on the operands in computer instruction words. In some processors,
the ALU is divided into two units, an arithmetic unit (AU) and a logic unit (LU). Some processors contain more
than one AU - for example, one for fixed-point operations and another for floating-point operations.
Typically, the ALU has direct input and output access to the processor controller, main memory
(random access memory or RAM in a personal computer), and input/output devices. Inputs and outputs flow
along an electronic path that is called a bus.
The input consists of an instruction word (sometimes called a machine instruction word) that contains
an operation code (sometimes called an "op code"), one or more operands, and sometimes a format code. The
operation code tells the ALU what operation to perform and the operands are used in the operation.
 The output consists of a result that is placed in a storage register and settings (flags) that indicate
whether the operation was performed successfully.
With ALU arithmetic operations like Addition, Subtraction, Increment, Decrement, Complement, Shifting
of numbers can be performed. Also Logical operations like AND, OR, XOR can be performed.
1.3.13 CONTROL UNIT
This unit provides the necessary timing and control information for all operation. It provides necessary
flow of control between Microprocessor, memory and peripherals at correct timing. The control unit in the EU
̅̅̅̅,WR
directs the internal operations likeRD ̅̅̅. It has an explicit control over the entire process of execution.
̅̅̅̅̅, M/IO
1.3.14 INSTRUCTION SET & ADDRESSING MODES
INSTRUCTION SET:
The following are the types of instructions that an 8086 system supports.
1. DATA TRANSFER INSTRUCTIONS – moving ,exchanging of data between registers and memory
2. ARITHMETIC INSTRUCTIONS – add, sub, increment, decrement, convert byte/word and compare.
3. LOGIC INSTRUCTIONS -- AND, OR, XOR, shift, rotate and test
4. STRING MANIPULATION INSTRUCTIONS – load, store, move, compare and scan for byte/word
5. CONTROL TRANSFER INSTRUCTIONS – conditional, unconditional, call subroutine and return from
subroutine
6. INPUT/OUTPUT INSTRUCTIONS – I/O port operations
7. OTHER INSTRUCTIONS – setting and clearing of flag bits ,stack operations, software interrupts.
ADDRESSING MODES: (The way in which data is acquired by the processor for its operation)
The term addressing modes refers to the way in which the operand of an instruction is specified. Information
contained in the instruction code is the value of the operand or the address of the result/operand. Following are
the main addressing modes that are used on various platforms and architectures. The following are the
Addressing modes that are compliance with 8086.
1. IMPLIED—The data value/address is implicitly associated with the instruction itself
2. REGISTER—References the data in a register or in a register pair
3. IMMEDIATE—the data itself is provided within the instruction
4. DIRECT—the instruction operand specifies the memory address where the data is located.
5. REGISTER INDIRECT—instruction specifies a register, containing an address, where the data is
located
6. BASED—8-bit or 16-bit instruction operand is added to the contents of a base register(BX or BP), the
resulting value is a pointer to the location where data resides.
7. INDEXED--8-bit or 16-bit instruction operand is added to the contents of an index register(SI or DI), the
resulting value is a pointer to the location where data resides.
8. BASED INDEXED --contents of base registers and index registers are added and the resulting value
corresponds to a pointer, which points to the location where data is available.
9. BASED INDEXED WITH DISPLACEMENT—an 8-bit or 16-bit instruction operand, contents of base
registers and index registers are added together and the resulting value corresponds to a pointer, which
points to the location where data is available.
1.3.15 INTERRUPTS
Interrupt is a signal to the processor emitted by hardware or software indicating an event that needs
immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of
the current code the processor is executing.
The processor responds by suspending its current activities, saving its state, and executing
a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event. This
interruption is temporary, and, after the interrupt handler finishes, the processor resumes normal activities.
There are two types of interrupts:
1. Hardware interrupts
2. Software interrupts .
 Hardware interrupts are used by devices to communicate that they require attention from the operating
system.
A software interrupt is caused either by an exceptional condition in the processor itself, or a
special instruction in the instruction set which causes an interrupt when it is executed.
The other way of classifying interrupts is based on their priority. That is, whether the interrupt is
maskable or non-maskable.
 H/W Interrupts for 8086—INTR --- (NON-MASKABLE), IRET instruction can be used to return from ISR.
 ---NMI –type 2 --- instruction code at address location 0008 H

 S/W Interrupts for 8086 are, INT instruction – breakpoint interrupt – type 3
 --- INT <interrupt number> instruction selects any interrupts among 256 types
 ---INTO –Interrupt on overflow
 ---Single-step interrupt –generated if the TF flag is set. This is a type 1 interrupt.
When the CPU processes this interrupt it clears TF flag before calling the ISR.

1.4 PIN DETAILS OF 8086

A 40 pin DIP 8086 is shown above. 8086 can operate in two modes. They are,
 Minimum mode – MN/MX ̅̅̅̅ pin (pin 33) is set (1) – Used in small systems with one CPU
 Maximum mode -- MN/MX ̅̅̅̅ pin (pin 33) is Reset (0) – Used in large systems with more than one CPU
 The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum
mode.
AD0 - AD15 (I/O): Address Data Bus
These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and
data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7.
A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the bus in memory or I/O
operations. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select
functions. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold
acknowledge".
A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status
During T1 state these lines are the four most significant address lines for memory operations. During
I/O operations these lines are low. During memory and I/O operations, status information is available on these
lines during T2, T3, and T4 states.S5: The status of the interrupt enable flag bit is updated at the beginning of
each cycle. The status of the flag is indicated through this bus.
S6:
When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the
8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus.
S3 & S4:
Lines are decoded as follows:
A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which
segment register generates the segment portion of the 8086 address. Thus by decoding these lines and using
the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega per segment) of memory
can be accesses. This feature also provides a degree of protection by preventing write operations to one
segment from erroneously overlapping into another segment and destroying information in that segment.
BHE /S7 (O): Bus High Enable/Status
During T1 state the BHE should be used to enable data onto the most significant half of the data bus,
pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control
chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte
is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4
states. The signal is active Low and floats to 3-state during "hold" state. This pin is Low during T1 state for the
first interrupt acknowledge cycle.
RD (O): READ
The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is
active low during T2 and T3 states and the Tw states of any read cycle. This signal floats to tri-state in hold
acknowledge cycle".
TEST (I)
TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues.
Otherwise the processor waits in an "idle" state. This input is synchronized internally during each clock cycle
on the leading edge of CLK.
INTR (I): Interrupt Request
It is a level triggered input which is sampled during the last clock cycle of each instruction to determine
if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an
interrupt vector look up table located in system memory. It can be internally masked by software resetting the
interrupt enable bit INTR is internally synchronized. This signal is active HIGH.
NMI (I): Non-Maskable Interrupt
An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector
look up table located in system memory.NMI is not maskable internally by software. A transition from a LOW to
HIGH on this pin initiates the interrupt at the end of the current instruction. This input is internally
synchronized.
Reset (I)
Reset causes the processor to immediately terminate its present activity. To be recognized, the signal
must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse.
It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes CS to FFFF H.
Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next instruction from the 20 bit
physical address FFFF0H. The reset signal to 8086 can be generated by the 8284. (Clock generation chip). To
guarantee reset from power-up, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has
reached the minimum supply voltage of 4.5V.
Ready (I)
Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data
transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY.
This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if
the setup and hold times are not met.
CLK (I): Clock
Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty
cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the design of 8086
processors incorporates dynamic cells. The maximum clock frequencies of the 8086-4, 8086 and 8086-2
are4MHz, 5MHz and 8MHz respectively.
Since the 8086 does not have on-chip clock generation circuitry, and 8284 clock generator chip must
be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3 times the 8086
internal frequency. The 8284 clock generation chip is used to generate READY, RESET and CLK.
MN/MX (I): Maximum / Minimum
This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all
the bus control signals.
Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode; MN/
MX = 1. The corresponding 8 pins function descriptions for maximum mode is explained later.
M/IO (O): Status line
This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it accesses
I/O and when high it access memory. M / IO become valid in the T4 state preceding a bus cycle and remain
valid until the final T4 of the cycle. M/IO floats to 3 - state OFF during local bus "hold acknowledge".
WR (O): Write
Indicates that the processor is performing a write memory or write IO cycle, depending on the state of
the M /IO signal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW, and floats to 3-state OFF
during local bus "hold acknowledge ".
INTA (O): Interrupt Acknowledge
It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and T4 of
each interrupt acknowledge cycle.
ALE (O): Address Latch Enable
ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active
high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive
In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction
of data flow through the transceiver. This signal floats to tri-state off during local bus "hold acknowledge".
DEN (O): Data Enable
It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver.
DEN is active LOW during each memory and IO access. It will be low beginning with T2 until the middle of T4,
while for a write cycle, it is active from the beginning of T2 until the middle of T4. It floats to tri-state off during
local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge
Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must
be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as an acknowledgement
in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus
and control lines.
After "HOLD" is detected as being Low, the processor will lower the HLDA and when the processor
needs to run another cycle, it will again drive the local bus and control lines. Maximum Mode The following
pins function descriptions are for the 8086/8088 systems in maximum mode (i.e.. MN/MX = 0). Only the pins
which are unique to maximum mode are described below.
S2, S1, S0 (O): Status Pins
These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or
Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O
operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning of a
bus cycle. These status lines are encoded as shown in table.
S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive State

QS0, QS1 (O): Queue – Status

Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1
provide status to allow external tracking of the internal 8086 instruction queue. The condition of queue status is
shown in table. Queue status allows external devices like In-circuit Emulators or special instruction set
extension co-processors to track the CPU instruction execution. Since instructions are executed from the 8086
internal queue, the queue status is presented each CPU clock cycle and is not related to the bus cycle activity.
This mechanism allows (1) A processor to detect execution of a ESCAPE instruction which directs the co-
processor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory
location.
QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

LOCK (O)
It indicates to another system bus master, not to gain control of the system bus while LOCK is active
Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of
the instruction. This signal is active Low and floats to tri-state OFF during 'hold acknowledge'.
RQ/GT0 and RQ/GT1 (I/O): Request/Grant
These pins are used by other processors in a multi-processor organization. Local bus masters of other
processors force the processor to release the local bus at the end of the processors current bus cycle. Each
pin is bi-directional and has an internal pull up resistors. Hence they may be left un-connected.

1.5 ADDRESSING MODES OF 8086

The set of mechanisms by which an instruction can specify how to obtain its operands is known as
Addressing modes. The CPU can access the operands (data) in a number of different modes.
The addressing modes available in Intel 8086 are:
1. Register Addressing Mode
2. Immediate Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Base Addressing mode
6. Indexed Addressing Mode
7. Based Indexed Addressing mode
8. String addressing Mode
9. I/O port Addressing Mode
10. Relative Addressing Mode
11. Implied Addressing Mode
Register Addressing Mode:
With the Register Addressing mode the operand to be accessed is specified as residing in an internal
register of the 8086.Both source and destination operands are internal registers of the processor. the operand
sizes must match.
Example: MOV AX , BX
This stands for move the contents of BX (the source operand) to AX (the destination operand).Both the
source and the destination operands have been specified as the contents of internal registers of the 8086.

Immediate Addressing Mode:

The data operand is supplied as a part of the instruction. The immediate operand can only be a
source.If a source operand is part of the instruction instead of the contents of a register or memory location, it
represents what is called the immediate operand and is accessed using immediate addressing mode. Typically
immediate operand represents constant data. Immediate operands can be either a byte or word of data.
Example: MOV AL , 015H
In this instruction the operand 015H is an example of a byte wide immediate source operand. The
destination operand, which consists of the contents of AL, uses register addressing. Thus this instruction
employs both immediate and registers addressing modes.
Direct Addressing Mode :
Direct addressing differs from immediate addressing, that the locations following the instruction op-code
hold an effective memory address (EA). This effective address is a 16-bit offset of the storage location of the
operand from the current value in the data segment (DS) register .EA is combined with the contents of DS in
the BIU to produce the physical address of the operand.
In this mode the 16 bit effective address (EA) is taken directly from the displacement field of instruction.
This EA or Displacement is the distance of the memory location from the current value of the Data segment
(DS) register in which the data is stored. The BIU shifts the [DS] four times to the left and adds the EA to
generate the 20 bit physical address.
Example: MOV CX , BETA
This stands for move the contents of the memory location, which is offset by BETA from the current
value in DS into internal register CX.
 MOV [0040 H], DL
This stands for move the contents of the lower order byte of DX register, into an effective address
location obtained by offsetting the values with DS. Contents of DL are moved to a 20 bit address location
formed by shift and add method explained below.

Register Indirect Addressing Mode:

Register indirect addressing is similar to direct addressing, that an effective address is combined with
the contents of DS to obtain a physical address. However it differs in a way that the offset is specified. Here EA
resides in either a pointer register or an index register within the 8086.The pointer register can be either a base
register BX or a base pointer register BP and the index register can be source index register SI or the
destination index register DI.
Example MOV AX , [SI]
This instruction moves the contents of the memory location offset by the value of EA in SI from the current
value in DS to
the AX register.
Based Addressing Mode:
In the based addressing mode, the physical address of the operand is obtained by adding a direct or indirect
displacement of
the contents of either base register BX or base pointer register BP and the current value in DS and SS
respectively.
Example MOV [BX] . BETA , AL
This instruction uses base register BX and direct displacement BETA to derive the EA of the destination
operand. The
based addressing mode is implemented by specifying the base register in the brackets followed by a period
and direct
displacement .The source operand is located in the byte accumulator AL.
Indexed Addressing Mode:
Indexed addressing mode works identically to the based addressing but it uses the contents of the index
registers instead of
BX or BP, in the generation of the physical address.
Example MOV AL , ARRAY [SI]
The source operand has been specified using direct index addressing. The notation this time is such ARRAY,
which is a
direct displacement, prefixes the selected index register, SI.
Based Indexed Addressing Mode:
Combining the based addressing mode and the indexed addressing mode together results in a new, more
powerful mode
known as based indexed addressing.
Example: MOV AH , [BX] . BETA [SI]
Here the source operand is accessed using the based indexed addressing mode. The effective address of the
source operand
is obtained as EA=(BX)+BETA+(SI)