NTHS5404

Power MOSFET
20 V, 7.2 A, N−Channel ChipFET

Features
• Low RDS(on) for Higher Efficiency http://onsemi.com
• Logic Level Gate Drive
• Miniature ChipFET Surface Mount Package Saves Board Space
V(BR)DSS RDS(on) TYP ID MAX
• Pb−Free Package is Available
20 V 25 m
@ 4.5 V 7.2 A
Applications
• Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards D

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Steady
G
Rating Symbol 5 Secs State Unit
Drain−Source Voltage VDS 20 V
S
Gate−Source Voltage VGS
12 V N−Channel MOSFET
Continuous Drain Current ID A
(TJ = 150°C) (Note 1)
TA = 25°C 7.2 5.2
ChipFET
TA = 85°C 5.2 3.8
CASE 1206A
Pulsed Drain Current IDM
20 A STYLE 1

Continuous Source Current IS 7.2 5.2 A

(Diode Conduction) (Note 1)
PIN MARKING
Maximum Power Dissipation PD W CONNECTIONS DIAGRAM
(Note 1)
TA = 25°C 2.5 1.3
1.3 0.7 D 8 1 D 1 8
TA = 85°C
Operating Junction and Storage TJ, Tstg −55 to +150 °C D 7 2 D 2
A2 M
7
Temperature Range
D 6 3 D 3 6
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not S 5 4 G 4 5
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
A2 = Specific Device Code
1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
M = Month Code
[1 oz] including traces).

ORDERING INFORMATION

Device Package Shipping†

NTHS5404T1 ChipFET 3000/Tape & Reel

NTHS5404T1G ChipFET 3000/Tape & Reel

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

 Semiconductor Components Industries, LLC, 2005 1 Publication Order Number:

February, 2005 − Rev. 4 NTHS5404T1/D
 NTHS5404

THERMAL CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Maximum Junction−to−Ambient (Note 2) RJA °C/W
t  5 sec 40 50
Steady State 80 95

Maximum Junction−to−Foot (Drain) RJF 15 20 °C/W

Steady State

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 0.6 − − V
Gate−Body Leakage IGSS VDS = 0 V, VGS =
12 V − −
100 nA
Zero Gate Voltage Drain Current IDSS VDS = 16 V, VGS = 0 V − − 1.0 A
VDS = 16 V, VGS = 0 V, − − 5.0
TJ = 85°C

On−State Drain Current (Note 3) ID(on) VDS  5.0 V, VGS = 4.5 V 20 − − A

Drain−Source On−State Resistance (Note 3) rDS(on)
( ) VGS = 4.5 V, ID = 5.2 A − 0.025 0.030

VGS = 2.5 V, ID = 4.3 A − 0.038 0.045
Forward Transconductance (Note 3) gfs VDS = 10 V, ID = 5.2 A − 20 − S
Dynamic (Note 4)
Total Gate Charge QG − 12 18 nC
Gate−Source Charge QGS VDS = 10 V, VGS = 4.5 V, − 2.4 −
ID = 5.2 A
Gate−Drain Charge QGD − 3.2 −
Turn−On Delay Time td(on) − 8.0 15 ns
Rise Time tr VDD = 10 V, RL = 10
− 7.0 15
ID  1.0
1 0 A,
A VGEN = 4 4.5
5VV,
Turn−Off Delay Time td(off) RG = 6
− 50 60
Fall Time tf − 28 40

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage (Note 3) VSD VGS = 0 V, IS = 5.2 A − 0.8 1.2 V
Reverse Recovery Time trr − 20.9 − ns
Charge Time ta VGS = 0 V, IS = 5.2 A, − 10.2 −
Discharge Time tb diS/dt = 100 A/s − 10.6 −
Reverse Recovery Time Qrr − 11 − nC
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width  300 s, Duty Cycle  2%.
4. Guaranteed by design, not subject to production testing.

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 NTHS5404

TYPICAL ELECTRICAL CHARACTERISTICS

12 12
5V 2V 1.8 V

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

10 10
VGS = 2 V − 5 V TJ = 25°C
8 8
1.6 V
6 6

4 4
1.4 V 125°C
2 2 25°C
VGS = 1.2 V TC = −55°C
0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (
)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (
)

0.06 0.040
TJ = 25°C
ID = 5.2 A 0.038
0.05
TJ = 25°C
0.036
0.04 VGS = 2.5 V
0.034

0.03 0.032

0.030
0.02 VGS = 4.5 V
0.028
0.01 VGS = 6 V
0.026
0 0.024
0 1 2 3 4 5 2 3 4 5 6 7 8 9 10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current

Gate−to−Source Voltage and Gate Voltage

1.6 1E−05
ID = 5.2 A
VGS = 0 V
VGS = 4.5 V
RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE

1.4
IDSS, LEAKAGE (AMPS)

1E−06
1.2

TJ = 150°C
1
1E−07
TJ = 100°C
0.8

0.6 1E−08
−50 −25 0 25 50 75 100 125 150 0 4 8 12 16 20
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current

Temperature versus Voltage

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 NTHS5404

TYPICAL ELECTRICAL CHARACTERISTICS

5 11

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

VDS = 0 V VGS = 0 V QG

VGS, GATE−TO−SOURCE VOLTAGE

10
1800 Ciss
TJ = 25°C 9
4
C, CAPACITANCE (pF)

1500 8
7
Crss 3
1200 6

(V)
5
900 2 QGD QGS 4
600 ID = 5.2 A 3
1 TJ = 25°C
Coss 2
300 QGD/QGS = 1.33
1
0 0 0
12 8 4 0 4 8 12 16 20 0 1 2 3 4 5 6 7 8 9 10 11 12
VGS VDS
QG, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Figure 7. Capacitance Variation Drain−to−Source Voltage versus Total Charge

100 IS, SOURCE CURRENT (AMPS) 5

td(off)
4 VGS = 0 V
tf TJ = 25°C
t, TIME (ns)

3
10 td(on)

2
tr

VDD = 10 V
1
ID = +1.0 A
VGS = 4.5 V
1 0
1 10 100 0 0.2 0.4 0.6 0.8
RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage versus
versus Gate Resistance Current

1
NORMALIZED EFFECTIVE TRANSIENT

Duty Cycle = 0.5

THERMAL IMPEDANCE

0.2

0.1 PDM PER UNIT BASE = RJA = 80°C/W

0.1 TJM − TA = PDMZJA(t)
0.05 SURFACE MOUNTED

t1
0.02
t2
DUTY CYCLE, D = t1/t2
Single Pulse
0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
SQUARE WAVE PULSE DURATION (sec)
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient

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 NTHS5404

SOLDERING FOOTPRINT*
2.032 2.032
0.08 0.08

0.457
0.018
0.635
0.025
1.727
0.068

0.457 0.178
0.018 0.007
0.711 0.711
0.028 0.028
0.66 0.66
0.026 0.026
Figure 12. Basic Figure 13. Style 1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.

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 NTHS5404

PACKAGE DIMENSIONS

ChipFET
CASE 1206A−03
NOTES:
ISSUE E 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
A M 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
8 7 6 5 K HORIZONTAL AND VERTICAL SHALL NOT EXCEED
5 6 7 8 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
S B BURRS.
4 3 2 1 6. NO MOLD FLASH ALLOWED ON THE TOP AND
1 2 3 4 BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
L D J MILLIMETERS INCHES
G DIM MIN MAX MIN MAX
A 2.95 3.10 0.116 0.122
B 1.55 1.70 0.061 0.067
C 1.00 1.10 0.039 0.043
D 0.25 0.35 0.010 0.014
G 0.65 BSC 0.025 BSC
J 0.10 0.20 0.004 0.008
C K 0.28 0.42 0.011 0.017
L 0.55 BSC 0.022 BSC
0.05 (0.002) M 5 ° NOM 5 ° NOM
S 1.80 2.00 0.072 0.080
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN

ChipFET is a trademark of Vishay Siliconix.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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