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ANSI/ TIA/ EIA-6 12 1993
APPROVED: November 2, 1993
TIAJEIA
STANDARD
TIAIEIA-612
DECEMBER 1993
NOTICE
W E I A Engineering Standards and Publications are designed to serve the public interest
through eliminating misunderstandings between manufacturers and purchasers, facilitating
interchangeability and improvement of products, and assisting the purchaser in selecting and
obtaining with minimum delay the proper product for his particular need. Existence of such
Standards and Publications shaU not in any respect preclude any member or nonmember of
TIAíEIA from manufacturing or seliing products not conforming to such Standards and
Publications, nor shall the existence of such Standards and Publications preclude their voluntary
use by those other than W E I A members, whether the standard is to be used either
domestically or internationally.
Recommended Standards and Publications are adopted by TINEIA in accordance with the
American National Standards Institute (ANSI)patent policy. By such action, W E I A does not
assume any liability to any patent owner, nor does it assume any obligation whatever to parties
adopting the Recommended Standard or Publication.
This Standard does not purport to address all safety problems associated with its use or ail
applicable regulatory requirements. It is the responsibility of the user of this Standard to
establish appropriate safety and health practices and to determine the applicability of regulatory
limitations before its use.
Published by
Contents Page
1 SCOPE ..................................................................................................................1
2 APPLICABILITY................................................................................................... 2
3 ELECTRICAL CHARACTERISTICS................................................................. 3
3.1 Generator Characteristics............................................................................3
3.1.1 Open Circuit Measurement ................................................................... 4
3.1.2 Test Termination Measurements........................................................... 5
3.1.3 Short Circuit Measurement .................................................................... 5
3.1.4 Output Signal Waveform ........................................................................ 6
Annex A (informative)................................................................................................... 12
A .1 Interconnecting Cable ................................................................................ 12
A.l.l Length ...................................................................................................... 12
A.1.2 Cable Physical Characteristics ..........................................................12
A.1.3 Cable Termination ................................................................................. 12
A.2 ECL Generators and Receivers................................................................13
A.2.1 ECL - Emitter Coupled Logic Technology ........................................13
A.2.2 Failsafe Biasing of Receivers ............................................................. 13
a References.................................................................................................... 14
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FOREWORD
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ANSI/TIA/EIA-612-1993
1 SCOPE
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ANSI/TIA/EIA-612-1993
2 APPLICABILITY
The provisions of this Standard may be applied to the circuits employed at the
interface between equipments where information being conveyed is in the form
of binary signals.
Typical points of applicability for this Standard are depicted in figure 1.
D D
T C
E E
Id L
Legend:
E = Interface Generator
@ = Interface Receiver
-
- = Balanced Interface Circuit
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Figure 1 Applications of balanced digital interface circuit
The balanced digital interface circuit will normally be utilized on data and
timing, or control circuits where the data signaling rate is up to a maximum limit
of 52 Mbiîís.
data signaling rate, expressed in the units bit/s (bits per second), is the
significant parameter. It may be different from the equipment's data transfer
rate, which employs the same units. Data signaling rate is defined as 1/T
where T is the minimum interval between two significant instants. In a binary
system for which this Standard is designed, the data signaling rate in bitk and
the modulation rate in bauds are numerically equal when the unit interval used
in each determination is the minimum interval.
star (*) represents the opposite input condition for a parameter. For example,
the symbol Q represents the receiver output state for one input condition, while
Q' represents the output state for the opposite input state.
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ANSITTINEIA-612-1993
3 ELECTRICAL CHARACTERISTICS
The balanced digital interface circuit is shown in figure 2. The circuit consists
of three parts: the generator (G), the balanced interconnecting cable, and the
load. The load is composed of a receiver (R) and a cable termination/faiIsafe
network. The electrical Characteristics of the generator and receiver are
specified in terms of direct electrical measurements while the interconnecting
cable is described in terms of its electrical characteristics.
1
Rt =
110 R
B
755- B'
Q
Rrp =
1.5 k(l
Vee
I I
Legend:
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Figure 2 Balanced digital interface circuit
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ANSITTINEIA-612-1993
NOTE -, The sense of data binary O (SPACE) and data binary 1 (MARK)
are inverted from that specified in ElMIA-422-A.
The logic function of the generator and the receiver is beyond the scope of this
Standard, and therefore is not defined.
I
Vee
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Figure 3 Open circuit measurement
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ANSITTINEIA-612-1993
With a test load of the resistors shown in figure 4, the magnitude of the
differential output voltage (Vt), shall be 590 mV or greater. For the opposite
binary state, the polarity of Vt shall be reversed (Vt*). The magnitude of the
difference between Vt and Vt' shall be less than 100 mV. The magnitude of the
generator offset voltage (Vos), measured between the center point of the test
load and the generator circuit common shall be -1.6 V or more positive for
either binary state. The magnitude of the difference of Vos for one binary state
and Vos' for the opposite binary state shall be 1O0 mV or less.
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Figure 4 Test termination measurements
Vee
-
Figure 5 Short-circuit measurement
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ANSI/TIA/EIA-612-1993
Legend: Vee
t b = Time duration of the unit interval
at the applicable data signaling rate.
0.5 ns 5 tr or tf 22.3 ns
Vss = Difference in the steady
state voltages
vss = 1 Vt - Vt* I
Vee
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Figure 6 Output signal waveform
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ANSITTINEIA-612-1993
With the voltage Via (or Vib) ranging from -0.5 V to -2.0 V while Vib (or Via) is
held at -1.32 V, the resultant input current lia (or lib) shall be no greater than
350 PA. These measurements apply with the receiver's power supply(s) in
both power-on and power-off conditions (as defined by the Integrated Circuit
manufacturer). Note that these measurements are made with any termination
resistor or failsafe provision disconnected.
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Figure 7 Receiver input current-voltage measurements
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ANSITTINEIA-612-1993
....
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Figure 8 Input sensitivity measurements
A'
I
d
to
= Measured Parameter
= Applied Voltage
B'
Note:
C' Vcrn = (Via + Vib)M,
Vid = IVia - Vibl
Applied Voltages
Resulting
Input
Voltage
Resulting
Common
Mode Voltage
I
Via I Vib Vid Vcrn
-0.50 V -0.65 V +150 mV -0.57 V
-0.65 V -0.50 V -150 mV -0.57 V
I -1.85 V
-2.00 V
-2.00 V
-1.85 V
+150 mV
-150 mV
-1.92 V
-1.92 V
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Figure 9 Receiver input sensitivity table
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ANSITTINEIA-612-1993
The cable shall consist of 25 twisted pairs of conductors of 28 AWG. The cable
has an overall foil/braid shield which serves the purpose of a signal shield.
The two wires of each pair shall be connected to the same signal, one to the
NA' and the other to the B/B' signal pins.
Maximum DC Resistance
(DCR) at 20 OC 3.5 n
Differential Impedance at 50 MHz 110 alt 11R
Maximum Signal Attenuation
at 50 MHz 4.5 dB
Mutual Capacitance within pair
at 1 kHz 47.6 56.5 pF/m (14.5 i 2.0 pF/ft)
Propagation Delay
maximum: 79 ns
skew (pair to pair) 2.0 ns
4 ENVIRONMENTAL CONSTRAINTS
b. The input voltage at the receiver is between -0.5 V and -2.0 V with
respect to receiver circuit common.
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5 CIRCUIT PROTECTION
Balanced digital interface generator and receiver devices, under either the
power-on or power-off condition, complying to this Standard shall not be
damaged under the following conditions:
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ANSI/TIA/EIA-612-1993 A
ANNEX A (Informative)
a
GUIDELINES FOR APPLICATION
A.l Interconnecting Cable
The following section provides further information to Section 3.3 and is
additional guidance concerning operational constraints imposed by the cable
parameters of length and termination.
A.1.1 Length
The nominal length of cable separating the generator and the load is 15 meters
(50 ft).
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Emitter Coupled Logic (ECL) families such as l O K , 10H, and 100K have been
developed that meet the requirements of this Standard by a number of
Integrated Circuit manufacturers. The 1OOK family is compensated for both
Power Supply Voltage and Operating Temperature variations, offering constant
thresholds and output levels over both ranges. Some other families are only
Power-Supply-Voltage-compensated. The 1OOK family also accepts a wide
range of power supply voltages (Vee) from -4.2 V to -5.7 V.
External resistors can be used to bias the receiver's input into a known state
(2150 mV differential) for the case of the disconnected cable. For example, a
1.5 kn pull up and pull down resistor will bias the receiver to 177 mV,defaulting
the receiver to a OFF state.
Vee
I
1.5 k@
A' .L
o
B'
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ANSITTINEIA-612-1993
ANNEX B (informative)
e
REFERENCES
ANSIíTIA/EIA-613-1993, High Speed Serial Intedace for Data Terminai
Equipment and Data Circuit-Terminating Equipment
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