Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:9

Topic Covered: TTL Logic gate characteristics .

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:10

Topic Covered: Open Collector.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:11

Topic Covered: Three State.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:12

Topic Covered: TTL Subfamilies.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:13

Topic Covered: MOS & CMOS logic families.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:14

Topic Covered: Realization of logic families in RTL, DTL, ECL, C MOS, and MOSFET.
.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)

Name of faculty: Yogesh Kumar

Subject: Digital Electronics Subject Code: 3EE3

Semester: III Session: 2017-18

Branch: EE

Date of submission: 13/11/17

Total no. of pages: 4

UNIT No.: 2 Lecture No:15

Topic Covered: Interfacing logic families to one another.

References:

[1]. M Morris Mano: Digital Logic and Computer Design, (2007).

[2]. R.P Jain: Digital Electronics, Tata Mc Gra Hill, (2006).

[3]. K.M Jaswal : Digital Electronics, Dhanpat Rai, (2013).

Faculty HOD Dean (Academics)