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 Introduction to SPI Protocol

 SPI Pins
 SPI Clock
 SPI Master Slave Connection
 MSP430 SPI
 SPI Registers
 Digital To Analog Convertor
 DAC Specifications
 DAC (LTC1661 -- SPI based) Interfacing to MSP430


The Serial Peripheral Interface or SPI-bus is a simple 4-wire serial communications interface used by
many microprocessor/microcontroller peripheral chips that enables the controllers and peripheral devices
to communicate each other. Even though it is developed primarily for the communication between host
processor and peripherals, a connection of two processors via SPI is just as well possible.
The SPI bus, which operates at full duplex can support up to 10Mbps of speed. The SPI Bus is usually
used only on the PCB. There are many facts, which prevent us from using it outside the PCB area. The SPI
Bus was designed to transfer data between various IC chips, at very high speeds. Due to this high-speed
aspect, the bus lines cannot be too long, because their reactance increases too much, and the Bus becomes
unusable. However, it is possible to use the SPI Bus outside the PCB at low speeds, but this is not quite

SPI uses 4 signal lines

a) Master Out Slave In (MOSI) - MOSI signal is generated by Master, recipient is the Slave.
b) Master In Slave Out (MISO) - Slaves generate MISO signals and recipient is the Master.
c) Serial Clock (SCLK or SCK) - SCLK signal is generated by the Master to synchronize data transfers
between the master and the slave.
d) Slave Select (SS) from master to Chip Select (CS) of slave - SS signal is generated by Master to select
individual slave/peripheral devices. The SS/CS is an active low signal.
Among these four logic signals, two of them MOSI & MISO can be grouped as data lines and other
two SS & SCLK as control lines.

The communication is initiated by the master all the time. The master first configures the clock, using a
frequency, which is less than or equal to the maximum frequency that the slave device supports. The
master then select the desired slave for communication by pulling the chip select (SS) line of that
particular slave-peripheral to "low" state. Master selects only one slave at a time. The slaves which have
not been selected will disregard the input clock and MOSI signals from the master, and must not drive

The communication between master and slave is full duplex. When the master sends a bit on the MOSI
line; the slave reads it from that same line and the slave sends a bit on the MISO line; the master reads it
from that same line. Master and slave exchange their register values.
There is a "multiple byte stream mode" available with SPI bus interface. In this mode the master can shift
bytes continuously. In this case, the slave select (SS) is kept low until all stream process gets finished.


SPI is a synchronous protocol and in addition to setting the clock frequency, the master must also
configure the clock polarity (CPOL) and phase (CPHA) with respect to the data. Clock polarity (CPOL)
and clock phase (CPHA) determine the edges of the clock signal on which the data are driven and
sampled. Based on CPOL and CPHA, there are four modes of operation.

a) Inverted Clock Polarity (CPOL = 0) ,Leading Clock Phase (CPHA = 0)

b) Non Inverted Clock Polarity (CPOL = 1) ,Leading Clock Phase (CPHA = 0)
c) Inverted Clock Polarity (CPOL = 0) ,Trailing Clock Phase (CPHA = 1)
d) Non Inverted Clock Polarity (CPOL = 1) ,Trailing Clock Phase (CPHA = 1)
SPI Master Slave connection

 All the clock lines (SCLK) are connected together

 All the MISO data lines are connected together
 All the MOSI data lines are connected together
 But the Chip Select (CS) pin from each peripheral must be connected to a separate Slave Select
(SS) pin on the master-microcontroller.


MSP430 has a built in module called USCI (Universal Serial Communications Interface) for serial data
communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4
pin) and I2C, and asynchronous communication protocols such as UART and enhanced UART.
Different USCI modules support different modes. Each different USCI module is named with a different
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

The MSP430G2553 has two SPI interfaces, mapped with the following pins:

Pin Name USCI_A0 USCI_B0 Description

SIMO P1.2 P1.7 Slave in Master Out
SOMI P1.1 P1.6 Slave out Master In
SCLK P1.4 P1.5 Clock
STE P1.5 P1.4 Slave Transmit Enable

1) UCBxCTL0 Register
This is the USCI module B (USCI_Bx) Control Register 0

2) UCBxCTL1 Register
This is the USCI module B (USCI_Bx) Control Register 1

When the USCI module is enabled by clearing the UCSWRST bit, it is ready to receive and
3) UCBxBR0 Register & UCBxBR1Register
This register holds the bit rate prescaler value. The 16-bit value of UCBRx in the bit rate control
registers (UCxxBR1 and UCxxBR0) is the division factor of the USCI clock source, BRCLK.

4) UCBxRXBUF Register
This is the USCI module B (USCI_Bx) Receive Buffer Register.

5) UCBxTXBUF Register
This is the USCI module B (USCI_Bx) Transmit Buffer Register.In master mode, writing to
UCxTXBUF activates the bit clock generator, and the data begins to transmit.

6) UCBxIFG Register
This is the USCI module B (USCI_Bx )Interrupt Flag Register.

Digital to Analog Conversion

A converter which converts a digital signal into analog signal is called DAC.A DAC converts a song
stored in binary form into an audio signal.

The reference voltage applied to DAC is also the maximum voltage the DAC can provide.


1) Resolution
In selecting a DAC, the first step is to determine the necessary resolution.The resolution of a DAC
is the smallest change in the output of the DAC for any change in digital input.i.e. if a input to
DAC changes one bit, how much analog output has changed in full scale deflection.
In a 10bit DAC,
Step size = ( 210 - 1)
Resolution = (1 / step size) * Vref voltage

2) Accuracy

Accuracy is a comparison of the actual output of a DAC with the expected output. It is expressed
as a percentage of a full-scale, or maximum, output voltage. For example, if a converter has a full-scale
output of 10V and the accuracy is ±0.1 %, then the maximum deviation is 10 V * 0.001 =10 mV.

3) Conversion speed
The conversion speed of the DAC is output analog value settling time period for a change in the
digital input. This is also called settling time period of DAC. Normally it will be micro seconds and in
some advanced micro controller DAC it may be nano seconds.

4) Linearity
An ideal DAC output should vary linearly with the input. A linear error is a deviation from the ideal
straight-line output of a DAC.

5) Monotonicity
The Digital to Analog Converter is said to be monotonic if its analog value is either increasing or
equal to previous value for an LSB change in input digital signal i.e it does not take any reverse steps
when it is sequenced over its entire range of input bits.

1) R2R
2) Binary Weighted ladder

MSP430 Connection To LTC1661

LTC1661 is a 10bit DAC.It integrates two DACs.The DAC communicates with the controller using SPI
protocol. The DAC is of binary weighted type.

Pin Number Description

1 chip select
2 Serial clock
3 Serial Data in
4 DAC Reference voltage
5 DAC analog voltage
6 Supply voltage
7 Ground
8 DAC analog voltage

Connections :-

ADC_CS -- P1.4
SPI_SCLK -- P1.5
MOSI_PIN -- P1.7 TX pin

The output voltage is given by:-

Vout = (K *Vref ) / 1024.Where K is the DAC input value.

Where INPUT CODE is the DAC input binary value.

Control Code selects the two outputs.
1001  DAC A
1010  DAC B