Beruflich Dokumente
Kultur Dokumente
2017 2018
VLSI
PROJECT PROJECT TITLE YEAR
CODE
SPVL05 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field 2017
Multiplier Using Factoring Technique
SPVL07 Low Complexity and Critical Path based VLSI Architecture for LMS 2017
Adaptive Filter using Distributed Arithmetic Algorithm and Architecture
Design of Adaptive Filters With Error Nonlinearities
SPVL09 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in 2017
the Presence of Process Variations
SPVL13 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression 2017
SPVL16 Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET 2017
Technology for Low-Voltage Operation
SPVL17 A1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130- 2017
nm CMOS
SPVL18 Hybrid LUT/Multiplexer FPGA Logic Architectures 2017
SPVL23 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for 2017
DLL Based Clock Generator
SPVL24 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data 2017
Streams for MIMO
SPVL25 A High Throughput List Decoder Architecture for Polar Codes 2017
SPVL32 Graph-Based Transistor Network Generation Method for Super gate Design 2017
SPVL38 A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for 2017
NAND-Flash Memory
SPVL39 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for 2017
MIMO Receivers
SPVL40 One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked 2017
Elements
SPVL41 Algorithm and Architecture of Configurable Joint Detection and Decoding 2017
for MIMO Wireless Communications with Convolution Codes
SPVL42 A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT 2017
SPVL46 A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and 2017
Frequency Scaling
SPVL47 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a 2017
Wide Range of Supply Voltage Levels
SPVL48 A High-Speed FPGA Implementation of an RSD-Based ECC Processor 2017
SPVL49 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units 2017
SPVL62 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its 2017
Application
SPVL63 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM 2017
Cell
LOW POWER 2017
SPVL64 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter 2017
Based on Delay Wrapping and Averaging
SPVL65 Coordinate Rotation-Based Low Complexity K-Means Clustering 2017
Architecture
SPVL66 Low-Power Scan-Based Built-In Self-Test Based on Weighted 2017
Pseudorandom Test Pattern Generation and Reseeding.
SPVL67 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture 2017
for Low-Energy Consumption.
SPVL70 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori 2017
Benchmarked on FPGA
SPVL71 High-Throughput and Energy-Efficient Belief Propagation Polar Code 2017
Decoder
SPVL72 High-Speed Parallel LFSR Architectures Based on Improved State-Space 2017
Transformations
SPVL73 Scalable Approach for Power Droop Reduction During Scan-Based Logic 2017
BIST
SPVL74 Stochastic Implementation and Analysis of Dynamical Systems Similar to 2017
the Logistic Map
SPVL75 Efficient Designs of Multi-ported Memory on FPGA 2017
SPVL83 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant 2017
Binary Encoding
SPVL93 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation 2017
for 8k Ultra-HD TV Encoding
SPVL94 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High- 2017
Speed yet Energy-Efficient Digital Signal Processing
SPVL95 Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations 2017
SPVL98 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in 2017
the Presence of Process Variations
SPVL99 Time-Encoded Values for Highly Efficient Stochastic Circuits 2017
VERIFICATION 2017
SPVL110 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply 2017
Applications
SPVL111 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock 2017
Generation Circuits in 130-nm CMOS
SPVL112 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application 2017
SPVL115 A Fault Tolerance Technique for Combinational Circuits Based on Selective 2017
Transistor Redundancy
SPVL116 Preweighted Linearized VCO Analog-to-Digital Converter 2017