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PCD8544
48 × 84 pixels matrix LCD
controller/driver
Product specification 1999 Apr 12
File under Integrated Circuits, IC17
Philips Semiconductors Product specification
CONTENTS 8 INSTRUCTIONS
8.1 Initialization
1 FEATURES
8.2 Reset function
2 GENERAL DESCRIPTION 8.3 Function set
3 APPLICATIONS 8.3.1 Bit PD
8.3.2 Bit V
4 ORDERING INFORMATION
8.3.3 Bit H
5 BLOCK DIAGRAM 8.4 Display control
6 PINNING 8.4.1 Bits D and E
6.1 Pin functions 8.5 Set Y address of RAM
6.1.1 R0 to R47 row driver outputs 8.6 Set X address of RAM
6.1.2 C0 to C83 column driver outputs 8.7 Temperature control
6.1.3 VSS1, VSS2: negative power supply rails 8.8 Bias value
6.1.4 VDD1, VDD2: positive power supply rails 8.9 Set VOP value
6.1.5 VLCD1, VLCD2: LCD power supply 9 LIMITING VALUES
6.1.6 T1, T2, T3 and T4: test pads 10 HANDLING
6.1.7 SDIN: serial data line
6.1.8 SCLK: serial clock line 11 DC CHARACTERISTICS
6.1.9 D/C: mode select 12 AC CHARACTERISTICS
6.1.10 SCE: chip enable 12.1 Serial interface
6.1.11 OSC: oscillator 12.2 Reset
6.1.12 RES: reset
13 APPLICATION INFORMATION
7 FUNCTIONAL DESCRIPTION
14 BONDING PAD LOCATIONS
7.1 Oscillator
14.1 Bonding pad information
7.2 Address Counter (AC)
14.2 Bonding pad location
7.3 Display Data RAM (DDRAM)
7.4 Timing generator 15 TRAY INFORMATION
7.5 Display address counter 16 DEFINITIONS
7.6 LCD row and column drivers
17 LIFE SUPPORT APPLICATIONS
7.7 Addressing
7.7.1 Data structure
7.8 Temperature compensation
1999 Apr 12 2
Philips Semiconductors Product specification
4 ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
PCD8544U − chip with bumps in tray; 168 bonding pads + 4 dummy pads −
1999 Apr 12 3
Philips Semiconductors Product specification
5 BLOCK DIAGRAM
RESET RES
OSCILLATOR OSC
VLCD
VLCD1
GENERATOR DISPLAY DATA RAM
(DDRAM)
TIMING
48 × 84
GENERATOR
VDD1 to VDD2
VSS1 to VSS2
DISPLAY
ADDRESS
T1 ADDRESS COUNTER COUNTER
T2
DATA
T3 PCD8544
REGISTER
T4
I/O BUFFER
MGL629
SDIN SCLK D/C SCE
1999 Apr 12 4
Philips Semiconductors Product specification
SYMBOL DESCRIPTION Positive power supply for the liquid crystal display. Supply
rails VLCD1 and VLCD2 must be connected together.
R0 to R47 LCD row driver outputs
C0 to C83 LCD column driver outputs 6.1.6 T1, T2, T3 AND T4: TEST PADS
VSS1, VSS2 ground
T1, T3 and T4 must be connected to VSS, T2 is to be left
VDD1, VDD2 supply voltage open. Not accessible to user.
VLCD1, VLCD2 LCD supply voltage
T1 test 1 input 6.1.7 SDIN: SERIAL DATA LINE
T2 test 2 output Input for the data line.
T3 test 3 input/output
T4 test 4 input 6.1.8 SCLK: SERIAL CLOCK LINE
SDIN serial data input Input for the clock signal: 0.0 to 4.0 Mbits/s.
SCLK serial clock input
6.1.9 D/C: MODE SELECT
D/C data/command
SCE chip enable Input to select either command/address or data input.
OSC oscillator
6.1.10 SCE: CHIP ENABLE
RES external reset input
The enable pin allows data to be clocked in. The signal is
dummy1, 2, 3, 4 not connected
active LOW.
Note
1. For further details, see Fig.18 and Table 7. 6.1.11 OSC: OSCILLATOR
When the on-chip oscillator is used, this input must be
6.1 Pin functions connected to VDD. An external clock signal, if used, is
connected to this input. If the oscillator and external clock
6.1.1 R0 TO R47 ROW DRIVER OUTPUTS
are both inhibited by connecting the OSC pin to VSS, the
These pads output the row signals. display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into
6.1.2 C0 TO C83 COLUMN DRIVER OUTPUTS Power-down mode before stopping the clock.
These pads output the column signals.
6.1.12 RES: RESET
6.1.3 VSS1, VSS2: NEGATIVE POWER SUPPLY RAILS This signal will reset the device and must be applied to
properly initialize the chip. The signal is active LOW.
Supply rails VSS1 and VSS2 must be connected together.
1999 Apr 12 5
Philips Semiconductors Product specification
1999 Apr 12 6
Philips Semiconductors Product specification
frame n frame n + 1
VLCD Vstate1(t)
V2 Vstate2(t)
V3
ROW 0
R0 (t) V4
V5
VSS
VLCD
V2
ROW 1 V3
R1 (t) V4
V5
VSS
VLCD
V2
COL 0 V3
C0 (t) V4
V5
VSS
VLCD
V2
COL 1 V3
C1 (t) V4
V5
VSS
VLCD
V3 - VSS
VLCD - V2 V4 - V5
Vstate1(t) 0V 0V
V3 - V2 VSS - V5
V4 - VLCD
−VLCD
VLCD
V3 - VSS
VLCD - V2 V4 - V5
Vstate2(t) 0V 0V
V3 - V2 VSS - V5
V4 - VLCD
−VLCD
1999 Apr 12 7
Philips Semiconductors Product specification
DDRAM
bank 0
top of LCD
R0
bank 1
R8
bank 2
R16
LCD
bank 3
R24
bank 4
R32
bank 5
R40
R47
MGL636
1999 Apr 12 8
Philips Semiconductors Product specification
7.7 Addressing Fig.5). After the last Y address (Y = 5), Y wraps around
to 0 and X increments to address the next column. In the
Data is downloaded in bytes into the 48 by 84 bits RAM
horizontal addressing mode (V = 0), the X address
data display matrix of PCD8544, as indicated in
increments after each byte (see Fig.6). After the last
Figs. 3, 4, 5 and 6. The columns are addressed by the
X address (X = 83), X wraps around to 0 and
address pointer. The address ranges are: X 0 to 83
Y increments to address the next row. After the very last
(1010011), Y 0 to 5 (101). Addresses outside these
address (X = 83 and Y = 5), the address pointers wrap
ranges are not allowed. In the vertical addressing mode
around to address (X = 0 and Y = 0).
(V = 1), the Y address increments after each byte (see
LSB
handbook, full pagewidth
0
Y-address
MSB
5
0 X-address 83
MGL638
handbook, halfpage
0 6 0
1 7
2
Y-address
3
5 503 5
0 83
X-address
MGL639
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
1999 Apr 12 9
Philips Semiconductors Product specification
handbook, halfpage
0 1 2 0
84 85 86
0 83
X-address
MGL640
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
7.8 Temperature compensation contrast. Figure 7 shows VLCD for high multiplex rates.
In the PCD8544, the temperature coefficient of VLCD, can
Due to the temperature dependency of the liquid crystals’
be selected from four values (see Table 2) by setting bits
viscosity, the LCD controlling voltage VLCD must be
TC1 and TC0.
increased at lower temperatures to maintain optimum
VLCD
handbook, halfpage
(1)
(2)
(3)
(4)
0 °C temperature
MGL641
1999 Apr 12 10
Philips Semiconductors Product specification
handbook,MSB
halfpage
(DB7) LSB (DB0)
data data
MGL666
MGL642
Figures 10 and 11 show the serial bus protocol. • If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects bit 7 of the next byte at
• When SCE is HIGH, SCLK clock signals are ignored;
the next positive edge of SCLK (see Fig.12)
during the HIGH time of SCE, the serial interface is
initialized (see Fig.12) • A reset pulse with RES interrupts the transmission.
No data is written into the RAM. The registers are
• SDIN is sampled at the positive edge of SCLK
cleared. If SCE is LOW after the positive edge of RES,
• D/C indicates whether the byte is a command (D/C = 0) the serial interface is ready to receive bit 7 of a
or RAM data (D/C = 1); it is read with the eighth SCLK command/data byte (see Fig.13).
pulse
1999 Apr 12 11
Philips Semiconductors Product specification
D/C
SCLK
D/C
SCLK
SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGL631
1999 Apr 12 12
Philips Semiconductors Product specification
D/C
RES
SCLK
SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGL632
RES
D/C
SCLK
SDIN DB7 DB6 DB5 DB4 DB3 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGL633
1999 Apr 12 13
Philips Semiconductors Product specification
COMMAND BYTE
INSTRUCTION D/C DESCRIPTION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(H = 0 or 1)
NOP 0 0 0 0 0 0 0 0 0 no operation
Function set 0 0 0 1 0 0 PD V H power down control; entry
mode; extended instruction set
control (H)
Write data 1 D7 D6 D5 D4 D3 D2 D1 D0 writes data to display RAM
(H = 0)
Reserved 0 0 0 0 0 0 1 X X do not use
Display control 0 0 0 0 0 1 D 0 E sets display configuration
Reserved 0 0 0 0 1 X X X X do not use
Set Y address of 0 0 1 0 0 0 Y2 Y1 Y0 sets Y-address of RAM;
RAM 0≤Y≤5
Set X address of 0 1 X6 X5 X4 X3 X2 X1 X0 sets X-address part of RAM;
RAM 0 ≤ X ≤ 83
(H = 1)
Reserved 0 0 0 0 0 0 0 0 1 do not use
0 0 0 0 0 0 0 1 X do not use
Temperature 0 0 0 0 0 0 1 TC1 TC0 set Temperature Coefficient
control (TCx)
Reserved 0 0 0 0 0 1 X X X do not use
Bias system 0 0 0 0 1 0 BS2 BS1 BS0 set Bias System (BSx)
Reserved 0 0 1 X X X X X X do not use
Set VOP 0 1 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 write VOP to register
BIT 0 1
PD chip is active chip is in Power-down mode
V horizontal addressing vertical addressing
H use basic instruction set use extended instruction set
D and E
00 display blank
10 normal mode
01 all display segments on
11 inverse video mode
TC1 and TC0
00 VLCD temperature coefficient 0
01 VLCD temperature coefficient 1
10 VLCD temperature coefficient 2
11 VLCD temperature coefficient 3
1999 Apr 12 14
Philips Semiconductors Product specification
After reset, the LCD driver has the following state: Y2 Y1 Y0 BANK
• Power-down mode (bit PD = 1) 0 0 0 0
• Horizontal addressing (bit V = 0) normal instruction set 0 0 1 1
(bit H = 0) 0 1 0 2
• Display blank (bit E = D = 0) 0 1 1 3
• Address counter X6 to X0 = 0; Y2 to Y0 = 0 1 0 0 4
• Temperature control mode (TC1 TC0 = 0) 1 0 1 5
• Bias system (BS2 to BS0 = 0)
8.6 Set X address of RAM
• VLCD is equal to 0, the HV generator is switched off
(VOP6 to VOP0 = 0) The X address points to the columns. The range of X is
• After power-on, the RAM contents are undefined. 0 to 83 (53H).
8.3.2 BIT V
When V = 0, the horizontal addressing is selected.
The data is written into the DDRAM as shown in Fig.6.
When V = 1, the vertical addressing is selected. The data
is written into the DDRAM, as shown in Fig.5.
1999 Apr 12 15
Philips Semiconductors Product specification
1999 Apr 12 16
Philips Semiconductors Product specification
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); see notes 1 and 2.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage note 3 −0.5 +7 V
VLCD supply voltage LCD note 4 −0.5 +10 V
Vi all input voltages −0.5 VDD + 0.5 V
ISS ground supply current −50 +50 mA
II, IO DC input or output current −10 +10 mA
Ptot total power dissipation − 300 mW
PO power dissipation per output − 30 mW
Tamb operating ambient temperature −25 +70 °C
Tj operating junction temperature −65 +150 °C
Tstg storage temperature −65 +150 °C
Notes
1. Stresses above those listed under limiting values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. With external LCD supply voltage externally supplied (voltage generator disabled). VDDmax = 5 V if LCD supply
voltage is internally generated (voltage generator enabled).
4. When setting VLCD by software, take care not to set a VOP that will exceed the maximum of 8.5 V when operating at
−25 °C, see Caution in Section 8.9.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
1999 Apr 12 17
Philips Semiconductors Product specification
11 DC CHARACTERISTICS
VDD = 2.7 to 3.3 V; VSS = 0 V; VLCD = 6.0 to 9.0 V; Tamb = −25 to +70 °C; unless otherwise specified.
1999 Apr 12 18
Philips Semiconductors Product specification
1999 Apr 12 19
Philips Semiconductors Product specification
12 AC CHARACTERISTICS
Notes
f clk ( ext )
1. T frame = -------------------
-
480
2. RES may be LOW before VDD goes HIGH.
3. th5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE
(see Fig.15).
1999 Apr 12 20
Philips Semiconductors Product specification
SCE
tsu3
th3 th5 th5
D/C
tWL1 tsu2
tWH1 Tcy
SCLK
tsu4
th4
SDIN
MGL644
12.2 Reset
tWL(RES)
tRW
RES
MGL645
1999 Apr 12 21
Philips Semiconductors Product specification
13 APPLICATION INFORMATION
Table 6 Programming example
SERIAL BUS BYTE
STEP DISPLAY OPERATION
D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 start SCE is going LOW
2 0 0 0 1 0 0 0 0 1 function set
PD = 0 and V = 0, select
extended instruction set
(H = 1 mode)
3 0 1 0 0 1 0 0 0 0 set VOP; VOP is set to a
+16 × b [V]
4 0 0 0 1 0 0 0 0 0 function set
PD = 0 and V = 0, select
normal instruction set
(H = 0 mode)
5 0 0 0 0 0 1 1 0 0 display control set
normal mode
(D = 1 and E = 0)
6 1 0 0 0 1 1 1 1 1 data write Y and X are
initialized to 0 by default,
so they are not set here
MGL673
7 1 0 0 0 0 0 1 0 1 data write
MGL674
8 1 0 0 0 0 0 1 1 1 data write
MGL675
9 1 0 0 0 0 0 0 0 0 data write
MGL675
10 1 0 0 0 1 1 1 1 1 data write
MGL676
1999 Apr 12 22
Philips Semiconductors Product specification
MGL677
12 1 0 0 0 1 1 1 1 1 data write
MGL678
MGL679
15 1 0 0 0 0 0 0 0 0 data write
MGL680
The pinning is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48 × 84 pixels.
1999 Apr 12 23
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1999 Apr 12
14.2
Philips Semiconductors
handbook, full pagewidth
PCD8544-1
2.5 mm
pitch
x
24
y
62
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PCD8544-1
2.5 x
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12.97 mm
MGR935
Product specification
PCD8544
Fig.18 Bonding pad locations.
Philips Semiconductors Product specification
1999 Apr 12 25
Philips Semiconductors Product specification
1999 Apr 12 26
Philips Semiconductors Product specification
1999 Apr 12 27
Philips Semiconductors Product specification
VSS1
VSS1
VLCD SUPPLY
VLCD1, VLCD2
T2, T3
VSS1 VDD2
INPUT PINS
VDD1
VSS1
SCLK, SDIN, OSC,
RES, D/C, SCE,
T1, T4 VSS2
VSS1
VSS1
VLCD2 VLCD1
VSS1 VSS1
VDD1 VSS2
MGL634
1999 Apr 12 28
Philips Semiconductors Product specification
15 TRAY INFORMATION
y D
E
MGL646
Table 8 Dimensions
1999 Apr 12 29
Philips Semiconductors Product specification
16 DEFINITIONS
1999 Apr 12 30
Philips Semiconductors Product specification
NOTES
1999 Apr 12 31
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Printed in The Netherlands 465008/750/01/pp32 Date of release: 1999 Apr 12 Document order number: 9397 750 05024