Lecture 11

Common Drain Stage

(Source Follower)

Jayant Charthad
Stanford University
jayantc@stanford.edu

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 1

 Common Drain Stage
VDD
Cgd+Cgb
vi
Vi
+
vgs Cgs ro gmvgs -gmbvo
Vo -
vo

IB RL CL RL Csb+CL

Cgd+Cgb
vi

+
vgs Cgs ro gmvgs -gmbvo
-
vo
Cgd+Cgb
RL Csb+CL
gmbvo

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 2

 CD Voltage Transfer (1)

æ 1 ö
vi
vo çç sCLtot + sCgs + ÷÷ - vi sCgs - g m (vi - vo ) = 0
è RLtot ø
+
vgs Cgs gmvgs vo g m + sCgs
=
- vi g + sC + sC + 1
Cgd+Cgb vo m gs Ltot
RLtot
CLtot RLtot
sCgs
1+
vo gm gm
= ×
vi g + 1 s (C gs + C Ltot )
m 1 +
1 RLtot 1
C Ltot = C L + Csb RLtot = RL || || ro gm +
g mb RLtot

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 3

 Low Frequency Gain
gm 1
av 0 = RLtot = RL || || ro
1 g mb
gm +
RLtot
• Interesting cases
– RL®¥, ro®¥, gmb=0 av 0 = 1
• PMOS, source tied to body, ideal current source
VDD VDD

gm
– RL®¥, ro®¥, gmb¹0 Vi av 0 =
Vo RLtot=1/gmb g m + g mb
Vi • NMOS, ideal current source) Vo
CL (typically @ 0.8)
Yin IB RL CL

gm
– ro®¥, gmb=0, RL finite av 0 =
1
• PMOS, source tied to body, load resistor gm +
RL

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 4

 High Frequency Gain

s 1
1- g gm +
v
av (s ) = o = av 0 × z z=- m RLtot
vi s C gs p=-
1- C gs + C Ltot
p

• Three scenarios

|z|<|p| |z|>|p| |z|=|p|

|av(s)| |av(s)| |av(s)|

f f f
(infinite bandwidth !?)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 5

 CD Input Impedance

Hint*:
I=Cgs(vi-vo) • By inspection*
vi
Yin = s (C gd + C gb ) + sC gs (1 - av ( s ))
Yin +
vgs Cgs gmvgs
- • Gain term av(s) is real and close to
Cgd+Cgb vo
unity up to fairly high frequencies
CLtot RLtot
• Hence, up to moderate
frequencies, we see a capacitor
looking into the input
– A fairly small one, Cgd + Cgb,
PS--Insight from Miller Theorem, plus a fraction of Cgs
p. 9 Lec#8 is consistent

*Really, try and be brave. This is important to having insight as a designer

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 6

 PMOS Stage with Body-Source Tie

• Gate-body capacitance is in
VDD parallel with Cgs
• gmb generator inactive
– Low frequency gain very
Vo
close to unity
Vi
CL • Very small input capacitance
Yin

Yin = sCgd + s(C gs + C gb )(1 - av ( s ))

Yin @ sCgd

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 7

 CD Output Impedance (1)

• Let's first look at an analytically

simple case
– Input driven by ideal voltage
+
source
vgs Cgs gmvgs
-
• By inspection*
vo
Cgd+Cgb
1 1
Zout Z out =
g m + g mb s(C gs + Csb )
Csb 1/gmb

• Low output impedance

– Resistive up to very high
frequencies

*Really, try and be brave. This is important to having insight as a designer

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 8

 CD Output Impedance (2)
• Now include finite source resistance
vg

Ri
Cgs gm(vg-vo)
Zx Zout
Cgd+Cgb vo
ix Csb 1/gmb

v ix = (vo - vg )(g m + sCgs ) vg Ri

Zx = o =
ix æ vg ö 1
÷÷(g m + sCgs )
vo + Ri
= vo çç1 -
è vo ø sC gs

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 9

 CD Output Impedance (3)

1 (1 + sRi C gs )
Zx @
gm æ sC gs ö
çç1 + ÷÷
è g m ø
• Two interesting cases

Ri < 1/gm Ri > 1/gm

|Zx(s)| |Zx(s)|

1/gm 1/gm

f f

Inductive behavior!

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 10

 Equivalent Circuit for Ri > 1/gm

Zx Zout
1
R1
R1 || R2 =
gm
R2 Csb 1/gmb R2 = Ri
L Ri2C gs
L=
g m Ri - 1

• This circuit is prone to ringing!

– L forms an LC tank with any capacitance at the output

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 11

 Inclusion of Parasitic Input Capacitance*

• What happens to this result if we don’t neglect Ci=Cgd+Cgb?

*Hint: on p. 10 1 (1 + sRi {C gs + Ci })
replace Ri with: Zx =
gm æ sC gs ö
Ri çç1 + ÷÷(1 + sRi Ci )
Zi = è g m ø
Ri + sC i Ri

1 gm 1 1 1 g
< < < < m
Ri {Cgs + Ci } Cgs Ri Ci Ri {Cgs + Ci } Ri Ci Cgs

|Zx(s)| |Zx(s)|

1/gm 1/gm

f f

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 12

 Application 1: Level Shifter

VDD

Vi

VGS=Vt+Vov @ const.
Vo

IB

• Output quiescent point is roughly Vt+Vov lower than input

quiescent point

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 13

 Application 2: Buffer
VDD

Rbig

Vo
Vi

IB Rsmall

• Low frequency voltage gain of the above circuit is ~gmRbig

– Would be ~gm(Rsmall||Rbig) without CD buffer stage

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 14

 Issues

• Several sources of nonlinearity

– Vt is a function of Vo (NMOS, without S to B connection)
– ID and thus Vov changes with Vo
• Gets worse with small RL
• Reduced input and output voltage swing
– Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V
• CD buffer stage consumes 50% of supply headroom!
– In low VDD applications that require large output swing, using
a CD buffer is often not possible
– CD buffers are more frequently used when the required
swing is small
• E.g. pre-amplifiers or LNAs that turn µV into mV at the output

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 15

 Application 3: Load Device

VDD • Advantages compared to resistor load

Added term vs.
previous PS – "Ratiometric"
examples
M2 • Gain depends on ratio of similar
1/(gm2+gmb2)
parameters
• Reduced process and
Vo temperature variations
Vi – First order cancellation of
M1 nonlinearities
• Disadvantage
– Reduced swing
g m1
av 0 =
g m 2 + g mb 2

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 16

 Summary – Elementary Transistor Stages

• Common source
– VCCS, makes a good voltage amplifier when terminated with
a high impedance
• Common gate
– Typically low input impedance, high output impedance
– Can be used to improve the intrinsic voltage gain of a
common source stage
• "Cascode" stage
• Common drain
– Typically high input impedance, low output impedance
– Great for shifting the DC operating point of signals
– Useful as a voltage buffer when swing and nonlinearity are
not an issue

A. Arbabian, R. Dutton, B. Murmann EE114/214A L11- 17