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Winter 2012
ME561
EE561
Source: http://www.ti.com/sc/docs/psheets/diagrams/dmc.htm
Output
y u e + r
Plant D/A Computer A/D
Reference
–
Clock
u(t) Discrete
u(kT)
Signal
u
Continuous
Average u(t) Signal
kT
1 2 3 4 5 6 7 8 9 10
Midterm 20%
Final 35%
Better Actuators
Provide more Muscle
Better Control
Provides more finesse by combining sensors and
actuators in more intelligent ways
http://www.engin.umich.edu/group/ctm/ or http://www.engin.umich.edu/class/ctms/
Kfd
4
feed->ft
Feed per tooth
Vf
Kfs 1
1 Ka -K- 2
tau_fs.s+1 1 f(u) 1
Vcf
Saturation Zero-Order Feed sl ide Sam pl ing Feed Force
Volt am p
Feed force
Hol d
F stiffness
Sf
Vz 2
Kzs 1 1 f(u) 2
2 Ka
Z Force
Vcz tau_zs.s+1 s 1 Z force
Saturation1 Zero-Order Integrator Sam p
Volt am p1 Z sl ide
Hold1 3
Z sti ffness delta_Z
d_nom
nom ianl depth Sz
3
Disturbance depth Example from 2001 machining project
y Plant u Controller e + r
G(s) C(s)
–
Clock
( s b )U ( s ) K ( s a ) E ( s ) u b u K ( e a e )
Euler approximation:
x ( k 1) x ( k )
x ( k )
T
u( k 1) u( k )
b u( k ) K
LM
e( k 1) e( k )
a e( k )
OP
T NT Q
u( k 1) (1 bT ) u( k ) K ( aT 1) e( k ) K e( k 1)
or u ( k ) (1 b T ) u ( k 1) K ( a T 1) e ( k 1) K e ( k )
1 s2
G( s) C( s ) 50
s( s 1) s 10
x o x x
1 50(s+2)
y
s 2 +s (s+10) Step
Response (Output)
Plant Lead Compensator
1 50z+50*(-0.9333) 1
y_digital
s 2 +s z-0.6667 1 Step
Response
Plant Zero-Order Discrete Implementation Sampling
(Output)
Hold
of the Lead Compensator
1 1
Unit Step Response
0 0
0 0.5 1 1.5 0 0.5 1 1.5
Time (sec) Time (sec)
1.6
1.2
1.4
1
1.2
1
Unit StepResponse
Unit StepResponse
0.8
5Hz 0.6
0.8
0.6
0.4
Analog Control 0.4
Digital Control (5 Hz) Analog Control
Sampled Digital Output (5 Hz)
0.2 Actual Output
0.2
0 0
0 0.5 1 1.5 0 0.5 1 1.5
Time (sec) Time (sec)
( ) (b)
Clock
1 1
Step Response
Step Response
0.8 0.8
0.6 0.6
0.4 0.4
Reference Step
0.2 Continuous-Time Response 0.2
Digital Response
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
1 1
Step Response
Step Response
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Time Time
2 s 0 1
1
Y ( s)
GCL ( s )
R( s ) s 0 3 2 s 0 2 2 s 0 1
y u r
Arm Amplifier Controller 1.5
GA(s) k C(s)
Position
1
0.5
0.8
Analog Control Response
0.6
Digital Control Response
Velocity
0.4 Sampled Response
0.2
0
-0.2
0 1 2 3 4 5 6 7 8 9 10
1
Control Input
0.5
-0.5
-1
0 1 2 3 4 5 6 7 8 9 10
Time
0.5 0.5
u(t) e(t)
Response
Input
0 C(s) 0
-0.5 -0.5
-1 -1
0 2 4 6 8 10 C(s) 0 2 4 6 8 10
Time
u(t) u(kT) Digitized e(kT) e(t)
D/A Control A/D
T
Algorithm
Clock
10 Hz sampling
1
1
0.5
Response
Sampled Input
0.5
0
0
-0.5
-0.5
-1
0 2 4 6 8 10 -1
Time 0 2 4 6 8 10
http://library.thinkquest.org/19537/java/Beats.html
Copyright © G.Chiu and H.Peng ME561 Lecture1- 38
4.9 Hz sine wave and 10Hz Sampling
0.8
0.6
0.4
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t=0:0.001:1;
y=sin(9.8*pi*t);
t2 = 0:0.1:1;
y2 = sin(9.8*pi*t2);
plot(t, y, t2, y2, 'ro')
Copyright © G.Chiu and H.Peng ME561 Lecture1- 39
Time Delay Due to Sample/Hold
u(kT) uH(t)
u
Average u(t)
kT
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 kT e
T
2
j 1 and e
T
2
j
T
2
Compression
x
Rebound
Performance
emulate Evaluation & Analysis
Discrete-Time
Controller Design
Select Sampling
Frequency
Performance
Performance Evaluation & Analysis
Evaluation & Analysis
Implementation
Copyright © G.Chiu and H.Peng ME561 Lecture1- 43