ESCUELA POLITÉCNICA NACIONAL

FACULTAD DE INGENIERÍA ELÉCTRICA Y ELECTRÓNICA

DEPARTAMENTO DE ELECTRÓNICA, TELECOMUNICACIONES Y
REDES DE INFORMACION

INFORME X TRABAJO PREPARATORIO

X Sistemas Digitales

Sistemas Analógicos Digitales

Práctica: 09 Tema: FLIP-FLOPS (Multivibradores biestables) VHDL

Realizado por:

Alumno (s): Fernando Benítez Grupo: GR8

Bryan Celi

(Espacio Reservado)
Fecha de entrega: 2018 / 02 / 09 f. ______________________
año mes día Recibido por:

Sanción: ________________________________________________

Semestre: OCT - MAR X

ABR - SEP 2017
1. Realizar contadores de tipo Ripple-Clock ascendente que se presenta en la siguiente tabla,
armarlos en los simuladores Proteus y Logisim además crear el código en VHDL y la
simulación en gtkwave (utilizar solo flip-flops J-K)
MODULO 16

0
0 0 1

U1:A U1:B U2:A U2:B

7
U1:A(CLK) 4 15 9 11 4 15 9 11
S

S
J Q J Q J Q J Q
1 6 1 6
CLK CLK CLK CLK
16 14 12 10 16 14 12 10
K Q K Q K Q K Q
R

R
3

8
74LS76 74LS76 74LS76 74LS76

VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity contador15 is
port (
clk0,x : in bit;
a0,a1,a2,a3: out bit
);
end contador15;

architecture behavior of contador15 is

component FF_JK
port(J: IN BIT;
K: IN BIT;
CLK: IN BIT;
PRESET: IN BIT;
CLEAR: IN BIT;
Q: OUT BIT;
Qc: OUT BIT
);
end component;
signal cl1,pr1,cl0,pr0,q_0,q_1,q_2,q_3 : bit;
signal a_0,a_1,a_2,a_3: bit;
begin
cl1<= (x nand '0');
pr1<= (x nand '1');
 cl0<= (x nand '1');
pr0<= (x nand '0');
ffjk0: FF_JK port map('1','1',clk0,pr1,cl1,q_0,a_0);
ffjk1: FF_JK port map('1','1',q_0,pr0,cl0,q_1,a_1);
ffjk2: FF_JK port map('1','1',q_1,pr0,cl0,q_2,a_2);
ffjk3: FF_JK port map('1','1',q_2,pr0,cl0,q_3,a_3);
a0<=q_0;
a1<=q_1;
a2<=q_2;
a3<=q_3;
end behavior;

TEST
library ieee;
use ieee.std_logic_1164.all;

entity contador15_tb is
end contador15_tb;

architecture test of contador15_tb is

component contador15
port(
clk0,x : in bit;
a0,a1,a2,a3: out bit
);
end component;
signal clk_0,x_0,a_0,a_1,a_2,a_3: bit;
begin
cont15: contador15 port map(
x=>x_0,
clk0=>clk_0,
a0=>a_0,
a1=>a_1,
a2=>a_2,
a3=>a_3);

process
begin
x_0<='1'; clk_0<='0'; wait for 10 fs;
x_0<='1'; clk_0<='1'; wait for 10 fs;
for i in 0 to 15 loop
x_0<='0';
clk_0<='0';
wait for 10 fs;
x_0<='0';
clk_0<='1';
wait for 10 fs;
end loop;

wait;
end process;
end test;
2. Realizar contadores de tipo Ripple-Clock descendente que se presenta en la siguiente tabla,
armarlos en los simuladores Proteus y Logisim además crear el código en VHDL y la
simulación en gtkwave (utilizar solo flip-flops J-K).
MODULO 15

U3:B U3:A U2:A U2:B

7
BAT1 9 11 4 15 4 15 9 11

S
J Q e3 J Q e2 J Q e1 J Q e0
10 U2:B(CLK)
6 1 1 6
CLK CLK CLK CLK
12 10 16 14 16 14 12 10
K Q q3 K Q q2 K Q q1 K Q q0

R
U5

8
7476 7476 7476 7476
e3
e2

e1
e0
NAND_4

U4 R7
10 9
q0
8
A1 S1
6
d0 U6 330 R8
q1 A2 S2 d1 U1
3 2 10 9
q2 A3 S3 d2 d0 A1 S1 330
1 15 8 6 7 13
q3 A4 S4 d3 d1
3
A2 S2
2 1
A QA
12
R9
d2 A3 S3 B QB
11 1 15 2 11
B1 d3 A4 S4 C QC 330
7 6 10 R10
B2 D QD
4 11 4 9
B3 B1 BI/RBO QE
16 7 5 15 330
B4 B2 RBI QF
4 3 14 R11
B3 LT QG
13 14 16
C0 C4 B4
74LS48 330
74LS83 13 14 R12
C0 C4
U4(C0) 74LS83 330
U7 R13
U14 d2 330
U11 R14
d1 U8
U15 AND_2 7 13 R15
330
NOT U9 A QA
1 12
U12 B QB
2 11 R16
330
d2 C QC
OR 6 10
D QD
4 9 R17
330
NOT d1 BI/RBO QE
5 15
RBI QF
AND_2 3 14 R18
330
U10 LT QG
OR
U16 74LS48 R19
330
d1 U13
d0 R20
330
AND_2 330
NOT d3
AND_2

VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont15des is
port (
clk0,x : in bit;
a0,a1,a2,a3: out bit
);
end cont15des;

architecture behavior of cont15des is

component FF_JK
port(J: IN BIT;
K: IN BIT;
CLK: IN BIT;
PRESET: IN BIT;
CLEAR: IN BIT;
Q: OUT BIT;
Qc: OUT BIT
);
end component;
signal cl1,pr1,cl0,pr0,q_0,q_1,q_2,q_3 : bit;
signal a_0,a_1,a_2,a_3: bit;
begin
cl1<= (x nand '0');
pr1<= (x nand '1');
cl0<= (x nand '1');
pr0<= (x nand '0');
ffjk0: FF_JK port map('1','1',clk0,pr1,cl1,q_0,a_0);
 ffjk1: FF_JK port map('1','1',q_0,pr0,cl0,q_1,a_1);
ffjk2: FF_JK port map('1','1',q_1,pr0,cl0,q_2,a_2);
ffjk3: FF_JK port map('1','1',q_2,pr0,cl0,q_3,a_3);

a0<=a_0;
a1<=a_1;
a2<=a_2;
a3<=a_3;
end behavior;
TEST
library ieee;
use ieee.std_logic_1164.all;

entity cont15des_tb is
end cont15des_tb;

architecture test of cont15des_tb is

component cont15des
port(
clk0,x : in bit;
a0,a1,a2,a3: out bit
);
end component;
signal clk_0,x_0,a_0,a_1,a_2,a_3: bit;
begin
contador15: cont15des port map(
x=>x_0,
clk0=>clk_0,
a0=>a_0,
a1=>a_1,
a2=>a_2,
a3=>a_3);

process
begin
x_0<='1'; clk_0<='0'; wait for 10 fs;
x_0<='1'; clk_0<='1'; wait for 10 fs;
for i in 0 to 15 loop
x_0<='0';
clk_0<='0';
wait for 10 fs;
x_0<='0';
clk_0<='1';
wait for 10 fs;
end loop;

wait;
end process;
end test;
3. Realizar el código en VHDL como las pruebas en gtkwave de las siguientes compuertas
lógicas 7490, 7492 y 7496.
VHDL 7490
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY c7490 IS
PORT ( Qa,Qb,Qc,Qd: OUT STD_LOGIC;
R01,R02,R91,R92: IN STD_LOGIC;
Clk: IN STD_LOGIC);
END c7490;

ARCHITECTURE behavior OF c7490 IS

SIGNAL count: UNSIGNED(3 DOWNTO 0) := "0000";

SIGNAL c : integer := 0;
SIGNAL Clk_new: STD_LOGIC:= '0';

BEGIN
Qa<=count(0);
Qb<=count(1);
Qc<=count(2);
Qd<=count(3);

PROCESS(Clk)
BEGIN
IF(rising_edge(Clk)) THEN
IF( c < 125000000) THEN
c<=c+1;
Clk_new<='0';
ELSIF( c < 25000000) THEN
c<=c+1;
Clk_new<='1';
ELSE
c<=0;
END IF;
END IF;
END PROCESS;

PROCESS(Clk_new,R01,R02,R91,R92)
BEGIN
 IF(R01='1' AND R02='1' AND R91='0') THEN
count<="0000";
ELSIF(R01='1' AND R02='1' AND R91='0') THEN
count<="0000";
ELSIF(R92='1' AND R91='1') THEN
count<="1001";
ELSIF(rising_edge(Clk_new)) THEN
count<=count+1;
IF(count="1001") THEN
count<="0000";
END IF;
END IF;
END PROCESS;
END behavior;
TEST
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY c7490_tb IS
END c7490_tb;

ARCHITECTURE behavior OF c7490_tb IS

COMPONENT c7490 PORT(
Qa,Qb,Qc,Qd: OUT STD_LOGIC;
R01,R02,R91,R92: IN STD_LOGIC;
Clk: IN STD_LOGIC);
END COMPONENT;

SIGNAL R01: STD_LOGIC := '0';

SIGNAL R02: STD_LOGIC := '0';
SIGNAL R91: STD_LOGIC := '0';
SIGNAL R92: STD_LOGIC := '0';
SIGNAL Clk: STD_LOGIC := '0';

SIGNAL Qa: STD_LOGIC;

SIGNAL Qb: STD_LOGIC;
SIGNAL Qc: STD_LOGIC;
SIGNAL Qd: STD_LOGIC;

CONSTANT Clk_period: time := 20 ns;

BEGIN
uut: c7490 PORT MAP(
Qa=>Qa,
Qb=>Qb,
Qc=>Qc,
Qd=>Qd,
R01=>R01,
R02=>R02,
R91=>R91,
R92=>R92,
 Clk=>Clk);

Clk_process: PROCESS --definicion del proceso del reloj

BEGIN
Clk<='0';
wait for Clk_period/2;
Clk<='1';
wait for Clk_period/2;
wait;
END PROCESS;
stim_process: PROCESS --definicion de las entradas o estimulos
BEGIN
wait for 150 ns;
R91<='1'; R92<='1';
wait for 120 ns;
R91<='0'; R92<='1';
R01<='1'; R02<='1';
wait for 150 ns;
R01<='0'; R02<='0'; R92<='0';
wait;
END PROCESS;

END behavioral;

4. Elaborar código en VHDL que permita implementar un flip-flop tipo D y T.

TIPO D
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fpd is
Port ( d:in std_logic;
clk: in std_logic;
pr: in std_logic;
cl: in std_logic;
q0: out std_logic;
q1: out std_logic
);
end fpd;

architecture Behavioral of fpd is

signal q: std_logic:='0';
begin
process (clk,d,pr,cl)
begin
IF pr='0' THEN q<='1';
ELSIF CL='0' THEN q<='0';
ELSIF CLK='0' AND CLK'EVENT THEN
if (d= '0') then q <= '0';
else q<='1';
end if;
END IF;
end process;
q0<= q;
q1<=(not q);
end Behavioral;
Prueba en Flancos de Bajada
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fpd_tb IS
END fpd_tb;

ARCHITECTURE behavior OF fpd_tb IS

COMPONENT fpd
PORT(d:in std_logic;
clk: in std_logic;
pr: in std_logic;
cl: in std_logic;
q0: out std_logic;
q1: out std_logic);
END COMPONENT;

SIGNAL d: std_logic := '0';

SIGNAL clk: std_logic := '0';
SIGNAL pr: std_logic := '0';
SIGNAL cl: std_logic := '0';
SIGNAL q0: std_logic;
SIGNAL q1: std_logic;

BEGIN
uut: fpd PORT MAP(
d=>d,
clk=>clk,
pr=>pr,
cl=>cl,
q0=>q0,
q1=>q1);

PROCESS
BEGIN
d<='0'; clk<='0'; pr<= '1'; cl<='0'; wait for 10 fs;
d<='1'; clk<='1'; pr<= '1'; cl<='1'; wait for 10 fs;
 d<='1'; clk<='0'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='0'; clk<='1'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='0'; clk<='0'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='1'; clk<='1'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='1'; clk<='0'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='0'; clk<='1'; pr<= '1'; cl<='1'; wait for 10 fs;
d<='0'; clk<='0'; pr<= '1'; cl<='1'; wait for 10 fs;

wait;
END PROCESS;
END behavior;

TIPO T
VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fpt is
Port ( t:in std_logic;
clk: in std_logic;
pr: in std_logic;
cl: in std_logic;
q0: out std_logic;
q1: out std_logic
);
end fpt;

architecture Behavioral of fpt is

signal q: std_logic:='0';
begin
process (clk,t,pr,cl)
begin
IF pr='0' THEN q<='1';
ELSIF CL='0' THEN q<='0';
ELSIF CLK='0' AND CLK'EVENT THEN
if (t= '0') then q <= q ;
else q<=not q;
end if;
END IF;
end process;
q0<= q;
q1<=(not q);
end Behavioral;
PRUEBA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fpt_tb is
end fpt_tb;

ARCHITECTURE behavioral OF fpt_tb IS

COMPONENT fpt
Port ( clk: in std_logic;
t:in std_logic;
pr: in std_logic;
cl: in std_logic;
q0,q1: out std_logic);
END COMPONENT;
signal clk:std_logic;
signal pr,cl: std_logic;
signal t:std_logic;
signal q0,q1:std_logic;

BEGIN
uut: fpt PORT MAP (
clk=> clk,
cl=>cl,
pr=>pr,
t => t,
q0 => q0,
q1 =>q1
);
process
begin
cl<='1';pr<='1';t <= '0'; clk <= '0'; wait for 10 Fs;
cl<='1';pr<='1';t <= '0'; clk <= '1'; wait for 10 Fs;
cl<='1';pr<='1';t <= '1'; clk <= '0'; wait for 10 Fs;
cl<='1';pr<='1';t <= '1'; clk <= '1'; wait for 10 Fs;
cl<='1';pr<='1';t <= '1'; clk <= '0'; wait for 10 Fs;
cl<='1';pr<='1';t <= '1'; clk <= '1'; wait for 10 Fs;
cl<='1';pr<='0';t <= '0'; clk <= '0'; wait for 10 Fs;
cl<='1';pr<='0';t <= '0'; clk <= '1'; wait for 10 Fs;
cl<='0';pr<='1';t <= '0'; clk <= '0'; wait for 10 Fs;
cl<='0';pr<='1';t <= '0'; clk <= '1'; wait for 10 Fs;
cl<='1';pr<='1';t <= '0'; clk <= '0'; wait;

end process;
END behavioral;
5. Realizar el código VHDL (con base de flip-flops J-K) necesario para implementar un
contador ascendente del módulo indicado en la siguiente tabla.

CÓDIGO VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont512 is
port (
clk0 : in bit;
q0,q1,q2,q3,q4,q5,q6,q7,q8,q9: out bit
);
end cont512;

architecture behavior of cont512 is

component FF_JK
port(J: IN BIT;
K: IN BIT;
CLK: IN BIT;
PRESET: IN BIT;
CLEAR: IN BIT;
Q: OUT BIT;
Qc: OUT BIT
);
end component;
signal res,q_0,q_1,q_2,q_3,q_4,q_5,q_6,q_7,q_8,q_9 : bit;
signal a_0,a_1,a_2,a_3,a_4,a_5,a_6,a_7,a_8,a_9 : bit;
begin
res<= not ((q_9)and(q_0));
ffjk0: FF_JK port map('1','1',clk0,'1',res,q_0,a_0);
ffjk1: FF_JK port map('1','1',q_0,'1',res,q_1,a_1);
ffjk2: FF_JK port map('1','1',q_1,'1',res,q_2,a_2);
ffjk3: FF_JK port map('1','1',q_2,'1',res,q_3,a_3);
ffjk4: FF_JK port map('1','1',q_3,'1',res,q_4,a_4);
ffjk5: FF_JK port map('1','1',q_4,'1',res,q_5,a_5);
ffjk6: FF_JK port map('1','1',q_5,'1',res,q_6,a_6);
ffjk7: FF_JK port map('1','1',q_6,'1',res,q_7,a_7);
ffjk8: FF_JK port map('1','1',q_7,'1',res,q_8,a_8);
ffjk9: FF_JK port map('1','1',q_8,'1',res,q_9,a_9);

q0<=q_0;
q1<=q_1;
q2<=q_2;
 q3<=q_3;
q4<=q_4;
q5<=q_5;
q6<=q_6;
q7<=q_7;
q8<=q_8;
q9<=q_9;
end behavior;
PRUEBA VHDL
entity cont512_tb is
end cont512_tb;

architecture test of cont512_tb is

component cont512
port(
clk0: in bit;
q0,q1,q2,q3,q4,q5,q6,q7,q8,q9: out bit
);
end component;
signal clk_0,q_0,q_1,q_2,q_3,q_4,q_5,q_6,q_7,q_8,q_9: bit;
begin
contador512: cont512 port map(

clk0=>clk_0,
q0=>q_0,
q1=>q_1,
q2=>q_2,
q3=>q_3,
q4=>q_4,
q5=>q_5,
q6=>q_6,
q7=>q_7,
q8=>q_8,
q9=>q_9);

process
begin

for i in 0 to 520 loop

clk_0<='0';
wait for 10 fs;
clk_0<='1';
wait for 10 fs;
end loop;

wait;
end process;
end test;
6. Realizar el código VHDL (con base de flip-flops J-K) necesario para implementar un
contador descendente del módulo indicado en la siguiente tabla.

CODIGO VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont612 is
port (
clk0,x : in bit;
a0,a1,a2,a3,a4,a5,a6,a7,a8,a9: out bit
);
end cont612;

architecture behavior of cont612 is

component FF_JK
port(J: IN BIT;
K: IN BIT;
CLK: IN BIT;
PRESET: IN BIT;
CLEAR: IN BIT;
Q: OUT BIT;
Qc: OUT BIT
);
end component;
signal cl1,pr1,cl0,pr0,q_0,q_1,q_2,q_3,q_4,q_5,q_6,q_7,q_8,q_9 : bit;
signal a_0,a_1,a_2,a_3,a_4,a_5,a_6,a_7,a_8,a_9 : bit;
begin
cl1<= (x nand '0');
pr1<= (x nand '1');
 cl0<= (x nand '1');
pr0<= (x nand '0');
ffjk0: FF_JK port map('1','1',clk0,pr1,cl1,q_0,a_0);
ffjk1: FF_JK port map('1','1',q_0,pr1,cl1,q_1,a_1);
ffjk2: FF_JK port map('1','1',q_1,pr0,cl0,q_2,a_2);
ffjk3: FF_JK port map('1','1',q_2,pr1,cl1,q_3,a_3);
ffjk4: FF_JK port map('1','1',q_3,pr1,cl1,q_4,a_4);
ffjk5: FF_JK port map('1','1',q_4,pr0,cl0,q_5,a_5);
ffjk6: FF_JK port map('1','1',q_5,pr0,cl0,q_6,a_6);
ffjk7: FF_JK port map('1','1',q_6,pr1,cl1,q_7,a_7);
ffjk8: FF_JK port map('1','1',q_7,pr1,cl1,q_8,a_8);
ffjk9: FF_JK port map('1','1',q_8,pr0,cl0,q_9,a_9);

a0<=a_0;
a1<=a_1;
a2<=a_2;
a3<=a_3;
a4<=a_4;
a5<=a_5;
a6<=a_6;
a7<=a_7;
a8<=a_8;
a9<=a_9;
end behavior;
PRUEBA
entity cont612_tb is
end cont612_tb;

architecture test of cont612_tb is

component cont612
port(
clk0,x : in bit;
a0,a1,a2,a3,a4,a5,a6,a7,a8,a9: out bit
);
end component;
signal clk_0,x_0,a_0,a_1,a_2,a_3,a_4,a_5,a_6,a_7,a_8,a_9 : bit;
begin
contador612: cont612 port map(
x=>x_0,
clk0=>clk_0,
a0=>a_0,
a1=>a_1,
a2=>a_2,
a3=>a_3,
a4=>a_4,
a5=>a_5,
a6=>a_6,
a7=>a_7,
a8=>a_8,
a9=>a_9);
 process
begin
x_0<='1'; clk_0<='0'; wait for 10 fs;
x_0<='1'; clk_0<='1'; wait for 10 fs;
for i in 0 to 612 loop
x_0<='0';
clk_0<='0';
wait for 10 fs;
x_0<='0';
clk_0<='1';
wait for 10 fs;
end loop
wait;
end process;
end test;

BIBLIOGRAFÍA

[1] T. L. Floyd, Fundamentos de Sistemas Digitales, Madrid: PEARSON EDUCACION, 2006.

[2] C. Novillo Montero, Sistemas Digitales, Quito: Escuela Politécnica Nacional, 2008.