VHDL Code Examples

VHSIC [Very High Speed Integrated Circuits] Hardware Description Language

IEEE-1076

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This is just a quick reference of some short VHDL code fragments. Above each code segment is a
circuit which represents the fragment.
In most cases the Process, and end of Process commands are not listed to keep the text down.

VHDL code for a D Flip Flop

process (signal names)

begin
if (clock’event and clock = ‘1’) then
output <= data;
end if;
end process

VHDL code for a D Flip Flop with Reset and Clear

if reset = ‘0’ then

output <= ‘0’;
elsif set = ‘0’ then
output <= ‘1’;
elsif (clock’event and clock = ‘1’) then
output <= data;
end if;
VHDL code for a D Flip Flop

if (clock’event and clock = ‘0’) then

if (reset = ‘0’ and data = ‘0’) then
output <= ‘0’;
elsif (reset = ‘0’ and data = ‘1’) then
output <= ‘0’;
elsif (reset = ‘1’ and data = ‘0’) then
output <= ‘0’;
elsif (reset = ‘1’ and data = ‘1’) then
output <= ‘1’;
end if;

VHDL code for a JK Flip Flop

if (clock’event and clock = ‘1’) then

if (in1 = ‘0’ and in2 = ‘0’) then
output <= output;
elsif (in1 = ‘1’ and in2 = ‘0’) then
output <= ‘1’;
elsif (in1 = ‘0’ and in2 = ‘1’) then
output <= ‘0’;
elsif (in1 = ‘1’ and in2 = ‘1’) then
output <= not(output);
end if;
end if;

VHDL code for a 2-to-1 Mux

if sel = ‘0’ then
output <= data1;
elsif sel = ‘1’ then
output <= data2;
end if;

VHDL code for a Serial to Parallel Converter

if clear = ‘0’ then

shift_reg <= “00000000”;
elsif (clock’event and clock = ‘1’) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;

VHDL code for a Parallel to Serial Converter

if load = ‘0’ then

shift_reg <= parallel;
elsif (clock’event and clock = ‘1’) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;

VHDL code for a 4 bit Counter

if load = ‘0’ then
output <= “1111”;
elsif (clock’event and clock = ‘1’) then
output <= data - ‘1’;
end if;
carry <= ‘0’ when output = “0000” else ‘1’;
load <= carry;

VHDL code for a 1 bit Adder

if c = ‘0’ then
if (a and b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘1’;
carry <= ‘0’
end if;
elsif c = ‘1’ then
if (a and b) = ‘1’ then
sum <= ‘1’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
end if;
end if;

VHDL code for a State Machine

if reset = ‘0’ then

state <= stateA;
output <= ‘0’;
elsif (clock’event and clock) = ‘1’ then
case state is
when stateA
output <= ‘0’;
state <= stateB
when stateB
output <= ‘1’;
if input = ‘1’ then
state <= stateB;
else
state <=stateC;
end if;
when stateC
output <= ‘0’
state <= stateA;
end case;

IEEE-1076: Standard VHDL Language Reference Manual IEEE Computer Society

Document
IEEE 1076.1: VHDL Analog and Mixed-Signal Extensions IEEE Computer Society Document
IEEE 1076.2: Standard VHDL Mathematical Packages IEEE Computer Society Document
IEEE 1076.3: Standard VHDL Synthesis Packages IEEE Computer Society Document
IEEE 1076.4: Standard for VITAL ASIC (Application Specific Integrated Circuit) Modeling
Specification IEEE Computer Society Document
IEEE 1076.6: Standard for VHDL Register Transfer Level (RTL) Synthesis IEEE Computer
Society Document

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 Last Modified 4/2/10
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