IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.
12, DECEMBER 2005
A Four-Antenna Receiver in 90-nm CMOS for
Beamforming and Spatial Diversity
Jeyanandh Paramesh, Member, IEEE, Ralph Bishop, K. Soumyanath, Member, IEEE, and
David J. Allstot, Fellow, IEEE
Abstract—A fully integrated four-channel multi-antenna re-
ceiver intended for beamforming and spatial diversity applications
is presented. It can also be used as a low-power area-efficient range
extender for spatially multiplexed multi-antenna systems that are
poised to become mainstream in the near future. Implemented in a
90-nm CMOS technology, each channel weights its input signal by
a complex weight with full 360 phase shift programmability using
vector combinations of variable-gain amplifiers, thus obviating
the need for expensive phase shifters. The chip consumes 140 mW
from a single 1.4-V supply and achieves 12 dB of array gain with
all four channels activated and 20 dB direction-of-arrival-de-
pendent interference rejection.
Index Terms—CMOS integrated circuits, diversity methods,
MIMO systems, phased arrays, radio receivers.
I. INTRODUCTION
T HE last decade has witnessed the deployment of wireless
local area networks (LANs) such as those governed by
the IEEE 802.11a standard that operates at a peak data rate of
54 Mb/s over 20-MHz channels located in the 5.15–5.35- and
5.725–5.825-GHz bands. A simplistic approach to further en-
hance data rates would be to increase spectral efficiency or band-
width, or both. Paulraj et al. [1] argue that in practical cell reuse
schemes, the realizable signal-to-interference-plus-noise ratio
(SINR) is capped at about 20 dB with a peak spectral efficiency
of about 4–6 b/s/Hz. Furthermore, aggressive increases in band-
width are impractical because of the unavailability of spectrum
below 6 GHz and excessive signal attenuation above 6 GHz.
MIMO systems promise to break this deadlock in the quest for
“gigabit” wireless through the use of multiple antennas at either
the transmitter or receiver or both. This potential has spurred
the inclusion of MIMO systems into upcoming wireless stan-
dards such as IEEE 802.11n and IEEE 802.16, which envision
replacement of hitherto wireline communication links by wire-
less ones. Excellent overviews of the state-of-the-art in MIMO
systems appear in [1] and [2].
Manuscript received April 26, 2005; revised July 15, 2005. This work was
supported by the National Science Foundation under Contract CCR-0086032
and Contract CCR-0120255 and by the Semiconductor Research Corporation
under Contract 2001-HJ-926 and Contract 2003-TJ-1093.
J. Paramesh was with Intel Corporation, Hillsboro, OR 97124 USA. He is
now with the Department of Electrical Engineering, University of Washington,
Seattle, WA 98105 USA (e-mail: Paramesh@ee.washington.edu).
R. Bishop and K. Soumyanath are with Intel Corporation, Hillsboro, OR
97124 USA (e-mail: Krishnamurthy.soumyanath@intel.com).
D. J. Allstot is with the Department of Electrical Engineering, University of
Washington, Seattle, WA 98105 USA (e-mail: Allstot@ee.washington.edu).
Digital Object Identifier 10.1109/JSSC.2005.857416
0018-9200/$20.00 © 2005 IEEE
2515
MIMO systems were originally conceived in the late
1930s and early 1940s with application to radar. Multiple-an-
tenna-based radar systems were proposed to enhance reception
of weak signals, enable direction finding, and increase immu-
nity to jamming. The basis for such an application was the
realization that an array of omnidirectional antenna elements
in conjunction with programmable delay elements or phase
shifters could mimic a directional antenna with a controllable
variable radiation pattern. Such a system, known as a phased
array or beamformer, often requires a priori knowledge of the
signal field. This basic concept was later extended to adaptive
or “smart” antenna systems wherein some aspect of signal
quality (e.g., SNR or SINR) could be optimized based on
real-time channel estimation. Extensive research has produced
a rich variety of optimization algorithms with different goals
and tradeoffs [3]. These approaches have found widespread
application in the areas of navigational aids, ground mapping,
weather detection, and, most notably, military applications.
The same concepts have also found application in wireless
communication with the goals of increased data rates, network
capacity, and quality of service. Typical wireless channels suffer
from fading, delay spread, and cochannel interference that ulti-
mately limit achievable data rates. Here again, antenna arrays
have played a key role in boosting signal quality through spa-
tial diversity [4], interference mitigation via spatial filtering, and
data rates with spatial multiplexing.
In this paper, a fully integrated four-channel beamforming/
spatial diversity receiver in a 90-nm CMOS technology is
presented. The remainder of this paper is organized as follows:
Section II gives a brief overview of MIMO systems including
their system-level benefits and implications for efficient fully
integrated CMOS implementations. Section III presents the
Cartesian combiner, which is the key circuit block required
for MIMO receivers for beamforming or spatial diversity ap-
plications. Section IV describes the CMOS implementation of
the four-channel prototype, and Section V provides measure-
ment results that quantify the array gain, SNR enhancement,
and interference mitigation properties of the multiple-antenna
receiver.
II. OVERVIEW OF MIMO SYSTEMS
A. Spatial Multiplexing [5], [6]
The most general MIMO system that uses antennas at
the transmitter and antennas at the receiver can be used to
transmit multiple independent data streams concurrently over
the same physical channel. This is referred to as an
2516 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

impinges on array element 1

at an angle (the look-angle) relative to the array normal. The
signal at the array element is then given by
, where is the relative time of flight be-
tween two adjacent elements, is the incident angle, and is the
propagation velocity of the wave. In a beamforming application,
the element spacing is often limited to a fraction of the car-
rier wavelength, i.e., . For a narrowband signal with
bandwidth , the array output for the system in Fig. 1(a)
can be expressed as

(1)

Finally, using the definition , the complex enve-

lope of the array output is derived as

(2)

Fig. 1. Beamformer theory. (a) Simple array. (b) Phased array using beam
steering. Theoretical array patterns with (c) no beam steering and (d) for a 30
look-angle.
spatially multiplexed MIMO system. In principle, distinct data
streams are transmitted from each transmit antenna, and conse-
quently, each antenna in the receive array receives signals from
all transmit antennas. When the channel is rich in multipath,
and when the line-of-sight factor between transmit and receive
arrays is small (such as in a typical office or home environment
where there is a large number of clustered scatterers), the data
streams may be separated at the receiver. In theory, then, a 2
2 MIMO system can double the data rate over a single-antenna
system with the same bandwidth. In practice, however, data rates
are lower than this upper bound when robustness issues associ-
ated with a specific implementation are considered [5].
B. Receive Spatial Diversity [4], [7]
Diversity receivers use multiple antennas at the receiver to
enhance signal quality in a multipath fading environment. The
receive antenna array consists of widely spaced elements so that
the fading at each element is uncorrelated to that at the other el-
ements. In a narrowband diversity receiver, complex weighting
circuits are inserted in each antenna path and programmed
via channel estimation hardware to an optimal set of weights
that maximizes SNR. This is called maximal-ratio combining
(MRC) in which the bit error rate (BER) at the receiver im-
proves as BER BER compared to the single-antenna case;
this corresponds to a logarithmic increase in channel capacity.
C. Receive Beamforming [8]
Fig. 1(a) shows an antenna array with isotropic ele-
ments separated by a distance from each other. A plane wave
The variable can be interpreted as equivalent to an “elec-
trical envelope phase shift” for each antenna input. Clearly, the
lowpass complex envelope of the array output is the product of
the complex envelope of the array input and an equivalent
array gain
(3)
Beam Steering: In the system of Fig. 1(b), programmable
phase shifts have been introduced in each channel such that the
envelope of the signal received by each array element is electri-
cally phase shifted by an angle relative to the previous adja-
cent element. The envelope of the array output can be expressed
as
(4)
i.e., the beam pattern rotates by an angle . This angle is equiv-
alent to a spatial angle . Thus, the
beam pattern now has a peak in the direction of the look-angle
. The relative spacing between the nulls remains the same as
before, but it is offset by an angle . Fig. 1(c) and (d) shows
the simulated array patterns (normalized to unity) for a four-el-
ement beamformer for two different cases. Notice that the array
pattern has a main lobe in the direction of the look-angle corre-
sponding to coherent signal addition and smaller side lobes in
other directions where the signals combine noncoherently. With
receive antennas, perfect cancellation occurs for signals in-
cident at specific angles. Thus, we can use this spa-
PARAMESH et al.: FOUR-ANTENNA RECEIVER IN 90-nm CMOS FOR BEAMFORMING AND SPATIAL DIVERSITY 2517

tial filtering property of antenna arrays to achieve interference

mitigation.

D. System Benefits
1) SNR Enhancement [9]: The elements in the antenna
array for a receive beamforming application are closely spaced
(typically ) so that the received signals are tightly
correlated in amplitude with well-defined time delays between
adjacent elements. In a beamforming receiver, programmable
delays (or programmable phase shifts for narrowband signals)
are inserted and the resultant coherent signals are summed.
Thus, the signals add in amplitude and any uncorrelated noise
signals from the different channels add in power. Consequently,
for every doubling in the number of antenna elements, up to
3 dB improvement in SNR is achieved when the additive noise
sources are uncorrelated.
2) Interference Cancellation [3]: The second key benefit of
multiple-antenna receivers is their ability to cancel cochannel
interference through the spatial filtering property. The simplest
case is when the signal field consists of a desired signal
and a cochannel interferer incident on the antenna array
at different angles and that are known a priori. The
antenna weights and can then be determined such that
the desired signals combine constructively (in-phase) and the
Fig. 2. (a) Using vector addition to obtain digitally programmable phase shifts.
interferers combine destructively (out-of-phase). This can be (b) Examples of first quadrant phase shifts. (c) Examples of third quadrant phase
accomplished by solving (please refer to the Appendix for shifts.
details)
where more diversity antennas are added without requiring ad-
ditional ADCs.

III. CARTESIAN-COMBINING TECHNIQUE

(5)
where . (LO) shifting. Phase shifters that are used in signal-shifting re-
It has been shown [3] that interference cancellation can be
achieved when only the direction of arrival (DOA) of the desired
signal is known. In principle, the DOA can be approximated
during channel estimation. Furthermore, with antennas in the
receive array, up to interferers may be cancelled without
having to estimate their DOAs.
E. Power Considerations in CMOS Implementations
The antenna weights for spatial diversity or beamforming ap-
plications are complex-valued scalars for narrowband signals.
Therefore, the signal processing required for each additional
antenna consists of the introduction of a programmable gain
and a programmable phase shift. The relative simplicity of the
required computation motivates the search for power-efficient
techniques that do not require an analog-to-digital converter
(ADC) for each antenna/receiver combination. Clearly, the so-
lution would be to implement the antenna weights as close as
possible to the antenna, i.e., at RF. This is in contrast to spatial
multiplexing systems that require complex digital processing
and, hence, the duplication of the ADC for each data stream.
The proposed RF combining technique can also be used as a
power-efficient range extender for spatial multiplexing systems
The weighting function in multiple-antenna receivers can be
implemented either through signal shifting or local oscillator
ceivers are expensive to implement in silicon [11] since they
generally occupy a large area, are lossy due to their passive na-
ture, and often do not achieve a full 360 phase-shift range. On
the other hand, LO-shifting architectures can be implemented
either with phase shifters in the LO path [12] or with multi-
phase oscillators in conjunction with phase selectors [9], [10].
The LO-shifting approach is attractive because it does not intro-
duce extra loss in the signal path. However, potential disadvan-
tages include the challenges of building high-performance phase
shifters in silicon and the resolution of the phase selectors.
In this section, the Cartesian combiner [13] that introduces
the antenna weight in the signal path by means of vector combi-
nations of variable-gain amplifier (VGA) outputs is described.
The development of the Cartesian combiner is depicted in Fig. 2
The complex weight in the channel could be
realized in its Cartesian form by means of VGAs
and a 90 phase-shift block. For example, to add a phase shift
corresponding to the first quadrant, the normalized gain of the
“real” amplifier is set to 1 with that of the “imaginary” amplifier
set to 1/2. When the outputs of these two amplifiers are added
in a vector fashion using a 90 phase shift, a phase-shift angle
of 26.5 is obtained. Similarly, to realize a phase shift in the
third quadrant, the gain of the “real” amplifier is programmed
2518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 3. Implementation of a phase-shifting downconverter.

Fig. 5. Cartesian combiner illustrated for a two-channel receiver.

Fig. 4. Architectural modification using signal-path linearity enables

combining the signals from two channels.

at 1/2 and that of the “imaginary” amplifier at 1; upon vector

addition through a 90 phase shift, a phase-shift angle of 243
is realized. Thus, we can synthesize arbitrary phase shifts in all
quadrants using VGAs whose gains can be sign inverted. How-
ever, 90 phase shifters that are realized using polyphase fil-
ters or lumped-element microwave couplers pose disadvantages
similar to those of conventional variable phase shifters. To over-
come these problems, we realize the 90 phase shift function in
the form of a complex downconversion. The signal processing
functions depicted in Fig. 2 are expressed as

(6)

which indicates that the each complex weight can be realized

using two VGAs followed by a quadrature downconversion.
The resultant architecture for this phase-shifting downconverter
is shown in Fig. 3. The magnitude and phase of the weight
are given by and ,
respectively.
The weighted signals from two antenna elements may be
combined as shown in Fig. 4. A major simplification is obtained
by observing that the complex downconversion is linear in the
signal path. Hence, signal combining may be implemented by
Fig. 6. (a) Simplified schematic of the VG-LNA. (b) Measured S-parameters.
appropriately summing the VGA outputs prior to mixing. Since
there are now only four mixers overall (as opposed to four
mixers per channel if combining is performed after the mixing), the programmability of its phase shift. 2) Note that for some
the routing and buffering of the LO signals to the mixers is values of phase shift, the gain of one of the two VGAs can be
vastly simplified. zero. However, the noise contribution of that VGA is nonzero.
The overall Cartesian combiner for two antennas is shown in The VG-LNA serves to absorb the variation in noise figure (NF)
Fig. 5. Note that the core of the combiner in each channel is with programmability in phase shifts. From a systems perspec-
preceded with a variable-gain low-noise amplifier (VG-LNA). tive, the VG-LNA has additional functions. For example, in a
Each VG-LNA performs two functions. 1) It decouples the pro- beamformer application, the array pattern may be tailored by ap-
grammability of the magnitude of each complex weight from plying weights of different magnitudes to each antenna element.
PARAMESH et al.: FOUR-ANTENNA RECEIVER IN 90-nm CMOS FOR BEAMFORMING AND SPATIAL DIVERSITY 2519

Fig. 9. 2–1–1 transformer.

Fig. 7. (a) Simplified schematic of the weight amplifiers. (b) Gain-control

DAC-associated bias circuits.

Fig. 10. Die microphotograph in a 90-nm CMOS technology.

Fig. 8. Simplified schematic of the Cartesian combiner on the “real” path. A

similar structure is used on the imaginary path.

In a diversity application using MRC, the optimum weight for a

narrowband signal requires programmable magnitudes.
There are several advantages to the Cartesian-combining ap-
proach. First, it is a simple method of extending single-antenna
receivers to diversity or beamforming receivers. The overhead
with respect to a single-antenna receiver is one VG-LNA and Fig. 11. Array pattern measurement setup.
two weight amplifiers (VGAs) per additional channel and two
extra mixers overall. This translates to an incremental increase IV. PROTOTYPE DESIGN
in die area and power consumption. Second, because the VGAs
are inherently broadband circuits, a full 360 phase shift can, in A. Variable-Gain Low-Noise Amplifier
principle, be achieved at any frequency [14]. Furthermore, the The VG-LNA (Fig. 6) is implemented using a differential in-
accuracy of the phase shift is limited only by the accuracy of the ductively source-degenerated structure. The variable gain func-
variable gains. Finally, as mentioned earlier, the routing of LO tionality is realized using differential pairs instead of a cascode
signals remains simple because the combining occurs before the device. The gain can be controlled by applying a differential
mixers. voltage across these differential pairs to divert some of the signal
2520 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 12. Measured array patterns for (a) broadside (0 ), (b) 30 , and (c) 90 incidence angles.

current to the power supply. The gain control is achieved using TABLE I
PERFORMANCE SUMMARY
a 6-bit digital-to-analog converter (DAC) and can be varied lin-
early over a 40-dB range with respect to the control code. An
unbuffered standalone VG-LNA without gate tuning was mea-
sured on a probe station with the addition of a simulated gate-
tuning inductor in the vector network analyzer. The gain of the
VG-LNA was 12.2 dB at 4.93 GHz [Fig. 6(b)] and NF was
estimated to be about 2 dB; the equivalent gain of a buffered
VG-LNA is 23 dB.

B. Weight Amplifiers and Gain Control

The weight amplifiers are also implemented using differen-
tial pairs as shown in Fig. 7(a). Because the gain of each am-
plifier must be invertible in sign, the variable gain feature is im-
plemented using a cross-coupled quad. The differential control
voltage is also generated through 6-bit DACs. Each DAC is a
segmented current-steering type with four thermometer-coded
most significant bits (MSBs) and two binary-coded least signif- erated by means of an op-amp-based current source that uses a
icant bits (LSBs). The reference current for each DAC is gen- resistor identical to the load resistor in the DAC [Fig. 7(b)].
PARAMESH et al.: FOUR-ANTENNA RECEIVER IN 90-nm CMOS FOR BEAMFORMING AND SPATIAL DIVERSITY
Fig. 13. Measured SNR improvement when a second channel is enabled.
C. Cartesian Combiner Core
Fig. 8 shows the implementation of one half of the Cartesian
combiner. The weighted currents from the “real” amplifiers are
summed in the current domain and fed into the primary winding
of a three-winding transformer. The secondary windings of the
transformer are fed to two Gilbert cells that are controlled by
quadrature phases of the local oscillator. An identical structure
is used to combine the “imaginary” path signals, and the outputs
of the Gilbert cells are summed in the current domain. This cur-
rent is then converted into a differential voltage by PMOS loads
whose common-mode voltage is controlled by a Miller-com-
pensated feedback loop. The 2–1–1 transformer shown in Fig. 9
consists of a four-turn primary and two symmetrical two-turn
secondary windings. The primary winding uses four turns of the
top metal layer M7 and each secondary winding consists of two
turns of M5 strapped with M4.
A four-channel prototype of the chip (Fig. 10) was fabricated
in a 90-nm CMOS process [15]. Each channel consisting of a
VG-LNA and a pair of weighting amplifiers is oriented symmet-
rically around the summing inputs to the core of the combiner
that is located at the center of the die. The entire receiver draws
140 mW from a single 1.4-V power supply.
V. MEASUREMENTS
The prototype was wafer-probed using a Cascade Microtech
membrane with 88 pads. The measurements focus on two areas
that demonstrate the major motivations for using beamforming
2521
or diversity multi-antenna receivers; namely, array gain and in-
terference cancellation. To demonstrate array gain and the as-
sociated benefits of SNR enhancement, off-chip variable phase
shifters were used at the input of each channel (Fig. 11) to
mimic a plane wave impinging on an antenna array with a pro-
grammable DOA. In all measurements, we imitate a linear array
with omnidirectional elements and spacing . The
weight controls on the receiver are then swept to measure the
array gain, which shows the measured array patterns for 0 ,
30 , and 90 angles of incidence with all four channels enabled
(Fig. 12). It is observed that the main lobe has a peak in the
“look” direction and the nulls appear in the locations predicted
by simple theory in accordance with (2). For example, at 30
incidence, two nulls appear at 0 and 90 ; the first null is due to
signal cancellation between antenna pairs (1, 3) and (2, 4) and
the other null is due to cancellation between antenna pairs (1, 2)
and (3, 4). The total array gain due to all four channels is mea-
sured at 12 dB as expected from theory (Table I).
To demonstrate the SNR enhancement property, modulated
signals were input to the receiver using a vector signal gener-
ator. A vector signal analyzer (VSA) is used to demodulate the
downconverted signals from the output of the receiver. Because
the VSA has a priori knowledge of the input bit-stream, it is
able to calculate the output SNR based on an internal BER cal-
culation. Fig. 13 shows the results of this measurement for a
64-quadrature amplitude modulation modulated signal incident
at 30 ; the SNR improves from 24.1 dB to about 30 dB when
all four channels are enabled.
2522
Fig. 14. Measured interference cancellation when a second channel is enabled.
To demonstrate interference cancellation, a “desired”
64-QAM modulated signal, along with a multitone interferer
separated by 5 MHz at 30 incidence relative to the desired
signal, is inputted to the receiver. The in-phase and quadrature
( ) output from the receiver is measured using a VSA
whose measurement bandwidth is set equal to the span; that is,
filtering is not performed to further attenuate the interferer prior
to demodulation. The weights on the receiver are adjusted so as
to cause signal addition for the desired signal and cancellation
of the interferer. This has the effect of attenuating the interferer
by more than 20 dB (Fig. 14) and boosting the desired signal by
6 dB. This interference cancellation property may be extended
to include cancellation of three interferers concurrently with
four-way in-phase signal addition by using all four channels.
In principle, any interferer that remains static during a given
packet interval may be attenuated as long as its angle of arrival
is different from that of the desired signal; this can include
cochannel interference or an image signal. Computation of the
required gain settings ( , ) is typically performed during
the preamble of most wireless LAN (WLAN) standards.
VI. CONCLUSION
The feasibility of fully integrated multi-antenna receivers in
a deep-submicron CMOS technology has been demonstrated.
Primarily intended for beamforming or spatial diversity appli-
cations, this receiver can potentially be used as a low-power
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
range extender to spatial-multiplexing MIMO systems. The
Cartesian-combining technique that utilizes vector combina-
tions of variable-gain elements realizes the antenna weights in
a compact power-efficient manner. Experimental results from
a four-channel prototype show an array gain of 12 dB with
a peak-to-null ratio of 20 dB and an SNR improvement of
6 dB over a single-antenna receiver. This receiver also achieves
a full 360 look-angle coverage. The ability of multi-antenna
receivers to achieve interference cancellation is a key advantage
over their single-antenna counterparts. It is also demonstrated
that an interferer may be attenuated by more than 20 dB with
two operational antennas. While this is strictly true only for
cochannel interferers, the multi-antenna receiver is also able
to reject signals over a small fractional bandwidth around the
desired channel.
APPENDIX
WEIGHT CALCULATIONS FOR INTERFERENCE CANCELLATION
This appendix describes the method used to calculate the an-
tenna weights for cancellation of an interferer incident at
a different angle from a desired signal . While this anal-
ysis is strictly valid only for cochannel interference (
below), it can be extended for an interferer at a small offset fre-
quency with respect to the desired signal. Let and denote
the angle of incidence of the desired signal and the interferer,
PARAMESH et al.: FOUR-ANTENNA RECEIVER IN 90-nm CMOS FOR BEAMFORMING AND SPATIAL DIVERSITY
respectively. We consider the case when only two channels are
operational. The total input signal at the two antennas is
(A1)
and
(A2)
where . Let and denote the com-
plex weights in the two antenna paths. The complex interme-
diate frequency (IF) signal may then be written as
(A3)
The goal is to determine the antenna weights such that the
desired signal combines constructively without distortion and
the interferer combines destructively; this is accomplished by
solving
(A4)
This cancellation assumes that the desired signal and the in-
terferer are incident at different angles.
ACKNOWLEDGMENT
The authors would like to thank C. Le, D. Martin, D. Trammo,
P. Hack, R. Hoelle, D. Ackelson, and M. Dibbattista of Intel
Corporation for their contributions. They would also like to
thank the staffs at the System-on-Chip Laboratory at UW and
the Communication Circuits Laboratory at Intel. J. Paramesh
is grateful to D. Somasekhar of Intel Corporation for helpful
technical discussions throughout this project.
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Jeyanandh Paramesh (M’98) received the B.Tech.
degree from the Indian Institute of Technology,
Madras, India, in 1996, and the M.S. degree from
Oregon State University, Corvallis, in 1998, both
in electrical engineering. He is currently working
toward the Ph.D. degree at the University of Wash-
ington, Seattle.
He was employed at AKM Semiconductor
(Analog Devices), San Diego, CA, and Motorola,
Austin, TX. He is currently with the University of
Washington. His research interests include MIMO
transceivers and sigma–delta data converters in addition to circuit design of
other kinds. He has also been employed as a Graduate Student Researcher with
the Communication Technology Laboratories, Intel Corporation, Hillsboro,
OR.
Mr. Paramesh was a recipient of the Chevron Engineering Scholarship (1997),
the Intel Foundation Doctoral Fellowship (2003–2004), and the Analog Devices
Outstanding Student Designer Award (2005).
Ralph Bishop received the associate degree from the
Oregon Institute of Technology and has also attended
Oregon State University, Corvallis.
He is the Lead Technician in the Communication
Circuits Laboratory, Intel Corporation, Hillsboro,
OR.
2524
K. Soumyanath (M’93) received the B.E. degree
in electronics and communication engineering from
the Regional Engineering College, Tiruchirappalli,
India, in 1979, the M.S. degree in electronics from
the Indian Institute of Science, Bangalore, India,
in 1985, and the Ph.D. degree in computer science
from the University of Nebraska at Lincoln in 1993.
Since 1996, he has been with Intel Corporation,
Hillsboro, OR, where he is a Senior Principal Engi-
neer and is the Director of the Communications Cir-
cuits Laboratory. He has published over 40 papers in
VLSI circuits and related areas and has 30 patents issued with several pending.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
David J. Allstot (S’72–M’72–SM’83–F’92) re-
ceived the B.S. degree from the University of
Portland, Portland, OR, the M.S. degree from
Oregon State University, Corvallis, and the Ph.D.
degree from the University of California, Berkeley.
He has held several industrial and academic
positions and has been the Boeing–Egtvedt Chair
Professor of Engineering at the University of Wash-
ington, Seattle, since 1999; he is currently Chair of
the Department of Electrical Engineering. He has
advised approximately 80 M.S. and Ph.D. graduates
and published more than 225 papers.
Dr. Allstot was the recipient of several outstanding teaching and advising
awards. His awards include the IEEE W. R. G. Baker Prize Paper Award in
1978, the IEEE Circuits and Systems Society Darlington Best Paper Award in
1995, the IEEE International Solid-State Circuits Conference Beatrice Winner
Award in 1998, the IEEE Circuits and Systems Society Golden Jubilee Medal
in 1999, the Technical Achievement Award of the IEEE Circuits and Systems
Society in 2004, and the Aristotle Award of the Semiconductor Research Cor-
poration in 2005. His professional service includes Associate Editor for the
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL
SIGNAL PROCESSING from 1990 to 1993, Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING from
1993 to 1995, a member of the Technical Program Committee of the IEEE
Custom IC Conference from 1990 to 1993, a member of the Board of Gov-
ernors of the IEEE Circuits and Systems Society from 1992 to 1995, a member
of the Technical Program Committee of the IEEE International Solid-State Cir-
cuits Conference from 1994 to 2004, Executive Committee Member and Short
Course Chair of the IEEE International Solid-State Circuits Conference from
1996 to 2000, Distinguished Lecturer of the IEEE Circuits and Systems Society
from 2000 to 2001, and Co-General Chair of the IEEE International Sympo-
sium on Circuits and Systems in 2002. He is a member of Eta Kappa Nu and
Sigma Xi.