Chapter 07 ISM PDF

Exercise 7–1
Ex: 7.1 Refer to Fig. 7.2(a) and 7.2(b). Av = −k n VOV RD

Coordinates of point A: Vt and VDD ; thus 0.4 V −10 = −0.4 × 10 × VOV × 17.5
and 1.8 V. To determine the coordinates of
Thus,
point B, we use Eqs. (7.7) and (7.8) as follows:
√ VOV = 0.14 V
2k n RD VDD + 1 − 1
VOV B =
k n RD VGS = Vt + VOV = 0.4 + 0.14 = 0.54 V
√
2 × 4 × 17.5 × 1.8 + 1 − 1 1 W
= ID = k n 2
VOV
4 × 17.5 2 L
= 0.213 V 1
= × 0.4 × 10 × 0.142 = 0.04 mA
2
Thus,
RD = 17.5 k
VGS B = Vt + VOV B = 0.4 + 0.213 = 0.613 V
VDS = VDD − RD ID
and
= 1.8 − 17.5 × 0.04 = 1.1 V
VDS B = VOV B = 0.213 V
Thus, coordinates of B are 0.613 V and 0.213 V. Ex: 7.3
At point C, the MOSFET is operating in the triode IC RC
Av = −
region, thus VT

1 1 × RC
iD = k n (v GS C − Vt )v DS C − v 2DS C −320 = − ⇒ RC = 8 k
2 0.025
VC = VCC − IC RC
If v DS C is very small,
= 10 − 1 × 8 = 2 V
iD k n (v GS C − Vt )v DS C
Since the collector voltage is allowed to decrease
= 4(1.8 − 0.4)v DS C
to +0.3 V, the largest negative swing allowed at

= 5.6v DS C , mA the output is 2 − 0.3 = 1.7 V. The corresponding
input signal amplitude can be found by dividing
But 1.7 V by the gain magnitude (320 V/V), resulting

VDD − v DS C VDD 1.8 in 5.3 mV.
iD = = = 0.1 mA
RD RD 17.5
Ex: 7.4
0.1
Thus, v DS C = = 0.018 V = 18 mV, which
5.6 5 V
is indeed very small, as assumed.
Ex: 7.2 Refer to Example 7.1 and Fig. 7.4(a). RD

RG
Design 1: vo
VOV = 0.2 V, VGS = 0.6 V

vi
ID = 0.8 mA
Now,
Av = −k n VOV RD
Thus,
Refer to the solution of Example 7.3. From
−10 = −0.4 × 10 × 0.2 × RD vo
Eq. (7.47), Av ≡ = −gm RD (note that RL
vi
⇒ RD = 12.5 k is absent).
VDS = VDD − RD ID Thus,
= 1.8 − 12.5 × 0.08 = 0.8 V gm RD = 25
Design 2: Substituting for gm = k n VOV , we have
RD = 17.5 k k n VOV RD = 25
SEDRA-ISM: “E-CH07” — 2014/11/8 — 14:02 — PAGE 1 — #1

Exercise 7–2
vt vt
where k n = 1 mA/V2 , thus it = +i = + gm v t
ro ro
VOV RD = 25 (1) vt 1
∴ Req = = ro
Next, consider the bias equation it gm
VGS = VDS = VDD − RD ID
Thus, Ex: 7.6
Vt + VOV = VDD − RD ID
Substituting Vt = 0.7 V, VDD = 5 V, and VDD
1 1 1 2
ID = k n VOV
2
= × 1 × VOV 2
= VOV
2 2 2
we obtain iD RD
1 2
0.7 + VOV = 5 − VOV RD (2) vDS
2 vgs
Equations (1) and (2) can be solved to obtain

VOV = 0.319 V
vGS
and
VGS
RD = 78.5 k
The dc current ID can be now found as
1
ID = k n VOV
2
= 50.9 μA VDD = 5 V
2
To determine the required value of RG we use Eq. VGS = 2 V
(7.48), again noting that RL is absent:
Vt = 1 V
RG
Rin = λ=0
1 + gm RD
RG k n = 20 μA/V2
0.5 M =
1 + 25 RD = 10 k
⇒ RG = 13 M W
= 20
Finally, the maximum allowable input signal v̂ i L
can be found as follows: (a) VGS = 2 V ⇒ VOV = 1 V
Vt 0.7 V 1 W 2
v̂ i = = = 27 mV ID = k V = 200 μA
|Av | + 1 25 + 1 2 n L OV
VDS = VDD − ID RD = +3 V
Ex: 7.5 W
(b) gm = k n VOV = 400 μA/V = 0.4 mA/V
L
v ds
(c) Av = = −gm RD = −4 V/V
v gs
D Req it
(d) v gs = 0.2 sinωt V
vt
v ds = −0.8 sinωt V
0
i v DS = VDS + v ds ⇒ 2.2 V ≤ v DS ≤ 3.8 V
ro (e) Using Eq. (7.28), we obtain
G
1
1 iD = k n (VGS − Vt )2
i 2
gm 1
+ k n (VGS − Vt )v gs + k n v 2gs
2
S iD = 200 + 80 sinωt
+ 8 sin2 ωt, μA

Exercise 7–3
= [200 + 80 sinωt + (4 − 4 cos2ωt)] 1 16

= × 60 × × (1.6 − 1)2
2 0.8
= 204 + 80 sinωt − 4 cos2ωt, μA
ID = 216 μA
ID shifts by 4 μA. 2 ID 2 × 216
gm = = = 720 μA/V
Thus, |VOV | 1.6 − 1
î2ω 4 μA = 0.72 mA/V

2HD = = = 0.05 (5%)
îω 80 μA 1 1
λ = 0.04 ⇒ VA = = = 25 V/μm
λ 0.04
Ex: 7.7 VA × L 25 × 0.8
ro = = = 92.6 k
2 ID ID 0.216
(a) gm =
VOV
1 W 2 1 Ex: 7.11
ID = k V = × 60 × 40 × (1.5 − 1)2
2 n L OV 2 2 ID VA 2VA
ID = 300 μA = 0.3 mA, VOV = 0.5 V gm ro = × =
VOV ID VOV
2 × 0.3 VA × L = VA
gm = = 1.2 mA/V
0.5
2 × 12.5 × 0.8
VA 15 L = 0.8 μm ⇒ gm ro =
ro = = = 50 k 0.2
ID 0.3
= 100 V/V
W
(b) ID = 0.5 mA ⇒ gm = 2 μn Cox ID
L
Ex: 7.12
= 2 × 60 × 40 × 0.5 × 103
∂iC
Given: gm =
gm = 1.55 mA/V ∂v BE iC = IC
VA 15
ro = = = 30 k where IC = IS eVBE /VT
ID 0.5
∂iC IS eVBE /VT IC
= =
Ex: 7.8 ∂v BE VT VT
Thus,
ID = 0.1 mA, gm = 1 mA/V, k n = 50 μA/V2
IC
2 ID 2 × 0.1 gm =
gm = ⇒ VOV = = 0.2 V VT
VOV 1
1 W 2 W 2 ID
ID = k V ⇒ = 2
2 n L OV L k n VOV Ex: 7.13
IC 0.5 mA
2 × 0.1 gm = = = 20 mA/V
= = 100 VT 25 mV
50
× 0.22
1000
Ex: 7.14
Ex: 7.9
W IC = 0.5 mA (constant)
gm = μn Cox VOV
L β = 50 β = 200
Same bias conditions, so same VOV and also same IC 0.5 mA
L and gm for both PMOS and NMOS. gm = =
VT 25 mV
μp Wn = 20 mA/V = 20 mA/V
μn Cox Wn = μp Cox Wp ⇒ = 0.4 =
μn Wp
IC 0.5 0.5
Wp IB = = =
⇒ = 2.5 β 50 200
Wn = 10 μA = 2.5 μA
β 50 200
Ex: 7.10 rπ = = =
gm 20 20
1 W
ID = k p (VSG − |Vt |)2 = 2.5 k = 10 k
2 L

Exercise 7–4
v be
Ex: 7.15 ic = βib = β
rπ
β = 100 IC = 1 mA
β
= v be = gm v be
1 mA rπ
gm = = 40 mA/V
25 mV v be
ie = ib + βib = (β + 1)ib = (β + 1)
VT αVT 25 mV rπ
re = = = 25
IE IC 1 mA v be v be
= =
β 100 rπ (β + 1) re
rπ = = = 2.5 k
gm 40
Ex: 7.18
Ex: 7.16
IC 1 mA C
gm = = = 40 mA/V
VT 25 mV
v ce
Av = = −gm RC gmvbe
v be
= −40 × 10 ib
B
= −400 V/V
re
VC = VCC − IC RC vbe
= 15 − 1 × 10 = 5 V

v C (t) = VC + v c (t) E
= (VCC − IC RC ) + Av v be (t)
v be
= (15 − 10) − 400 × 0.005 sinωt ib = − gm v be
re

= 5 − 2 sinωt 1
= v be − gm
re
iB (t) = IB + ib (t)
1 β
where = v be −
rπ/β+1 rπ
IC 1 mA
IB = = = 10 μA β +1 β v be
β 100 = v be − =
rπ rπ rπ
gm v be (t)
and ib (t) =
β
Ex: 7.19
40 × 0.005 sinωt
=
100
10 V
= 2 sinωt, μA
Thus,
iB (t) = 10 + 2 sinωt, μA RE 10 k
CC1
Ex: 7.17
vi
ib ic
CC2
B C vo

vbe rp bib
RC 7.5 k

10 V
E

Exercise 7–5
10 − 0.7 VE = −0.1 − 0.7 = −0.8 V

IE = = 0.93 mA
10
IC 0.99
IC = αIE = 0.99 × 0.93 (b) gm = = 40 mA/V
VT 0.025
= 0.92 mA
β 100
rπ = = 2.5 k
VC = −10 + IC RC gm 40
= −10 + 0.92 × 7.5 = −3.1 V VA 100
ro = = = 101 100 k
vo αRC IC 0.99
Av = =
vi re (c) Rsig = 2 k RB = 10 k rπ = 2.5 k
25 mV
where re = = 26.9 gm = 40 mA/V
0.93 mA
0.99 × 7.5 × 103 RC = 8 k RL = 8 k ro = 100 k
Av = = 276.2 V/V
26.9 Vy Vπ Vy
= ×
For v̂ i = 10 mV, v̂ o = 276.2 × 10 = 2.76 V Vsig Vsig Vπ
RB rπ
= × −gm (RC RL ro )
Ex: 7.20 (RB rπ ) + Rsig
10 2.5
10V = × −40(8 8 100)
(10 2.5) + 2
−0.5 × 40 × 3.846 = −77 V/V
8 k Vy
If ro is negelected, = −80, for an error
Vsig
Y of 3.9%.

X
Ex: 7.21
2ID 2 × 0.25
10 k Z gm = = = 2 mA/V
VOV 0.25
I 1 mA Rin = ∞
Av o = −gm RD = −2 × 20 = −40 V/V
Ro = RD = 20 k
RL 20
IE = 1 mA Av = Av o = −40 ×
RL + Ro 20 + 20
100
IC = × 1 = 0.99 mA = −20 V/V
101
1 Gv = Av = −20 V/V
IB = × 1 = 0.0099 mA
101 v̂ i = 0.1 × 2VOV = 0.2 × 2 × 0.25 = 0.05 V
(a) VC = 10 − 8 × 0.99 = 2.08 2.1 V
v̂ o = 0.05 × 20 = 1 V
VB = −10 × 0.0099 = −0.099 −0.1 V
This figure belongs to Exercise 7.20c.

Rsig
X Y

Vsig Vp Vy

RB rp gmVp ro RC RL


Exercise 7–6
Ex: 7.22
IC = 0.5 mA
IC 0.5 mA
gm = = = 20 mA/V Rsig îb îe /(b 1)
VT 0.025 V
β 100
rπ = = = 5 k îe vˆ p re
gm 20
Rin = rπ = 5 k vˆp re
Av o = −gm RC = −20 × 10 = −200 V/V

vˆsig E
Ro = RC = 10 k
RL 5 Re
Av = Av o = −200 ×
RL + Ro 5 + 10
= −66.7 V/V
Rin 5
Gv = Av = × −66.7
Rin + Rsig 5+5
= −33.3 V/V For IC = 0.5 mA and β = 100,
v̂ π = 5 mV ⇒ v̂ sig = 2 × 5 = 10 mV VT αVT 0.99 × 25

re = = = 50
IE IC 0.5
v̂ o = 10 × 33.3 = 0.33 V
rπ = (β + 1)re 5 k
Although a larger fraction of the input signal
For v̂ sig = 100 mV, Rsig = 10 k and with v̂ π
reaches the amplifier input, linearity
limited to 10 mV, the value of Re required can be
considerations cause the output signal to be in
found from
fact smaller than in the original design!
Re 10
100 = 10 1 + +
50 5
Ex: 7.23 Refer to the solution to Exercise 7.21. If ⇒ Re = 350
v̂ sig = 0.2 V and we wish to keep v̂ gs = 50 mV,
Rin = (β + 1)(re + Re ) = 101 × (50 + 350)
3
then we need to connect a resistance Rs = in = 40.4 k
gm
the source lead. Thus, RC RL
Gv = −β
3 Rsig + (β + 1)(re + Re )
Rs = = 1.5 k
2 mA/V 10
= −100 = −19.8 V/V
RD RL 10 + 101 × 0.4
Gv = Av = −
1
+ Rs
gm
Ex: 7.25
2020
=− = −5 V/V 1
0.5 + 1.5 = Rsig = 100
gm
v̂ o = Gv v̂ sig = 5 × 0.2 = 1 V (unchanged)
1
⇒ gm = = 10 mA/V
0.1 k
But
Ex: 7.24
2ID
gm =
From the following figure we see that VOV
v̂ sig = îb Rsig + v̂ π + îe Re Thus,
ie 2ID
= Rsig + v̂ π + îe Re 10 =
β +1 0.2
⇒ ID = 1 mA
v̂ π v̂ π
= Rsig + v̂ π + Re Rin
(β + 1)re re Gv = × gm RD
Rin + Rsig
Re Rsig
v̂ sig = v̂ π 1 + + Q.E.D = 0.5 × 10 × 2 = 10 V/V
re rπ

Exercise 7–7
Ex: 7.26 1
= 200
gm
IC = 1 mA
⇒ gm = 5 mA/V
VT VT 25 mV
re = = = 25 But
IE IC 1 mA
Rin = re = 25 W
gm = k n VOV
L
Av o = gm RC = 40 × 5 = 200 V/V
Thus,
Ro = RC = 5 k
W
RL 5 5 = 0.4 × × 0.25
Av = Av o = 200 × = 100 V/V L
RL + Ro 5+5 W
⇒ = 50
Rin L
Gv = × Av
Rin + Rsig 1 W 2
ID = k n VOV
25 2 L
= × 100 = 0.5 V/V
25 + 5000 1
= × 0.4 × 50 × 0.252
2
Ex: 7.27 = 0.625 mA
Rin = re = 50 RL = 1 k to 10 k
VT 25 mV Correspondingly,
⇒ IE = = = 0.5 mA
re 50 RL RL
Gv = =
IC IE = 0.5 mA RL + Ro RL + 0.2
RC RL will range from
Gv =
re + Rsig 1
Gv = = 0.83 V/V
RC RL 1 + 0.2
40 =
(50 + 50) to
RC RL = 4 k 10
Gv = = 0.98 V/V
10 + 0.2
Ex: 7.28 Refer to Fig. 7.41(c).

Ro = 100
Thus, Ex: 7.30
1 IC = 5 mA
= 100 ⇒ gm = 10 mA/V
gm VT VT 25 mV
re = = =5
But IE IC 5 mA
2ID Rsig = 10 k RL = 1 k
gm =
VOV Rin = (β + 1) (re + RL )
Thus,
= 101 × (0.005 + 1)
10 × 0.25
ID = = 1.25 mA = 101.5 k
2
RL 1 Gv o = 1 V/V
v̂ o = v̂ i × =1× = 0.91 V
RL + Ro 1 + 0.1 Rsig
Rout = re +
1 β +1
gm 0.1 10,000
v̂ gs = v̂ i =1× = 91 mV =5+ = 104
1 0.1 + 1
+ RL 101
gm
RL RL
Gv = =
Rsig RL + Rout
RL + re +
β +1
Ex: 7.29
1
Ro = 200 = = 0.91 V/V
1 + 0.104

Exercise 7–8
re
vπ = vsig VS = −5 + 6.2 × 0.49 = −1.96 V
Rsig
re + RL +
β +1 VD = 5 − 6.2 × 0.49 = +1.96 V

RL Rsig RG should be selected in the range of 1 M to
v̂ sig = v̂ π 1 + +
re (β + 1) re 10 M to have low current.

1000 10,000
v̂ sig =5 1+ + = 1.1 V/V
5 101 × 5
Ex: 7.33
Correspondingly,
1 W 2
v̂ o = Gv × 1.1 = 0.91 × 1.1 = 1 V ID = 0.5 mA = k V
2 n L OV
0.5 × 2
⇒ VOV
2
= =1
1
Ex: 7.31
⇒ VOV = 1 V ⇒ VGS = 1 + 1 = 2 V
1 W
ID = k n (VGS − Vt )2 5−2
2 L = VD ⇒ RD = = 6 k
0.5
1
0.5 = × 1(VGS − 1)2 ⇒ RD = 6.2 k (standard value). For this RD we
2 have to recalculate ID :
⇒ VGS = 2 V 1
ID = × 1 × (VGS − 1)2
If Vt = 1.5 V, then 2
1
1 = (VDD − RD ID − 1)2
ID = × 1 × (2 − 1.5)2 = 0.125 mA 2
2
(VGS = VD = VDD − RD ID )
ID 0.125 − 0.5
⇒ = = −0.75 = −75% 1
ID 0.5 ID = (4 − 6.2 ID )2 ⇒ ID ∼
= 0.49 mA
2
VD = 5 − 6.2 × 0.49 = 1.96 V
Ex: 7.32
VDD − VD 5−2
RD = = = 6 k
ID 0.5 Ex: 7.34 Refer to Example 7.12.
→ RD = 6.2 k (a) For design 1, RE = 3 k, R1 = 80 k, and
R2 = 40 k. Thus, VBB = 4 V.
1 W 2 1
ID = k V ⇒ 0.5 = × 1 × VOV
2
VBB − VBE
2 n L OV 2 IE =
R1 R2
⇒ VOV = 1 V RE +
β +1
⇒ VGS = VOV + Vt = 1 + 1 = 2 V For the nominal case, β = 100 and
⇒ VS = −2 V 4 − 0.7
IE = = 1.01 1 mA
4080
VS − VSS −2 − (−5) 3+
RS = = = 6 k 101
ID 0.5
For β = 50,
→ RS = 6.2 k
4 − 0.7
If we choose RD = RS = 6.2 k, then ID will IE = = 0.94 mA
4080
change slightly: 3+
51
ID =
1
× 1 × (VGS − 1)2 . Also For β = 150,
2 4 − 0.7
VGS = −VS = 5 − RS ID IE = = 1.04 mA
4080
3+
2 ID = (4 − 6.2 ID )2 151
Thus, IE varies over a range approximately 10%
⇒ 38.44 ID2 − 51.6 ID2 + 16 = 0
of the nominal value of 1 mA.
⇒ ID = 0.49 mA, 0.86 mA
(b) For design 2, RE = 3.3 k, R1 = 8 k, and
ID = 0.86 results in VS > 0 or VS > VG , which is R2 = 4 k. Thus, VBB = 4 V. For the nominal
not acceptable. Therefore ID = 0.49 mA and case, β = 100 and

Exercise 7–9
4 − 0.7 To maintain active-mode operation at all times,

IE = = 0.99 1 mA
48 the collector voltage should not be allowed
3.3 +
101 to fall below the value that causes the CBJ to
For β = 50, become forward biased, namely, −0.4 V.
4 − 0.7 Thus, the lowest possible dc voltage at the
IE = = 0.984 mA collector is −0.4 V + 2V = +1.6 V.
48
3.3 + Correspondingly,
51
10 − 1.6 10 − 1.6
For β = 150, RC = = 8.4 k
IC 1 mA
4 − 0.7
IE = = 0.995 mA
48
3.3 + Ex: 7.36 Refer to Fig. 7.54. For IE = 1 mA and
151
VC = 2.3 V,
Thus, IE varies over a range of 1.1% of the
nominal value of 1 mA. Note that lowering VCC − VC
IE =
the resistances of the voltage divider considerably RC
decreases the dependence on the value of β, a 10 − 2.3
highly desirable result obtained at the expense 1=
RC
of increased current and hence power
dissipation. ⇒ RC = 7.7 k
Now, using Eq. (7.147), we obtain
Ex: 7.35 Refer to Fig. 7.53. Since the circuit is to VCC − VBE
IE =
be used as a common-base amplifier, we can RB
RC +
dispense with RB altogether and ground the base; β +1
thus RB = 0. The circuit takes the form shown in 10 − 0.7
the figure below. 1=
RB
7.7 +
101
10 V ⇒ RB = 162 k
Selecting standard 5% resistors (Appendix J), we
use
RC
RB = 160 k and RC = 7.5 k
vo The resulting value of IE is found as
10 − 0.7
IE = = 1.02 mA
160
7.5 +
101
and the collector voltage will be
RE vi
VC = VCC − IE RC = 2.3 V
Ex: 7.37 Refer to Fig. 7.55(b).

5V
VS = 3.5 and ID = 0.5 mA; thus
VS 3.5
To establish IE = 1mA, RS = = = 7 k
ID 0.5
5 − VBE
IE = VDD = 15 V and VD = 6 V; thus
RE
VDD − VD 15 − 6
5 − 0.7 RD = = = 18 k
1 mA = ID 0.5 mA
RE
To obtain VOV , we use
⇒ RE = 4.3 k
vo 1
The voltage gain = gm RC , where gm =
IC
= ID = k n VOV
2
vi VT 2
40 mA/V. To maximize the voltage gain, we 1
0.5 = × 4VOV 2
select RC as large as possible, consistent with 2

obtaining a ±2-V signal swing at the collector. ⇒ VOV = 0.5 V

Exercise 7–10
Thus, Ex: 7.40 Refer to Fig. 7.56(a). For VB = 5 V and

50-μA current through RB2 , we have
VGS = Vt + VOV = 1 + 0.5 = 1.5 V
5V
We now can obtain the dc voltage required at the RB2 = = 100 k
0.05 mA
gate,
The base current is
VG = VS + VGS = 3.5 + 1.5 = 5 V IE 0.5 mA
IB = = 5 μA
Using a current of 2 μA in the voltage divider, we β +1 100
have The current through RB1 is
5V
RG2 = = 2.5 M IRB1 = IB + IRB2 = 5 + 50 = 55 μA
2 μA
The voltage drop across RG1 is 10 V, thus Since the voltage drop across RB1 is
VCC − VB = 10 V, the value of RB1 can be
10 V found from
RG1 = = 5 M
2 μA 10 V
RB1 = = 182 k
This completes the bias design. To obtain gm and 0.055 μA
ro , we use
The value of RE can be found from
2ID 2 × 0.5
gm = = = 2 mA/V VB − VBE
VOV 0.5 IE =
RE
VA 100
ro = = = 200 k 5 − 0.7
ID 0.5 ⇒ RE = = 8.6 k
0.5
The value of RC can be found from
Ex: 7.38 Refer to Fig. 7.55(a) and (c) and to the VC = VCC − IC RC
values found in the solution to Exercise 7.37 6 = 15 − 0.99 × 0.5 × RC
above.
RC 18 k
Rin = RG1 RG2 = 52.5 = 1.67 M
This completes the bias design. The values of gm ,
Ro = RD ro = 18200 = 16.5 k rπ , and ro can be found as follows:
Rin IC 0.5 mA
Gv = − gm (ro RD RL ) gm = = 20 mA/V
Rin + Rsig VT 0.025 V
1.67 β 100
=− × 2 × (2001820) rπ = = = 5 k
1.67 + 0.1 gm 20
= −17.1 V/V VA 100
ro = = 200 k
IC 0.5
Ex: 7.39 To reduce v gs to half its value, the Ex: 7.41 Refer to Fig. 7.56(b) and to the solution
unbypassed Rs is given by of Exercise 7.40 above.
1 Rin = RB1 RB2 rπ
Rs =
gm
= 182 100 5 = 4.64 k
From the solution to Exercise 7.37 above,
gm = 2 mA/V. Thus Ro = RC ro = 18 200 = 16.51 k
1 Rin
Rs = = 0.5 k Gv = − gm (RC RL ro )
2 Rin + Rsig
Neglecting ro , Gv is given by 4.64
Gv = − × 20 × (18 20 200)
4.64 + 10
Rin RD RL
Gv = − ×− = −57.3 V/V
Rin + Rsig 1
+ Rs
gm
Ex: 7.42 Refer to the solutions of Exercises 7.40
1.67 1820
=− × and 7.41 above. With Re included (i.e., left
1.67 + 0.1 0.5 + 0.5 unbypassed), the input resistance becomes [refer
= −8.9 V/V to Fig. 7.57(b)]

Exercise 7–11
Rin = RB1 RB2 [(β + 1)(re + Re )] 50

= × 20(88)
50 + 50
Thus,
= 40 V/V
10 = 182 100 [101(0.05 + Re )]
v̂ o = 40 v̂ sig = 40 × 10 mV = 0.4 V
VT
where we have substituted re = =
IE
Ex: 7.44 Refer to Fig. 7.59. Consider first
25
= 50 . The value of Re is found from the the bias design of the circuit in Fig. 7.59(a).
0.5 Since the required IE = 1 mA, the base current
equation above to be
Re = 67.7 IE 1
IB = = 0.01 mA. For a dc voltage
β +1 101
The overall voltage gain can be found from
drop across RB of 1 V, we obtain
Rin RC RL
Gv = −α 1V
Rin + Rsig re + Re RB = = 100 k
0.01 mA
10 18 20
Gv = −0.99 × The result is a base voltage of –1 V and an emitter
10 + 10 0.05 + 0.0677 voltage of –1.7 V. The required value of RE can
= −39.8 V/V now be determined as
−1.7 − (−5) 3.3
RE = = = 3.3 k
Ex: 7.43 Refer to Fig. 7.58. IE 1 mA
Rin = RB [(β + 1)[re + (RE ro RL )]
Rin = 50 = re RE re
VA 100 V
VT where ro = = = 100 k
re = 50 = IC 1 mA
IE
Rin = 100 (100 + 1)[0.025 + (3.3 100 1)]
⇒ IE = 0.5 mA
= 44.3 k
IC = αIE IE = 0.5 mA
vi Rin 44.3
VC = VCC − RC IC = = = 0.469 V/V
v sig Rin + Rsig 44.3 + 50
For VC = 1 V and VCC = 5 V, we have vo RE ro RL
= = 0.968 V/V
1 = 5 − RC × 0.5 vi re + (RE ro RL )
vo
⇒ RC = 8 k Gv ≡ = 0.469 × 0.968 = 0.454 V/V
v sig
To obtain the required value of RE , we note that
RB + Rsig
the voltage drop across it is (VEE − VBE ) = 4.3 V. Rout = ro RE re +
Thus, β +1

4.3 100 50
RE = = 8.6 k = 100 3.3 0.025 +
0.5 101
Rin = 320
Gv = gm (RC RL )
Rin + Rsig

Chapter 7–1
7.1 Coordinates of point A: v GS = Vt = 0.5 V The lowest instantaneous

voltage allowed at the
and v DS = VDD = 5 V. output is VDS B = 0.22 V. Thus the maximum
allowable negative signal swing at the output is
To obtain the coordinates of point B, we first use VDSQ − 0.22 = 1 − 0.22 = 0.78 V. The
Eq. (7.6) to determine VGS B as
corresponding peak input signal is
√
2k n RD VDD + 1 − 1

VGS B = Vt + v̂ gs =
0.78 V
=
0.78
= 19.5 mV
k n RD | Av | 40
√
2 × 10 × 20 × 5 + 1 − 1
= 0.5 +
10 × 20 7.4 From Eq. (7.18):
= 0.5 + 0.22 = 0.72 V
VDD − VOV B
| Av max | =
The vertical coordinate of point B is VDS B , VOV B /2

VDS B = VGS B − Vt = VOV B = 0.22 V 2 − VOV B
14 =
VOV B /2

7.2 VDS B = VOV B = 0.5 V ⇒ VOV B = 0.25 V
Thus, Now, using Eq. (7.15) at point B, we have

1
ID B = k n VDS2 1
= × 5 × 0.52 = 0.625 mA Av B = −k n VOV B RD
2 B 2
Thus,
The value of RD required can now be found as
−14 = −k n RD × 0.25
VDD − VDS B
RD =
ID B ⇒ k n RD = 56
5 − 0.5 To obtain a gain of −12 V/V at point Q:

= = 7.2 k
0.625 −12 = −k n RD VOV Q
If the transistor is replaced with
another having
twice the value of k n , then ID B will be twice as = −56VOV Q
large and the required value of RD will be half that Thus,
used before, that is, 3.6 k.
12
VOV Q = = 0.214 V
56

7.3 Bias point Q: VOV = 0.2 V and VDS = 1 V. To obtain the required VDS Q , we use Eq. (7.17),
1
IDQ = k n VOV VDD − VDS Q
2
2 Av = −
1 VOV /2
Q
= × 10 × 0.04 = 0.2 mA
2 2 − VDS Q
VDD − VDS 5−1 −12 = −
RD = = = 20 k 0.214/2
IDQ 0.2

⇒ VDS Q = 0.714 V
Coordinates of point B:
Equation (7.6):
√ 7.5
2k n RD VDD + 1 − 1 VDD
VGS B = Vt +
k n RD
√ iD
2 × 10 × 20 × 5 + 1 − 1
= 0.5 + RD
10 × 20
= 0.5 + 0.22 = 0.72 V vDS
Equations (7.7) and (7.8):

√
2k n RD VDD + 1 − 1
VDS B = = 0.22 V ⵑ vgs
k n RD
Av = −k n RD VOV
VGS
= −10 × 20 × 0.2 = −40 V/V
Chapter 7–2
W mA 7.6 RD = 20 k
VDD = 5 V, k n =1 2
L V
k n = 200 μA/V2
RD = 24 k, Vt = 1 V
VRD = 1.5 V
(a) Endpoints of saturation transfer segment:
VGS = 0.7 V
Point A occurs at VGS = Vt = 1 V, iD = 0
Av = −10 V/V
Point A = (1 V, 5 V) ( VGS , VDS )
Av = −k n VOV RD
Point B occurs at sat/triode boundary ( VGD = Vt ) 1
VRD = ID RD = k n VOV
2
RD
VGD = 1 V ⇒ V GS − [ 5 − iD RD ] = 1 2
Av −2 −10
1 = =
VGS − 5 + (1)(24) [ VGS − 1 ]2 − 1 = 0 VRD VOV 1.5
2
∴ VOV = 0.30 V
2
12VGS − 23VGS + 6 = 0
Vt = VGS −VOV = 0.40 V
VGS = 1.605 V Av −10
kn = =
iD = 0.183 mA VDS = 0.608 V VOV RD −0.3 × 20
= 1.67 mA/V2
Point B = ( +1.61 V, 0.61 V )
W
(b) For VOV = VGS −Vt = 0.5 V, we have k n = k n = 1.67 mA/V2
L
VGS = 1.5 V W
∴ = 8.33
L
1
ID = k n (VGS − Vt )2
2
1 7.7 At sat/triode boundary
= × 1(1.5 − 1)2
2
v GS B = VGS + v̂ gs
ID = 0.125 mA VDS = +2.00 V
v DS B = VDS − v̂ o
Point Q = ( 1.50 V, 2.00 V )
v̂ o = max downward amplitude , we get
Av = −k n VOV RD = −12 V/V
v̂ o
v DS B = v GS B − Vt = VGS + − Vt
(c) From part (a) above, the maximum | Av |
instantaneous input signal while the transistor
= VDS − v̂ o
remains in saturation is 1.61 V and the
corresponding output voltage is 0.61 V. Thus, the v̂ o
VOV + = VDS − v̂ o
maximum amplitude of input sine wave is | Av |
(1.61 − 1.5) = 0.11 V. That is, v GS ranges from VDS − VOV
1.5 − 0.11 = 1.39 V, at which v̂ o = (1)
1 + | A1v |
1
iD = × 1 × (1.39 − 1)2 = 0.076 mA For VDD = 5 V, VOV = 0.5 V, and
2
W
and k n = 1 mA/V2 , we use
L
v DS = 5 − 0.076 × 24 = 3.175 V −2(VDD − VDS )
Av =
and v GS = 1.5 + 0.11 = 1.61 V at which VOV
v DS = 0.61 V. and Eq. (1) to obtain
Thus, the large-signal gain is

V DS Av v̂ o v̂ i
0.61 − 3.175
= −11.7 V/V 1V −16 471 mV 29.4 mV
1.61 − 1.39
1.5 V −14 933 mV 66.7 mV
whose magnitude is slightly less (−2.5%) than
the incremental or small-signal gain (−12 V/V). 2V −12 1385 mV 115 mV
This is an indication that the transfer 2.5 V −10 1818 mV 182 mV
characteristic is not a straight line.
Chapter 7–3
For VDS = 1 V, Av = −16 = −k n VOV RD Substituting VDD = 5 V, rearranging the equation

to obtain a quadratic equation in k n RD , and
∴ RD = 32 k
solving the resulting quadratic equation
ID RD = 4 V, ID = 0.125 mA results in
k n RD = 213.7
7.8
which can be substituted into Eq. (2) to
obtain
vDS
VDS B = 0.212 V
The value of VDS at the bias point can now be

found from Eq. (1) as

VDS Q = 0.212 + 0.5 = 0.712 V
(b) The gain achieved can be found as
Q Av = −k n RD VOV
VDSQ
= −213.7 × 0.2 = −42.7 V/V
0.5 V 0.5 0.5
v̂ gs = = = 11.7 mV
B | Av | 42.7
VDSB
(c) ID = 100 μA
VOV
VDD − VDS Q
RD =
vGS ID
Vt vˆ gs
5 − 0.712
= = 42.88 k
VDSB 0.1
213.7
(d) k n = = 4.98 mA/V2
42.88
To obtain maximum gain while allowing for a
−0.5-V signal swing at the output, we bias the W 4.98
= = 24.9
MOSFET at point Q where L 0.2

VDS Q = VDS B + 0.5 V (1)
7.9
as indicated in the figure above. Now, VDS B is
VDD
given by Eq. (7.8) [together with Eq. (7.7)],
√
2k n RD VDD + 1 − 1

VDS B = (2)
k n RD
Q2
From the figure we see that

VDS B = VOV + v̂ gs
vO
where VOV = 0.2 V (given) and
Q1
0.5 V vI
v̂ gs =
| Av |
iD
0.5 0.5 2.5
= = = (3)
k n RD VOV k n RD × 0.2 k n RD
Thus, given Vt1 = Vt2 = Vt

2.5 1 W
VDS B = 0.2 + For Q2 , iD = k n [ VDD − v O − Vt ]2
k n RD 2 L 2

Substituting for VDS B from Eq. (2), we obtain 1 W
For Q1 , iD = k n [ v I − Vt ]2
√ 2 L 1
2k n RD VDD + 1 − 1 2.5
= 0.2 + For Vt ≤ v I ≤ v O + Vt ,
k n RD k n RD
Chapter 7–4
equate iD1 and iD2 max +v O = 5 − 4.5 = 0.5 V

W max −v O = 4.5 − 0.3 = 4.2 V
[ VDD − v O + Vt ]2
L 2
Similarly →

W
= [ v I − Vt ]2
L 1
IC VCE Av POS Neg
(mA) (V) (V/V) v O (V) v O (V)
( W/L)1
[ VDD − v O − Vt ] = · [ v I − Vt ] 0.5 4.5 –20 0.5 4.2
( W/L )2
1.0 4.0 –40 1.0 3.7
( W/L )1
v O = VDD − Vt + Vt 2.5 2.5 –100 2.5 2.2
( W/L )2
4.0 1.0 –160 4.0 0.7
( W/L )1
−v I 4.5 0.5 –180 4.5 0.2
( W/L )2

50

√
( W/L )1 0.5
For = = 10, 7.12
( W/L )2
5
0.5
√
Av = − 10 = −3.16 V/V
7.10 Refer to Fig. 7.6.

VCC − VCE
Av = −
VT
5−1
=− = −160 V/V
0.025
The transistor enters saturation when v CE ≤ 0.3 V,
thus the maximum allowable output voltage
swing is 1 − 0.3 = 0.7 V. The corresponding
maximum input signal permitted v̂ be is
0.7 V 0.7
v̂ be = = = 4.4 mV IC RC VCC − VCE
| Av | 160 Av = − =−
VT VT
On the verge of satuation
7.11
VCE − v̂ ce = 0.3 V
5 V For linear operation, v ce = Av v be
VCE − | Av v̂ be | = 0.3
RC
IC
1 k ( 5 − IC RC ) − | Av | × 5 × 10−3 = 0.3
vO
But
v IC RC
be | Av | =
VT
VBE
Thus,
IC RC = | Av |VT
and
For IC = 0.5 mA, we have
5 − | Av |VT − | Av | × 5 × 10−3 = 0.3
IC RC 0.5
Av = − =− = −20 V/V | Av |( 0.025 + 0.005 ) = 5 − 0.3
VT 0.025
VCE = VCC − IC RC | Av | = 156.67. Note AV is negative.
= 5 − 0.5 = 4.5 V ∴ Av = −156.67 V/V
Chapter 7–5
Now we can find the dc collector voltage. The resulting gain will be
Referring to the sketch of the output voltage, we
VCC − VCE
see that Av = −
VT
VCE = 0.3 + | Av | 0.005 = 1.08 V
which results in VCC of
VCC = VCE + | Av |VT

7.13 To determine | Av max |, we use Eq. (7.23),
VCC − 0.3 Thus the minimum required VCC will be
| Av max | =
VT VCCmin = VCEsat + P + | Av |VT
VCC
Then, for VCE = we obtain but we have to make sure that the amplifier
2
can support a positive peak amplitude of P,
VCC that is,
VCC −
| Av | = 2
VT | Av |VT ≥ P
VCC In the results obtained, tabulated below, VCEsat =
=
2VT 0.3 V and VCC is the nearest 0.5 V to VCCmin .
Finally, if a negative-going output signal swing of
0.4 is required, the transistor must be biased at Case Av (V/V) P (V) | Av |VT VCCmin VCC
VCE = 0.4 + 0.3 = 0.7 V and the gain achieved
becomes a −20 0.2 0.5 1.0 1.0
VCC − 0.7 b −50 0.5 1.25 2.05 2.5
| Av | = .
VT c −100 0.5 2.5 3.3 3.5
The results are as follows: d −100 1.0 2.5 3.8 4.0
e −200 1.0 5.0 6.3 6.5
VCC 1.0 1.5 2.0 3.0 (V)
f −500 1.0 12.5 13.8 14.0
VCC − 0.3 0.7 1.2 1.7 2.7 (V)
| Av max | 28 48 68 108 (V/V) g −500 2.0 12.5 14.8 15.0
VCC /2 0.5 0.75 1.0 1.5 (V)

| Av | 20 30 40 60 (V/V) 7.15 See figure below
VCC − 0.7 0.3 0.8 1.3 2.3 (V) IC RC 0.3 × 5
Av = − =− = −60 V/V
| Av | 12 32 52 92 (V/V) VT 0.025
7.14 To obtain an output signal of peak 7.16 (a) See figure on next page
amplitude P volts and maximum gain, we bias the (b) See figure on next page
transistor at
Note that in part (b) the graph is shifted right by
VCE = VCEsat + P +5 V and up by +5 V.
This figure belongs to Problem 7.15.

5 V 2.5 V
10 k 5 k
Thévenin
vO vO
vI 0.3 mA 10 k vI 0.3 mA
Chapter 7–6
This figure belongs to Problem 7.16(a).

vO
0.5 V
vI
0
B 0.3 V
vI
vO
RC
5 V 5 V
A
This figure belongs to Problem 7.16(b).

vO
5 V
5V
B
vI 4.7 V
vO
RC
0 A
0 4.5 V 5 V vI

v CE Substituting IC RC = VCC − VCE , we obtain
7.17 iC = IS ev BE /VT 1 +
VA
(VCC − VCE )/VT
VCE Av = − Q.E.D
IC = IS eVBE /VT 1 + VCC − VCE
VA 1+
VA + VCE
v CE = VCC − RC iC
For VCC = 5 V, VCE = 3 V, and VA = 100 V,
VCE = VCC − RC IC 5−3
Av (without the Early effect) = −
dv CE 0.025
Av =
dv BE v BE =VBE , v CE =VCE = −80 V/V
−80
VCE 1 Av (with the Early effect) =
= −RC IS 1 + eVBE /VT 2
VA VT 1+
100 + 3
dv CE 1
−RC IS eVBE /VT = −78.5 V/V
dv BE VA

1 IC 1 VCC − VCE 5−2
= −RC IC − RC A 7.18 IC = = = 3 mA
VT VCE VA v RC 1
1+
VA VCC − VCE 3
Av = − =− = −120 V/V
Thus, VT 0.025
−IC RC /VT Using the small-signal voltage gain with
Av = Q.E.D
IC RC v BE = +5 mV, we have
1+
VA + VCE
v O = Av × v BE = −120 × 5 mV = −0.6 V
Chapter 7–7
Using the exponential characteristic (e) Assuming linear operation around the bias
yields point, we obtain
iC = IC ev BE /VT v ce = Av × v be
=3×e 5/25
= 3.66 mA = −60 × 5 sin ωt = −300 sin ωt, mV
Thus, iC = 0.66 mA and = −0.3 sin ωt, V
v O = − iC RC −v ce
(f) ic = = 0.1 sin ωt, mA
RC
= −0.66 × 1 = −0.66 V
IC 0.5 mA
Repeating for v BE = −5 mV as (g) IB = = = 0.005 mA
follows. β 100
ic 0.1
Using the small-signal voltage ib = = sin ωt = 0.001 sin ωt, mA
β 100
gain:
v O = −120 × −5 = +0.6 V v̂ be
(h) Small-signal input resistance ≡
v̂ b
Using the exponential characteristic:
5 mV
= = 5 k
iC = IC ev BE /VT 0.001 mA
= 3 × e−5/25 = 2.46 mA
Thus, iC = 2.46 − 3 = −0.54 mA and (i)
v O = 0.54 × 1 = 0.54 V
vBE
vbe
vBE vO (exp) vO (linear) 5 mV
VBE 0.673 V
+5 mV −660 mV −600 mV
−5 mV +540 mV +600 mV
Thus, using the small-signal approximation 0 t

underestimates |v O | for positive v BE by about
10% and overestimates |v O | for negative v BE vCE vce
1.8 V
by about 10%. VCE 1.5 V
0.3 V
1.2 V
7.19 (a) Using Eq. (7.23) yields
VCC − 0.3 3 − 0.3 0 t
| Av max | = = = 108 V/V
VT 0.025
iC
(mA) 0.6 mA
(b) Using Eq. (7.22) with Av = −60 yields 0.1 mA
IC 0.5 mA
VCC − VCE 3 − VCE 0.4 mA
−60 = − =−
VT 0.025
⇒ VCE = 1.5 V
0
t
(c) IC = 0.5 mA
iB
IC RC = VCC − VCE = 3 − 1.5 = 1.5 V (A) ib
6 A
1 A
1.5 IB 5 A
RC = = 3 k
0.5 4 A
VBE /VT
(d) IC = IS e
0.5 × 10−3 = 10−15 eVBE /0.025

0 t
⇒ VBE = 0.673 V
Chapter 7–8

IC Eq. of L1 ⇒ iC = IC ( 1 + v CE /VA )
7.20 Av = − RC
VT
= 5 ( 1 + v CE /100 )
But
v O − iC RC = 5 + 0.05v CE
Av ≡ = = −gm RC
v BE v BE VCC − v CE
Load line ⇒ iC = = 10 − v CE
Thus, RC
gm = IC /VT ∴ 10 − v CE = 5 + 0.05v CE
For a transistor biased at IC = 0.5 mA, we have VCE = v CE = 4.76 V

0.5 IC = iC = 10 − v CE = 5.24 mA
gm = = 20 mA/V
0.025
Now for a signal of 30-μA peak superimposed on
IB = 50 μA, the operating point moves along the
load line between points N and M. To obtain the
7.21
coordinates of point M, we solve the load line and
line L2 to find the intersection M, and the load
line and line L3 to find N:
For point M:
iC = 8 + (8/100)v CE and iC = 10 − v CE

∴ iC M = 8.15 mA, v CE M = 1.85 V
For point N:
iC = 2 + 0.02v CE and iC = 10 − v CE

v CE N = 7.84 V, iC N = 2.16 mA
Peak-to-peak v C swing = 4 − 1 = 3 V
For point Q at VCC /2 = 2.5 V, we obtain
VCE = 2.5 V, IC = 2.5 mA
IB = 25 μA
VBB − 0.7
IB = = 25 μA
RB
⇒ VBB = IB RB + 0.7 = 2.5 + 0.7 = 3.2 V
7.22 See the graphical construction that follows.

For this circuit:
VCC = 10 V, β = 100,
RC = 1 k, VA = 100 V,
IB = 50 μA (dc bias),
At v CE = 0, iC = βiB Thus the collector current varies as follows:
∴ IC = 50 × 100
2.91 mA
= 5 mA (dc bias)
8.15 mA
Given the base bias current of 50 mA, the dc or
5.24 mA i 5.99 mA,
bias point of the collector current IC , and voltage
peak to peak
VCE can be found from the intersection of the load
2.16 mA
line and the transistor line L1 of iB = 50 μA.
Specifically: 3.08 mA
Chapter 7–9
And the collector voltage varies as follows: gm = k n VOV = 10 × 0.2 = 2 mA/V

which is an identical result.
3.08 V
7.84 V
1
4.76 V v 5.99 V 7.25 (a) ID = k n (VGS − Vt2 )
2
1
1.85 V = × 5(0.6 − 0.4)2 = 0.1 mA
2
2.91 V
VDS = VDD − ID RD = 1.8 − 0.1 × 10 = 0.8 V
7.23 Substituting v gs = Vgs sin ωt in Eq. (7.28), (b) gm = k n VOV = 5 × 0.2 = 1 mA/V
1 (c) Av = −gm RD = −1 × 10 = −10 V/V
iD = k n (VGS − Vt )2 + k n (VGS − Vt )Vgs sin ωt
2 1
(d) λ = 0.1 V−1 , VA = = 10 V
1
+ k n Vgs2 sin2 ωt λ
2 VA 10
1 ro = = = 100 k
= k n (VGS − Vt )2 + k n (VGS − Vt )Vgs sin ωt ID 0.1
2 Av = −gm (RD
ro )
1 1 1
+ k n Vgs2 ( − cos 2 ωt) = −1(10
100) = −9.1 V/V
2 2 2
Second-harmonic distortion
1
k n Vgs2 7.26 Av = −10 = −gm RD = −gm × 20
= 4 × 100
k n (VGS − Vt )Vgs gm = 0.5 mA/V
1 Vgs To allow for a −0.2-V signal swing at the drain
= × 100 Q.E.D
4 VOV while maintaining saturation-region operation,
For Vgs = 10 mV, to keep the second-harmonic the minimum voltage at the drain must be at least
distortion to less than 1%, the minimum overdrive equal to VOV . Thus
voltage required is VDS = 0.2 + VOV
1 0.01 × 100
VOV = × = 0.25 V Since
4 1
VDD − VDS
Av = −
1
1 1 VOV
7.24 ID = k n VOV
2
= × 10 × 0.22 = 0.2 mA 2
2 2
1.8 − 0.2 − VOV
v GS = VGS + v gs , where v gs = 0.02 V −10 = −
0.5VOV
v OV = 0.2 + 0.02 = 0.22 V
⇒ VOV = 0.27 V
1 1
iD = k n v 2OV = × 10 × 0.222 = 0.242 mA The value of ID can be found from
2 2
2ID
Thus, gm =
VOV
id = 0.242 − 0.2 = 0.042 mA
2 × ID
0.5 =
For 0.27
v gs = −0.02 V, v OV = 0.2 − 0.02 = 0.18 V ⇒ ID = 0.067 mA
1 1 The required value of k n can be found from

iD = k n v 2OV = × 10 × 0.182 = 0.162 mA
2 2 1
ID = k n VOV
2
Thus, 2
id = 0.2 − 0.162 = 0.038 mA 1
0.067 = k n × 0.272
2
Thus, an estimate of gm can be obtained as
follows: ⇒ k n = 1.83 mA/V2
0.042 + 0.038 Since k n = 0.2 mA/V2 , the W/L ratio must be
gm = = 2 mA/V
0.04 W kn 1.83
Alternatively, using Eq. (7.33), we can write = = = 9.14
L kn 0.2
Chapter 7–10
Finally, VOV = mv̂ i = 15 × 20 = 0.3 V

VGS = Vt + VOV = 0.4 + 0.27 = 0.67 V 0.3 + 0.02 + 2 × 2.5 × (0.02/0.3)
VDS =
1 + 2(0.02/0.3)
= 0.576 V
7.27 Av = −gm RD
2(VDD − VDS ) 2(2.5 − 0.576)
Av = − =−
Upon substituting for gm from Eq. (7.42), we can VOV 0.3
write
= −12.82 V/V
2ID RD
Av = − v̂ o = | Av |v̂ i = 12.82 × 20 mV = 0.256 V
VOV
2(VDD − VDS ) To operate at ID = 200 μA = 0.2 mA,
=− Q.E.D (1)
VOV 2.5 − 0.576
RD = = 9.62 k
v GS max = VGS + v̂ i = Vt + VOV + v̂ i 0.2
1
v DS min = VDS − | Av |v̂ i ID = k n VOV
2
2
To just maintain saturation-mode operation, 1
0.2 = k n × 0.32
v GS max = v DS min + Vt 2
which results in ⇒ k n = 4.44 mA/V2
VOV + v̂ i = VDS − | Av |v̂ i The required W/L ratio can now be found as
W kn 4.44
Substituting for | Av | from Eq. (1) yields = = = 44.4
L kn 0.1
2(VDD − VDS )
VOV + v̂ i = VDS − v̂ i
VOV
7.28 Given μn = 500 cm2 /V·s,
VDS [1 + 2(v̂ i /VOV )]
μp = 250 cm2 /V·s, and Cox = 0.4 fF/μm2 ,
= VOV + v̂ i + 2VDD (v̂ i /VOV )
k n = μn Cox = 20 μA/V2
VOV + v̂ i + 2VDD (v̂ i /VOV )
⇒ VDS = Q.E.D
1 + 2(v̂ i /VOV ) k p = 10 μA/V2
For See table below.
VDD = 2.5 V, v̂ i = 20 mV and m = 15
Chapter 7–11
7.29 Given μn Cox = 250 μA/V2 , vd −RD −gm RD

= =
vi 1 1 + gm RS
Vt = 0.5 V, + RS
gm
L = 0.5 μm
For gm = 2 mA/V2 and ID = 0.25 mA, 7.31

W W
gm = 2μn Cox ID ⇒ = 32
L L VDD
∴ W = 16 μm
2ID
VOV = = 0.25 V I 500 μA
gm
∴ VGS = VOV + Vt = 0.75 V RG
10 M
vo
7.30

VDD vi RL
10 k
RD
vd
Vt = 0.5 V
vi VA = 50 V
vs
Given VDS = VGS = 1 V. Also, ID = 0.5 mA.
RS 2ID
VOV = 0.5 V, gm = = 2 mA/V
VOV
VA
VSS ro = = 100 k
ID
vo
= −gm ( RG
RL
ro ) = −18.2 V/V
D vd vi
For ID = 1 mA:

gmvgs RD 1 √
VOV increases by = 2 to
0.5
G √
vi 2 × 0.5 = 0.707 V.
1 VGS = VDS = 1.207 V
vgs gm
gm = 2.83 mA/V, ro = 50 k and
vo
S = −23.6 V/V
vi
vs
RS
7.32 For the NMOS device:
1 W 2
ID = 100 = μn Cox VOV
2 L
1 10
1 = × 400 × × VOV
2
v i = gm v gs + RS 2 0.5
gm ⇒ VOV = 0.16 V
v d = −gm v gs RD 2ID 2 × 0.1 mA
gm = = = 1.25 mA/V
v s = +gm v gs RS VOV 0.16
vs RS +gm RS VA = 5L = 5 × 0.5 = 2.5 V
∴ = =
vi 1 1 + gm RS VA 2.5
+ RS ro = = = 25 k
gm ID 0.1
Chapter 7–12
For the PMOS device: Since the drain voltage (+7 V) is higher than the
1 W 2 gate voltage (+5 V), the transistor is operating in
ID = 100 = μp Cox VOV saturation.
2 L
1 10 From the circuit
= × 100 × × VOV
2
2 0.5 VD = VDD − ID RD = 15 − 0.5 × 16 = +7 V, as
⇒ VOV = 0.316 V assumed
2ID 2 × 0.1
gm = = = 0.63 mA/V Finally,
VOV 0.316
VGS = 1.5 V, thus VOV = 1.5 − Vt = 1.5 − 1
VA = 6L = 6 × 0.5 = 3 V
= 0.5 V
VA 3
ro = = = 30 k 1
ID = k n VOV2 1
= × 4 × 0.52 = 0.5 mA
ID 0.1 2 2
which is equal to the given value. Thus the bias
7.33 (a) Open-circuit the capacitors to obtain the calculations are all consistent.
bias circuit shown in Fig. 1, which indicates the 2ID 2 × 0.5
given values. (b) gm = = = 2 mA/V
VOV 0.5
VA 100
15 V ro = = = 200 k
ID 0.5
0.5 mA (c) See Fig. 2 below.
10 M 16 k (d) Rin = 10 M
5 M = 3.33 M
7 V v gs Rin 3.33
= =
v sig Rin + Rsig 3.33 + 0.2

1.5 V 0.5 mA = 0.94 V/V

vo
5 M 7 k = −gm (200
16
16)
v gs
= −2 × 7.69 = −15.38 V/V
vo v gs vo
= × = −0.94 × 15.38
Figure 1 v sig v sig v gs
= −14.5 V/V
From the voltage divider, we have
5 7.34 (a) Using the exponential characteristic:
VG = 15 =5V
10 + 5
ic = IC ev be /VT − IC
From the circuit, we obtain
ic
VG = VGS + 0.5 × 7 giving = ev be /VT − 1
IC
= 1.5 + 3.5 = 5 V (b) Using small-signal approximation:
which is consistent with the value provided by the IC
ic = gm v be = · v be
voltage divider. VT
This figure belongs to Problem 7.33, part (c).

Rsig 200 k
vo

vsig
vgs gmvgs
10 M 5 M 200 k 16 k 16 k

Rin
Figure 2
Chapter 7–13
ic v be v ce 0.55 V
Thus, = Voltage gain, Av = =−
IC VT v be 5 mV
See table below. = −110 V/V
For signals at ±5 mV, the error introduced by the Using small-signal approximation, we write
small-signal approximation is 10%.
Av = −gm RC
The error increases to above 20% for signals at
where
±10 mV.
IC 0.5 mA
gm = = = 20 mA/V
v be i c /I C i c /I C Error VT 0.025 V
(mV) Exponential Small signal (%) Av = −20 × 5 = −100 V/V
+1 +0.041 +0.040 –2.4 Thus, the small-signal approximation at this
–1 –0.039 –0.040 +2.4 signal level (v be = 5 mV) introduces an error of
−9.1% in the gain magnitude.
+2 +0.083 +0.080 –3.6
–2 –0.077 –0.080 +3.9 7.36 At IC = 0.5 mA,
+5 +0.221 +0.200 –9.7 IC 0.5 mA
gm = = = 20 mA/V
–5 –0.181 –0.200 +10.3 VT 0.025 V
β 100
+8 +0.377 +0.320 –15.2 rπ = = = 5 k
gm 20 mA/V
–8 –0.274 –0.320 +16.8 VT αVT
re = =
+10 +0.492 +0.400 –18.7 IE IC
–10 –0.330 –0.400 +21.3 where

β 100
+12 +0.616 +0.480 –22.1 α= = = 0.99
β +1 100 + 1
–12 –0.381 –0.480 +25.9 0.99 × 25 mV
re = 50
0.5 mA
7.35 At IC = 50 μA = 0.05 mA,
IC 0.05
gm = = = 2 mA/V
5 V VT 0.025
β 100
rπ = = = 50 k
0.5 mA gm 2 mA/V
5 k
αVT 0.99 × 25 mV
re = = 500
VC IC 0.5 mA

IC 1 mA
7.37 gm = = = 40 mA/V
vBE VT 0.025 V
α 0.99
re = = 25
gm 40 mA/V
β 100
With v BE = 0.700 V rπ = = = 2.5 k
gm 40 mA/V
VC = VCC − RC IC Av = −gm RC = −40 × 5 = −200 V/V
= 5 − 5 × 0.5 = 2.5 V v̂ o = | Av |v̂ be = 200 × 5 mV = 1 V
For v BE = 705 mV ⇒ v be = 5 mV
iC = IC ev be /VT 7.38 For gm = 30 mA/V,
= 0.5 × e 5/25
= 0.611 mA IC
gm = ⇒ IC = gm VT = 30×0.025 = 0.75 mA
VT
v C = VCC − RC iC = 5 − 5 × 0.611 = 1.95 V
β β
v ce = v C − VC = 1.95 − 2.5 = −0.55 V rπ = =
gm 30 mA/V
Chapter 7–14
For rπ ≥ 3 k, we require then

β ≥ 90 V̂be
VCC − IC RC − IC RC = 0.3
VT
That is, βmin = 90.
which can be manipulated to yield
β VCC − 0.3
7.39 rπ = IC RC = (1)
gm V̂be
1+
where VT
IC Since the voltage gain is given by
gm =
VT IC RC
Av = −
Nominally, gm = 40 mA/V. However, IC varies by VT
±20%, so gm ranges from 32 mA/V to 48 mA/V. then
Thus VCC − 0.3
50 to 150 Av =
rπ = VT + V̂be
32 to 48 mA/V
50 For VCC = 3 V and V̂be = 5 mV,
Thus, the extreme values of rπ are = 1.04 k
48 3 − 0.3
IC RC = = 2.25 V
150 5
and = 4.7 k. 1+
32 25
Thus,
7.40 VCC = 3 V, VC = 1 V, RC = 2 k VCE = VCC − IC RC
3−1
IC = = 1 mA = 3 − 2.25 = 0.75 V
2
IC 1 mA V̂o = VCE − 0.3 = 0.75 − 0.3 = 0.45 V
gm = = = 40 mA/V
VT 0.025 V 3 − 0.3
Av = − = −90 V/V
v be = 0.005 sin ωt 0.025 + 0.005
Check:
ic = gm v be = 0.2 sin ωt, mA
IC RC 2.25
iC (t) = IC + ic = 1 + 0.2 sin ωt, mA Av = −gm RC = − =− = −90 V/V
VT 0.025
v C (t) = VCC − RC iC V̂o = | Av | × V̂be = 90 × 5 = 450 mV = 0.45 V
= 3 − 2(1 + 0.2 sin ωt)
= 1 − 0.4 sin ωt, V 7.42
iB (t) = iC (t)/β Transistor a b c d e f g

= 0.01 + 0.002 sin ωt, mA α 1.000 0.990 0.980 1 0.990 0.900 0.940
vc 0.4 β ∞ 100 50 ∞ 100 9 15.9
Av = =− = −80 V/V
v be 0.005 IC (mA) 1.00 0.99 1.00 1.00 0.248 4.5 17.5
IE (mA) 1.00 1.00 1.02 1.00 0.25 5 18.6
7.41 Since V̂be is the maximum value for IB (mA) 0 0.010 0.020 0 0.002 0.5 1.10
acceptable linearity, the largest signal at the gm (mA/V) 40 39.6 40 40 9.92 180 700
collector will be obtained by designing for
re () 25 25 24.5 25 100 5 1.34
maximum gain magnitude. This in turn is
achieved by biasing the transistor at the lowest rπ () ∞ 2.525 k 1.25 k ∞ 10.1 k 50 22.7
VCE consistent with the transistor remaining in the
active mode at the negative peak of v o . Thus
7.43 IC = 1 mA, β = 100, VA = 100 V
VCE − | Av |V̂be = 0.3
IC 1 mA
gm = = = 40 mA/V
where we have assumed VCEsat = 0.3 V. Since VT 0.025 V
VCE = VCC − IC RC β 100
rπ = = = 2.5 k
and gm 40 mA/V
IC VA 100 V
| Av | = gm RC = RC ro = = = 100 k
VT IC 1 mA
Chapter 7–15

ib
B C C
B

vp rp ro rp ro
gmvp bib

E E
rp 2.5 k, gm 40 mA/V ro 100 k, b 100
C C
gmvp ai
B B
ro ro

vp re re
i
E E
re 24.75 , gm 40 mA/V ro 100 k, a 0.99
g
β 100 ib = v be
m
− gm
α= = = 0.99 α
β +1 100 + 1
1−α
VT αVT 0.99 × 25 mV = gm v be
re = = = = 24.75 α
IE IC 1 mA
gm v be
=
β
7.44 v be β
Rin ≡ = = rπ Q.E.D
ib gm

gmvbe v be α
ic = αie = α = v be
ib re re
B
= gm v be Q.E.D

vbe vbe re 7.46 The large-signal model of Fig. 6.5(d) is

shown in Fig. 1.
E
iB
B C

Rin
vBE DB biB
( ISB IS )
v be b
ib = − gm v be
re
E
1
= v be − gm
re Figure 1
Since
α
re = For v BE undergoing an incremental change v be
gm from its equilibrium value of VBE , the current iB
Chapter 7–16
changes from IB by an increment ib , which is C

related to v be by the incremental resistance of DB
at the bias current IB . This resistance is given by
VT /IB , which is rπ .
aiE
The collector current βiB changes from βIB to
β(IB + ib ). The incremental changes around the
B
equilibrium or bias point are related to each other ie
by the circuit shown in Fig. 2, re
vbe
ib
B C E

bib Figure 2
vbe rp
which is the small-signal T model of

Fig. 7.26(b). Q.E.D.
E 7.48 Refer to Fig. P7.48:

Figure 2 VC = 3 − 0.2 × 10 = 1 V
VT 25 mV
re = = = 125
which is the hybrid-π model of IE 0.2 mA
Fig. 7.24(b). Q.E.D. Replacing the BJT with the T model of
Fig. 7.26(b), we obtain the equivalent circuit
shown below.
7.47 The large-signal T model of Fig. 6.5(b) is
shown below in Fig. 1.
aiE
B
iE
vBE DE
IS
(
ISE a )

E
Figure 1
If iE undergoes an incremental change ie from its

equilibrium or bias value IE , the voltage v BE will
correspondingly change by an incremental
amount v be (from its equilibrium or bias value v c = −ie × 10 k
VBE ), which is related to ie by the incremental
resistance of diode DE . The latter is equal to where
VT /IE , which is re . vi vi
ie = − =−
re 0.125 k
The incremental change ie in iE gives rise to an
incremental change αie in the current of the Thus,
controlled source. vc 10 k
=
The incremental quantities can be related vi 0.125 k
by the equivalent circuit model shown in Fig. 2, = 80 V/V
Chapter 7–17
7.51 Replacing the BJT with the T model of

7.49 v ce = | Av |v be Fig. 7.26(b), we obtain the circuit shown below.
| Av | = gm RC = 50 × 2 = 100 V/V
ix
For v ce being 1 V peak to peak, C
1V
v be = = 0.01 V peak to peak
100 aie
v be
ib = v
rπ
B x
ie
where
re
β 100
rπ = = = 2 k
gm 50
E
Thus,
0.01 V r v
ib = = 0.005 mA peak to peak x
ix
2 k
vx
Since v x appears across re and ix = ie = , the
7.50 re
vπ small-signal resistance r is given by
Rin ≡ = rπ
ib vx vx
r≡ = = re
ix ie
vπ rπ
=
v sig rπ + Rsig
7.52 Refer to Fig. P7.52. Replacing the BJT with
v o = −gm v π RC the T model of Fig. 7.26(b) results in the
vo following amplifier equivalent circuit:
= −gm RC
vπ
The overall voltage gain can be obtained as

C
follows:
vo vo vπ
= aie
v sig v π v sig
ib
B
rπ
= −gm RC
rπ + Rsig ie re
vi E
RC
= −gm rπ
rπ + Rsig Re vo

βRC
=− Q.E.D. Rin
rπ + Rsig
Chapter 7–18
vi vi
Rin ≡ = The input resistance Rin can be found by
ib (1 − α)ie inspection to be
From the circuit we see that
vi Rin = re = 75
ie =
re + Re To determine the voltage gain (v o /v i ) we first
Thus, find ie :
vi vi vi
re + Re ie = − =− =−
Rin = Rsig + re 150 0.15 k
1−α
But The output voltage v o is given by
1 v o = −α ie (RC
RL )
1−α =
β +1
= −0.99 ie × (12
12) = −0.99 × 6ie
Thus, −v i
= −0.99 × 6 ×
Rin = (β + 1)(re + Re ) Q.E.D. 0.15
From the equivalent circuit, we see that v o and v i Thus,
are related by the ratio of the voltage divider vo
= 39.6 V/V
formed by re and Re : vi
vo Re
= Q.E.D. 7.54 Refer to Fig. P7.54.
vi Re + re
β 200
α= = = 0.995
7.53 Refer to Fig. P7.53. The transistor is biased β +1 201
at IE = 0.33 mA. Thus IC = α × IE = 0.995 × 10 = 9.95 mA
VT 25 mV VC = IC RC = 9.95 × 0.1 k = 0.995 V 1 V
re = = = 75
IE 0.33 mA
Replacing the BJT with its hybrid-π model
Replacing the BJT with its T model results in the
results in the circuit shown below.
following amplifier equivalent circuit.
IC 10 mA
gm = = 400 mA/V
VT 0.025 V
β 200
rπ = = = 0.5 k
gm 400
Rib = rπ = 0.5 k
Rin = 10 k
0.5 k = 0.476 k
vπ Rin 0.476
= = = 0.322 V/V
vo
= −gm RC = −400 × 0.1 = −40 V/V
vπ
vo
= −40 × 0.322 = −12.9 V/V
v sig

Rsig 1 k
vb
vo

vp rp RC
vsig 10 k gmvp

Rin Rib
Chapter 7–19

B
C

vsig vp rp gmvp vo
ro

RL very high
For 7.57
v o = ±0.4 V/V
±0.4
vb = vπ = = ∓0.01 V = ∓10 mV 5 V
−40
±0.4
v sig = = ∓31 mV
−12.9
RE
Rsig 50
7.55 The largest possible voltage gain is obtained
when RL → ∞, in which case
vo IC VA vsig
= −gm ro = −
v sig VT IC Rin re
VA 50 vo
=−
VT
RC
vo 25
For VA = 25 V, =−
v sig 0.025
= −1000 V/V 5 V
vo 125
For VA = 125 V, =−
v sig 0.025
= −5000 V/V VT
re = 50 =
IE
⇒ IE = 0.5 mA
7.56 Refer to Fig. 7.30:
Thus,
Rin re
5 − VE
= 0.5 mA
To obtain an input resistance of 75 , RE
VT where
re = 75 =
IE
VE 0.7 V
Thus,
⇒ RE = 8.6 k
25 mV
IE = = 0.33 mA To obtain maximum gain and the largest possible
75
signal swing at the output for v eb of 10 mV, we
This current is obtained by raising RE to the value
select a value for RC that results in
found from
10 − 0.7 VC + | Av | × 0.01 V = +0.4 V
IE = = 0.33 mA
RE which is the highest allowable voltage at the
⇒ RE = 28.2 k collector while the transistor remains in the active
region. Since
Note that the dc voltage at the collector
remains unchanged. The voltage gain VC = −5 + IC RC −5 + 0.5RC
now becomes
then
vo αRC 0.99 × 14.1
= = = 186 V/V −5 + 0.5RC + gm RC × 0.01 = 0.4
vi re 0.075
Chapter 7–20
Substituting gm = 20 mA/V results in For α 1,

RC = 7.7 k VT 25 mV
re = = = 50
IE 0.5 mA
The overall voltage gain achieved is
v o1 3.6
vo Rin = = 0.986 V/V
= × gm RC vi 3.6 + 0.05
v sig Rin + Rsig
v o2 3.3
50 =− = 0.904 V/V
= × 20 × 7.7 vi 3.6 + 0.05
50 + 50
= 77 V/V If v o1 is connected to ground, RE will in effect be
short-circuited at signal frequencies, and v o2 /v i
will become
7.58 Refer to Fig. P7.58. Since β is very large, v o2 αRC 3.3
the dc base current can be neglected. Thus the dc =− =− = −66 V/V
vi re 0.05
voltage at the base is determined by the voltage
divider,
100 7.59 See figure on next page.
VB = 5 = 2.5 V
100 + 100 Gv =
Rin
Av o
RL
and the dc voltage at the emitter will be Rin + Rsig RL + Ro
VE = VB − 0.7 = 1.8 V 100 2

= × 100 ×
100 + 20 2 + 0.1
The dc emitter current can now be found as
= 79.4 V/V
VE 1.8
IE = = = 0.5 mA vo
RE 3.6 io =
RL
and
v sig
IC IE = 0.5 mA ii =
Rsig + Rin
Replacing the BJT with the T model of io v o Rsig + Rin
Fig. 7.26(b) results in the following equivalent =
ii v sig RL
circuit model for the amplifier.
vi Rsig + Rin
ie = = Gv
RE + re RL
RE 20 + 100
v o1 = ie RE = v i = 79.4 × = 4762 A/A
RE + re 2
v o1 RE
= Q.E.D. Rin
vi RE + re 7.60 (a) = 0.95
vi Rin + Rsig
v o2 = −αie RC = −α RC
RE + re Rin
= 0.95
v o2 αRC Rin + 100
=− Q.E.D.
vi RE + re ⇒ Rin = 1.9 M

vo2
aie RC
ie
re
vi vo1
100 100 RE
k k
Chapter 7–21

Rsig 20 k Ro 100

vsig Rin Av ovi RL

vi vo
100 k 2 k

Av o 100

Rsig Ro

vsig Rin Av ovi RL

vi vo

(b) With RL = 2 k, 7.61 The circuit in Fig. 1(b) (see figure on next
page) is that in Fig. P7.61, with the output current
2
v o = Av o v i source expressed as Gm v i . Thus, for equivalence,
2 + Ro we write
With RL = 1 k, Av o
Gm =
1 Ro
v o = Av o v i
1 + Ro To determine Gm (at least conceptually), we
Thus the change in v o is short-circuit the output of the equivalent circuit in
Fig. 1(b). The short-circuit current will be
2 1
v o = Av o v i − io = Gm v i
2 + Ro 1 + Ro
Thus Gm is defined as
To limit this change to 5% of the value with
RL = 2 k, we require io
Gm =
v i RL = 0
2 1 2
− = 0.05
2 + Ro 1 + Ro 2 + Ro and is known as the short-circuit
transconductance. From Fig. 2 on next page,
1
⇒ Ro = k = 111 vi Rin
9 =
v sig Rin + Rsig
Rin RL
(c) Gv = 10 = Av o
Rin + Rsig RL + Ro v o = Gm v i (Ro
RL )
1.9 2 Thus,
= × Av o ×
1.9 + 0.1 2 + 0.111 vo Rin
= Gm (Ro
RL )
⇒ Av o = 11.1 V/V v sig Rin + Rsig
The values found about are limit values; that is, 7.62
we require
v o
Gv o =
Rin ≥ 1.9 M v sig RL = ∞
Ro ≤ 111 Now, setting RL = ∞ in the equivalent circuit in

Fig. 1(b), we can determine Gv o from
Av o ≥ 11.1 V/V
Chapter 7–22

Ro
io io
Norton

Avovi
vi Rin Avovi vo equivalent vi Rin vo
Ro Ro
of output Gmvi

circuit
(a) (b)
Figure 1
Rsig

vsig Rin Gmvi

vi Ro RL vo

Figure 2

Rsig Rout

vsig Rin Gv ovsig

vi RL vo

(a)
Rsig Ro

vsig Rin Av ovi

vi RL vo

(b)
Figure 1

Rin RL
Gv o = Av o Gv = Gv o Q.E.D.
Rin + Rsig RL =∞ RL + Rout
Denoting Rin with RL = ∞ as Ri , we can express
Gv o as
7.63 Refer to Fig. P7.63. To determine Rin , we
Ri simplify the circuit as shown in Fig. 1, where
Gv o = Av o Q.E.D.
Ri + Rsig vi vi
Rin ≡ = R1
Rin , where Rin ≡
From the equivalent circuit in Fig. 1(a), the ii if
overall voltage Gv can be obtained as v i = if Rf + (if − gm v i )(R2
RL )
Chapter 7–23
Figure 1
Thus, controlled source gm v i . Thus, looking between

the output terminals (behind RL ), we see R2 in
v i [1 + gm (R2
RL )] = if [Rf + (R2
RL )]
parallel with Rf ,
vi Rf + (R2
RL )
Rin ≡ = Ro = R2
Rf Q.E.D.
if 1 + gm (R2
RL )
For R1 = 100 k, Rf = 1 M, gm = 100 mA/V
and
R2 = 100 and RL = 1 k
Rin = R1
Rin
1000 + (0.1
1)
Rf + (R2
RL ) Rin = 100
= 100
99.1
= R1
Q.E.D. 1 + 100(0.1
1)
1 + gm (R2
RL )
= 49.8 k
To determine Av o , we open-circuit RL and use the
circuit in Fig. 2, where Without Rf present (i.e., Rf = ∞), Rin = 100 k
and
Rf if 1 − (1/100 × 1000)
Av o = −100 × 0.1
0.1
vo 1+
1000
R2
vi R1 gmvi vo −10 V/V
R2
Without Rf , −Av o = 10 V/V and

Ro = 0.1
1000 0.1 k = 100
Without Rf , Ro = 100 .
Figure 2
Thus the only parameter that is significantly
vo affected by the presence of Rf is Rin , which is
if = gm v i +
R2 reduced by a factor of 2!

vo Rin RL
v i = if Rf + v o = gm v i + Rf + vo Gv = Av o
R2 Rin + Rsig RL + Ro

Rf With Rf ,
v i (1 − gm Rf ) = v o 1 +
R2 49.8 1
Gv = × −10 ×
Thus, 49.8 + 100 1 + 0.1
vo 1 − gm Rf = −3 V/V
Av o ≡ =
vi Rf Without Rf ,
1+
R2
100 1
which can be manipulated to the form Gv = × −10 × = −4.5 V/V
100 + 100 1 + 0.1
1 − 1/gm Rf
Av o = −gm R2 Q.E.D.
1 + (R2 /Rf )
7.64 Rsig = 1 M, RL = 10 k
Finally, to obtain Ro we short-circuit v i in the
circuit of Fig. P7.63. This will disable the gm = 2 mA/V, RD = 10 k
Chapter 7–24
Gv = −gm (RD
RL ) 2ID 2 × 0.3
(b) gm1 = gm2 = = = 3 mA/V
VOV 0.2
= −2(10
10) = −10 V/V
RD1 = RD2 = 10 k
RL = 10 k
7.65 Rin = ∞
v gs2 vo
1 W 2 Gv = ×
ID = μn Cox VOV v gs1 v gs2
2 L
= −gm1 RD1 × −gm2 (RD2
RL )
1
320 = × 400 × 10 × VOV
2
2 = 3 × 10 × 3 × (10
10)
⇒ VOV = 0.4 V = 450 V/V
2ID 2 × 0.32
gm = = = 1.6 mA/V
VOV 0.4
IC 0.5 mA
Av o = −gm RD = −1.6 × 10 = −16 V/V 7.68 gm = = = 20 mA/V
VT 0.025 V
Ro = RD = 10 k β 100
rπ = = = 5 k
RL gm 20 mA/V
Gv = Av o
RL + Ro Rin = rπ = 5 k
10
= −16 × = −8 V/V Ro = RC = 10 k
10 + 10
Av o = −gm RC = −20 × 10 = −200 V/V
0.2 V
Peak value of v sig = = 25 mV.
8 RL 10
Av = Av o = −200 ×
RL + Ro 10 + 10
7.66 RD = 2RL = 30 k = −100 V/V
VOV = 0.25 V Gv =
Rin
Av
Rin + Rsig
Gv = −gm (RD
RL )
5
−10 = −gm (30
15) = × −100
5 + 10
⇒ gm = 1 mA/V = −33.3 V/V
2ID For v̂ π = 5 mV, v̂ sig can be found from
gm =
VOV
Rin 5
2 × ID v̂ π = v̂ sig × = v̂ sig ×
1= Rin + Rsig 5 + 10
0.25
⇒ v̂ sig = 15 mV
⇒ ID = 0.125 mA = 125 μA
Correspondingly, v̂ o will be
If RD is reduced to 15 k,
v̂ o = Gvv̂ sig
Gv = −gm (RD
RL )
= 15 × 33.3 = 500 mV = 0.5 V
= −1 × (15
15) = −7.5 V/V
7.67 (a) See figure below.

Rsig 200 k

vsig vgs1 gm1vgs1 RD1 vgs2 gm2vgs2

RD2 R L vo

Chapter 7–25
RL That is,

7.69 | Gv | =
(Rsig /β) + (1/gm )
8 10
IC =
RL = 10 k, Rsig = 10 k, gm = 0.1 + (1/gm ) 0.2 + (1/gm )
VT
1
1 ⇒ = 0.3 or gm = 3.33 mA/V
= = 40 mA/V gm
0.025
10
Nominal β = 100 | Gv nominal = = 25 V/V
0.1 + 0.3
10 10
(a) Nominal | Gv | = | Gv min =
(10/100) + 0.025 0.2 + 0.3
= 80 V/V = 20 V/V (−20% of nominal)
10
(b) β = 50, | Gv | = We need to check the value obtained for
(10/50) + 0.025 β = 150,
= 44.4 V/V 10
| Gv max = = 27.3 V/V
10 10/150 + 0.3
β = 150, | Gv | =
(10/150) + 0.025 which is less than the allowable value of
= 109.1 V/V 1.2 | Gv nominal = 30 V/V. Thus, the new bias
current is
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V.
IC = gm × VT = 3.33 × 0.025 = 0.083 mA
(c) For | Gv | to be within ±20% of nominal (i.e.,

ranging between 64 V/V and 96 V/V), the | Gv nominal = 25 V/V
corresponding allowable range of β can be found
as follows:
10 7.70 (a) See figure below.
64 =
(10/βmin ) + 0.025 (b) RC1 = RC2 = 10 k Rsig = 10 k
⇒ βmin = 76.2 RL = 10 k
10 IC 0.25 mA
96 = gm1 = gm2 = = = 10 mA/V
(10/βmax ) + 0.025 VT 0.025 V
⇒ βmax = 126.3 β 100
rπ1 = rπ2 = = = 10 k
(d) By varying IC , we vary the term 1/gm in the gm 10
denominator of the | Gv | expression. If β varies in v π1 rπ1 10
the range 50 to 150 and we wish to keep | Gv | = = = 0.5 V/V
v sig rπ1 + Rsig 10 + 10
within ±20% of a new nominal value of | Gv |
given by v π2
= −gm1 (RC1
rπ2 ) = −10(10
10)
v π1
10
| Gv nominal = = −50 V/V
(10/100) + (1/gm )
vo
then = −gm2 (RC2
RL )
v π2
10
0.8 | Gv nominal = = −10(10
10) = −50 V/V
(10/50) + (1/gm )

Rsig 10 k

vsig vp1 rp1 rp2

vp2 vo
gm1vp1 RC1 gm2vp2 RC2 RL

Chapter 7–26
vo vo v π2 v π1 30.3 + 10
= × × v̂ sig = 5 × = 6.65 mV
v sig vπ2 v π1 v sig 30.3
= −50 × −50 × 0.5 v̂ o = v̂ sig × | Gv |
= 1250 V/V = 6.65 × 15 100 mV
gm
7.71 gm effective = 7.75 Rin = (β + 1)(re + Re )
1 + gm Rs
5 15 = 75(re + Re )
2=
1 + 5Rs 15 k
re + Re = = 200
⇒ Rs = 0.3 k = 300 75
Rin re
v̂ π = v̂ sig
7.72 The gain magnitude is reduced by a factor Rin + Rsig re + Re
of (1 + gm Rs ). Thus, to reduce the gain from
15 re
−10 V/V to −5 V/V, we write 5 = 150 ×
15 + 30 re + Re
2 = 1 + gm Rs re
⇒ = 0.1
1 1 re + Re
⇒ Rs = = = 0.5 k
gm 2 But re + Re = 200 , thus
re = 20
7.73 Including Rs reduced the gain by a factor of
2, thus which requires a bias current IE of
VT 25 mV
1 + gm Rs = 2 IE = = = 1.25 mA
re 20
1 1
⇒ gm = = = 2 mA/V IC IE = 1.25 mA
Rs 0.5
The gain without Rs is −20 V/V. To obtain a gain Re = 180
of −16 V/V, we write Rin
Gv =
20 20 Rin + Rsig
16 = =
1 + gm Rs 1 + 2Rs −α × Total resistance in collector
×
⇒ Rs = 125 Total resistance in emitter
15 −0.99 × 6
= ×
IC 0.5 15 + 30 0.2
7.74 gm = = = 20 mA/V
VT 0.025 −10 V/V
1 v̂ 0 = 0.15 × | Gv | = 1.5 V
re = 50
gm
Rin = (β + 1)(re + Re )
7.76 Using Eq. (7.113), we have
= 101(50 + 250) = 30.3 k
RC
RL
αRC 0.99 × 12 Gv = −β
Av o = − =− −40 V/V Rsig + (β + 1)(re + Re )
re + Re 0.3
RC
RL
Ro = RC = 12 k −
(Rsig /β) + (re + Re )
RL
Av = Av o 10
RL + Ro | Gv | =
(10/β) + 0.025 + Re
12
= −40 × = −20 V/V Without Re ,
12 + 12
Rin 10
Gv = × Av | Gv | =
Rin + Rsig (10/β) + 0.025
30.3 For the nominal case, β = 100,

= × −20 = −15 V/V
30.3 + 10 Gv =
10
= 80 V/V
nominal 0.1 + 0.025
Rin + Rsig
v̂ π = 5 mV ⇒ v̂ sig = v̂ π For β = 50,
Rin
Chapter 7–27
10
Gv = = 44.4 V/V 7.78 Adding a resistance of 100 in series with
low 0.2 + 0.025 the 100- Rsig changes the input voltage divider
For β = 150, ratio from
10 1/gm 1/gm
Gv = = 109.1 V/V to
high (1/15) + 0.025 (1/gm ) + 100 1/gm + 200
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V Since this has changed the overall voltage gain
with a nominal value of 80 V/V. This is a range of from 12 to 10, then
−44.5% to +36.4% of nominal. 12 (1/gm ) + 200
= , where gm is in A/V
To limit the range of | Gv | to ±20% of a new 10 (1/gm ) + 100
nominal value, we connect a resistance Re and
0.2
find its value as follows. With Re , ⇒ gm = A/V = 2.5 mA/V
80
10
Gv = For ID = 0.25 mA
nominal (10/100) + 0.025 + Re
2ID 2 × 0.25
10 2.5 = =
= VOV VOV
0.125 + Re
⇒ VOV = 0.2 V
Now, β = 50,
10
Gv =
low 0.225 + Re
7.79 For Rin = Rsig = 50 ,
To limit this value to −20% of Gv nominal ,
we use re = 50
10
= 0.8 ×
10 and, with α 1,
0.225 + Re 0.125 + Re
VT 25 mV
⇒ Re = 0.275 k = 275 IC = = 0.5 mA
re 50
With this value of Re , gm = IC /VT = 20 mA/V
10
Gv = = 25 V/V Rin
nominal 0.125 + 0.275 Gv = gm (RC
RL )
Rin + Rsig
10
Gv = 50
low 0.225 + 0.275 Gv = × 20 × (10
10)
50 + 50
= 20 V/V (−20% of nominal)
= 50 V/V
10
Gv =
high (1/15) + 0.025 + 0.275
= 27.3 V/V (+9.1% of nominal) 7.80 Refer to the circuit in Fig. P7.80. Since
Rsig re , most of isig flows into the emitter of the
BJT. Thus
1 1
7.77 Rin = = = 0.5 k ie isig
gm 2 mA/V
Rin and
Gv = × gm (RD
RL )
Rin + Rsig ic = αie isig
0.5
= × 2(5
5) Thus,
0.5 + 0.75
= 2 V/V v o = ic RC = isig RC
For Rin = Rsig = 0.75 k

1 VT 25 mV
= 0.75 ⇒ gm = 1.33 mA/V 7.81 Rin = re = = = 125
gm IE 0.2 mA

Since gm = 2k n ID , then to change gm by a factor IC 0.2 mA
gm = = 8 mA/V
1.33 VT 0.025 V
= 0.67, ID must be changed by a factor of
2 Rin
(0.67)2 = 0.45. Gv = gm (RC
RL )
Rin + Rsig
Chapter 7–28
0.125 7.83
= × 8(10
10) = 8 V/V
0.125 + 0.5
Rin
v̂ π = v̂ sig
Rin + Rsig
0.125
10 = v̂ sig Rsig
0.125 + 0.5 i
⇒ v̂ sig = 50 mV
i
v̂ o = Gv v̂ sig = 8 × 50 = 400 mV = 0.4 V 50 mV (peak)
1
vsig
gm

RL 0.5 V (peak)
7.82 Av =
RL + Ro RL
2
Av nominal =
2 + Ro
1.5 From the figure above, we have
Av low =
1.5 + Ro 1
= 0.1 × RL
5 gm
Av high =
5 + Ro = 0.1 × 2 = 0.2 k

For Av high = 1.1 Av nominal gm = 5 mA/V

5 1.1 × 2 gm = 2k n ID
=
5 + Ro 2 + Ro
5 = 2 × 5 × ID
⇒ Ro = 0.357 k
ID = 2.5 mA
2
Av nominal = = 0.85 V/V At the peak of the sine wave,
2.357
5 0.5 V
Av high = id = = 0.25 mA, thus
5.357 2 k
= 0.93 iDmax = ID + 0.25 = 2.75 mA
(+10% above nominal) iDmin = ID − 0.25 = 2.25 mA
1.5 v̂ sig = v̂ gs + v̂ o = 0.05 + 0.5 = 0.55 V

Av low =
1.5 + 0.357
= 0.81 (−5% from nominal) 7.84
1
= Ro = 0.357 k
gm
Rsig/(b + 1)
⇒ gm = 2.8 mA/V
To find ID , we use
vbe
gm = 2k n ID re
vsig
⇒ ID = gm2 /2k n

2.82 vo
= = 1.6 mA RL
2 × 2.5
1
ID = k n VOV
2
2
1 v̂ o = 0.5 V
1.6 = × 2.5 × VOV
2
2 RL = 2 k
⇒ VOV = 1.13 V v̂ be = 5 mV
Chapter 7–29
From the figure above we see that (b)

re 5 mV
=
RL 500 mV
RL
⇒ re = = 20
100 Rsig ai
B
VT 25 mV
IE = = = 1.25 mA
re 20
i vbe
At the peak of the output sine wave, we have re
vsig
v̂ o 0.5
îe = = = 0.25 mA
RL 2
RL vo
Thus,
iEmax = 1.25 + 0.25 = 1.5 mA Rin
and
v̂ be = 10 mV
iEmin = 1.25 − 0.25 = 1.0 mA
RL
From the figure, we have v̂ o = × v̂ be
re
vo RL 500
Gv = = = × 10
v sig Rsig 12.5
RL + re +
β +1
= 400 mV = 0.4 V
2 v̂ o 0.4
= = 0.5 V/V v̂ sig = = = 0.488 V
200
2 + 0.02 + Gv 0.82
101
(c) Gv o = 1
Thus,
Rsig 10,000
v̂ o 0.5 V Rout = re + = 12.5 +
v̂ sig = = =1V β +1 101
Gv 0.5 V/V
= 111.5
Thus,
7.85 IC = 2 mA
RL
Gv = Gv o
VT VT 25 RL + Rout
re = = = 12.5
IE IC 2 500
=1× = 0.82 V/V
(a) Rin = (β + 1) (re + RL ) 500 + 111.5
which is the same value obtained in (a) above.
= 101 × (12.5 + 500) = 51.76 k
For RL = 250 ,
vb Rin 51.76
= = RL
v sig Rin + Rsig 51.76 + 10 Gv = Gv o
RL + Rout
= 0.84 V/V 250
=1× = 0.69 V/V
vo vb vo 250 + 111.5
= ×
v sig v sig vb
RL Rsig
= 0.84 × 7.86 Rout = re +
RL + re β +1
VT VT 25 mV
0.5 re = = = 50
= 0.84 × IE IC 0.5 mA
0.5 + 0.0125
10,000
= 0.82 V/V Rout = 50 + = 50 + 99 = 149
101
Chapter 7–30
RL RL ic RC
Gv = = =−
Rsig RL + Rout ib ie
RL + re + RB + (re + RE )
β +1 ib
1000 RC
= = 0.87 V = −β
1000 + 149 RB + (β + 1)(re + RE )
If β varies between 50 and 150, then we have ve −ie RE
=
10,000 v sig ib RB + ie (re + RE )
Routmax = 50 + = 50 + 196
51 RE
=
= 246 RB
+ re + RE
β +1
10,000
Routmin = 50 + = 50 + 66.2
151 (b)
= 116
RL 1000 vc
Gv min = =
RL + Routmax 1000 + 246 ic
= 0.80 V/V
RC
RL 1000
Gv max = =
RL + Routmin 1000 + 116
ie RE
= 0.90 V/V
Rsig Y
7.87 Rout = re + vsig
β +1
5000
150 = re + (1)
β +1
250 = re +
10,000
(2) v sig
ie = −
β +1 re + RE
Subtracting Eq. (1) from Eq. (2), we have ic = −ic RC = −αie RC
5000 vc −ic RC RC
100 = = =α
β +1 v sig ie (re + RE ) re + RE
β + 1 = 50
Substituting in Eq. (1) yields

7.89 With the Early effect neglected, we can
5000 write
150 = re +
50
Gv = −100 V/V
⇒ re = 50
With the Early effect taken into account, the
RL effective resistance in the collector is reduced
Gv =
Rsig from RC = 10 k to (RC
ro ), where
RL + re +
β +1
VA 100 V
1000 ro = = = 100 k
= = 0.8 V/V IC 1 mA
10, 000
1000 + 50 + (RC
ro ) = 10
100 = 9.1 k
50
Thus, Gv becomes
7.88 (a) Refer to Fig. P7.88. 9.1 k
Gv = −100 ×
vc −ic RC 10 k
=
v sig ib RB + ie (re + RE )
= −91 V/V
Chapter 7–31
7.90 Thus,
10
ro
| Gv | = (1)
1
0.1 +
gm
i ro 1
where ro and are in kilohms and are given by
Rsig gm
0 G
VA 25 V
i ro = = (2)
1 IC IC mA
gm
vg 1 VT 0.025 V
vsig = = (3)
gm IC IC mA
RL vo

I C (mA) 1/g m (k) r o (k) | Gv | (V/V)
0.1 0.250 250 27.5
v g = v sig 0.2 0.125 125 41.2
Noting that ro appears in effect in parallel with 0.5 0.050 50 55.6
RL , v o is obtained as the ratio of the voltage
1.0 0.025 25 57.1
divider formed by (1/gm ) and (RL
ro ),
1.25 0.020 20 55.6
vo vo (RL
ro )
Gv = = = Q.E.D.
v sig vg 1
(RL
ro ) + Observe that initially | Gv | increases as IC is
gm
increased. However, above about 1 mA this trend
With RL removed, reverses because of the effect of ro . From the
ro table we see that gain of 50 is obtained for IC
Gv = = 0.98 (1)
1 between 0.2 and 0.5 mA and also for IC above
ro +
gm 1.25 mA. Practically speaking, one normally uses
With RL = 500 , the low value to minimize power dissipation. The
required value of IC is found by substituting for ro
(500
ro ) and 1/gm from Eqs. (2) and (3), respectively, in
Gv = = 0.49 (2)
1 Eq. (1) and equating Gv to 50. The result (after
(500
ro ) +
gm some manipulations) is the quadratic equation.
From Eq. (1), we have IC2 − 2.25IC + 0.625 = 0
1 ro
= The two roots of this equation are IC = 0.325 mA
gm 49
and 1.925 mA; our preferred choice is
Substituting in Eq. (2) and solving for ro gives IC = 0.325 mA.
ro = 25,000 = 25 k
Thus 7.92
1 25,000
=
gm 49 VDD 9 V
⇒ gm = 1.96 mA/V
ID
RG1 RD
7.91 Adapting Eq. (7.114) gives VD
RC
RL
ro
Gv = −β VG
Rsig + (β + 1)re
VS
RC
RL
ro
=− RS
Rsig β +1 RG2
+ re
β β
RC
RL
ro
=−
Rsig 1
+
β gm
Chapter 7–32
ID = 1 mA 7.93
1
ID = k n VOV
2
5 V
2
1
1= × 2 × VOV
2
2
RD
⇒ VOV = 1 V
0 ID
VGS = Vt + VOV = 1 + 1 = 2 V VG 0
VDD
Now, selecting VS = =3V
3
RG RS
ID RS = 3
3 10 M
RS = = 3 k
1
Also, 5 V
VDD
ID RD = =3V For ID = 0.5 mA
3
3 1
⇒ RD = = 3 k 0.5 = k n VOV
2
1 2
VG = VS + VGS 1
= × 1 × VOV
2
2
=3+2=5V
⇒ VOV = 1 V
Thus the voltage drop across RG2 (5 V) is VGS = Vt + VOV = 1 + 1 = 2 V
larger than that across RG1 (4 V). So we
select Since
RG2 = 22 M VG = 0 V, VS = −VGS = −2 V
and determine RG1 from which leads to

VS − (−5) −2 + 5
RG1 4V RS = = = 6 k
= IC 0.5
RG2 5V
VD is required to be halfway between cutoff
⇒ RG1 = 0.8RG2 = 0.8 × 22
(+5 V) and saturation (0 − Vt = −1 V). Thus
= 17.6 M VD = +2 V
Using only two significant figures, we and
have
5−2
RD = = 6 k
RG1 = 18 M 0.5
Note that this will cause VG to deviate

slightly from the required value of 5 V. 7.94
Specifically,
VDD 15 V
RG2
VG = VDD
RG2 + RG1
22
=9× = 4.95 V 10 M RG1 RD
22 + 18
It can be shown (after simple but somewhat
tedious analysis) that the resulting ID will be
ID = 0.986 mA, which is sufficiently close to the
desired 1 mA. Since VD = VDD − ID RD +6 V
RS
and VG 5 V, and the drain voltage can go down 5.1 M RG2
to VG − Vt = 4 V, the drain voltage is 2 V above
the value that causes the MOSFET to leave the
saturation region.
Chapter 7–33
RG2 which is the maximum value. The minimum

VG = VDD
RG1 + RG2 value can be obtained by using k n = 0.2 mA/V2
5.1 and Vt = 1.5 V in Eq. (1),
= 15 × = 5.07 V
10 + 5.1 1
ID = × 0.2(3.57 − 0.62ID )2
k n = 0.2 to 0.3 mA/V 2 2
= 0.1(3.572 − 2 × 3.57 × 0.62ID + 0.622 ID2 )
Vt = 1.0 V to 1.5 V
0.038 ID2 − 1.442ID + 1.274 = 0
1
ID = k n (VGS − Vt2 )
2 which results in
With RS = 0, ID = 37 mA or 0.91 mA
1
ID = k n (VG − Vt2 ) Here again, the physically meaningful answer is
2 ID = 0.91 mA, which is the minimum value of ID .
IDmax is obtained with Vtmin and k nmax : Thus with a 0.62-k resistance connected in the
1 source lead, the value of ID is limited to the range
IDmax = × 0.3(5.07 − 1)2 = 2.48 mA of 0.91 mA to 1.5 mA.
2
IDmin is obtained with Vtmax and k nmin :
1 7.95
IDmin = × 0.2(5.07 − 1.5)2 = 1.27 mA
2
VDD
With RS installed and Vt = 1 V,
k n = 0.3 mA/V2 , we required ID = 1.5 mA:
1
1.5 = × 0.3(VGS − 1)2 RG1 RD
2
ID
⇒ VGS = 4.16 V
VG 5 V
Since VG = 5.07 V, ID
VS = VG − VGS = 5.07 − 4.16 = 0.91 V RS
RG2
Thus, 3 k
VS 0.91
RS = = = 607
ID 1.5
From Appendix J, the closest 5% resistor is
620 . With RS = 620 ,
VS = ID RS = 3ID
VS = ID RS = 0.62ID VGS = 5 − VS = 5 − 3ID
VGS = VG − VS = 5.07 − 0.62ID 1
1 2
2 1
= × 2(5 − 3ID − 1)2
1 2
= k n (5.07 − 0.62ID − Vt )2
2 = 16 − 24ID + 9ID2
For k n = 0.3 mA/V and Vt = 1,
2
9ID2 − 25I + 16 = 0
1 ID = 1.78 mA or 1 mA
ID = × 0.3(4.07 − 0.62ID )2
2
The first answer is physically meaningless, as it
= 0.15(4.072 − 2 × 4.07 × 0.62ID + 0.622 ID2 ) would result in VS = 5.33 V, which is greater
0.058ID2 − 1.757ID + 2.488 = 0 than VG , implying that the transistor is cut off.
Thus, ID = 1 mA.
which results in
If a transistor for which k n = 3 mA/V2 is used,
ID = 28.8 mA, or 1.49 mA then
The first value does not make physical sense. 1
ID = × 3(5 − 3ID − 1)2
Thus, 2
ID = 1.49 mA 1.5 mA = 1.5(16 − 24I + 9ID2 )

Chapter 7–34
9ID2 − 24.67ID + 16 = 0 5 V
whose physically meaningful solution is
ID = 1.05 mA RD
ID
VD
7.96
RG VS
ID
VDD RS
RD
ID
5 V
VG 5 V
VS 2 V
ID Maximum gain is obtained by using the largest
RS 2 k possible value of RD , that is, the lowest possible
value of VD that is consistent with allowing
negative voltage signal swing at the drain of 1 V.
Thus
VD − 1 = v Dmin = VG − Vt = 0 − 1
2V ⇒ VD = 0 V
ID = = 1 mA
2 k
where we have assumed that the signal voltage at
But the gate is small. Now,
1
ID = k n (VGS − Vt )2 VD = 0 = VDD − ID RD
2
0 = 5 − 0.5 × RD
1
1= × 2(VG − VS − Vt )2
2 ⇒ RD = 10 k
1 = (5 − 2 − Vt ) 2
Vt = 2 V 7.98
If Vt = 1.5 V, then we have

VDD 10 V
VS = ID RS = 2ID
IG
VGS = VG − VS = 5 − 2ID
R1 RS
1 ID
ID = × 2(5 − 2ID − 1.5)2 VS
2
4ID2 − 15ID + 12.25 = 0 VG
VD 3 V
ID = 1.2 mA ID 1 mA
VS = 2.4 V R2 RD
1
7.97 ID = 0.5 mA = × 4(VGS − 1)2
2
⇒ VGS = 1.5 V ID = 1 mA and VD = 3 V
Since VG = 0 V, VS = −1.5 V, and Thus,
−1.5 − (−5) VD 3V
RS = = 7 k RD = = = 3 k
0.5 ID 1 mA
Chapter 7–35
For the transistor to operate 1 V from the edge of 7.99

saturation
VDD
VD = VG + |Vt | − 1
Thus,
3 = VG + |Vt | − 1 RD
ID
VG + |Vt | = 4 V
0V

(a) |Vt | = 1 V and k p = 0.5 mA/V2 VGS ID
RG

VG = 3 V RS
VG 3V
R2 = = = 0.3 M
IG 10 μA
VSS
VDD − VG 7V
R1 = = = 0.7 M
IG 10 μA
VD = 3 V (a) VGS + ID RS = VSS
RD = 3 k But

1 W
1 ID = k n (VGS − Vt )2
ID = k p (VSG − |Vt |)2 2 L
2
1 = K(VGS − Vt )2
1= × 0.5(VSG − 1)2
2 ID
⇒ VGS = Vt +
⇒ VSG = 3 V K
VS = VG + 3 = 3 + 3 = 6 V Thus,

VDD − VS ID
RS = Vt + + ID RS = VSS
ID K
10 − 6 Differentiating relative to K, we have

= = 4 k
1 1 1 ∂ID ID ∂ID
0+ √ − 2 + RS =0
(b) |Vt | = 2 V and k p = 1.25 mA/V2 2 ID /K K ∂K K ∂K
∂ID K 1
VG = 4 − |Vt | = 2 V = √
∂K ID 1 + 2 KID RS
VG 2V
R2 = = = 0.2 M SKID = 1/[1 + 2 KID RS ] Q.E.D
IG 10 μA
K
VDD − VG 8V (b) K = 100 μA/V2 , = ±0.1, and
R1 = = = 0.8 M K
IG 10 μA
Vt = 1 V. We require ID = 100 μA and
VD = 3 V ID
= ±0.01. Thus,
RD = 3 k ID
ID /ID 0.01
1 SKID = = = 0.1
ID = k p (VSG − |Vt |)2 K/K 0.10
2
1 Substituting in the expression derived in (a),
1= × 1.25(VSG − 2)2
2 1
0.1 = √
VSG = 3.265 V 1 + 2 0.1 × 0.1RS
⇒ RS = 45 k
VS = VG + 3.265 = 2 + 3.265
To find VGS ,
= 5.265 V
10 − 5.265 ID = K(VGS − Vt )2
RS = = 4.7 k
1 100 = 100(VGS − 1)2
Chapter 7–36
VGS = 2 V Differentiating relative to Vt , we have
VGS + ID RS = VSS 1 2 ∂ID ∂ID

1+ √ + RS =0
2 2ID /k n k n ∂Vt ∂Vt
2 + 0.1 × 45 = 6.5 V
∂ID 1
(c) For VSS = 5 V and VGS = 2 V, √ + RS = −1
∂Vt 2k n ID
ID RS = 3 V ∂ID 1
=−
3 ∂Vt 1
RS = = 30 k √ + RS
0.1 2k n ID
1 1 ∂ID Vt Vt
SKID = √ = SVIDt = = −
1 + 2 0.1 × 0.1 × 30 7 ∂Vt ID ID
+ ID RS
ID 1 K 1 2k n
= × = × ±10% = ±1.4%
ID 7 K 7 But

1 2ID
ID = k n VOV
2
⇒ VOV =
2 kn
7.100 (a) With a fixed VGS ,
1 Thus
ID = k n (VGS − Vt )2 2Vt
2 SVIDt = − Q.E.D
VOV + 2ID RS
∂ID
= −k n (VGS − Vt ) Vt
∂Vt For Vt = 0.5 V, = ±5%, and
Vt
∂ID Vt k n (VGS − Vt )Vt ID
SVIDt ≡ =− VOV = 0.25 V, to limit to +5% we
∂Vt ID ID ID
require
k n (VGS − Vt )Vt
=−
1
k n (VGS − Vt )2 SVIDt = 1
2
Thus
2Vt 2Vt
=− =− Q.E.D 2 × 0.5
VGS − Vt VOV −1 = −
0.25 + 2ID RS
Vt
For Vt = 0.5 V, = ±5%, and ⇒ ID RS = 0.375 V
Vt
VOV = 0.25 V, we have For ID = 0.1 mA,

ID Vt 0.375
= SVIDt RS = = 3.75 k
ID Vt 0.1
2 × 0.5
=− × ±5%
0.25 7.101
= ∓20%
(b) For fixed bias at the gate VG and a resistance VDD 10 V
RS in the source lead, we have
VG = VGS + ID RS
RD 10 k
where VGS is obtained from ID
RG 0
1
2
ID
10 M
2ID
⇒ VGS = Vt +
kn VDS
Thus VGS

2ID
Vt + + ID RS = VG
kn
Chapter 7–37
VGS = VDD − ID RD 7.103

= 10 − 10ID
VDD 5 V
(a) Vt = 1 V and k n = 0.5 mA/V2
1 ~
– 1 mA
2 RD
1
ID = × 0.5(10 − 10 ID − 1)2 RG1
2 VD
⇒ ID2 − 1.84ID + 0.81 = 0 IG 1 mA
ID = 1.11 mA or 0.73 mA
The first root results in VD = −0.11 V, which is
physically meaningless. Thus RG2
ID = 0.73 mA
VG = VD = 10 − 10 × 0.73 = 2.7 V
(b) Vt = 2 V and k n = 1.25 mA/V2 1
ID = k n VOV
2
1 2
ID = × 1.25(10 − 10ID − 2)2 1
2 1= × 8VOV
2
2
⇒ ID2 − 1.616ID + 0.64 = 0
⇒ VOV = 0.5 V
ID = 0.92 mA or 0.695 mA
Since the transistor leaves the saturation region of
The first root can be shown to be physically operation when v D < VOV , we select
meaningless, thus
VD = VOV + 2
ID = 0.695 mA
VD = 2.5 V
VG = VD = 10 − 10 × 0.695 = 3.05 V
Since IG ID , we can write
VDD − VD 5 − 2.5
RD = = = 2.5 k
7.102 ID 1
VGS = Vt + VOV = 0.8 + 0.5 = 1.3 V
5V Thus the voltage drop across RG2 is 1.3 V and that

across RG1 is (2.5 − 1.3) = 1.2 V. Thus RG2 is
the larger of the two resistances, and we select
RD RG2 = 22 M and find RG1 from
ID RG1 1.2
0 = ⇒ RG1 = 20.3 M
RG RG2 1.3
VD VG VGS
Specifying all resistors to two significant digits,
we have RD = 2.5 k, RG1 = 22 M, and
RG1 = 20 M.
RB1
7.104 × 3 = 0.710
RB1 + RB2
RB2
⇒ = 3.225
RB1
1
ID = 0.2 = × 10(VGS − Vt )2 Given that RB1 and RB2 are 1% resistors, the
2 maximum and minimum values of the ratio
⇒ VGS = 1.2 V RB2 /RB1 will be 3.225 × 1.02 = 3.2895 and
3.225 × 0.98 = 3.1605. The resulting VBE will be
5 − 1.2
RD = = 19 k 0.699 V and 0.721 V, respectively.
0.2 Correspondingly, IC will be
Chapter 7–38
ICmax = 1 × e(0.710−0.699)/0.025 7.106
= 1.55 mA
VCC 9 V
and
0.06 mA 0.6 mA
ICmin = 1 × e(0.710−0.721)/0.025

ICmin = 0.64 mA
RC 3V
R1

VCE will range from
VCE 3 V
VCEmin = 3 − 1.55 × 2 = −0.1 V

which is impossible, implying that the transistor
will saturate at this value of dc bias! 3V
RE
R2
VCEmax = 3 − 0.64 × 2 = 1.72 V
It should be clear that this biasing arrangement is

useless, since even the small and inevitable
tolerances in RB1 and RB2 caused such huge Initial design: β = ∞
variations in IC that in one extreme the transistor
left the active mode of operation altogether! 3V
RC = RE = = 5 k
0.6
9
R1 + R2 = = 150 k
7.105 0.06
VB = VE + VBE = 3 + 0.7 = 3.7 V
VCC 3 V 3.7
R2 = = 61.7 k
0.06
R1 = 150 − 61.7 = 88.3 k
RC 2 k
Using 5% resistors from Appendix J, and
VCE selecting R1 and R2 so as to obtain a VBB that is
RB
slightly higher than 3.7 V, we write
R1 = 82 k and R2 = 62 k
IB RE = 5.1 k and RC = 5.1 k
R2 62
VBB = VCC =9× = 3.875
R1 + R2 62 + 82
VBB − VBE
To obtain IC = 1 mA, we write IE =
RB
RE +
IC 1 mA β +1
IB = = = 0.01 mA
β 100
where
Thus,
RB = R1
R2 = 62
82 = 35.3 k
VCC − VBE 3 − 0.7
RB = = 230 k 3.875 − 0.7
IB 0.01 IE = = 0.58 mA
35.3
5.1 +
Since β ranges from 50 to 150 and IB is fixed at 91
0.01 mA, the collector current IC will range from VE = 0.58 × 5.1 = 3.18
0.01 × 50 = 0.5 mA to 0.01 × 150 = 1.5 mA.
Correspondingly, VCE will range from VB = 3.88 V
(3 − 0.5 × 2) = 1 V to (3 − 1.5 × 2) = 0 V. The 90
latter value implies that the high-β transistor will IC = αIE = × 0.58 = 0.57 mA
91
leave the active region of operation and saturate.
Obviously, this bias method is very intolerant of VC = 6.1 V
the inevitable variations in β. Thus it is not a VB 3.88
good method for biasing the BJT. IR2 = = = 0.063 mA
R2 62
Chapter 7–39
IE 0.58 β 3.774 − 0.7

IB = = = 0.006 mA and 0.57 =
β +1 91 β +1 18
13
5.1 +
IR1 = 0.069 mA β +1
β × 3.074
=
7.107 5.1(β + 1) + 7.548
⇒ β = 75.7
VCC 9 V
0.3 mA 0.6 mA
R1 3V
RC
VBB − VBE
(a) IE =
RB
RE +
3V β +1
VB
VBB − VBE
IE nominal =
RB
RE +
3V 101
R2 RE VBB − VBE
IE high =
RB
RE +
151
Initial design: β = ∞ VBE − VBE

IE low =
RB
3V RE +
RC = RE = = 5 k 51
0.6 mA

9 Let’s constrain IE low to be equal to IE nominal ×
R1 + R2 = = 30 k
0.3 0.95 and then check IE :high
VB = VE + VBE = 3.7 V
VBB − VBE VBB − VBE
3.7 0.95 =
R2 = = 12.3 k RB RB
0.3 RE + RE +
101 51
R1 = 30 − 12.3 = 17.7 k
RB /RE
If we select 5% resistors, we will have 1+
0.95 = 101
RB /RE
RE = RC = 5.1 k 1+
51
R1 = 18 k, R2 = 13 k
RB
13 ⇒ = 5.73
VBB = 9 × = 3.774 V RE
13 + 18
VBB − VBE 3.774 − 0.7 For this value,
IE = = =
R1
R2 18
13 VBB − VBE
RE + 5.1 + IE nominal = 0.946
β +1 91 RE
0.593 mA

VBB − VBE
VE = IE RE = 3.02 V IE low = 0.90 = 0.95 IE nominal
RE
VB = 3.72 V

VBE − VBE
IC = αIE =
90
× 0.593 = 0.586 mA IE high = 0.963 = 1.02 IE nominal
91 RE
VC = VCC − IC RC = 9 − 0.586 × 5.1 = 6 V Thus, the maximum allowable ratio is
IC falls to the value obtained in Problem 7.106,
RB
namely, 0.57 mA at the value of β obtained = 5.73
from RE
VBB − VBE VBB − VBE

IC = α (b) IE =
R1
R2 RB /RE
RE + RE 1 +
β +1 β +1
Chapter 7–40
VBB − VBE 7.109

IE RE =
5.73
1+
β +1
VCC VBB − VBE 5 V
=
3 5.73
1+
101
⇒ VBB = VBE + 0.352VCC RC
IC
VC
(c) VCC = 5 V
IB
VBB = 0.7 + 0.352 × 5 = 2.46 V
VCC /3 5/3
RE = = = 3.33 k VE
IE 0.5
RB IE
RB = 5.73 × RE = 19.08 k RE
R2
VBB = VCC
R1 + R2 5 V
R2
2.46 = 5
R1 + R2
R1 R2 Required: IC = 0.5 mA and VC = VE + 2.
2.46R1 = 5 = 5RB
R1 + R2
(a) β = ∞
= 5 × 19.08
VB = 0
⇒ R1 = 38.8 k VE = −0.7 V

1 1 VE − (−5) 4.3
R2 = 1 − = 37.5 k IE = 0.5 = =
RB R1 RE RE
⇒ RE = 8.6 k
(d) VCE = VCC − RC IG
VC = VE + 2 = −0.7 + 2 = +1.3 V
1 = 5 − RC × 0.99 × 0.5
VCC − VC 5 − 1.3
RC = = = 7.4 k
⇒ RC = 8.1 k IC 0.5
(b) βmin = 50
Check design:
IE 0.5
R2 37.5 IBmax = = 0.01 mA
VBB = VCC =5× 51 51
R1 + R2 37.5 + 38.8 IE RE = 0.5 × 8.6 = 4.3 V
= 2.46 V IBmax RBmax = 0.1IE RE = 0.43 V
RB = R1
R2 = 37.5
38.8 = 19.07 k 0.43
RBmax = = 43 k
0.01
2.46 − 0.7
IE nominal = = 0.5 mA (c) Standard 5% resistors:
19.07
3.33 +
101 RB = 43 k
2.46 − 0.7 RE = 8.2 k
IE low = = 0.475 mA
19.07 RC = 7.5 k
3.33 +
51
(d) β = ∞:
which is 5% lower than IE nominal , and
VB = 0, VE = −0.7 V
2.46 − 0.7
IE = = 0.509 mA −0.7 − (−5)
high 19.07 IE = = 0.52 mA
3.33 + 8.2
151
IC = 0.52 mA

which is 1.8% higher than IE nominal . VC = 5 − 0.52 × 7.5 = 1.1 V
Chapter 7–41
β = 50: where β is the increased value of 150,

5 − 0.7 150
IE = = 0.48 mA IC = × 0.435 mA
43 151
8.2 +
51 = 0.432 mA
VE = −5 + 0.48 × 8.2 = −1.064 V Thus,
VB = −0.364 V IC = 0.432 − 0.39 = 0.042 mA
50 for a percentage increase of
IC = αIE = × 0.48 = 0.47 mA
51
IC 0.042
VC = 5 − 0.47 × 7.5 = 1.475 V × 100 = × 100 = 10.8%
IC 0.39
7.111
7.110
3 V
3 V
IE
RC
RC IE/(b 1)
VC VC
IC
RB
0.7 V
RE IE
0.4 mA
3 V VC = VCEsat + 1 V
= 1.3 V
−0.7 − (−3) 3 − 1.3
RE = IE = = 0.5 mA
0.4 RC
= 5.75 k ⇒ RC = 3.4 k
IE 0.5
To maximize gain while allowing for ±1 V signal IB = = 0.005 mA
swing at the collector, design for the lowest β +1 101
possible VC consistent with VC = VBE + IB RB
VC − 1 = −0.7 + VCEsat 1.3 = 0.7 + 0.005 × RB
= −0.7 + 0.3 = −0.4 V ⇒ RB = 120 k
VC = 0.6 V Standard 5% resistors:
VCC − VC 3 − 0.6 RC = 3.3 k

RC = = = 6.2 k
IC 0.39 RB = 120 k
As temperature increases from 25◦ C to 125◦ C, If the actual BJT has β = 50, then
(i.e., by 100◦ C), VBE decreases by 2 mV × 100 =
VCC − VBE 3 − 0.7
0.2 V IE = = = 0.41 mA
− 200 mV. Thus IE increases by = RB 120
RE RC + 3.3 +
β +1 51
0.2 V
= 0.035 mA to become 0.435 mA. The VC = 3 − IE RC = 3 − 0.41 × 3.3 = 1.65 V
5.75 k
collector current becomes Allowable negative signal swing at the collector
β is as follows:
IC = × 0.435
β +1 VC − VCEsat = 1.65 − 0.3 = 1.35 V
Chapter 7–42
An equal positive swing is just possible. For 3 V

β = 150:
3 − 0.7
IE = = 0.56 mA RC
120
3.3 + IC 2IB
151
VC = 3 − IE RC = 3 − 0.56 × 3.3 = 1.15 V 2IB
IC 1 mA
RB1
Allowable negative signal swing at the collector
= 1.15 − 0.3 = 0.85 V. An equal positive swing 0.7 V
is possible. IB
IB2 IB
RB2
7.112
3 V
Figure 2
1.01 mA
RC IC 1
0.01 mA IB = = = 0.01 mA
β 100
1.5 V
0.7 0.7
1 mA RB2 = =
IB2 0.01
RB
= 70 k
1.5 = 2IB RB1 + 0.7
0.8 = 2 × 0.01 × RB1
RB1 = 40 k
Figure 1
3 − 1.5 1.5
RC = = = 1.47 k
(a) From the circuit diagram of Fig. 1, we can IC + 2IB 1.02
write For β = ∞:
3 − 1.5 0.7 0.7
RC = 1.5 k IB = 0, IB2 = = = 0.01 mA
1.01 mA RB2 70
1.5 = 0.01RB + VBE IB1 = IB2 = 0.01 mA
= 0.01RB + 0.7 VC = 0.01RB1 + 0.7 = 0.01 × 40 + 0.7
⇒ RB = 80 k = 1.1 V
(b) Selecting 5% resistors, we have 3 − 1.1 3 − 1.1
IC + 0.01 = = = 1.29
RC 1.47
RC = 1.5 k
IC = 1.28 mA
RB = 82 k
VCC − VBE
IE =
RB 7.113
RC +
β +1
3 − 0.7
= = 0.99 mA
82
1.5 +
101 I
IC = αIE = 0.99 × 0.99 = 0.98 mA
VC = 3 − 1.5 × 0.99 = 1.52 V VC
(c) β = ∞: IB RB IC
VCC − VBE 3 − 0.7
IC = IE = = = 1.53 mA
RC 1.5
VC = 0.7 V
(d) From the circuit diagram of Fig. 2, we can
write
Chapter 7–43
IC = 1 mA 7.115
I = IC + IB
IC VCC
= IC +
β R1 I
IO
1
=1 1+
β
I = 1.01 mA 0
Q1
VC = 1.5 V = IB RB + VBE VB
I
1.5 = 0.01 × RB + 0.7
Q2 IO
RB = 80 k RE
R2
7.114 Refer to the circuit in Fig. P7.114.

Replacing VCC together with the voltage divider
(R1 , R2 ) by its Thévenin equivalent results in the
VCC − VBE1 − VBE2
circuit shown below. I=
R1 + R2
VB = IR2 + VBE2 + VBE1
VE3 = VB − VBE3
IO aIE VE3 = IR2 + VBE2 + VBE1 − VBE3
R2
IE /(b1) = (VCC − VBE1 − VBE2 ) + VBE1
R1 + R2
+VBE2 − VBE3
RB
VE α R2
VBB IE IO = = (VCC − VBE1 − VBE2 )
RE RE R1 + R2

RE + VBE1 + VBE2 − VBE3
Now, for R1 = R2 and the currents in all junctions

equal,
VBE1 = VBE2 = VBE3 = VBE
where
1 1
IO = (VCC − 2VBE ) × + VBE
R2 RE 2
VBB = VCC
R1 + R2
VCC
IO = Q.E.D
and 2RE
RB = (R1
R2 ) Thus,
VCC
Now, IO RE =
2
IE
VBB = RB + VBE + IE RE VB =
VCC
+ VBE
β +1 2
VBB − VBE
IE = VCC
RE + (R1
R2 )/(β + 1) I = (VB − 2VBE )/R2 = − VBE R2
2
IC = αIE But since I must be equal to IO , we have
VCC [R2 /(R1 + R2 )] − VBE VCC VCC /2 − VBE
=α =
RE + (R1
R2 )/(β + 1) 2RE R2
Chapter 7–44
Thus, 7.117 Refer to the equivalent circuit in

Fig. 7.55(b).
VCC − 2VBE
R1 = R2 = RE Rin
VCC Gv = − gm (RD
RL
ro )
Rin + Rsig
For VCC = 10 V and VBE = 0.7 V,
=−
RG
gm (RD
RL
ro )
10 − 1.4 RG + Rsig
R1 = R2 = RE = 0.86RE
10
10
To obtain IO = 0.5 mA, =− × 3 × (10
20
100)
10 + 1
0.5 =
VCC
=
10 = −17 V/V
2RE 2RE
⇒ RE = 10 k 7.118 (a) Refer to Fig. P7.118. The dc circuit can
be obtained by opening all coupling and bypass
R1 = R2 = 8.6 k
capacitors, resulting in the circuit shown
in Fig. 1.
7.116
5 V
50.7
IE R
R
0.7 V
IO
Figure 1
IO = αIE 0.5 mA
See analysis on figure.
IE = 0.5 mA
VGS = 2 − 1 = 1 V
5 − 0.7
⇒R= = 8.6 k VOV = VGS − Vt = 1 − 0.7 = 0.3 V
0.5
v Cmax = 0.7 − VECsat = 0.7 − 0.3 Since VD at 2.5 V is 1.2 V higher than
VS + VOV = 1 + 0.3 = 1.3 V, the transistor is
= +0.4 V

Rsig

vsig vgs vo

RG1 RG2 gmvgs ro RD RL
5 k 5 k

Rin RG RG1 // RG2
Figure 2
Chapter 7–45
indeed operating in saturation. (Equivalent 7.119 Refer to Fig. P7.119.

VD = 2.5 V is higher than VG − Vt = 1.3 V by
1.2 V.) (a) DC bias:
1 |VOV | = 0.3 V ⇒ VSG = |Vtp | + |VOV | = 1 V

ID = k n VOV
2
2 Since VG = 0 V, VS = VSG = +1 V, and
1
0.5 = k n × 0.33 2.5 − 1
2 ID = = 0.3 mA
RS
⇒ k n = 11.1 mA/V2
1.5
(b) The amplifier small-signal equivalent-circuit ⇒ RS = = 5 k
0.3
model is shown in Fig. 2.
(b) Gv = −gm RD
Rin = RG1
RG2 = 300 k
200 k = 120 k
where
2ID 2 × 0.5
gm = = = 3.33 mA/V 2ID 2 × 0.3
VOV 0.3 gm = = = 2 mA/V
VOV 0.3
VA 50
ro = = = 100 k Thus,
ID 0.5
Rin −10 = −2RD ⇒ RD = 5 k
Gv = − gm (ro
RD
RL )
Rin + Rsig (c) v G = 0 V (dc) + v sig
120
=− × 3.33 × (100
5
5) v Gmin = −v̂ sig
120 + 120
= −4.1 V/V v̂ D = VD + | Gv |v̂ sig
(c) VG = 2 V, VD = 2.5 V where
v̂ GS = 2 + v̂ gs , v̂ DS = 2.5 − | Av |v̂ gs VD = −2.5 + ID RD = −2.5 + 0.3 × 5 = −1 V

where To remain in saturation,
| Av | = gm (ro
RD
RL ) = 8.1 V/V v̂ D ≤ v̂ G + |Vtp |
To remain in saturation, −1 + 10 v̂ sig ≤ −v̂ sig + 0.7
v̂ DS ≥ v̂ GS − Vt Satisfying this constraint with equality gives
2.5 − 8.1v̂ gs ≥ 2 + v̂ gs − 0.7
v̂ sig = 0.154 V
This is satisfied with equality at
and the corresponding output voltage
2.5 − 1.3
v̂ gs = = 0.132 V v̂ d = | Gv |v̂ sig = 1.54 V
9.1
The corresponding value of v̂ sig is (d) If v̂ sig = 50 mV, then

120 + 120 VD + | Gv |v̂ sig = −v̂ sig + |Vtp |
v̂ sig = v̂ gs = 2 × 0.132 = 0.264 V
120
where
The corresponding amplitude at the output
will be VD = −2.5 + ID RD = −2.5 + 0.3RD
| Gv |v̂ sig = 4.1 × 0.264 = 1.08 V and

(d) To be able to double v̂ sig without leaving | Gv | = gm RD = 2RD
saturation, we must reduce v̂ gs to half of what
would be its new value; that is, we must keep v̂ gs Thus
unchanged. This in turn can be achieved by −2.5 + 0.3RD + 2RD v̂ sig = −v̂ sig + |Vtp |
connecting an unbypassed Rs equal to 1/gm ,
1 −2.5 + 0.3RD + 2RD × 0.05 = −0.05 + 0.7
Rs = = 300
3.33 mA/V 0.4RD = 3.15
Since v̂ gs does not change, the output voltage also ⇒ RD = 7.875 k
will not change, thus v̂ o = 1.08 V.
Gv = −gm RD = −2 × 7.875 = −15.75 V/V
Chapter 7–46
7.120 Refer to Fig. P7.120. 10

=− × 2 × (100
12.5
10)
10 + 1
1
Ri2 = = 50 = −9.6 V/V
gm2
1 (d) If terminal Y is grounded, the circuit becomes
⇒ gm2 = A/V = 20 mA/V a CD or source-follower amplifier:
50
vz (RS
ro )
If Q1 is biased at the same point as Q2 , then =
vx 1
gm1 = gm2 = 20 mA/V (RS
ro ) +
gm
id 1 = gm1 × 5 (mV) (9.5
100)
= = 0.946 V/V
1
= 20 × 0.005 = 0.1 mA (9.5
100) +
2
v d 1 = id 1 × 50 Looking into terminal Z, we see Ro :
= 0.1 × 50 = 5 mV 1
Ro = RS
ro
gm
v o = id 1 RD = 1 V
1
1V = 9.5
100
= 473
RD = = 10 k 2
0.1 mA
(e) If X is grounded, the circuit becomes a CG
amplifier.
7.121 (a) DC bias: Refer to the circuit in Fig.
P7.121 with all capacitors eliminated:
Rin at gate = RG = 10 M
VG = 0, thus VS = −VGS , where VGS can be RD
obtained from
vy
1
ID = k n VOV
2
2
1 vsg
0.4 = × 5 × VOV
2
2
⇒ VOV = 0.4 V RS isig 50 A
VGS = Vt + 0.4 = 0.8 + 0.4 = 1.2 V

VS = −1.2 V Rsig 100 k
−1.2 − (−5)
RS = = 9.5 k
0.4 The figure shows the circuit prepared for signal
To remain in saturation, the minimum drain calculations.

voltage must be limited to VG − Vt = 1
0 − 0.8 = −0.8 V. Now, to allow for 0.8-V v sg = isig × Rsig
RS
gm
negative signal swing, we must have
1
VD = 0 V = 50 × 10−3 (mA) 100
9.5
(k)
2
and = 0.024 V
5−0 v y = (gm RD )v sg
RD = = 12.5 k
0.4
= (2 × 12.5) × 0.024 = 0.6 V
2ID 2 × 0.4
(b) gm = = = 2 mA/V
VOV 0.4
VA 40 7.122 (a) Refer to the circuit of Fig. P7.122(a):
ro = = = 100 k
ID 0.4 v o1 10 10
Av o ≡ = = = 0.99 V/V
(c) If terminal Z is connected to ground, the vi 1 1
10 + 10 +
circuit becomes a CS amplifier, gm 10
vy RG 1
Gv = − = × −gm (ro
RD
RL ) Ro =
10 k = 0.1
10 = 99
v sig RG + Rsig gm
Chapter 7–47
(b) Refer to Fig. P7.122(b): VD = 5VGS = 5 × 0.8 = 4 V

1 1 VDS
Rin = 10 k
= 10
0.1 = 99 ID = k n VOV
2
1+
gm 2 VA
vo 5
2
= = 10(5
2) = 14.3 V/V 1 4
v i2 1/gm ID = × 5 × 0.22 1 +
2 60
Rin = 0.107 mA
(c) v i2 = (Av o v i )
Rin + Ro
The current in the voltage divider is
99
= 0.99 × v i ×
99 + 99 VD 4
I= = = 1.6 μA = 0.0016 mA
0.5v i R1 + R2 2.5
v o = 14.3 × v i2 = 14.3 × 0.5v i Thus the current through RD will be

(0.107 + 0.0016) 0.109 mA and
vo
= 7.15 V/V
vi VDD − VD 10 − 4
RD = = = 55 k
0.109 0.109
7.123 (a) DC bias: 2ID 2 × 0.107
(b) gm = = = 1.07 mA/V
VOV 0.2
VDD 10 V VA 60
ro = = = 561 k
ID 0.107
(c) Upon replacing the MOSFET with its
RD
hybrid-π model, we obtain the small-signal
R2 2 M equivalent circuit of the amplifier, shown in
VD Fig. 2.
ID Node equation at the output:
vo vo v o − v gs
+ + + gm v gs = 0
RD ro R2
VGS R1 0.5 M
1 1 1 1
vo + + = −gm 1 − v gs
RD ro R2 gm R2
Thus,
Figure 1
A

1
VGS = Vt + VOV v o = − gm (RD
ro
R2 ) 1 − v gs (1)
gm R2
= 0.6 + 0.2 = 0.8 V
Next, we express v gs in terms of v sig and v o using
From the voltage divider (R1 , R2 : see Fig. 1), we superposition:
can write
R2 R1
R1 0.5 v gs = v sig + vo (2)
VGS = VD = VD R1 + R2 R1 + R2
R1 + R2 0.5 + 2
This figure belongs to Problem 7.123(c).

(vo vgs)⁄R2
R2
R1

vsig gmvgs vo
vgs RD ro

Figure 2
Chapter 7–48
Substituting for v gs from Eq. (2) into Eq. (1) VOV = 0.2 V
yields
VGS = Vt + VOV
R2 R1
v o = −Av sig − Av o = 0.6 + 0.2 = 0.8 V
R1 + R2 R1 + R2
where From the voltage divider (R1 , R2 : see Fig. 1), we
can write
1
A = gm (RD
ro
R2 ) 1 − R1 0.5
gm R2 VGS = VD = VD = 0.5VD
R1 + R2 0.5 + 0.5
Thus,
Thus
R1 R2
vo 1 + A = −A v sig
R1 + R2 R1 + R2 VD = 2VGS = 1.6 V
R2 1
−A ID = k n VOV
2
vo R1 + R2 2
=
v sig R1
1+A 1
R1 + R2 = × 5 × 0.22 = 0.1 mA
2
−R2 /R1
= VD 1.6 V
1 + R2 /R1 Idivider = = = 1.6 μA
1+ 1 M 1 M
A
Thus, IRD = 0.1 + 0.0016 0.102 mA
vo R2 /R1
=− VDD − VD 10 − 1.6
v sig 1 + R2 /R1 RD = = = 82.4 k
1+ IRD 0.102
gm (RD
ro
R2 )(1 − 1/gm R2 )
2ID 2 × 0.1
Q.E.D (b) gm = = = 1 mA/V
VOV 0.2
Substituting numerical values yields
(c) Replacing the MOSFET with its T model
vo
= results in the amplifier equivalent circuit shown in
v sig Fig. 2. At the output node,
2/0.5
−
1 + (2/0.5) v o = i[RD
(R1 + R2 )]
1+
1.07(55
561
2000)(1 − 1/1.07 × 2000) v o = iRD (1)
4
= −
5
1+
52.6 vo
= −3.65 V/V
Note that the gain is nearly equal to −R2 /R1 = R2 i RD
− 4, which is the gain of an op amp connected in
0
the inverting configuration.
bvo
1/gm
7.124 (a) DC bias: i
R1
VDD 10 V vsig

RD
R2 0.5 M Figure 2
VD
where RD = RD
(R1 + R2 ). The voltage at the
gate is a fraction β of v o with
R1
β=
VGS R1 + R2
R1 0.5 M
Now, the current i can be found from

v sig − βv o
i= = gmv sig − βgmv o (2)
Figure 1 1/gm
Chapter 7–49
Substituting for i from Eq. (2) into Eq. (1) yields 7.125 Refer to the circuit of Fig. P7.125.
v o = (gm v sig − βgm v o )RD α(VBB − VBE )
IC =
RB
Thus RE +
β +1
vo gm RD
= where
v sig 1 + βgm RD
R2 15
1/β VBB = VCC = 15 × = 5.357 V
= R2 + R1 15 + 27
1/β
1+ RB = R1
R2 = 15
27 = 9.643 k
gm RD
0.99(5.357 − 0.7)
1 + (R2 /R1 ) IC = = 1.85 mA
= Q.E.D (3) 9.643
1 + R2 /R1 2.4 +
1+ 101
gm RD
IC 1.85 mA
The input resistance Rin can be obtained as gm = = = 74 mA/V
VT 0.025 V
follows:
v sig β 100
Rin = rπ = = = 1.35 k
i gm 74
Substituting for i from Eq. (1) yields Replacing the BJT with its hybrid-π model
v sig results in the equivalent circuit shown at the
Rin = R bottom of the page:
vo D
v sig Rin = R1
R2
rπ = RB
rπ = 9.643
1.35
and replacing by the inverse of the gain
vo = 1.18 k
expression in Eq. (3) gives
vπ Rin 1.18
1 1 = = = 0.371 V/V
Rin = RD + v sig Rin + Rsig 1.18 + 2
gm RD 1 + (R2 /R1 )
vo
1 R1 = −gm (RC
RL )
Rin = 1 + gm RD Q.E.D vπ
gm R1 + R2
= −74(3.9
2) = −97.83
(d) Substituting numerical values: vo
= −0.371 × 97.83 = −36.3 V/V
vo 1 + (0.5/0.5) v sig
=
v sig 1 + (0.5/0.5)
1+
1 × (82.4
1000) 7.126 Refer to the circuit of Fig. P7.125.
2 DC design:
= = 1.95 V/V
2
1+ VB = 5 V, VBE = 0.7 V
76.13
R2 VE = 4.3 V
Note that the gain 1 + = 2, similar to that
R1 For
of an op amp connected in the noninverting
configuration! VE 4.3
IE = 2 mA, RE = = = 2.15 k
IE 2
1 0.5
Rin = 1 + 1 × (82.4
1000) 5
1 0.5 + 0.5 IR2 = 0.2 mA, R2 = = 25 k
0.2
= 39.1 k
IE 2
IB = = 0.02 mA
β +1 101
Rsig
vo

vsig vp rp gmvp RC RL
R1 R2

Rin
Chapter 7–50
IR1 = IR2 + IB = 0.2 + 0.02 = 0.22 mA which is slightly higher than the required gain,
and we will obtain
VCC − VB 15 − 5
R1 = = = 45.5 k
IR1 0.22 VC = 15 − 5.1 × 1.84 = 5.6 V
Choosing 5% resistors: which allows for only 1.2-V negative signal
swing.
RE = 2.2 k, R1 = 47 k, R2 = 24 k
For these values,
7.127 Refer to the circuit of Fig. P7.125:
VBB − VBE
IE = α(VBB − VBE )
RB IC =
RE + RB
β +1 RE +
β +1
where
R2 24 where
VBB = VCC = 15 × = 5.07 V R2 47
R1 + R2 24 + 47 VBB = VCC = 15 × = 5.465 V
R2 + R1 47 + 82
RB = R1
R2 = 47
24 = 15.89 k
RB = R1
R2 = 47
82 = 29.88 k
5.07 − 0.7
IE = = 1.85 mA 0.99(5.465 − 0.7)
15.89 IC = = 0.63 mA
2.2 + 29.88
101 7.2 +
101
VB = IE RE + VBE = 1.85 × 2.2 + 0.7 = 4.8 V
IC 0.63
gm = = = 25.2 mA/V
IC = αIE = 0.99 × 1.85 = 1.84 mA VT 0.025
IC 1.84 β 100
gm = = = 73.4 mA/V rπ = = = 4 k
VT 0.025 gm 25.2
β 100 Rin = R1
R2
rπ = RB
rπ
rπ = = = 1.36 k
gm 73.4 = 29.88
4 = 3.5 k
Rin = R1
R2
rπ = 47
24
1.36 = 1.25 k vπ 3.5
= = 0.636 V/V
vπ Rin 1.25 v sig 3.5 + 2
= = = 0.385 V/V
v sig Rin + Rsig 1.25 + 2 vo
= −gm (RC
RL )
For an overall gain of −40 V/V, vπ
vo 40 = −25.2(12
2) = −43.2 V/V
=− = −104 V/V vo
vπ 0.385 = −0.636 × 43.2 = −27.5 V/V
v sig
But
vo Comparing the results above to those of Problem
= −gm (RC
RL )
vπ 7.125, we see that raising the resistance values
has indeed resulted in increasing the transmission
−104 = −73.4 (RC
2)
from source to transistor base, from 0.371 V/V to
(RC
2) = 1.416 0.636 V/V. However, because IC has decreased
and gm has correspondingly decreased, the gain
RC = 4.86 k
from base to collector has decreased by a larger
We can select either 4.7 k or 5.1 k. With factor (from 97.83 V/V to 43.2 V/V), with the
4.7 k, the gain will be result that the overall gain has in fact decreased
vo (from 36.3 V/V to 27.5 V/V). Thus, this is not a
= −0.385 × 73.4 × (4.7
2) = −39.6 V/V successful strategy!
v sig
which is slightly lower than the required
−40 V/V, and we will obtain 7.128 Refer to the circuit of Fig. P7.128.
VC = 15 − 4.7 × 1.84 = 6.4 V DC voltage drop across RB = 0.2 V, and
allowing for about 2 V of negative signal swing IB RB = 0.2 V
at the collector. If we choose 5.1 k, the gain I
will be RB = 0.2 V
β +1
vo
= −0.385 × 73.4 × (5.1
2) = −40.6 V/V IRB = 0.2 × 101 (1)
v sig
Chapter 7–51
Rin = RB
rπ = 10 k ⇒ RC = 21.2 k
VT Selecting 5% resistors, we find
RB
= 10
IB
RB = 91 k
0.025
RB
= 10 RC = 22 k
I /(β + 1)
and specifying I to one significant digit gives
0.025 × 101
RB
= 10
I I = 0.2 mA
0.025 × 101 αIC 0.2
RB × gm = = 8 mA/V
I VT 0.025
= 10
0.025 × 101 Av o = −gm RC = −8 × 22 = −176 V/V
RB +
I β 100
0.025 × 101RB rπ = = = 12.5 k
= 10 (2) gm 8
IRB + 0.025 × 101
Rin = RB
rπ = 91
12.5 = 11 k
Substituting for IRB from Eq. (1) yields 11
Gv = − × 8(22
20)
0.025 × 101RB 20 + 11
= 10
0.2 × 101 + 0.025 × 101 = −29.7 V/V
0.025RB
= 10
0.225
7.129 Refer to the circuit of Fig. P7.129.
⇒ RB = 90 k
(a) IE = 0.5 mA. Writing a loop equation for the
0.2 × 101
I= = 0.22 mA base–emitter circuit results in
90
To maximize the open-circuit voltage gain IB Rsig + VBE + IE RE = 3
between base and collector while ensuring that IE
Rsig + VBE + IE RE = 3
the instantaneous collector voltage does not fall β +1
below (v B − 0.4) when v be is as high as 5 mV, we
0.5
impose the constraint × 2.5 + 0.7 + 0.5RE = 3
101
VC − | Av o | × 0.005 = VB + 0.005 − 0.4
⇒ RE = 4.6 k
where
(b) IC = αIE 0.5 mA
VC = VCC − IC RC
VC = 0.5 = 3 − 0.5RC
= 5 − 0.99 × 0.22RC
⇒ RC = 5 k
= 5 − 0.22RC
IC 0.5 mA
0.99 × 0.22 (c) gm = = = 20 mA/V
| Av o | = gm RC = RC = 8.7RC VT 0.025 V
0.025
β 100
and rπ = = = 5 k
gm 20
0.22
VB = − × 90 = −0.2 V vo 5
101 Gv = =− × 20 × (5
10)
Thus, v sig 5 + 2.5
= −44.4 V/V
5 − 0.22RC − 8.7RC × 0.005 = −0.2 − 0.395

Rsig
vo

vsig rp vp

gmvp RC RL

Chapter 7–52
7.130 Refer to the circuit of Fig. P7.130. IC 0.1 mA

gm = = 4 mA/V
VT 0.025 V
(a) DC analysis of each of the two stages:
Note that the emitter has a resistance
R2 47 Re = 250 .
VBB = VCC = 15 = 4.8 V
R1 + R2 100 + 47
Rin = 200 k
(β + 1)(re + Re )
RB = R1
R2 = 100
47 = 32 k
= 200
[101 × (0.25 + 0.25)]
VBB − VBE
IE = = 200
50.5 = 40.3 k
RB
RE +
β +1 vb Rin 40.3
= = = 0.668 V/V
4.8 − 0.7 v sig Rin + Rsig 40.3 + 20
= = 0.97 mA 1 mA
32 vo Total resistance in collector
3.9 + = −α
101 vb Total resistance in emitter
IC = αIE 1 mA 20
20
− = −20 V/V
VC = VCC − IC RC = 15 − 1 × 6.8 = 8.2 V 0.25 + 0.25
vo
(b) See figure above. Gv = = −0.668 × 20 = −13.4 V/V
v sig
IC
gm = = 40 mA/V For v be to be limited to 5 mV, the signal between
VT base and ground will be 10 mV (because of the
β 5 mV across Re ). The limit on v sig can be obtained
rπ = = 2.5 k by dividing the 10 mV by v b /v sig ,
gm
(c) Rin1 = R1
R2
rπ = RB
rπ = 32
2.5 10 mV
v̂ sig = = 15 mV
0.668
= 2.32 k
Correspondingly, at the output we have
v b1 Rin 2.32
= = = 0.32 V/V
v sig Rin + Rsig 2.32 + 5 v̂ o = | Gv |v̂ sig = 13.4 × 15 = 200 mV = 0.2 V
(d) Rin2 = R1
R2
rπ = Rin1 = 2.32 k
7.132 (a)
v b2 v b2
= = −gm (RC
Rin2 )
v b1 vπ1
= −40(6.8
2.32) = −69.2 V/V
vo vo 0.5 mA
(e) = = −gm (RC
RL )
v b2 v π2
= −40(6.8
2) = −61.8 V/V VC
vo vo v b2 v b1 0.495 mA
(f) = × × = −61.8 200 k
v sig v b2 v b1 v sig
× − 69.2 × 0.32 = 1368.5 V/V
0.005 mA
0.5 mA
7.131 Refer to the circuit in Fig. P7.131:
200
IE = 0.1 mA
VT 25 mV
re = = = 250
IE 0.1 mA Figure 1
Chapter 7–53
vo
From Fig. 1 we see that
IC = 0.495 mA 100 k ie 5 k
VC = IB × 200 k + IE × 0.2 k + VBE
= 0.005 × 200 + 0.5 × 0.2 + 0.7
ie
= 1.18 V re 50
Rsig 50
(b)
vo v
sig
vo vi
200
i Rin re 50
200 k 20 k
−v sig −v sig
= =
100 0.1 k
i re 50 At the output node,

vi v o = −αie (5
100)
200 v sig
=α (5
100)
0.1
vo 5
100
=α 47.6 V/V
Figure 2 v sig 0.1
From Fig. 2, we have 3 − 0.7

7.134 (a) IE =
IC 0.495 100
gm = = 20 mA/V 1+
VT 0.025 β +1
VT β = 50:
re = = 50
IE 2.3
IE = = 0.78 mA
vi vi 100
i= = 1+
re + Re 50 + 200 51
vi vi VE = IE RE = 0.78 V
= = = 4 v i , mA
250 0.25 k VB = VE + 0.7 = 1.48 V
Node equation at the output:
β = 200:
vo vo − vi
+ αi + =0 2.3
20 200 IE = = 1.54 mA
vo vo vi 100
+ 0.99 × 4v i + − =0 1+
20 200 200 201
VE = IE RE = 1.54 V
1 1 1
vo + = −v i 4 × 0.99 −
20 200 200 VB = VE + 0.7 = 2.24 V
vo (b) Rin = 100
(β + 1)[re + (1
1)]
= −71.9 V/V
vi
= 100
(β + 1)(re + 0.5)
β = 50:
VT 25 mV
The dc emitter current is equal to 0.5 mA, and re = = = 32.1
IE 0.78 mA
IC = αIE 0.5 mA; also,
Rin = 100
[51 × (0.0321 + 0.5)]
VT 25 mV
re = = = 50 = 21.3 k
IE 0.5 mA
Rin = re = 50 β = 200:
−v sig −v sig VT 25 mV
ie = = re = = = 16.2
re + Rsig 50 + 50 IE 1.54 mA
Chapter 7–54
Rin = 100
[201 × (0.0162 + 0.5)] io vo 130.4
= × = 0.964 × 65.2
ii vb 2
= 50.9 k
= 62.9 A/A
vb Rin
(c) = 100
v sig Rin + Rsig Rout = 3.3
re +
β +1
vo (1
1) 500
= = (re in ) 100
vb (1
1) + re 500 + re = 3.3
0.0463 +
101
β = 50:
= 0.789 k = 789
vb 21.3
= = 0.68 V/V
v sig 21.3 + 10
vo 500
= = 0.94 V/V For dc analysis, open-circuit the two coupling
vb 500 + 32.1
capacitors. Then replace the 9-V source and the
vo
= 0.68 × 0.94 = 0.64 V/V two 20-k resistors by their Thévenin equivalent,
v sig namely, a 4.5-V source and a 10-k series
β = 200: resistance. The latter can be added to the 10-k
resistor that is connected to the base. The result is
vb 50.9
= = 0.836 V/V the circuit shown in Fig. 1, which can be used to
v sig 50.9 + 10 calculate IE .
vo 500
= = 0.969 V/V
vb 500 + 16.2 9 V
vo
= 0.836 × 0.969 = 0.81 V/V
v sig
4.5 V 20 k

IE
3 − 0.7
IE = 2 k
100
3.3 +
β +1
2.3
= = 0.54 mA
100
3.3 + Figure 1
101
VT 25 mV 4.5 − 0.7
re = = = 46.3 (a) IE =
IE 0.54 mA 20
2+
Rin = (β + 1)[re + (3.3
2)] β +1
= 101 × (0.0463 + 1.245) 3.8

= = 1.73 mA
20
= 130.4 k 2+
101
vb Rin 130.4 IC = αIE = 0.99 × 1.73 mA
= =
v sig Rin + Rsig 130.4 + 100
= 1.71 mA
= 0.566 V/V IC
gm = = 68.4 mA/V
vo 3.3
2 1.245 VT
= =
vb (3.3
2) + re 1.245 + 0.0463 VT 25 mV
re = = = 14.5
= 0.964 V/V IE 1.73 mA
vo = 0.0145 k
= 0.566 × 0.964 = 0.55 V/V
v sig rπ = (β + 1)re = 101 × 0.0145
vo
io = = 1.4645 k
2 k
vi vb (b) Replacing the BJT with its T model (without
ii = = ro ) and replacing the capacitors with short circuits
Rin 130.4 k
Chapter 7–55
results in the equivalent-circuit model shown in

Fig. 2.
Figure 3
Thus,
Figure 2 Rin = 20 k
Rib
= 20 k
(β + 1)(Re + 2)
From Fig. 2 we see that
= 20
101 × 2.0145
re
v e = ie + ie (10
2) = 18.21 k
10
re
v b = v e + ie re = ie (10
2) 1 + + ie re which is greatly reduced because of the absence
10 of bootstrapping. The latter causes the lower node
re of the 10-k base-biasing resistor to rise with the
ii = (1 − α)ie + ie
10 output voltage, thus causing a much reduced
ie re signal current in the 10-k resistor and a
= + ie correspondingly larger effective resistance across
β +1 10
the amplifier input.
We can now obtain Rin from
re The reduced Rin will result in a reduction in
vb (10
2) 1 + + re v b /v sig ,
Rin ≡ = 10
ii 1 re vb Rin 18.21
+ = =
β + 1 10 v sig Rin + Rsig 28.21
re
(β + 1)(10
2) 1 + + (β + 1)re = 0.646 V/V
= 10
re vo 2
1 + (β + 1) = = 0.993
10 vb 2 + 0.0145
101 × (10
2) × (1 + 0.00145) + 101 × 0.0145 vo
= Gv ≡ = 0.646 × 0.993
1 + 101 × 0.00145 v sig
168.577 + 1.4645 = 0.64 V/V
= = 148.3 k
1 + 0.14645
which is much reduced relative to the value
vb Rin 148.3
= = = 0.937 obtained with bootstrapping.
re
vo ve i e 1 + (10
2) 7.137
= = r 10
vb vb ie 1 +
e
(10
2) + ie re (a) Applying Thévenin’s theorem to the
10 base-biasing circuit of Q1 results in the dc circuit
1.00145 × (10
2) shown below. From our partial analysis on the
=
1.00145 × (10
2) + 0.0145 figure, we can write
= 0.991 V/V IE1 = 0.1 mA
vo
Gv ≡ = 0.937 × 0.991 = 0.93 V/V IE2 = 5 mA
v sig
VB1 can be obtained as
(c) When CB is open-circuited, the equivalent
circuit becomes that shown in Fig. 3. VB1 = 2.5 − 2 μA × 0.5 M = 1.5 V
Chapter 7–56
Rin = 0.5 M
[51 × (0.25 + 101.5)] k
0.5 M
= 0.5 M
5.2 M
100 2 A = 456 k
51 100 A
2.5 V 0.1 mA v e1 Rib 101.5
= =
v b1 Rib + re1 101.5 + 0.25
0.05 mA
= 0.9975 V/V
50 A
v b1 Rin 456
50 A 5 mA (d) = = = 0.82 V/V
v sig Rin + Rsig 456 + 100
vo
(e) = 0.82 × 0.9975 × 0.995 = 0.814 V/V
v sig
and VB2 can be found as 7.138 We need to raise fH by a factor of

VB2 = VB1 − 0.7 = 0.8 V 2 MHz
= 4. Thus
500 kHz
(b) Refer to the circuit in Fig. P7.137. With a 1 + gm Re = 4
load resistance RL = 1 k connected to the
output terminal, the voltage gain v o /v b2 can be 3
⇒ Re =
found as gm
vo RL Since
=
v b2 RL + re1 IC 1 mA
gm = = = 40 mA/V
where VT 0.025 V
25 mV 3
re2 = =5 Re = = 75
5 mA 0.04
vo 1000 The new value of fL will be
= = 0.995 V/V
v b2 1000 + 5 100 Hz 100
Rib2 = (β2 + 1)(re2 + RL ) fL = = = 25 Hz
1 + gm Re 4
= 101 × 1.005 = 101.5 k and the midband gain will become
(c) Rin = 1 M
1 M
(β + 1)(re1 + Rib2 ) | AM | =
100
=
100
= 25 V/V
1 + gm Re 4
where
VT 25 mV
re = = = 250 = 0.25 k
IE1 0.1 mA

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Exercise 7–1

Ex: 7.1 Refer to Fig. 7.2(a) and 7.2(b). Av = −k n VOV RD

Ex: 7.2 Refer to Example 7.1 and Fig. 7.4(a). RD

VOV = 0.2 V, VGS = 0.6 V

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= [200 + 80 sinωt + (4 − 4 cos2ωt)] 1 16

î2ω 4 μA = 0.72 mA/V

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10 − 0.7 VE = −0.1 − 0.7 = −0.8 V

This ﬁgure belongs to Exercise 7.20c.

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Av o = −gm RC = −20 × 10 = −200 V/V

v̂ π = 5 mV ⇒ v̂ sig = 2 × 5 = 10 mV VT αVT 0.99 × 25

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Ex: 7.28 Refer to Fig. 7.41(c).

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4 − 0.7 To maintain active-mode operation at all times,

Ex: 7.37 Refer to Fig. 7.55(b).

select RC as large as possible, consistent with 2

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Thus, Ex: 7.40 Refer to Fig. 7.56(a). For VB = 5 V and

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Rin = RB1  RB2  [(β + 1)(re + Re )] 50

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7.1 Coordinates of point A: v GS = Vt = 0.5 V The lowest instantaneous

5 − 0.5 To obtain a gain of −12 V/V at point Q:

Equations (7.7) and (7.8):

Thus, the large-signal gain is

For VDS = 1 V, Av = −16 = −k n VOV RD Substituting VDD = 5 V, rearranging the equation

The value of VDS at the bias point can now be

(b) The gain achieved can be found as

equate iD1 and iD2 max +v O = 5 − 4.5 = 0.5 V

7.10 Refer to Fig. 7.6.

VCC = VCE + | Av |VT

VCC /2 0.5 0.75 1.0 1.5 (V)

This ﬁgure belongs to Problem 7.15.

This ﬁgure belongs to Problem 7.16(a).

This ﬁgure belongs to Problem 7.16(b).

Thus, using the small-signal approximation 0 t

0.5 × 10−3 = 10−15 eVBE /0.025

For a transistor biased at IC = 0.5 mA, we have VCE = v CE = 4.76 V

7.22 See the graphical construction that follows.

And the collector voltage varies as follows: gm = k n VOV = 10 × 0.2 = 2 mA/V

1 1 The required value of k n can be found from

Finally, VOV = mv̂ i = 15 × 20 = 0.3 V

which results in ⇒ k n = 4.44 mA/V2

7.29 Given μn Cox = 250 μA/V2 , vd −RD −gm RD

This ﬁgure belongs to Problem 7.33, part (c).

–10 –0.330 –0.400 +21.3 where

For rπ ≥ 3 k, we require then

iB (t) = iC (t)/β Transistor a b c d e f g

This ﬁgure belongs to Problem 7.43.

7.45 Refer to Fig. 7.26.

vbe vbe re 7.46 The large-signal model of Fig. 6.5(d) is

changes from IB by an increment ib , which is C

which is the small-signal T model of

E 7.48 Refer to Fig. P7.48:

If iE undergoes an incremental change ie from its

This ﬁgure belongs to Problem 7.50.

7.51 Replacing the BJT with the T model of

Rin = RB1 RB2 [(β + 1)(re + Re )] 50

Rin RG RG1 // RG2