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You are on page 1of 20

Tim Williams

Elmac Services

1

– to split or not to split?

Outline

• Why split the GP?

• What are the disadvantages of split GPs?

• What happens if you don’t split?

1

The purpose of the ground plane

via connections directly to ground plane

ground plane

power plane

side view

connections to ground plane minimise total loop area for each track

element

inductance LG

di/dt

VN

circulating currents di/dt

in ground plane

VN = -LG · di/dt

total noise voltage = ΣVN

• don’t cross the edges, and keep them free of high di/dt return currents

2

The effect of a discontinuity in Iret

low ground inductance

Iret

Iret

Iret

Iret

VN

generates noise across radiating dipole

Advice to split

Example

ground planes with a 2 to 3 mm gap and

connects them at one point beneath the codec

with a single 3 to 4 mm wide link. ... The link

between the planes, as close to the codec as

possible, prevents any potential difference due

to ESD or fault currents. Without the link, these

currents could flow through the codec’s

substrate degrading performance. You should

try to avoid running any digital or analog signal

traces across the gap between the digital and

analog planes…”

useful to provide removable links between the

ground planes in several PCB locations, to

permit debugging and testing for ground

isolation…”

3

Why separate A & D ground planes?

pollute sensitive wideband circuits on AGND

– common impedance coupling is a threat if there are mixed

ground connections

• most application notes advise it

– guards against inadequate layout practices in either analogue

or digital section

• “we’ve always done it this way”

• if properly done, it gives good internal signal integrity,

but it is a common cause of poor external EMC

single point connection at ADC

ADC

analogue & digital currents

kept separate, but...

other signal tracks unless

carried across the link,

so large loop area

plane is an effective

dipole structure

can be grounded to cannot be grounded to

chassis chassis (or vice versa)

4

Multiple A-D devices

Thinks: how

From Analog useful is this

Devices

Engineering

advice?

Note EE-28

ADC1

noise injection (both internal and

externally caused) across the chip

ADC2

digital analogue

plane noise plane noise

voltages voltages

Differences on-chip between AGND

and DGND contribute to driving the

radiating dipole

ADC3

10

5

Multiple A-D packages: several links

digital currents can now

contaminate analogue circuits

(this is a ground loop)

ADC2

digital … but, will they, and,

plane noise how badly?

voltages

… and anyway,

ADC3 implementing multiple links

is nearly all the way to a full

ground plane … so why

have splits at all?

11

each analogue

digital noise circuit carefully

currents ADC1 grouped

both AGND and

DGND connected to

common GP

ADC2 no opportunity for an

enhanced dipole

• but A and D ground

currents could intermix,

so…

ADC3 • lay out the circuits as if

there were separate

ground planes: observe

strict segmentation rules

12

6

So why ...

DGND pins if we’re not going to use them?

• Because of bond wire inductance, that’s why ...

chip

Internal AGND

remains unaffected

by digital noise

High digital ∆Ι

ground current

Little or no analogue

∆Ι ground current

Bond wires add

ground inductance

package

DGND AGND

13

10Ω

3cm L x 0.5mm W track * 5cm wide ground

plane at 0.8mm under

1Ω finite ground plane * 3cm length of track

100mΩ

ohms per square of

infinite plane

10mΩ

1-oz Cu plane

1mΩ

0.1 1.0 MHz 10 100 1G

L ≈ 5·d/W nH per cm

where d is the height of signal track above GP

W is width of GP

10µV across two points on the plane (from Ohm’s Law)

14

7

Issue 2: Digital decoupling

Outline

• The purpose of decoupling

• Capacitor selection and layout

• Paralleling capacitors

• The planes as a transmission line

• Resistive damping

• Segmenting the power plane with inductors

15

across power supply impedance

– power source impedance is largely inductive

– digital IC totem-pole switching gives high transient di/dt

through power pins, and ∆Vsupply ≈ -L·di/dt

– voltage droop from an ideal capacitor ∆V = I·t/C

– reduce radiated emissions since the loop area for high

spectral content switching current is reduced

16

8

Decoupling regime vs frequency

LT LP

LC LC +

CBULK -

CD CD

to get distributed capacitance

17

inductance

compromise the effectiveness of CD

∆I

current

loop • the best position for CD is directly

underneath the package to maximize

capacitor

mutual inductance of wires and traces

lead

inductance

ground connection

inductance

18

9

SM capacitor impedances (1)

pattern Ω

mΩ nH

P2 12 0.61

P3 17 1.32

P4 22 2.00

P5 54 7.11

P6 95 15.7

P7 53 10.3

W length D spacing W nH

0.263 0.34 11.0

0.223 0.21 7.2

D 0.173 0.21 5.7

0.163 0.14 4.2

0.057 0.22 2.2

0.037 0.17 1.2

19

Ceramic capacitor ESR

1500

H (mils) L (pH)

1000 NPO

20 300

H X7R

mΩ

30 450

Ω

40 600

50 700 500

1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06

pF

Link to

4 Murata

capacitor

3 data

Progression of decoupling

1

capacitor pad and via layout

nH

years

20

10

Capacitor value

Capacitor self resonance

40.0

30.0

20.0

10.0

100nF 10nH

dB ohms

10nF 10nH

-10.0 2.2nF 10nH

100nF 2nH

-20.0

22nF 2nH

2.2nF 2nH

-40.0

1.00E+06 1.00E+07 1.00E+08 1.00E+09

Hz

• above self resonance, value is unimportant – less inductance = better decoupling

21

L1 L2 L3 L4

ZPLANE C1 C2 C3 C4 CBULK

CPLANE

RIC

R1 R2 R3 R4

CPLANE - parallel L

effect of CBULK

Modelled with:

ZPLANE C1 - 4 = 22nF

dBΩ L1 = 1nH, L2 = 2nH, L3 = 3nH, L4 = 4nH

CBULK = 1µF, L = 15nH, R = 0.1Ω

RIC = 50Ω

CPLANE = 3nF

effect of C1 - 4

22

11

Parallel capacitors

dBΩ

• 2 capacitors of

different values at 47nF // 1µF

one point are

dangerous

• Multiple capacitors

of the same value

9 x 22nF, 2nH

with power/ground

planes are useful

of different values different

with power/ground capacitors,

100nF to

planes give a wider 220pF

low-Z bandwidth

23

• The previous model assumed the board was small with respect to a wavelength (< λ/10)

a quarter wavelength in FR4 (εr ≈ 4) at 300MHz is 12.5cm! 3 · 108

λ =

… the board then acts as a parallel-plate transmission line √εr · frequency

I

n=1

n=2

VCC

reflected at the

plane edges

GND

24

12

Transmission line impedance

W h

Z0

Parallel plate transmission line Z0, h = 50

10 6

Z0, h = 200

h Z0, h = 800

Z0 = 120 · π ·

5

C, h = 50

√εr · W 1

C, h = 200

4

C, h = 800

Z0 Ω

A (cm2) 3

C nF

C (pF) = 0.0885 ·

0.1 2

h (cm)

1

Width cm

capacitance for 20cm long line 0.0 5.0 10.0 15.0 20.0

25

• effect of decoupling ESR is to damp resonance and reduce Z0

• because power plane Z0 is low, a lot of capacitors are needed

• resonances can be reduced independently by adding resistance at

the plane edges, across the planes (with DC blocking)

• resistance must be very low ESL and match Z0, but not perfectly

26

13

Segmenting the power plane

ground plane

3V3 plane B

3V3 plane C

3V3 plane A

1V8 plane

3V3 plane D

• splitting the power plane(s) (not the ground plane) into several

segments, each decoupled by a choke, creates “islands” for noisy

or sensitive circuits and reduces the impact of plane resonances

27

Conclusions

• include capacitor stray inductance in all considerations

• at VHF, package and via inductance is more important

than value

– decoupling capacitor value and position can be modelled with a

circuit simulator

• at UHF, board resonances are significant and can only be

dealt with by resistive damping or segmentation

– decoupling capacitor, damping resistor and IC positioning can be

modelled by treating the plane as a network of distributed

transmission lines

28

14

Issue 3: Mode conversion

in interface filters

Outline

• Typical circuits

• Model equivalent circuit for conducted immunity

• The problem of CM to DM conversion

• Some results and inferences

29

Input amplifier

Input cable

induced by external

interference source

30

15

Typical filter circuit

Input amplifier

Common-mode choke

Input terminals

3-terminal

capacitors to Input 0V

chassis capacitors

to 0V

chassis ground

31

CM choke

Input 3-T caps

Injection CDN to chassis Input

impedance VDM

Source

DM

impedance

VCM

Input caps

to 0V

VIN

32

16

Conversion from CM to DM

the differential circuit are exactly balanced, there is no

CM-to-DM conversion:

|VDM | /|VCM | = 0

• but if there is any imbalance in any component in the

two halves of the circuit, some differential mode voltage

results:

|VDM | /|VCM | > 0

• the most likely source of imbalance is in the capacitor

values, which can easily be ±20%

33

Modelling

previous equivalent circuit:

– transfer function versus frequency, 100kHz – 100MHz

various components in the equivalent circuit

34

17

Model results: initial assumptions

Near-perfect balance

0

Differential mode

-40

-60

dB VDM/VIN

-80

-100

-120 (otherwise differential mode would be zero)

-140

1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08

35

Differential mode only

Effect of capacitive unbalance

0

Unbalance in 100pF connector caps C1, C2

-20

-40

-60

dB

Unbalance in 1000pF input caps C5, C6

-80

-100 C1 120pF, C2 80pF: ±20%

C5 1.01nF, C6 1nF: +1%

-120 C5 1.1nF, C6 0.9nF: ±10%

C5 1.2nF, C6 0.8nF: ±20%

-140

1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08

36

18

Model results: real life

0

-20

-40

-60

dB

-80

-100 RCHK2 increased 10%,

LC6 5nH, LC1A,B 7nH, C6

= 1050pF, C1 = 105pF

CDN unbalance only: R2 =

-120 Effect of unbalance in CDN feed resistors

315R (+5%)

-140

1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08

37

0

-20 can give an extra 15-20dB where it matters

-40

-60

dB

-80

DM capacitor

C5 1200pF only

-120

-140

1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08

38

19

Conclusions

imbalance in differential interface circuits, especially

related to capacitor value tolerances

• Common mode attenuation is easily achievable but

common to differential mode conversion may be

significant

• Modelling the circuit to adjust the values is easy:

39

End

Thanks for your attention!

40

20

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