Electrode

DC checkpoint
ESD protection

PAD201
HF rejection and user current limiter
Channel 2 - CH2- R202 R208 R207 G=12.2 +5V/2 G=40
Electrode
2k2 2k2 2k2 IC202
HP 1 pole fc=0.16 Hz
G=6..100 G=16 C234

Q205 Q201 2

100pF
33nF 5%

C205

3
BC547 BC557 R214 1µF
2 2 1 IC205A C229 R232 R228 IC205B
6 3 5
2k2
C209

10pF
ADIN1

1 1

1 1
1 7
R215

R224
C220 1µF 10k 15k

220nF 5%
C231
VGND 8 2 6

1M
2 2 5 C217 TLC277P TLC277P +5V/2

R231
100pF 2k2
C204

3 7 100nF

1M
Q207 Q203 V+

3
BC547 BC557 4 C214

100nF
R220 VGND

2
100nF R221 R229 R230

C227
V-
CH2+ 2k2 3 1

VCC
Channel 2 + 2k2 2k2
INA114P

8
Electrode 3 1 100k 8.2k 100k
R201 R205 R206 AGND VGND 1k
P202 VGND C232 IC205PWR

C225
IC204B

100nF
20k C222
R219 5 VGND VGND

GND
4
Input Voltage Full Scale (10 Bit) = 512uVpp 7 1nF
6 1nF
Input Voltage Resolution (1 LSB) = 0.5 uVpp 10k TLC277P 3rd order "Besselworth" filter, fc = 59 Hz.
Total gain = 7812.5 The 3rd pole is located on the digital board.
Input can handle up to +/-100mV DC electrode offset Electrode AGND
DC checkpoint

PAD202
Channel 1 - CH1- R204 R212 R211 G=12.2 +5V/2 G=40
Electrode
2k2 2k2 2k2 IC203
HP 1 pole fc=0.16 Hz
G=6..100 G=16 C236

Q206 Q202 2
100pF

33nF 5%
C207

BC547 BC557 R216 1µF

2 2 1 IC206A C228 R237 R233 IC206B
2k2 6 3 5
C210

10pF

ADIN0
1 1

1 1

1 7

R226
R217 C221 1µF 10k 15k

220nF 5%
C235
VGND 8 2 6

1M
2 2 2k2 5 C218 TLC277P TLC277P +5V/2

R236
100pF
C206

3 7 100nF

1M
Q208 Q204 V+
3

BC547 BC557 4 C215

100nF
R222 VGND

2
100nF R225 R234 R235

C230
2k2 V-
2k2 2k2 3 1

VCC
Channel 1 + CH1+
INA114P

8
Electrode 3 1 100k 8.2k 100k
R203 R209 R210 AGND VGND 1k
PAD205 P203 VGND C233 IC206PWR

C223
+5V/2

100nF
COM 20k C224
VGND VGND

GND
100nF

4
PAD206 1nF 1nF
AGND C226
right leg driver AGND
VCC

IC204A
8

AGND
C216 R218 3
1 VGND +5V/2
IC204PWR
2
1nF 10k TLC277P C211
GND

R_LEG Only insert IC201 on _one_ board

4

IC201A
Right Leg R213 TLC277P 6 VGND when using 2 or 3 amplifier boards

8
R_LEG 2.0V
Electrode 7 100nF 3

C202
5 C219 1
1

C203 10nF
200k
1

2
P201
20k

C212 IC201B 2 VGND ref. voltage TLC277P

10nF
C213
+
47µF
100nF +5V/2
3

C208

4
AGND +2V, buffered
100nF
3

1nF simulates electrode impedance +

Vcc analog
Right-leg driver (DRL) notes: AGND C201
PAD204 R238

ADIN0

ADIN1
P201 is not needed when INA114 instrumentation amplifiers are used. 47µF tan 1ohm
You may replace it with a short wire from pin 2 and pin 1 (VGND). Cal_GND 10k 2.0V
J201
If P201 is needed, adjust potentiometer so DRL=0mV (referred to VGND) AGND 1 2
when _all_ amplifier inputs are shorted to the DRL output (R_LEG). R240 2.0V buf 3 4 1 2 SJ201
100
u cal

5 6 1 2 SJ202
Important usage instructions for the DRL. Ground plane is VGND 7 8 1 2 SJ203
PAD203 R239 R227 R223 9 10 1 2 SJ204
If you only want to use one channel, never let the other channel float. 11 12 1 2 SJ205
Always connect the unused terminals to VGND, or the DRL will not work properly. U_cal AGND 13 14 1 2 SJ206
10k 1M 1M 15 16
The solder-jumpers (SJ201 - SJ206) 17 18
voltage divider 1:20000 to the right, are used for channel 19 20
DRL design from http://www.biosemi.com/publications/artikel7.htm, fig.3 5Vp-p +/-10% => 250µVp-p +/-10% mapping. This allows multiple amplifier 21 22
boards to share the same connector. 23 24
See http://openeeg.sf.net for more information.
250µVpp +/-10%, 0.1 .. 100Hz 25 26
Authors: Moritz v. Buttlar, Joerg Hansmann, Andreas R 2 channels must be selected on each 27 28
Square wave Calibration Signal board by closing two jumper gaps with 29 30 PWM
solder. 31 32
modEEGamp_v1_1_Rev. A Use SJ201 and SJ204 for the first board.
33 34

PINHD-2X17
Olimex LTD, Bulgaria, 2013 PWM cal (PB1)

https://www.olimex.com Output Voltage Full Scale (10 Bit) = 4.000 Vp-p (Range 0..4V)
=> 3.9mV bitstep at 10 bit resolution.

This hardware design by Olimex LTD is licensed under a Creative Commons Attribution-ShareAlike 3.0 Unported License.