Notice of Violation of IEEE Publication Principles

“A 160-2550MHz CMOS active clock deskewing PLL using analog phase interpolation”
by Maxim, A.
in the Proceedings of the 2004 IEEE International Solid-State Circuits Conference, 2004. Digest
of Technical Papers. ISSCC.
15-19 Feb. 2004 Vol.1, Page(s):346 - 532

After careful and considered review, it has been determined that the above paper is in violation
of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In
response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people
who have been listed as co-authors on several of his papers are fabricated names and that he is
the only author:

C. Turinici D. Smith S. Dupue

M. Gheorge R. Johns D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was
discovered in some cases that he had not consulted with them while writing the papers, and
submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot
assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past
references to the above paper, and to refrain from any future references.
ISSCC 2004 / SESSION 19 / CLOCK GENERATION AND DISTRIBUTION / 19.3
19.3 A 160-2550MHz CMOS Active Clock Deskewing
PLL Using Analog Phase Interpolation
Adrian Maxim
Maxim, Crystal Semiconductor, Austin TX
The aggressive device geometry scaling and continuous die size
increase of today’s ASICs make the within-die process variation
a significant contributor to the clock skew across the chip.
Balanced clock trees, load matching and clock path length tun-
ing have been used to minimize the static clock skew compo-
nents. Active deskewing [1] was recently introduced to compen-
sate the dynamic skew. It consists of a PLL frequency synthesiz-
er and multiple deskewing DLLs using capacitive controlled
delay lines to generate the local clocks. This leads to a large die
area, process variation of the phase step and significant latency
that limits the speed of the deskewing process. Phase interpola-
tion was previously used to extend DLL’s phase capture range
[2]. This paper presents an alternative active deskewing tech-
nique using analog phase interpolation to replace the area con-
suming capacitive controlled delay lines from the deskew DLLs.
This technique minimizes the die area, provides a process inde-
pendent phase step and assures a latency–free phase shifting
that accelerates the clock deskewing process.
Figure 19.3.1 presents the top level diagram of the clock genera-
tion and distribution. A core PLL using a four differential-invert-
er ring oscillator synthesizes the system frequency. The four
phases generated by the ring inverters, together with their four
negative counterparts constitute a 45O uniformly spaced refer-
ence phase system. The key idea of interpolation based deskew-
ing is to generate the local clocks by summing thermometer
weighted versions of the two adjacent phases from the reference
system that contain the required output phase. One of the inter-
polation blocks is hardwired to generate a clock in the middle of
the phase deskew range: this is used as reference to which all the
other clocks are aligned. The other interpolation blocks generate
the local clocks which have a phase shift from the reference clock
determined by the phase control counters and decoders. The
binary phase control word is decoded to a set of select and sign
signals that decide the two reference phases and polarities that
are used in the interpolation, and a thermometer weighting code
that gives the multiplication coefficients for the two phases. The
die is partitioned in regional clock domains that use a grid-type
distribution. Each domain receives two clocks from the core PLL:
the reference and the interpolated one, both being routed via a
balanced H-tree. A set of tri-state phase detectors compare the
phase of the feedback clocks sampled from the local grids with
the one of the reference clock, providing lead/lag output signals
that control the delay counters and decoders.
Figure 19.3.2 shows the top level diagram of the core PLL con-
sisting of a phase and frequency detector (PFD), proportional
and integral charge-pumps (CPp, CPi), a feed-forward current
mode loop filter (LF), a ring oscillator (ICO) with V-to-I convert-
ers, select and polarity switches (SPSW), a phase interpolator
(PI), and an output comparator (COMP). A bandgap referencing
technique [3] provides a tracking mechanism between the loop
natural frequency (fn) and stabilizing zero (fz), leading to a
process independent damping factor (ζ=fn/2fz). Feedback divider
(N) independent loop time constants are obtained by adjusting
the charge-pump currents (Icp) and oscillator gain (Kico) such that
the Kico•Icp/N term is kept constant for all the output frequency
settings. Phase margin degradation due to sampling effects was
avoided by scaling the loop time constants inversely proportion-
al to the input divider modulus (M), while keeping a constant
damping factor and pole-zero separation (pz=fp/fz).
Figure 19.3.3 illustrates the PLL loop filter schematic. A differ-
ential integral path (Mi) is implemented to reduce the sensitivi-
ty to supply and substrate injected noise. A high linearity differ-
ential integral transconductance stage is achieved by using both
source degeneration (Ri) and a feed-forward correction loop real-
ized with Mf and Mc. The two integral capacitors (Cip and Cin) are
charged/discharged in opposite directions by two integral charge-
pumps (CPip, CPin) operated complementary. A source switch
(Msw) cascoded charge-pump configuration with discharge
devices (Mdcg) is used to increase the speed and minimize the
clock feedthrough. A single-ended current-mode proportional
path is implemented with the Mp-Mm current mirror, which is
prebiased by the Ipreb sources to minimize the proportional cur-
rent switching delay. The ripple pole (fp) is set by Cp and Rp which
are closely matched to Ci and Ri, leading to a process independ-
ent pole-zero separation.
Figure 19.3.4 depicts the ICO differential inverter schematic. A
saturated PMOS load (Mp1, Mp2) was used to maximize the output
voltage swing and extend the constant slew rate region around
the crossover point, improving the accuracy of phase interpola-
tion. A differential current-mode phase interpolator is used to
improve the supply and substrate noise rejection. The differen-
tial output voltages of the ring inverters (OUTp, OUTn) are con-
verted into differential currents with resistively degenerated (Rd)
V-to-I transconductance stages using zero-VT devices (Mnz).
Differential switches (Mswp, Mswn) select the pair of reference
phases that are used by the φ0-φ4 interpolators. They also deter-
mine the polarity of the selected phases by flipping the two out-
put currents via a cross-coupled connection.
Figure 19.3.5 presents the ring oscillator and phase interpolator
top level. As the interpolation is done always between two adja-
cent phases, the two odd (Io1, Io2) and two even (Ie1, Ie2) output cur-
rents can be summed without interfering with each other. The
resulting currents are sent to the interpolator cell, where they are
first split into a number of equal currents by the Msplit mirrors and
then pass through the differential weighting switches (Mw) that
perform the complementary thermometer weighting by sending
the fractional currents to the load resistors (RLp, RLn) or dumping
them to ground. An output comparator provides the differential to
single-ended conversion and squares-up the waveform, assuring a
constant slew rate for all the interpolated phases.
Figure 19.3.6 shows the measured jitter histogram for one of the
deskewed clocks, having a 3.9ps RMS jitter at the maximum
operating frequency of 2.55GHz. Figure 19.3.7 is a detail of the
chip micrograph showing the clock deskew PLL. The IC specifi-
cations include a 160-2550MHz frequency range, a 2.8O phase
step, RMS jitter < 1%Tosc, and a 1.5V supply. Fabricated in a
0.15µm CMOS process, the PLL dissipates 60mW in an area of
400x800µm2.
References:
[1] S. Rusu, S. Tam, “Clock Generation and Distribution for the First IA-
64 Microprocessor,” ISSCC Dig. Tech. Papers, pp 176-177, Feb. 2000.
[2] S. Sidiropoulos, M. Horowitz, “A Semi-Digital Delay Locked Loop with
Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,”
ISSCC Dig. Tech. Papers, pp 332-333, Feb. 1997.
[3] A. Maxim et al., “A Low Jitter 125-1250MHz Process Independent
0.18µm CMOS PLL Based on a Sample-Reset Loop Filter,” ISSCC Dig.
Tech. Papers, pp 394-395, Feb. 2001.
 ISSCC 2004 / February 18, 2004 / Salon 7 / 8:30 AM

Figure 19.3.1: Clock generation and distribution. Figure 19.3.2: Deskew PLL top level diagram.

Figure 19.3.3: Current-mode loop filter. Figure 19.3.4: ICO differential inverter with V-to-I converters.

Figure 19.3.5: Ring oscillator and phase interpolator. Figure 19.3.6: Jitter histogram at 2.55GHz.
Figure 19.3.7: Chip micrograph – detail of deskew PLL.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.1: Clock generation and distribution.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.2: Deskew PLL top level diagram.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.3: Current-mode loop filter.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.4: ICO differential inverter with V-to-I converters.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.5: Ring oscillator and phase interpolator.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.6: Jitter histogram at 2.55GHz.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 19.3.7: Chip micrograph – detail of deskew PLL.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE