PC & Peripheral Architecture

Compiled & Published by CFS Documentation Cell
Centre for Electronics Design and Technology of India

An Autonomous Scientific Society under Department of Electronics,
Govt. of India,
New Delhi.
First Edition: 1999
TRADEMARKS: All brand name and product names mentioned in this book are trademarks or registered trademark of their
respective companies.
Every effort has been made to supply complete and accurate information. However, CEDTI assumes no responsibility for its
use, nor for any infringement of the intellectual property rights of third parties which would result from such use.
No part of this publication may be stored in a retrieval system, transmitted or reproduced in any forms or by any means,
electronic, photocopy, photograph, magnetic or otherwise, without written permission of CEDTI.
CEDTI/CFS/99/8/E-1/R1
FOREWORD
The information technology and telecom sectors have suddenly opened up avenues,
which require a very large specially trained manpower. These sectors are highly dynamic and
need training and re-training of manpower at a rapid rate. The growing gap of requirement of
the industry and its fulfillment has created a challenging situation before manpower training
institutes of the country. To meet this challenge most effectively, Centre for Electronics Design
and Technology of India (CEDTI) has launched its nation-wide franchising scheme.
Centre for Electronics Design and Technology of India (CEDTI) is an Autonomous

Scientific Society under the Govt. of India, Department of Electronics with its Headquarters at
New Delhi. It operates seven centres located at Aurangabad, Calicut, Gorakhpur, Imphal,
Mohali, Jammu and Tezpur. The scheme will be implemented and coordinated by these centres.
The scheme endeavours to promote high quality computer and information technology
education in the country at an affordable cost while ensuring uniform standards in order to
build a national resource of trained manpower. Low course fees will make this education
available to people in relatively small, semi urban and rural areas. State-of-the-art training will
be provided keeping in view the existing and emerging needs of the industrial and Govt.
sectors. The examinations will be conducted by CEDTI and certificates will also be awarded
by CEDTI. The scheme will be operated through all the seven centres of CEDTI.
The CEDTI functions under the overall control and guidance of the Governing Council
with Secretary, Department of Electronics as its Chairman. The members of the council are
drawn from scientific, government and industrial sectors. The Centres have separate executive
committees headed by Director General, CEDTI. The members of these committees are from
academic/professional institutes, state governments, industry and department of electronics.
CEDTI is a quality conscious organisation and has taken steps to formally get recognition
of the quality and standards in various activities. CEDTI, Mohali was granted the prestigious
ISO 9002 certificate in 1997. The other centres have taken steps to obtain the certification as
early as possible. This quality consciousness will assist CEDTI in globalizing some of its
activities. In keeping with its philosophy of ‘Quality in every Activity’, CEDTI will endeavour to
impart state of the art – computer and IT training through its franchising scheme.
The thrust of the Software Courses is to train the students at various levels to carry out
the Management Information System functions of a medium sized establishment, manufacture
Software for domestic and export use, make multimedia presentations for management and
effectively produce various manufacturing and architectural designs.
The thrust of the Hardware Courses at Technician and Telecommunication Equipment
Maintenance Course levels is to train the students to diagnose the faults and carry out repairs
at card level in computers, instruments, EPABX, Fax etc. and other office equipment. At
Engineer and Network Engineer levels the thrust is to train them as System Engineers to
install and supervise the Window NT, Netware and Unix Networking Systems and repair
Microcontrollers / Microprocessor based electronic applications.
An Advisory Committee comprising eminent and expert personalities from the Information
Technology field have been constituted to advise CEDTI on introduction of new courses and
revising the syllabus of existing courses to meet the changing IT needs of the trade, industry
and service sectors. The ultimate objective is to provide industry-specific quality education in
modular form to supplement the formal education.
The study material has been prepared by the CEDTI, document centre. It is based on
the vast and rich instructional experience of all the CEDTI centres. Any suggestions on the
improvement of the study material will be most welcome.
(R. S. Khandpur)
Director General (CEDTI)
TABLE OF CONTENTS
UNIT CHAPTER NAME PAGE NO.
1 Classification 11
2 Memory: Concept & Troubleshooting 17
3 Motherboards 27
4 Installation of Motherboard 53
5 Keyboard and Mouse 65
6 Floppy Disk Drives 73
7 Hard Disk Drives 81
8 Printers 99
9 Monitor and Display Cards 111
Appendix - Case of L & T Drives 133

PC & Peripherals Architecture
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CHAPTER - 1
CLASSIFICATION
ARCHITECTURE & CLASSIFICATION OF SYSTEMS
THE BASIC PARTS OF THE IBM PC
An IBM PC, computer has five basic parts:
* An arithmetic logic unit

* A memory unit
* An input unit
* An output unit
* A control unit
These parts are associated as shown in Fig. 1-1.
CONTROL
UNIT
INPUT ARITHMATIC OUTPUT

UNIT LOGIC UNIT UNIT
MEMORY
Fig. 1.1 : The five basic parts of IBM PC
Math and number crunching occur in the arithmetic logic unit (ALU). All the adding,
subtracting, multiplying, dividing, comparing, and other manipulations are done by the ALU.
The memory unit is used to store programs, calculations, and results. As shown in Fig.
1.2, this unit includes two types of memory - RAM (random-access-memory), which can be
read from and written to, and ROM (read-only-memory), which can be read from but not
written to. RAM is called main memory.
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When you turn off power to your IBM PC, whatever you had stored in RAM is lost unless you
have first saved it on a disk. The program in ROM is placed there by IBM or by manufacturer
during manufacturing, and it remains even when the power is off. Since the ROM program
(software is in a device hardware), we call it firmware.
The input unit lets you enter information into the computer, it is way for you to “Talk” to your
PC. This communication is called the “man-to-machine” interface. You can communicate
with your computer through your keyboard, a light pen that reacts as you touch a place on
the screen, a special pen and a graphics tablet, a mouse that moves your cursor about the
screen as you move the mouse on your desktop, or a voice-recognition board and a
microphone.
CONTROL UNIT
CPU
INPUT OUTPUT
UNIT ARITHMATIC UNIT
LOGIC UNIT
RAM ROM
Fig.1.2: Memory and I/O Interface
An output unit gets information from the computer to you. We call this machine-to-man interface.
You can also use a printer to produce hard copy, or paper output. Other ways for your PC
to communicate include turning on motors and lights, making music and arcade sounds,
and even talking in your own language with a speech synthesizer board and a speaker.
Some computer devices are for both input and output. One Input/Output (I/O) device
includes a form of memory external to the computer-mass storage. You save your programs
to mass storage and retrieve them as needed. Mass storage includes floppy disks, cassette
tapes, hard disks, and the country ( if not the world) using either dedicated telephone lines or
the standard four-wire telephone lines of your home or office.
Input/Output devices are called peripherals. Some can be built into your computer for
instance, your speaker. Others are connected to your IBM PC through printer circuit cards
called interfaces, or, that plug into slots, those long sockets on your PC system board, or
motherboard. A large number and of interface cards are available for the PC. Some cards
provide interface to the devices needed to make your system function the display monitor,
the disk drive, and the printer. Only five expansion slots are available in the PC. This limits
the configuration that can be developed. The number of expansion slots can be increased
by adding an expansion chassis to the system board. This will use only one slot in the main
system unit, but will add eight slots of expansion capability.
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Everything your PC does is directed by the control unit. This unit interprets computer
instructions and initiates the signals that cause the computer’s circuits to do certain tasks.
The control unit and the arithmetic logic unit are combined into a single chip called the
central unit, or CPU. As shown in Fig. 1.2, the CPU on IBM PC motherboard is 8088,
80286, 80386SX, 80386DX, 80486, PENTIUM or PENTIUM PRO. CPU looks into memory,
fetches an instruction from that location, interprets the instructions, performs the actions the
instruction requires(e.g., adding two numbers), and then moves on to process the next
instruction. The next instruction directs the CPU to a particular memory location to carry
out the instruction to the next instruction in sequential memory locations (one step after the
other). Perhaps the most important difference between your stepping through a program
(sequence of instructions) and your PC’s doing the stepping is that the PC can handle
about a million of these steps in each second.
SYSTEM CONFIGURATION
In Fig. 1.3 you see the “standard” IBM PC configuration. A printer has been added to
provide hard copy, or printed output. The memory has been expanded to the standard
memory size for current software package.
DISPLAY
KEYBOARD IBM PC PRINTER

SYSTEM UNIT
DISK DRIVES
Fig.1.3 : Standard IBM PC Configuration
Small business users generally configure a system as shown in Fig. 1.4. Connecting an
optional memory module brings the total RAM to 4MB/8MB/16MB/32MB. The addition of a
Windows 95, operating system and the magneto optical drives , CD drives let you use
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larger software programs that actually need more than one disk drive to run.
DISPLAY
KEYBOARD IBM PC PRINTER

SYSTEM
FDD & HDD
CD-ROM / CTD
Fig. 1.4 : IBM PC-AT Systems with Additional Drives
CLASSIFICATION OF SYSTEMS
This topic covers the differences in system architecture of IBM and compatible systems as
well as usage of memory. From a Hardware as well as software engineer’s point of view, all
IBM and compatible systems can be broken down into following basic system types with few
subcategories.
PC Type of Systems
* Industry Standard Architecture

Bus 8088 CPU (8-Bit ISA).
* Mass storage Media Floppy diskettes driven by either 360 KB or 1.2 MB FDDs.
XT Type of Systems
* Industry Standard Architecture (ISA)

Bus 8088 CPU (8-Bit ISA).
* Mass Storage Media Hard disk (HDD)
10 MB, 20 MB, 40 MB HDD.
AT Type of Systems
* Industry Standard Architecture (ISA) ( 16 Bit ISA BUS)

80286 CPU, 80386 CPU, 80486 CPU, PENTIUM CPU
* VESA Local Bus ( 32 Bit VL Bus )

80386 CPU , 80486 CPU , PENTIUM CPU.
* Enhanced Industry standard Architecture (EISA) Bus

80486 CPU, PENTIUM CPU.
* Peripheral Component Interconnect Bus (PCI Bus )
80486, PENTIUM, PENTIUM PRO CPUs (32 Bit PCI BUS)
PENTIUM, PENTIUM Pro (64 Bit PCI Bus)
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One usually can tell AT systems by their use of the Intel 80286 or higher processors. Some
AT systems differ in the types of slots included on the main system board. The earlier standard
called for 8-bit and 16-bit slots that were compatible with the original IBM PC and AT. The
later standards are IBM’s Micro Channel Architecture (MCA), and it consists of 16 and 32 bit
slots, with the 32-bit slots present only on 80386-based systems. Later versions of AT
Systems have 16 bit ISA plus 32 bit EISA or VL or PCI Bus.
Some manufacturers have integrated proprietary 32-bit slots in their non-Micro Channel AT
systems, but no expansion boards are usually available to take advantage of these special
32-bit AT type of slot. The basic AT system design provided twice the number of interrupts
and DMA channels for adapter boards to use, which allows for greater system expansion
with fewer conflicts among adapters.
Another difference between PC and AT types of systems is the use of a real time clock; the
AT architecture sees one, and the PC types of systems don’t. A real time clock is the built-
in clock implemented by a special MOS memory chip on the motherboard that is found in
any AT system. You can have a clock added on some expansion adapters of a PC system.
This CMOS memory in the AT system also stores the system’s basic configuration.
DIFFERENCES BETWEEN PCS/ XTS/ ATS
The abbreviations used in table on next page are given below:
ISA = Industry Standard Architecture

MCA = Micro Channel Architecture
NMI = Non-Maskable Interrupt
DMA = Direct Memory Access
RAM = Random-Access Memory
ROM = Read only Memory
CMOS = Complementary mental Oxide Semiconductor
BIOS = Basic Input/Output System
UART = Universal Asynchronous Receiver Transmitter
PCI = Peripheral Component Interconnect
Note:
(1) The V-20 is NEC replacement chip for the Intel 8088.
(2) Virtual real mode is supported only on 80386 and above based systems .
(3) 32-bits slots and upwards are supported on ‘386 and upward -based systems only.
(4) Maximum DRAM is supported on certain systems only.
The following table gives a comparison of the IBM PC, PC/XT, PC/AT systems:
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SYSTEM ATTRIBUTES PC OR XT TYPE AT TYPE

Supported Processors: 8088 80286
V-20 (1*) 80386SX
80386DX
80486SX
80486DX
80486DX2
80486DX4
PENTIUM
PENTIUM Pro
Processor Modes: Real Real,
Protected
Virtual Real (2*)
Expansion slot 8-Bit ISA 16-bit ISA,
MCA, 32-bit (3*)
MCA, 32-bit VL
32 bit PCI, 64 bit PCI
Total interrupts: 8+NMI 15+NMI
Total DMA Channels 4 8
Maximum RAM: 1 MB 16 or 4,096 MB (4*)
physically on motherboard and much more.
Basic Configuration: Switches/jumpers CMOS Memory
Motherboard ROM F0000-FFFF 0E0000-0FFFFF
and FE0000-FFFFF
Floppy Controller: Double density High/Double density
Hard disk BIOS: Controller ROM Motherboard ROM
Serial port UART: 8250 B 16250 & 16450-A
Keyboard Interface Unidirectional Bi-directional
CMOS setup No Yes
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CHAPTER - 2
MEMORY: CONCEPT & TROUBLESHOOTING
Solid-state memory faults contribute to a large percentage of computer problems. Memory

ICs contain the program instructions and data needed for execution by a microprocessor,
thus the loss of even one bit can have great damaging effects for the system.
Data Storage in Memory
Memory ICs store programs and data as a sequence of binary digits (1s and 0s) where a 1
represents the presence of a signal voltage, and a 0 represents the absence of a signal
voltage. Each bit represents a voltage level, and hence the voltage must be stored in an
electronic circuit. Each circuit is known as a storage cell. The contents of storage cells can be
copied to a bus or other waiting device (known as reading). Some storage cells can be set to
new values by copying data from external bus signals (called writing). The exact structure and
construction of a storage cell depends on the characteristics of the particular memory device.
By combining storage cells into arrays as shown in fig., memory circuits are manufactured to
hold many millions of bits. There are many types of storage cells in use today: SRAM, DRAM,
ROM, PROM, EPROM, and EEPROM.
SRAM
SRAM (static RAM) stores bits in cells that act like electronic switches. An SRAM cell is
usually a flip-flop circuit that is preset (logic 1) or reset (logic 0) when written.
The flip-flop stores the condition of the bit until it is altered by a subsequent write operation (or
until power is removed). Once data is stored in an SRAM cell, it will be retained indefinitely
without any further interaction by the computer. SRAM cells are physically large and consume
a relatively large amount of power in active use. Today’s SRAM ICs are generally (256K) bits
ICs.
DRAM
DRAM ( dynamic RAM) uses an approach that stores bits in the form of electrical charges on
small solid-state capacitors. A single MOS transistor is included with each capacitor to act as
a switch or control element. The presence or storage capacitor very small, charges can be
added or withdrawn from a capacitor in only a few nanoseconds. Because each storage cell
is extremely small and uses almost no current, storage density is very high, and power
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dissipation is very low. The system memory is corrupted. To preserve the charge conditions
in a DRAM, each cell must be periodically refreshed. This memory is thus termed as Dynamic
RAM. A refresh controller determines the time between refresh cycles, and a refresh counter
ensures that the entire array (all rows) are refreshed.
ROM
ROM (Read Only Memory) cells are the absence (logic 1) or presence (logic 0) of a physical
electrical connection. The precise pattern of 1s and 0s is specified by the purchaser and
fabricated onto the ROM during its manufacturing process. Once a mask ROM IC is created,
its contents can never be changed. Because no active circuitry is needed to store 1s or 0s,
ROM ICs have the highest storage densities available. ROM devices also are available in a
number of other programmable versions (PROM, EPROM, and EEPROM). All types of ROM
devices, do not lose their contents when computer power is turned off. This memory is also
known as Non-Volatile memory. The BIOS ROM used in many earlier PCs are mask-type
(although there is a growing trend toward PROM devices).
PROM
As mask ROM need to be manufactured, it is usually much faster and less expensive for PC
BIOS makers to program own ROMs. PROM (programmable read-only memory) ICs work like
mask ROMs, they have logic levels established by the presence of the simple electrical
connections. However, PROMs are manufactured with all possible connections in place (all
logic 0s). A equipment called a PROM Programmer reads the program to be loaded from the
computer and steps through each address. Each bit that must be a logic 1 is forced written
with a high-voltage pulse that breaks that connection to form a logic 1. This writing process is
called burning the PROM. Once a PROM is programmed, its contents cannot be cleared or
rewritten. This is writable once only. The ROM-BIOS on motherboards (upto 486 or pentium
based) is mostly PROM type.
EPROM
The drawback with above ICs is that they need to be thrown even if there is a single bit error.
Thus, EPROMs (Erasable PROMS) are used to provide thousands of erase-rewrite cycles in
a lifetime. EPROM bits are not stored as physical connections, but as electrical charges
deposited onto the IC’s substrate. Very small transistors detect the presence or absence of
charge as a logic 1 or logic 0 respectively. Once a charge is deposited, it remains in place
permanently (unlike DRAM devices whose charges last only a few milliseconds).
To erase an EPROM, the semiconductor IC holding the electrical charges must be exposed to
short-wavelength ultraviolet (UV) light. UV allows the charges to dissipate and return each
EPROM storage cell to a blank condition. EPROM ICs thus have a glass (quartz) or plastic
window in the IC body. Sunlight and fluorescent light also contain wavelengths that can slowly
erase EPROM data, so it is always suggested to keep the erasure window covered with a
piece of black tape or a label sticker.
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EPROMs cannot be programmed in circuit. The programming voltage is normally 21volts or

higher. Thus, a microprocessor working with 5V on motherboard cannot program the EPROM
in circuit. So EPROM needs to be taken out and programmed externally on a EPROM
programmer.
EEPROM
Removing an IC from a circuit in order to erase and reprogram it can be a very inconvenient.
An Electrically Erasable PROM (EEPROM) or flash memory is a modified version of EPROM
technology whose contents can be erased using electrical pulses instead of ultraviolet light.
This approach allows blocks of addresses (not necessarily the entire device) to be erased
and rewritten while the IC is still in the circuit. These IC also retains its information without
power. A large number of PC manufacturers are using flash memory instead of conventional
ROM devices. This allows BIOS upgrades to be programmed right on the motherboard without
even removing the BIOS IC. The upgrades are available as downloads from manufacturers on
Internet. (This is the latest trend)
MEMORY IC OPERATIONS
Memory ICs are much more than simple storage cells. Most memory ICs can be broken down
into four major segments: the storage array, the address buffer and decoding circuits, the data
bus buffer circuits, and the control circuits. Each of these elements is very important to all
memory operations.
STORAGE ARRAY
Storage cells are organised into a two-dimensional array (or matrix) made up of rows and
columns. This memory array actually stores entire information (Data). This memory array is
where information is actually stored. Depending on the type of cells used, there can be millions
of cells in the array. Thus, additional circuitry is needed to :-
a. Select which cells in the array are active.
b. Manage the data at those cells, and
c. Control the flow of data into or out of the IC.
ADDRESS CIRCUITS
Address signals select the active cells. Once valid address signals are applied to the IC,
address-decoding circuitry enables the proper cells. Each address can select 1,2,4,8, 16 or
32 cells depending on the array’s configuration and its address decoding circuitry. For Example:
Memory Organisation: Memory ICs can be organised in a one bit per address, four bits per
address, eight bits per address, 16 bit per address or 32-bit per address. Memory IC holds 16
kilobits, but that does indicate how the IC is organized. This 16-kilobit IC can be organized as
16k x 1 bit (16,384 address locations with 1 bit at every location), or 4K x 4 bits ( 4096
addresses with 4 bits per address), 2K x 8 bits (2048 addresses with 8 bits per address), and
so on, but each of these organizations would still be 16-kilobit ICs.
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CONTROL AND DATA CIRCUITS
Control signals determine how the IC responds to data, after the desired cells are active.
There are two common control signals: - Chip Select (-CS) and –Write Enable (-WE) or Read-
Write (R/-W). When the chip select is logic 1, the IC is disabled, so it will not interact with the
data bus at all regardless of what address is applied. In the disabled state, the IC’s data lines
are neither logic 1 or logic 0, but a high-impedance state that effectively disconnects the IC
from the data bus. The chip select signal is needed for controlling multiple memory ICs that
share the same data bus.
Address decoding, data buffering, and IC control all must work together to operate the memory
storage array.
ACCESS TIME
As an ideal memory device, the selected data should be instantly available at the IC’s data
lines. In practice, however, there is always some finite amount of time delay between the point
at which an address input is valid, and the point at which selected data becomes valid at the
data lines. This time delay is known as access time. Even though memory IC access time is of
the order of nanoseconds, it has very big impact on the overall performance of computer.
Table below illustrates typical access times for DRAM, cache, and tag memory versus CPU
speed.
Memory devices that are not fast enough to keep pace with the microprocessor can seriously
slow down the performance of the system as wait states are used. (explained in this chapter).
SRAM components typically offer the lower access times , and EPROM and EEPROM devices
usually offer the highest access times. The wait state puts the microprocessor in a hold states
for one or more clock cycles, while memory is read or written. The lower the access time the
faster is the memory IC.
Typical Memory Speed Parameters

CPU Speed DRAM Cache Tag
8 MHz 120 ns 35 ns 35 ns
10 MHz 120 ns 35 ns 30 ns
12 MHz 120 ns 35 ns 30 ns
16 MHz 100 ns 30 ns 30 ns
20 MHz 100 ns 30 ns 30 ns
25 MHz 80 ns 25 ns 25 ns
33 MHz 80 ns 25 ns 25 ns
40 MHz 80 ns 20 ns 20 ns
50 MHz 70 ns 20 ns 15 ns
66 MHz 70 ns 20 ns 15 ns
100 MHz 50 ns 10-15 ns 15 ns
(20)
The number of wait states depends on memory speed related to microprocessor speed. Larger
differences require more wait states, and vice versa.
TIP: Use ICs with same memory access time or as close as possible.
Refresh Operation
The electrical charges placed in each DRAM storage cell must be refreshed periodically
every few milliseconds. Without refresh, DRAM data will be lost. As a principle, refresh requires
that each storage cell be read and rewritten to the memory array. In actual operation, a row of
bits is automatically refreshed whenever an array row is selected. Thus, the entire memory
array can be refreshed by reading each row in the array every few milliseconds.
Enhanced Memory Concepts
Memory speed is closely related to the computer system’s performance. Microprocessors

regularly access system memory for instructions and data. If memory is not fast enough to
keep up with the CPU, the wait states that need to be added slow down the system and waste
the potential power offered by new generation CPUs. Improving memory performance: In
some cases memory technology has been modified to supply enhanced performance in certain
operating modes.
Cache and Tag Memory
Even the fastest DRAM is still not able to keep pace with the current generation of fast CPUs.
Caching is a memory speed enhancement technique used with today’s highest-performance
systems. A cache places a (relatively) small amount of very fast memory (typically SRAM)
between the CPU and the bulk of system memory. By keeping fast cache memory filled with
data (that the CPU needs), data can be accessed without wait states; performance is improved.
There are generally three elements to a cache system: tag RAM, cache logic, and cache
RAM.
It is important to know if a copy of needed information is in the cache or not. When information
is copied into the cache, the system memory address where that data is stored, is kept in tag
RAM along with status bits needed by the cache logic. Each cache entry is referred to as a
tag. Thus, tag RAM acts as the cache librarian.
There are generally two ways of implementing a cache system: internal or external. Internal
cache is part of the CPU; all of the elements of a cache system are fabricated into the
microprocessor itself. For example, Intel’s Pentium microprocessor contains two internal 8K
caches (one for instructions, and the other for data). External cache is built onto the
motherboard. Although external cache is a bit slower byte-for-byte when compared with an
internal cache, the size and expand ability of an external cache often provides superior
performance overall.
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Shadow Memory
ROM devices (BIOS-ROM and ROM on add on cards) are very slow with access times often
exceeding several hundred nanoseconds. ROM access thus requires a large number of wait
states that will slow down the system’s performance. BIOS routines and video ROM routines
are frequently used, thus the motherboard design is such that the contents of BIOS-ROM and
other ROM on add on card can be loaded in RAM area. This is selectable in CMOS setup.
RAM is faster than ROM thus the delay in loading routines is eliminated.
LATEST TYPES OF DRAMs USED ON MOTHERBOARDS
BASIC DRAM OPERATION
A DRAM memory array is a table of cells. These cells are comprised of capacitors, and contain
one or more ‘bits’ of data, depending upon the chip configuration. This table is addressed via
row and column decoders, which in turn receive their signals from the RAS and CAS clock
generators. In order to minimize the package size, the row and column addresses are
multiplexed into row and column address buffers. address lines, there will be 11 row and 11
column address buffers. Access transistors called ‘sense amps’ are connected to the each
column and provide the read and restore operations of the chip. Since the cells are capacitors
that discharge for each read operation, the sense amp must restore the data before the end of
the access cycle.
The capacitors used for data cells tend to discharge off their charge, and therefore require a
periodic refresh cycle or data will be lost. A refresh controller determines the time between
refresh cycles, and a refresh counter ensures that the entire array (all rows) are refreshed.
A typical memory access takes place as below: First, the row address bits are placed onto the
address pins. After a period of time the RAS\ signal falls, which activates the sense amps and
causes the row address to be latched into the row address buffer. When the RAS\ signal
stabilizes, the selected row is transferred onto the sense amps. Next, the column address bits
are set up, and then latched into the column address buffer when CAS\ falls, at which time the
output buffer is also turned on. When CAS\ stabilizes, the selected sense amp feeds its data
onto the output buffer.
ASYNCHRONOUS OPERATION
An asynchronous interface is one where a minimum period of time is determined to be

necessary to ensure an operation is complete. Each of the internal operations of an
asynchronous DRAM chip are assigned minimum time values, so that if a clock cycle occurs
any time prior to that minimum time another cycle must occur before the next operation is
allowed to begin.
Thus it is obvious that all of these operations require a significant amount of time (hence slow
operation).
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PAGE MODE ACCESS
By implementing special access modes, designers eliminate some of the internal operations
for certain types of access. The first significant implementation was called Page Mode access.
Using this method, the RAS\ signal is held active so that an entire ‘page’ of data is held on the
sense amps. New column addresses can then be repeatedly clocked in only by cycling CAS\.
This provides much faster random access reads, since the row address setup and hold times
are eliminated.
While some applications benefit greatly from this type of access, there are others that do not
benefit at all. The original Page Mode was improved upon and replaced very quickly. Now this
type of RAM is obsolete.
FAST PAGE MODE
Fast Page mode is improved upon the original page mode. It eliminates the column address
setup time during the page cycle. This was accomplished by activating the column address
buffers on the falling edge of RAS\ (rather than CAS\). Since RAS\ remains low for the entire
page cycle, this acts as a transparent latch when CAS\ is high, and allows address setup to
occur as soon as the column address is valid, rather than waiting for CAS\ to fall.
Fast Page mode became the most widely used access method for DRAMs, and is still used
on many systems. The benefit of FPM memory is reduced power consumption. The main
drawback is that it adds at least 5ns to the cycle time.
Today, FPM memory is the least desirable of all available DRAM memory. Use this if system
such as 486 based systems does not support any of the later memory types. Typical timings
are 6-3-3-3 (initial latency of 3 clocks, with a 3-clock page access).
HYPER PAGE MODE (EDO)
Major improvement to asynchronous DRAMs came with the Hyperpage mode, or Extended
DataOut. This innovation was simply to no longer turn off the output buffers upon the rising
edge of /CAS. In essence, this eliminates the column precharge time while latching the data
out. This allows the minimum time for /CAS to be low to be reduced, and the rising edge can
come earlier.
A 40% or greater improvement in access times is achieved by EDO over previous FPM-RAM.
EDO uses the same amount of silicon and the same package size. EDO works well with
memory bus speeds up to 83MHz. If the chips are sufficiently fast (55ns or faster), EDO can
be used even with a 100MHz memory bus. One of the best reasons to use EDO is that all of
the current motherboard chipsets support it with no compatibility problems, unlike much of the
synchronous memory now being used.
Note : EDO RAM vs. SDRAM : SDRAM should be used for bus speeds above 83MHz.
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With a typical EDO timing of 5-2-2-2 at 66MHz, there is almost no improvement with SDRAM
over EDO. At 83MHz it is still negligible. At 100MHz bus operation, EDO will lag far behind
current SDRAM in performance even if it does operate at that speed, due to the need for 6-3-
3-3 timings.
BURST EDO (BEDO)
Burst mode is an advancement over page mode, in that after the first address input, the next
3 addresses are generated internally, thereby eliminating the time necessary to input a new
column address.
SYNCHRONOUS OPERATION (in case of DRAMs)
With an asynchronous interface, the processor waits (middle state) for the DRAM to complete
its internal operations, which takes about 60ns. With synchronous control, the DRAM latches
information from the processor under the control of its system clock. These latches store the
addresses, data and control signals, which allows the processor to handle other tasks
meanwhile. After a specific number of clock cycles the data becomes available and the
processor can read it from the output lines.
Another advantage in case of a synchronous interface is that the system clock is the only
timing edge that needs to be provided to the DRAM. This eliminates the need for multiple
timing strobes to be given. The inputs are simplified as well, since the control signals, addresses
and data can all be latched in without the processor monitoring setup and hold timings. Similar
benefits are for output operations also.
JEDEC SDRAM
All DRAMs that have a synchronous interface are known generically as SDRAM. This includes
CDRAM (Cache DRAM), RDRAM (Rambus DRAM), ESDRAM (Enhanced SDRAM) and others,
however the type that most often is called SDRAM is the JEDEC standard synchronous DRAM.
JEDEC SDRAM not only has a synchronous interface controlled by the system clock, it also
includes a dual-bank architecture.
ENHANCED SDRAM (ESDRAM)
ESDRAM is essentially SDRAM, plus a small amount of SRAM cache on the chip included
which allows for lower latency times and burst operations up to 200MHz. Just as with external
cache memory, the goal of a cache DRAM is to hold the most frequently used data in the
SRAM cache to minimize accesses to the slower DRAM. One advantage to the on-chip SRAM
is that a wider bus can be used between the SRAM and DRAM, effectively increasing the
bandwidth and increasing the speed of the DRAM even when there is a cache miss.
(24)
SLDRAM
SLDRAM is a protocol-based design, just as RDRAM is, it is an open-industry-standard.
Due to the use of packets for address, data and control signals, SLDRAM can operate on a
faster bus than standard SDRAM – up to at least 200MHz. Just as DDR SDRAM operates the
output signal at twice the clock rate, so can SLDRAM. This puts the output operation as high
as 400MHz.
Compared to DRDRAM, it seems that SLDRAM is a much better solution due to the lower
actual clock speed (reducing signal problems), lower latency timings and lower cost due to
the royalty-free design and operation on current bus designs. It appears that even the bandwidth
of SLDRAM is much higher than DRDRAM at 3.2GB/s vs. 1.6GB/s.
Protocol Based DRAM
All of the previously discussed DRAM have separate address, data and control lines which
limits the speed at which the device can operate with current technology. In order to overcome
this limitation, several designs implement all of these signals on the same bus. The two protocol
based designs currently getting the most attention are SyncLink DRAM (now called SLDRAM
due to trademark issues) and Direct Rambus DRAM (DRDRAM) licensed by Rambus, Inc.
DDR SDRAM
One limitation of JEDEC SDRAM is that the theoretical limitation of the design is 125MHz,
though technology advances may allow up to 133MHz operation. Essentially, this design allows
the activation of output operations on the chip to occur on both the rising and falling edge of
the clock. Currently, only the rising edge signals an event to occur, so the DDR SDRAM
design can effectively double the speed of operation up to at least 200MHz. There is already
one Socket 7 chipset that has support for DDR SDRAM.
(25)
(26)
CHAPTER - 3
MOTHERBOARDS
INTRODUCTION
This chapter covers motherboard, various microprocessors, their compatibility, bus architecture
and support chips.
SYSTEM CLOCK : All the operations are timed by the system clock, which makes sure that
every step is synchronized. This clock is totally different and independent from the Windows
clock, which is the one that shows the time on your screen like 3:42 PM. This is the clock for
microprocessor and system board.
THE MICROPROCESSOR & COMPATIBILITY
In all PCs, the microprocessor is the chip that runs programs. The Microprocessor, or central
processing unit (CPU), carries out a variety of computations, numeric comparisons, and data
transfers in response to programs stored in memory.
The CPU controls the computer’s basic operation by sending and receiving control signals,
memory addresses, and data from one part of the computer to another along a group of
interconnecting electronic pathways called a bus. Located along the bus are input and output
(I/O) ports that connect the various memory and support chips to the bus. Data passes
through these I/O ports while it travels to and from the CPU and the other parts of the
computer.
In IBM PCs, the CPU always belongs to the Intel 8086 family of microprocessors. The
similarities and differences between the different microprocessors are pointed out as they
are described.
8088 Microprocessor
The 8088 is the 16-bit microprocessor that controls the standard IBM personal computers,
including the original PC , PC/XT. Almost every bit of data that enters or leaves the computer
passes through the CPU to be processed. Inside the 8088, 14 registers provide a working
area for data transfer and processing. These internal registers forming an area 28 bytes in
size, are able to temporarily store data, memory addresses, instruction pointers, and status
(27)
and control flags. Through these registers, the 8088 can access 1 MB (megabyte), or more
than one million bytes of memory. In other words it can address one million memory
address locations. The microprocessor has an external data bus 8 bits wide whereas internally
data bus is used as 16 bits wide. NEC V-20 is pin compatible to Intel 8088 IC and is faster
and efficient than the later.
8086 Microprocessor
The 8086 is used in the PS/2 models 25 and 30 (and also in many IBM PC clones). The 8086
differs from the 8088 in only one minor respect. It uses a full 16 bit data bus instead of the 8-
bit bus that the 8088 uses. The difference between 8 bit and 16 bit buses is discussed later)
virtually anything that you read about the 8086 also applies to the 8088 for programming
purposes, consider them identical.
NEC V-30 is pin compatible to 8086 .
80286 Microprocessor
The 80286 is used in the PC/AT and in the PS/2 models 50 and 60. Although fully
compatible with the 8086, the 80286 supports extra programming features that lets it
execute programs much more quickly than the 8086. Perhaps the most important
enhancement to the 80286 is its support for multitasking.
Multitasking is the ability of a CPU to perform several tasks at a time such as printing a
document and calculating a spreadsheet or documenting a document by quickly switching
its attention among the controlling programs.
The 80286 used in a PC or PC/AT can support multitasking with the help of sophisticated
control software. however, an 80286 can do a much better job of multitasking because it
executes programs more quickly and addresses much more memory than the 8088.
Moreover, the 80286 was designed to prevent tasks from interfering with each other.
The 80286 can run in either of two operating modes: real mode or protected mode. In real
mode, the 80286 is programmed exactly like an 8086. It can access the same 1 MB range
of memory addresses as the 8086. In protected mode however, the 80286 reserves a
predetermined amount of memory for an executing program, preventing that memory from
being used by any other program. This means that several programs can execute
concurrently without the risk of one program accidentally changing the contents of
another program’s memory area. An operating system using 80286 protected mode can
allocate memory among several different tasks much more effectively than can an 8086
based operating system.
The PC/AT 386 model uses the 80386, a faster more powerful microprocessor than the
80286. The 80386 support the same basic functions as the 8086 and offers the same protected
mode memory management as the 80286. However, the 80386 offers two important
advantages over its predecessors:
(28)
* The 80386 is a 32 bit microprocessor with 32 bit registers. It can perform computations
and address memory 32 bits at a time instead of 16-bits at a time.
* The 80386SX microprocessor has an internal computation capacity of 32 bits but its
external data bus is 16 bits wide. That is it transfers data in two time cycles. The
address bus of 80386SX CPU is of 24 bits same as of 80286 CPU.
· The 80386 offers more flexible memory management than the 80286 and 8086.
Math Coprocessor
The 8086, 80286 and 80386 can work only with integers. To perform floating-point computations
on an 8086-family microprocessor, you must represent floating-point values in memory and
manipulate them using only integer operations. During compilation, the language translator
represents each floating-point computation as a long, slow series of integer operations.
Thus, “number crunching” programs run very slowly, this is a problem if a large number of
calculations are to be performed.
Math coprocessor performs floating-point calculations and can solve above problem. Each
of the 8086 family microprocessor: the 8087 math processor is used with an 8086 or 8088
the 80287 math coprocessor is used with an 80286 and the 80387 math coprocessor is used
with an 80386. Each PC , PC/XT, PC/AT-286, 386 is built with an empty socket on its
motherboard into which you can plug a math coprocessor chip.
From a programmer’s point of view, the 8087 80287 and 80387 and math coprocessors are
fundamentally the same. They all perform arithmetic with a higher degree of precision and
with much greater speed than is usually achieved with integer software emulation. In
particular, programs that use math coprocessors to perform trigonometric and logarithmic
operations can run up to 10 times faster than their counter parts that use integer emulation.
The 486 is fully instruction-set-compatible with previous Intel processors, such as the 386, but
offers several additional instructions (most of which have to do with controlling the internal
cache).
Like the 386DX, the 486 CPU can address 4G of physical memory and manage as much as
64 terabytes of virtual memory. The 486 fully supports the three operating modes introduced
in the 386: real mode, protected mode, and virtual real mode.
The 486DX series has a built-in math coprocessor that sometimes is called an MCP (math
coprocessor or FPU (Floating-Point-Unit). This series is unlike previous Intel CPU chips, which
required you to add a math coprocessor if you needed faster calculations for complex
mathematics.
The main features that make 486 processor roughly twice as fast as an equivalent MHz 386
chip are:
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* Reduced instruction-execution time. Instructions in the 486 take an average of only

2 clock cycles to complete, compared with an average of more than 4 cycles on the
386.
* Internal (level 1) cache. The built-in cache has a hit ratio of 90 percent , which describes
how often zero-wait-state read operations will occur. External caches can improve this
ratio further.
* Built-in(synchronous) enhanced math coprocessor (some versions). The math
coprocessor runs synchronously with the main processor and executes math instructions
in fewer cycles than previous designs do.
The 486 Processor Series
Following are the primary versions of the 486:

* 486SX - 486 CPU without FPU (Floating-point-Unit)
* 486DX - 486 CPU plus FPU
* 486DX2 - Double-speed(Overdrive) 486 CPU plus FPU
* 486DX4 - Triple-speed 486 CPU plus FPU
Intel DX2 and DX4 operating Speeds version versus Motherboard Clock Speeds
Motherboard 16 MHz 20 MHz 25 MHz 33 MHz 50 Mhz
Clock Speed
DX2 processor speed 32 MHz 40 MHz 50 MHz 66 MHz N/A
DX4(2x mode) speed 32 MHz 40 MHz 50 MHz 66 MHz 100 MHz
DX4(2.5x mode) speed 40 MHz 50 MHz 62.5 MHz 83 MHz N/A
DX4(3x mode) speed 48 MHz 60 MHz 75 MHz 100 MHz N/A
The DX, DX2, and SX processors have a virtually identical 168-pin configuration.. The DX4 is
different because it requires 3.3 volts to operate instead of 5 volts, like most of the other chips.
If you are putting one of the new DX4 processors in an older system, you need some type of
adapter to regulate the voltage down to 3.3 volts. If you put the DX4 in a 5V socket, you will
destroy expensive chip.
Internal Cache Memory : cache basically is an area of very fast memory built into the processor
that is used to hold some of the current working set of code and data. Cache memory can be
assessed with no wait states, because it can fully keep up with the processor.
Internal (level 1) Cache : All 486 family CPUs include, as a standard feature, an integrated
(Level 1) cache controller with either 8K of 16K of cache memory included. Using cache
memory reduces a traditional system bottleneck, because system RAM often is much slower
than the CPU. This prevents the processor from having to wait for code and data from much
slower main memory, therefore improving performance. Without the cache, a 486 frequently
would be forced to wait until system memory is caught up. If the data that the 486 chip wants
is already in the internal cache, the CPU does not have to wait. If the data is not in the cache,
the CPU must fetch it from the secondary processor cache or (in less sophisticated system
designs) from the system bus.
(30)
Special software or programs are not needed to take advantage of this cache it works invisibly
inside the chip. Because the cache stores both program instructions (code) and data, it is
called a unified cache.
External (Level 2) Cache : An external secondary cache (Level 2) of up to 512K or more of

extremely fast Static RAM (SRAM) chips also is used in most 486-based systems to further
reduce the amount of time that the CPU must spend waiting for data from system memory.
Fetching information from the secondary processor cache rather than from system memory is
much faster because of the extremely fast speed of the SRAM chips-20 nanoseconds(ns) or
less.
POWER MANAGEMENT ARCHITECTURE
A power-management architecture called System Management Mode(SMM) has been

introduced by INTEL. This new mode of operation is totally isolated and independent from
other CPU hardware and software. SMM provides hardware resources such as I/O logic,
timers & registers that can control and power down-computer components without interfering
with any of the other system resources. It works in a dedicated memory space called System
Management Memory, which is not visible and does not interfere with operating-system and
application software.
PENTIUM MICROPROCESSOR
The Pentium is fully compatible with previous Intel processors, but it also differs from them in
many ways. Pentium features twin data pipelines, which enable it to execute two instructions
at the same time. The 486 and all preceding chips can perform only a single instruction at a
time. Intel calls this capability to execute two instructions at the same time as superscalar
technology. With superscalar technology, the Pentium can execute many instructions at a rate
of two instructions per cycle.
The standard 486 chip can execute a single instruction in an average two clock cycles-cut to
an average of one clock cycle with the advent of internal clock multiplication used in the DX2
and DX4 processors.
Super-scalar architecture usually is associated with high-output RISC (Reduced Instruction
Set Computer) microprocessors. The Pentium is almost like having two 486 chips in one
package.
Table shows the Pentium processor specifications.
Maximum rated speeds 60, 66 ; 75, 90, 100 , 133 MHz

Operating voltage 5v (first launch), 3.3v (second launch)
External data bus 64-bit
Memory address bus 4G
CPU clock multiplier 1x (first launch), 1.5x-2x (second launch)
Register Size 32-bit
Integral-cache-size 8K code, 8K data
Burst-mode transfers Yes
(31)
External package 273-pin PGA , 296-pin SPGA

Math Coprocessor Built-in FPU (Floating-point-unit)
Power management SMM(System management Mode), enhanced in second
launch
PGA = Pin Grid Array

SPGA = Staggered Pin Grid Array
The Pentium Pro
Pentium Pro processor family consists of processors working at 150, 166, 180 and 200 MHz.
The Pentium Pro processor family’s significant performance improvement over previous Intel
architectures is primarily based on “Dynamic Execution”, which is the next step beyond the
superscalar architecture. Dynamic execution encompasses the following technology
innovations:
> Multiple branch prediction: predicts the flow of the program through several branches.
> Data flow analysis: schedules instructions to be executed when ready, independent of
the original program order.
> Speculative execution: increases the rate of execution by looking ahead of the program
counter and executing instructions that are likely to be needed.
Other significant features of the Pentium Pro processor that provide improvements over existing
processors include:
> 256K or 512K non-blocking level two cache, which improves performance by reducing
the average memory access time and providing fast access to recently used instructions
and data. The performance of this cache is enhanced through a dedicated internal 64-
bit data bus, running at full CPU core speed.
> A pipelined Floating-Point-Unit (FPU) for supporting the 32-bit and 64-bit formats. The
FPU is object-code compatible with the Intel Pentium processor FPU and Intel 1486
processor FPU.
> Support for up to four same microprocessors. This enables low cost 4-way
symmetric multiprocessing, providing a significant performance boost for multi-threaded
applications.
Pentium Pro processor is optimised’ for 32-bit performance. Most standard business
productivity software applications are now available in 32-bit versions. The Pentium Pro
processor offers unsurpassed performance for standard 32-bit software, offering twice the
performance of a Pentium processor 133 MHz when running 32-bit business applications on
Windows NT (based on Pentium Pro processor-200 MHz). The performance of the Pentium
Pro processor on 16-bit software running under windows 95 or Windows 3.1 is similar to that
of a fast Pentium processor.
(32)
The Pentium Pro processor looks different than other chips. It will not fit into a Pentium
processor socket. The Pentium Pro processor bus is quite different from Pentium processor
bus so it is not designed to be pin compatible. The component bus of Pentium processor is
designed to interface to an external L2 cache. It also includes features to optimize CPU-to-
cache data transfers. In contrast, Pentium Pro processor includes a 256KB L2 cache in the
same package and the CPU communicates with its L2 cache using a private internal bus.
Multi-processing is easier with the Pentium Pro processor. The Pentium Pro processor
bus was designed to support multiple Pentium Pro processor connected in parallel. The Pentium
Pro processor component bus is a symmetric multiprocessing bus. Pentium Pro processor
system designs are made so that no additional system logic is required for multi-processing
or the interconnection of up to four Pentium Pro processors. This means that it’s very easy-
and cost effective-for mother board designers to include multiple Pentium Pro processors, by
just providing sockets for the additional processors.
The Pentium Pro processor is not a 64-bit processor. Like all Intel processors since the
Intel 386 processor, the Pentium Pro processor is a true 32-bit processor. The general purpose
registers are the same as on previous generations of Intel architecture processors and the
instruction set is supported with only one new instruction being introduced. However, there
are a variety of wider data paths both inside and outside the chip. One visible feature that is
sometimes misinterpreted is that the Pentium Pro processor, like the Pentium processor, has
an external 64-bit bus in order to communicate more efficiently with the system memory. This
wider external data path increases bandwidth between the Pentium Pro processor and the
system, but doesn’t make it a 64-bit machine.
Pentium- MMX
Pentium MMX processor incorporates Pentium with MMX technology which is a significant
enhancement to the Intel’s microprocessor Architecture. It enhances the performance of
complex media-intensive and communications applications and enable new features and
capabilities.
MMX technology incorporates new instructions and data types. These instructions and data
types can be used by any type of software, not just multimedia applications.
MMX technology improves file transfer rate and network performance by enabling faster
compression, decompression and smaller file sizes.
MMX TECHNOLOGY
MMX technology instructions allow several small data quantities to be concatenated into a
single larger quantity, permitting rapid, parallel computations on multiple data quantities at
once. For example, graphics information is commonly represented in small, 8-bit, byte sized
quantities. Previously, manipulating 8 bytes of graphics data required 8 repetitions of a single
instruction. The same manipulation can now be performed with a single MMX technology
instruction, operating on all 8 bytes simultaneously,. The result is an 8x (8 times) improvement
(33)
in execution time. This speedy, parallel processing of combined data quantities is termed the
Single Instruction Multiple Data (SIMD model).
PENTIUM II PROCESSOR
The Pentium II processor integrates the best attributes of Intel’s processors, the Dynamic
Execution performance of the Pentium Pro processor plus the capabilities of MMX technology.
The Pentium II processor is easily scalable to two microprocessors in a multiprocessor system.
The Pentium II processor extends the power of the Pentium Pro processor with performance
for business media, communication and Internet capabilities.
Software designed for Intel’s MMX technology unleash full-screen, full-motion video, enhanced
color, realistic graphics and other multimedia enhancements.
Pentium Pro processor’s Dynamic Execution technology is :
> Multiple branch prediction: predicts the flow of the program through several branches,
accelerating the flow of work to the processor.
> Data flow analysis: creates an optimized reordered schedule of instructions by analyzing
data dependencies between instructions.
> Speculative execution: carries out instructions speculatively, based on this optimized
schedule, keeping the processor’s superscaler execution units busy and boosting overall
performance.
Intel’s MMX Media Enhancement Technology is :
> Intel’s MMX technology includes new instruction and data types that allow applications
to achieve a new level of performance. Intel’s MMX technology is designed as a set of basic,
general purpose integer instructions that can be easily applied to the needs of a wide diversity
of multimedia and communications applications. The highlights of the technology are:
* Single Instruction, Multiple Data (SIMD) technique
* 57 new instructions
* Eight 64-bit wide MMX technology registers
Other significant features of the Pentium II processor include:
> High-performance Dual Independent Bus architecture (system bus cache bus) for high
bandwidth.
> The system bus supports multiple transactions to increase bandwidth availability. It
also provides “glueless” support for two Pentium-II processors. This enables low-cost,
2-way symmetric multiprocessing, providing performance boost for multi-tasking
operating systems and multi-threaded applications.
> A 512K Byte unified non-blocking level two cache, which improves performance by
reducing the average memory access time and providing fast access to recently used
instructions and data. The performance is enhanced through a dedicated 64-bit cache
bus.
(34)
> A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit formats.
IDENTIFYING PENTIUM-II PROCESSOR
Original Intel P-II processor had product details marked on the CPU like this :
Afterwards that has been changed as shown:
CYRIX PROCESSORS
The Cyrix MII is more clearly labeled than the PII. These processors are Socket 7 processors.
The MII 300 PR uses a 66 MHz bus, while the MII 333 PR uses an 83 MHz bus.
Note that the 300 or the 333 does not refer to the actual clock speed of the chip, but to the
“Performance Rating”. That is, the MII 300 is rated equal to a 300 MHz chip (read from Intel)
in performance. Similarly, the MII 333 has a performance equal to 333 MHz chip. So what is
the actual clock speed? Simple, Multiply the bus speed by the multiplier. So, the MII 300 PR
has an actual clock speed of 66 x 3.5 = 231 MHz, and the 333 PR has an actual clock speed
of 83 x 3 = 249 MHz.
(35)
Various CPU Sockets
Intel has created a set of six socket designs, named Socket 1 through Socket 6. Each socket
is designed to support a different range of original and upgrade processors.
Intel 486/PENTIUM CPU Socket Types and Specifications

Socket No. of Pin
Number Pins Layout Voltage Supported Processors
Socket 1 169 17x17 PGA 5V SX/SX2. DX/DX2*
Socket 2 238 19x19 PGA 5V SX/SX2, DX/DX2*, PENTIUM

Overdrive
Socket 3 237 19x19 PGA 5V/3.3V SX/SX2, DX/DX2, DX4,

PENTIUM Overdrive, DX4
PENTIUM Overdrive
Socket 4 273 21x21 PGA 5V PENTIUM 60/66, PENTIUM 60/

66 Overdrive
Socket 5 320 37x37 SPGA 3.3V PENTIUM 90/100, PENTIUM

90/100 Overdrive
Socket 6 235 19x19 PGA 3.3V DX4, DX4 PENTIUM Overdrive
Socket 7 3.3V PENTIUM / MMX, K6 (AMD),

3.45V CYRIX MII 233, 300, 333 PR**
Slot 1 242 A1-A121DIP Add-on 3.3V PENTIUM II, 333, 350, 400,
450MHz,
B1-B121 Card Celeron 300, 333 MHz.
*DX4 also can be supported with addition of an aftermarket 3.3V voltage-regulator adapter.
PGA = Pin Grid Array
SPGA = Staggered Pin Grid Array
**PR = Performance Rating. This does not refers to the actual clock speed of the chip, but to
the performance rating i.e. performance equivalent to an Intel chip of mentioned speed.
PROCESSORS NEED TO BE KEPT COOL
Most processors which run at speed in excess of 60 MHz need cooling fans on the chip. As
processors become more powerful, so does their need to keep cool. The Intel Pentium II for
example, consumes 38 watts of power compared to the 28 watts of the earlier Pentium.
To cool the chip, the on-chip fan assembly typically includes a heat sink and a fan.
(36)
THE SUPPORT CHIPS
The microprocessor cannot control the entire computer without some help-nor should it. By
delegating certain control functions to other chips, the CPU is free to attend to its own
processing or other work. These support chips can be responsible for such process as
controlling the flow of information throughout the controller and controlling the flow of
information to or from a particular device (such as a video display or disk drive) attached
to the computer. These are called device controllers. Device controllers may be present on
mother board or on a separate board that plugs into one of the PCs expansion slots.
Many support chips in the PCs , PC-ATs are programmable which means they can be
manipulated to perform specialized tasks. Details about programming individual chips is not
in the scope of this course. These chips are mostly integrated as Surface Mounted device
(SMD). These SMDs are custom built and normally availability of inside technical details is
rare being company’s trade secret.
The Programmable Interrupt Controller
In a PC or PC-ATs , one of the CPU’s essential tasks is to respond to hardware interrupts.

A hardware interrupt is a signal generated by a component of the computer, indicating
that the component needs CPU attention. For example the keyboard, the disk drive controllers
, ports, the system timer all generate hardware interrupt for carrying out an appropriate
hardware-specific activity, such as processing a keystroke, data transfers, incrementing
time-of-day counter respectively.
Each PC and PC-AT has a programmable interrupt controller (PIC) circuit that monitors
interrupts and forwards them one at a time to the CPU. The CPU responds to the interrupts
by executing a particular software routine called an interrupt handler. Because each
hardware interrupt has own interrupt handler in the ROM BIOS or in DOS, the CPU can
recognize and respond specifically to the hardware that generates each hardware interrupts.
In the PC & PC/XT the PIC can handle eight (8) different hardware interrupts.
In the PC/AT two PICs are chained together to allow a total of fifteen (15) different hardware
interrupts to be processed.
The DMA Controller
Some parts of the computer are able to transfer data to and from the computer’s memory
without passing through the CPU. This operation is called direct memory access, DMA . The
main purpose of DMA controller is to allow disk drives to read or write data without involving
the microprocessor. Because disk I/O is relatively slow compared to CPU speeds DMA speeds
up the computer’s overall performance. In PC/AT, eight DMA channels are provided.
(37)
BUSES
The bus carries more than data, it carries power and control information such as timing
signals (from the system clock) and interrupt signals, as well as the addresses of the millions
of memory cells and the many devices attached to the bus. To accommodate these
different functions the bus is divided into four parts: the power lines, the control bus, the
address bus, and the data bus.
Buses can be identified by their architecture. The main types of I/O bus architectures are:
* ISA
* Micro channel
* EISA
* Local Bus
* VESA local bus
* PCI Bus
The differences among these buses consist primarily of the amount of data that they can
transfer at one time and the speed at which they can do it. Each bus architecture is implemented
by a chipset that is connected to the processor bus. Normally, this chipset also controls the
memory bus. The following sections describe the different types of PC buses.
The ISA Bus
ISA (Industry Standard Architecture), is the bus architecture that was introduced with the
original IBM PC and later expanded with the IBM PC/AT.
Two versions of the ISA bus exist, based on the number of data bits that can be transferred on
the bus at a time. The older version is an 8-bit bus; the newer version is a 16-bit bus. both
versions of the bus operate at an 8 MHz cycle rate, with data transfers requiring anywhere
from two to eight cycles. The theoretical maximum data rate of the ISA bus is 8M per second.
The 8-Bit ISA Bus. The 8-bit ISA expansion slot physically allows an add on adapter card
with 62 gold contracts on its bottom edge to plug into a slot in the motherboard that has 62
matching gold contracts. Electronically, this slot provides 8 data lines and 20 addressing lines,
enabling the slot to handle 1M of memory.
The 16-bit ISA Bus. The second-generation Intel 80286 chip can handle 16 bits on the I/O
bus at a time, as compared to 8 bits in older CPUs . Thus IBM developed a system that could
support both 8-bit and 16-bit add on cards. An older 8-bit card can be plugged into the
forward part (62 pin) of the slot and 16-bit card can be plugged into both parts of the slot.
The second part of each expansion slot adds 36 connector pins to carry the extra signals
necessary to implement the 16 bit data path.
(38)
Micro-Channel Architecture (MCA)
In April 1987, IBM announced a new computer line, the Personal Computer/2 (PS/2). It
featured a new expansion bus based on a new concept called micro channel architecture
(MCA). The MCA increased data throughput to 20 megabytes per second. This is more than
ten times the speed of the AT-ISA bus.
MCA expansion cards were smaller than those used in the ISA bus and used surface mounted
components. It was a full 32-bit bus. Every fourth pin was a ground, this reduced interference
and allowed much faster cycle times. Expansion cards could communicate directly with the
video graphics array(VGA) card.
Expansion cards can be configured by the microprocessor, there is no need to set micro-
switches/ DIP switches by the users. Expansion cards could now have their own processor
and memory. The main processor was now free from handling data transfer among the devices.
Cards could now be more powerful and intelligent, freeing the main CPU for additional
tasks. The disadvantage of the MCA was that it was not compatible with the old ISA cards.
Extended Industry Standards Architecture (EISA)
The EISA was designed to suceed ISA bus. The EISA bus provides 32 bit slots for use with
386DX or higher systems. EISA remained compatible with the old ISA boards. EISA was a
32-bit standard, even faster than the MCA, with a maximum transfer rate of 33 megabytes
per second. The expansion cards were almost twice as large, allowing for more components.
The EISA bus is synchronous and can perform transfers in long rapid-fire bursts. Only the
80386 and 80486 chips can use EISA. Interrupts no longer are edge-triggered and can be
shared.
EISA disk controllers reduce hard disk access times below the 1 milli second. On-board
intelligence and memory made extremely fast response, increased performance, and
widely enhanced video resolutions.
Local Bus
I/O buses discussed above are relatively having slow speed. This speed limitation is from the
days of the original PC, when the I/O bus operated at the same speed as the processor bus.
As the speed of the processor bus increased, the I/O bus designs made only nominal speed
improvements, primarily from an increase in the bandwidth (wider data path) of the bus. The
I/O bus had to remain at a slower speed, because the previously huge installed base of
adapter cards could operate only at slower speeds. Figure shows a block diagram of the
buses in a computer system.
Acute speed problem came when graphical user interfaces (such as Windows) became popular.
These systems required the processing of so much video data that the I/O bus gave lowest
throughput in the entire computer system. CPU was capable of 66 MHz speed where as data
transfer in the I/O bus were at a rate of only 8 MHz.
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Fig.: IBM-PC Bus Layout
So, the solution to this problem is to move the slotted I/O to an area where it could access the
fast speed processor bus - much the same way as the external cache.
Fig.: Local Bus Functional Block Diagram
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CACHE MEMORY
The fastest of processors can be slowed down if it interacts with slow subsystems like hard
disks and DRAM. To solve this bottleneck, caches are used. These usually have dedicated
memory that is much faster than the subsystem to be cached.
A disk cache stores recently read data in memory, and intercepts requests to read data from
the disk, to check if it has been already read, and if so, if that is still in the cache memory.
Since memory access is much faster than disk access, this boosts performance if the
same bit of data is accessed repeatedly.
Write caches intercept requests to write the disk and store it in the RAM. After collecting a
number of such requests, it writes them in one go, thus speeding performance.
Very fast SRAM chips are used by Processor as cache memory. The processor writes to the
fast SRAM without slowing down, and gets on with its work. The cache controller then writes
this data to the slower DRAM at its own speed, thus keeping the processor from slowing
down.
Local Bus working. Above arrangement became known as local bus, because external devices
(adapter cards) now could access the part of the bus that was local to the CPU-the processor
bus.
Physically, the slots provided in this new configuration are different from existing bus slots, to
prevent adapter cards designed for slower buses from being plugged into the higher bus
speeds( that this design made accessible).
Local-bus solutions do not replace earlier standards, such as ISA and EISA; they are designed
to augment these standards. Therefore, a system can be based on ISA or EISA and has one
or more local-bus slots available as well. Older cards still are compatible with the system, but
high-speed adapter cards can take advantage of the local bus slots as well.
The VESA Local Bus
Video Electronics Standards Association (VESA) developed a standardized local-bus

specification known as VESA Local Bus or simply VL-Bus.
The VL-bus slot offers direct access to system memory at the speed of the processor itself.
The VL-Bus can move data 32 bits at a time. This enables data to flow between the CPU and
a compatible video subsystem or hard drive at the full (32-bit ) data width of the 486 chip. The
maximum rated throughput of the VL-Bus is 128M to 132M per second.
The VL-bus connector has 112 contacts in two rows of 56 contacts spaced at 0.05-inch. It
support 32 data lines and 30 address lines to address four gigabits of RAM using the 486’s
memory addressing method.
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Automatic configuration is not possible with VL-bus as was possible with MCA bus. The
cards have either jumpers / DIP switches or their own installation software.
Despite the benefits of the VL-Bus, this technology has a few drawbacks, which are described
in the following list:
* Dependence on a 486 CPU. The VL-Bus inherently is tied to the 486 processor bus.
This bus is quite different from that used by Pentium processors (or by future processors).
* Speed limitations. The VL-bus specification provides for speeds of up of 66 MHz on

the bus, but the electrical characteristics of the VL-Bus connector limit an adapter card
to no more than 50 MHz. If the main CPU uses a clock modifier (such as the kind that
doubles clock speeds), the VL-Bus uses the unmodified CPU clock speed as its bus
speed.
* Card limitations. Depending on the electrical loading of a system, the number of VL-
Bus card is limited. As the system-board load increases and the clock rate increases,
the number of cards supported decreases. Although the VL-Bus specification provides
for three cards, this can be achieved only at clock rates of up to 40 MHz with low load
system-board. Only one VL-Bus card can be supported at 50 MHz with a high system-
board load.
Physically, the VL-Bus slot is an extension of the slots used for whatever type of base
system it has. If the system has an ISA system, the VL-Bus is positioned as an extension of
your existing 16-bit ISA slots. Likewise, if you have an EISA system or MCA system, the VL-
Bus slots are extensions of those existing slots.
VL-Bus 20 Version : Introduced in 1993, with the release of the 64-bit Pentium processor.
> This specification defines a 64-bit interface based on a 32-bit micro-channel connector
and maintains full compatibility with the VL-bus.
> Allows up to three slots at 40MHz and two slots at 50 MHz.
> Allows write-back caching which can minimise the number of necessary disk updates
by accumulating data to be written in a buffer and then writing it all at once at an
appropriate moment.
> Adds a new status signal that the bus can use to identify 486-based systems that
support the high-speed burst protocols from which some newer peripherals can benefit.
Peripheral Components Interconnect (PCI)
The peripheral component interconnect (PCI) bus is a high-performance connection

between the motherboard components and expansion boards.
A fundamental part of a PCI design is the PCI-to-host bridge chip that connects devices to
the PCI bus. With host bridge chip available, a new processor has access to all available
PCI components. This allows the PCI bus standard to be processor independent . Once the
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host bridge chip is available, only the PCI-to-bridge chip needs to be replaced the rest of the
system remains unchanged. PCI bus does not replace the standard expansion bus that are
popular today, but instead it complements them.
Fig.: PCI Bus Architecture
PCI bus standard has three advantages :
* It gives a low-cost, high-performance local-bus interface.

* It gives automatic configuration of components and add-on boards.
* The design has the versatility to support future generations of peripherals.
PCI standard reduces the cost by using multiplexed address and data bus that reduces the
pin count and size of the components.
(43)
PCI technology has the power to bring color-filled, high-resolution video in multiple windows.
A PCI bus running 33 MHz can move data at a peak rate of 132 megabytes per seconds
during data bursts. This fast wide bus is needed for multimedia applications.
Wide variety of chips with specialised functions, including not only video controllers but also
SCSI controllers, LAN adapters, and audio and video products for multimedia systems
have been developed and PCI adapter cards made.
Two types of PCI buses are :
> 32 bit data bus having 124-pin microchannel type connector. Only 47 of these
connections are used by an expansion board, the balance are for multiple power
supply and ground signals. Every active signal on the PCI bus is either next to or
opposite to a power ground or ground signal. This technique minimises stray radiation.
> 64-bit data bus having 188 pins in its connector.
PCI specifications include design for two connector types:

> 5V design
> 3.3V connector for lower-power designs.
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Both these designs are at times combined on a single-board.
PCI support software configuration without the need to set jumpers or DIP switches. All PCI
expansion boards must include 256 registers intended to store configuration information.
A special signal dedicated to each slot is used to read and write configuration information.
COMPACT PCI
Compact PCI is a new specification developed by PCI Industrial Computers Manufacturer’s

Group (PICMG). This specification merges the electrical and software standards of the PCI
bus with the Eurocard (VME) mechanical structure and a high-density, 2-mm pin and socket
connector.
Compact PCI improves the mechanics of a PCI system for higher reliability.
It provides all the plug-and-play solutions available for the desktop.
AGP
The Accelerated Graphics Port (AGP) is a new data super-highway on the PC platform for 3D
graphics and full-motion video.
AGP relieves the graphics bottleneck by adding a new dedicated high speed bus directly
between the chipset and the video graphics controller. This removes bandwidth-intensive 3D
and video traffic from the constraints of the PCI bus. In addition, AGP allows textures to be
accessed directly from system memory during rendering rather than being pre-fetched to
local graphics memory. Segments of system memory can be dynamically reserved by the OS
for use by the graphics controller, this memory is termed as AGP memory or non-local video
memory.
The net result is that the graphics controller is required to keep fewer texture maps in local
video memory.
This eliminates the size constraint for local graphics memory, thus enabling applications to
use much larger texture maps and further improving realism and image quality.
Also the PCI bus is free from video data traffic so that other devices can fully use PCI bus
bandwidth.
While the PCI bus supports a maximum of 132 Mbps, AGP at 66MHz runs at 533Mbps peak.
It gets this speed increase by transferring data on both the rising and falling edges of the 66
MHz clock and through the use of data transfer modes that are more efficient.
AGP MEMORY
AGP Memory is just dynamically allocated areas of system motherboard memory, which the
graphic controller can access quickly.
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CACHING CONCEPT
Memory Caching
Memory caching does not by itself speed up the system, as often wrongly thought to do so.
It is useful only in today’s very fast PC’s in which the speed of the CPU outstrips the speed
of the memory chips.
The memory cache consists of cache controller and a small amount- typically 32K to 128K of
very high speed memory. It is functionally between the CPU and the addressable RAM.
When the CPU requests data from the system memory, the cache controller looks up the
cache memory to see if the requested block of data is there. If so, the data is passed
quickly to the CPU.
If not, the CPU waits while data is fetched from the slower RAM. The data passes through
the cache memory which keeps a copy of it. The cache’s high-speed memory allows the
CPU to write data to cache memory at full speed and quickly return to other tasks. The cache
controller then copies the data to the intended memory destination in the slower RAM,
thereby improving the overall system performance.
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Disk Caching
Unlike memory caching, disk cache can be added to any system either by installing a cache
disk controller or by using a memory resident caching program that uses the RAM
(conventional, expanded or extended) as the cache area.
Accessing the data from the fastest disk-drives is much slower than the slowest RAM.
So when the CPU requests disk data, the disk cache program (or controller) intervenes
and first checks the disk cache memory (area in RAM or disk-cache area). If the requested
data is present in the disk cache memory, it is quickly passed on to the CPU. If not, the cache
controller reads the requested data from the disk into the disk cache memory area in RAM.
Smart controllers also read a few adjacent sectors or blocks of data, anticipating that the CPU
may soon request that data as well, thereby giving an extra boost to the performance.
When the cache is full and does not contain the requested data, newly read data from the
disk replaces a portion of the disk cache memory. All disk cache programs employ a unique
algorithm to achieve this.
The size of the cache directly effects the system performance: if it is too large, more time is
spent searching the cache area, if it is too small, time is wasted looking up in the cache for
the data that is not there.
MOTHERBOARD UPGRADATION
A checklist is given below for upgrading and evaluating any IBM compatible system.
Form Factor. For maximum flexibility, the motherboard should come in a Baby-AT form factor.
This will allow it to be installed in the widest variety of case designs.
Built-In Interfaces. Ideally a motherboard should contain as many built-in standard controllers
and interfaces as possible (except video). A motherboard should have a built-in floppy controller
that supports 2.88M drives, a built-in local bus (PCI or VL-bus) IDE connector, one or two
built-in serial ports (must use 16550A type UARTS), and a built-in parallel port (must be EPP
or ECP compliant). A built in mouse port would be preferable,
Processor. A 486 motherboard should be equipped with a 486DX2 or DX4-type processor-

the faster the better. The 486 processor should be an SL Enhanced version ( Power saving
feature), which is standard on DX4 model. A Pentium motherboard should only use the
second generation 3.3v Pentium Processor, which has a 296-pin configuration that differs
physically from the 273-pin first generation design. All second generation Pentiums are fully
SL enhanced. Pentium MMX Mother boards are to be used for Multimedia applications. Pentium
Pro based mother boards can be used for network servers.Pentium II @ 300 MHz (Pentium
Pro and MMX technology combined) can be used for network servers or for multimedia
applications both.
(47)
Processor Sockets. A 486 motherboard should have a ZIF (zero insertion force) processor
socket that follows the Intel socket 3 or socket 6 specifications. A Pentium motherboard should
have 1 or 2 ZIF sockets that follows the Intel sockets specification.
Pentium Pro does not have any of above sockets. It is quad type package.
Pentium II has Pins single in line and does not fit into any of the above motherboards.
Motherboard Speed. A 486 motherboard should run at 66/100 Mhz for maximum performance
and compatibility. Switchable speed selection is preferable as it allows other speeds to be
selected as well.
A Pentium motherboard should run at 100/133 MHz. All components should be rated to run at
the maximum allowable-speed.
Pentium Pro motherboard and Pentium II motherboard presently works at a max. speed of
133 MHz.
Cache Memory. 486 motherboards should have 256K Level 2 cache onboard. Pentium
motherboards should have 512K Level 2 cache onboard for maximum performance. Pentium
Pro , MMX, PII Mother boards should have 512 KB pipelined burst SRAM on board.
The level 2 Cache should be populated with chips that are fast enough to support the maximum
motherboard speed.
Memory Support : SIMM :- 486 motherboards should ideally use 72-pin SIMMs which support
a single bank per SIMM. 30-pin SIMMs are only acceptable upgrade boards designed to
reuse memory from older motherboards.
Pentium motherboards must only use 72-pin SIMMs. The SIMMs should be rated at 70 ns or
faster, preferably EDO RAM (Extended Data Output RAM).
DIMM Support : The DIMM socket on the motherboard support 168- pins, 3.3-volts SDRAM/
EDO memory modules. Pentium Pro, Pentium MMX, Pentium II based motherboards have
support for Synchronous DRAM.
PERFORMANCE : Data transfer rate for SDRAM is a maximum of 528MB per second whereas
for a EDO RAM is 264MB per second.
Bus Type. Motherboards should have an ISA Bus with PCI Bus.
BIOS . The motherboard should have an industry standard BIOS such as those from AMI,
Phoenix, or Award. The BIOS should be of a Flash ROM design for easy updating. It should
also support Enhanced IDE as well as 2.88M floppy drives. APM (Advanced Power
Management) should be built-into the BIOS as well.
Although one of the serial ports can be used for a mouse as well. A built-in SCSI port confirming
to ASPI (Advanced SCSI Programming Interface) standards is preferable. In- Built network
adapters are acceptable, but usually an ISA slot / PCI slot network adapter card is more
easily supported via standard drivers and is more easily upgraded as well.
Built-in video adapters are undesirable, since there are large and better choices in external
local bus video adapters.
(48)
Power Management. The motherboard should fully support SL Enhanced processors with
APM ( Advanced Power Management) and SMM (System management Mode) protocols that
allow for powering down various system components to different levels of readiness and
power consumption.
Documentation. Good technical documentation is a requirement. Documents should include

information on connector pin-outs for all connectors, any and all jumpers and switches found
on the board, specifications for cache RAM chips, SIMMs and other plug-in components, and
any other relevant applicable technical information.
New Motherboards
Name Mfr. Type Bus Speed

SE440 BX-2 INTEL Slot 1 100 MHz
6220 440 BX ATrend Slot 1 100 MHz
6310 440 EX ATrend Slot 1 100 MHz
P 5A-B Asus Socket 7 100 MHz
MOTHERBOARD PHYSICAL DIMENSIONS
There are several compatible dimensions used for motherboards. The form factor refers to the
physical dimensions and size of the board, and specifies what type of size of the board will fit
into. The types of motherboard form factors generally available are the following:
* Full-size AT
* Baby-AT
* LPX
MotherBoard Width Depth Case

ATX (Full size) 12" 9.6" ATX (mini-tower)
Mini-ATX (Baby) 11.2" 8.2" ATX (mini-tower)
NLX (LPX) 8-9" 10-13.6" Slimline
THE POWER-UP PROCESS
Cold Boot
When the monitor is powered ON, and then the PC is turned ON, the PC beeps and either
asks to insert a bootable disk in drive A or automatically comes up with the familiar screen of
DOS or other OS. This process is called as cold booting the system.
In Cold Booting process following process is followed :

1. POST (Power on self test )
2. Loading of Boot Strap program
When power is first applied to PC, the switching power supply generates a “Power Good”
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signal to the clock generator, which generates a +5-volt RESET pulse that is sent to reset pin
of the CPU. This signal starts the boot-up routine. It’s called a “cold boot” because the system
is being reset and initialized with all the start-up conditions necessary to operate and enable
the man-machine communication interface. The bootstrap program in PC is in the ROM.. This
ROM can be EPROM, PROM. It is a firmware program which starts the computer.
The following flowchart shows the actions that occurs in IBM PC during a cold boot, from the
time the power is turned ON.
Power-On Self-Test (POST) program
APPLY POWER
POWER SUPPLY SENDS “POWER GOOD” SIGNAL

CLOCK STARTS
+5V RESET PULSE IS PLACED ON RESET PIN OF CPU.

|
(Address of First Instruction is generated)
CPU Executes First Instruction- i.e

Jumps to POWER-ON SELF TEST
INTERRUPTS ARE DISABLED
CPU FLAGS ARE SET.

READ/WRITE TEST OF CPU REGISTERS OCCURS
(Write a pattern, verify correct pattern read back)
PERFORMS ROM-BIOS CHECKSUM TEST

(Compares Sum total of bytes in certain BIOS locations with known stored value)
INITIALIZES PROGRAMMABLE DIRECT MEMORY ACCESS (DMA) CHIP

(writes a pattern to all registers; verifies correct pattern read back)
TEST FOR WARM START

(if YES, skip memory test).
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TESTS RAM
(writes few patterns into memory & verifies correct read back)
INITIALIZES PROGRAMMABLE INTERRUPT CONTROLLER

(tests interrupt controller; conducts write/read test of interrupt mask register;
it masks interrupts & then verifies that none occur).
TEST TIMER FOR PROPER COUNT SPEED
INITIALIZES AND STARTS CRT CONTROLLER

(reads system board CMOS for display type;
sets video mode; conducts write/read test of video RAM.
DISPLAY CURSOR
TESTS KEYBOARD
(sends software RESET to keyboard electronics;
Enables keyboard; verifies scan code is correct
verifies no key is stuck i.e AA scan code;)
TESTS FOR INSTALLED DISK DRIVE

(checks system board CMOS setup)
TEST PRINTER AND RS-232 PORT

(performs write/read test to printer port;
stores addresses of valid ports)
ENABLE INTERRUPTS
BEEPS SPEAKER
PERFORMS INTERRUPT 19H (DISK DRIVE)

(if disk drive is attached, passes control to Boot Record
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WAITS FOR KEYBOARD COMMAND ACTION BY YOU.
** NOTE : The above sequence of test operations are only suggestive for explanation of the functioning , in
practice the programming of the ROM-BIOS may differ from company to company and from model to model. Thus
the test sequences may vary from case to case.
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CHAPTER - 4
INSTALLATION OF MOTHERBOARDS
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MOTHERBOARD INSTALLATION STEPS
Before switching ON the computer, complete the following steps:

1. Set jumpers on the motherboard.
2. Install memory modules.
3. Install the processor.
4. Install expansion cards.
5. Connect ribbon cables, and power supply.
6. Set up the BIOS software.
PRECAUTIONS
Computer motherboards and other subassemblies contain very delicate integrated circuit (IC)
chips. To protect the motherboard and other components against damage from static electricity,
follow some precautions whenever you work on your computer.
1. Unplug your computer before opening the computer.
2. Touch both of your hands to a safely grounded object or to a metal object, such as the
power supply case.
3. Hold the components by the edges and do not touch the IC chips, leads or circuitry.
4. Place components on a grounded antistatic pad or on the bag that came with the
component whenever the components are separated from the system. Never keep
them on a metallic table.1
TYPE OF JUMPER SETTINGS ON MOTHERBOARD (Socket 7)
Various types of setting available on a motherboard are explained below:
1. Flash Memory Boot Block Programming:
This is used to upgrade BIOS. Default value is write protect. This sets the operation mode of
the boot block area of the programmable flash memory to allow programming in the Boot
Block Write Enable position. This is required only if prompted by the Flash Memory Writer
Utility.
2. Real Time Clock (RTC) RAM:
The CMOS RAM holds the user preference or selections. The CMOS RAM is powered by the
onboard button cell battery. To clear the RTC data: (I) Turn off the computer and unplug the AC
power, (II) Move this jumper to “Clear CMOS”, (III) Move the jumper back to “Keep CMOS”,
(IV) Turn on your computer, (V) Hold down <Delete> during bootup and enter BIOS setup to
re-enter user preferences.
3. Voltage Regulator Output Selection:
These jumpers select the voltage supplied to the CPU. The onboard voltage regulators will
automatically detect and switch between single power plane and dual power plane CPUs. A
CPU is usually referred to by its Vcore voltage.
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4. CPU External (Bus) Frequency Selection:
These jumpers tell the clock generator what frequency to send to the CPU. These allow the
selection of the CPU’s external frequency (or bus block). The bus clock times the bus ratio
equals the CPU’s internal frequency (the CPU speed printed on IC).
5. CPU to Bus Frequency Ratio (BF0, BF1):
These jumpers set the frequency ratio between the internal frequency of the CPU and the
external frequency (called the bus clock) within the CPU. These must be set together with the
jumpers for CPU External (Bus) Frequency Selection. A typical case of frequency selection
can be as below:
Frequency Ratio Bus Frequency

233 MHz 3.5x 66 MHz
200 MHz 3.0x 66 MHz
166 MHz 2.5x 66 MHz
150 MHz 2.5x 60 MHz
133 MHz 2.0x 66 MHz
120 MHz 2.0x 60 MHz
100 MHz 1.5x 66 MHz
90 MHz 1.5x 60 MHz
INSTALLING MEMORY MODULES
Normally, the motherboard supports four 72-pin, 32-bit single inline memory modules (SIMMs)
of 4, 8, 16, 32 or 64 MB each, to form a memory size between 8 and 256 MB. SIMMs must be
installed in pairs so that each row contains 64 bits of the same size and type of chips. One
side of the SIMM module (with chips) takes up half a row on the motherboard. The SIMM can
be asymmetric or symmetric, Fast Page Mode (FPM) or Enhanced Data Out (EDO) memory.
Dual inline memory modules (DIMMs) can be used if SIMMs are not used. Two sockets are
available for 3.3-volt power level, unbuffered synchronous DRAMs (SDRAMs) or EDO DRAMs
of either 8, 16, 32, 64 or 128 MB each to form a memory size between 8 and 256 MB. One
side of the DIMM module (with chips) takes up one row on the motherboard.
NOTE: Set up memory speed through “Auto Configuration” in the BIOS Chips Setup of the
BIOS Software. If both 60ns and 70ns memory are used, set “Auto Configuration” to 70ns.
Memory modules with more than 24 chips may sometimes exceed the design specifications
of the memory subsystem and can be unstable.
WARNING: Do not install both SIMMs and DIMMs at the same time as this can burn the
memory modules. To mix SIMMs and DIMMs, use 5.0-volt-tolerant (signal level) memory chips.
PRACTICAL DETAILS OF SIMM MEMORY INSTALLATION
The SIMM memory modules fits in only one orientation, because of a plastic safety tab on one
end of the SIMM sockets which fits the notched end of the SIMM memory modules.
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1. Press the memory module firmly into place starting from about 45-degree angle and making
sure that all the contacts are aligned with the socket.
2. With your fingertips, the memory module into a vertical position so that it clicks into place.
The plastic guides go through the two mounting holes on one side, and the metal clips snap
on the other side.
To release the memory module, press both metal clips outward and rock the module out of the metal
clips.
DIMM MEMORY INSTALLATION
Use 3.3-volt unbuffered DIMMs, and insert the modules in specified sockets. The modules will fit in
only one orientation as shown because different numbers of pins are located between notches. The
notches in the DIMM modules identify the type and also prevent the wrong type of DIMM from
being inserted into the DIMM socket.
(56)
168-Pin DIMM Notch Key Definitions
Various clock signals are supported on motherboards. Check the specification of clock speed
/ access time before purchasing memory modules.
INSTALLATION OF MICROPROCESSOR
The motherboard provides a ZIF Socket 7 or ZIF Socket 5. The processor that comes with the
motherboard should have a fan attached to it to prevent overheating. If this is not the case,
then purchase and install a fan before the computer is turned on.
To install a processor, first turn off computer system and remove its cover. Open the ZIF
Socket by first pulling the lever sideways away from the socket then upward to a 90-degree
right angle. Insert the CPU with the correct orientation as described. White dot on CPU should
be placed on the blank spot on the socket. Use the notched corner of the CPU with the white
dot as your guide. The white dot should point toward the end of the lever. The CPU will fit in
only one orientation. Once the processor is completely inserted, close the socket’s lever.
INSTALLATION OF EXPANSION CARDS
First unplug your power supply before adding or removing expansion cards or other system
components, otherwise severe damage to both your motherboard and expansion cards may
occur.
EXPANSION CARDS INSTALLATION PROCEDURE
1. Read the documentation for your expansion card, if necessary, set any necessary
jumpers on your expansion card.
2. Remove your computer system’s cover.
3. Remove the bracket on the slot you intend to use.
4. Align carefully the card’s connectors and press firmly.
5. Secure the card on the slot with the screw you removed from bracket in step 3.
6. Replace back the computer system’s cover.
7. Setup the BIOS if necessary (such as “IRQ xx Used by ISA: Yes” in PCI Setup”)
8. Install the necessary software drivers for your expansion card.
ASSIGNING IRQS FOR EXPANSION CARDS
Some expansion cards use an IRQ (Interrupt Request) to operate. Generally an IRQ must be
exclusively assigned to one card use. In a standard design, 16 IRQs are available, but most of
them are already in use, leaving 6 free for expansion cards.
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TROUBLESHOOTING IRQ RELATED PROBLEMS
Both ISA and PCI expansion cards may require IRQs. IRQs in a system are available to cards
installed in the ISA expansion bus first, then any remaining IRQs are available to PCI cards.
Two types of ISA cards currently exist: the original (legacy) cards, and Plug and Play (PnP)
cards.
In Legacy (older version) ISA card designs, jumpers are manually set and then the card is
installed in any available slot on the ISA bus. Microsoft’s Diagnostic utility (MSD.EXE, located
in the \windows directory) can display map of available and used IRQs.
In Windows 95, the Device Manager (accessed from the System selection on the Control
Panel) can display the IRQ number being used by that device. Ensure that no two devices use
the same IRQ, or the computer will exerience problems when those two devices are in use at
the same time.
PnP CONFIGURATION
Plug and Play (PnP) allows automatic system configuration whenever a PnP-compliant card
is added to the system. For PnP cards, IRQs are assigned automatically from those available.
If in a system both legacy and PnP ISA cards are installed, then IRQs are assigned to PnP
cards from those not used by legacy cards.
An IRQ number is automatically assigned to PCI expansion cards after those used by legacy
and PnP ISA cards.
ASSIGNING DMA CHANNELS FOR ISA CARDS
Some ISA cards (both legacy and PnP) might also require a direct memory access (DMA)
channel. DMA assignments for the motherboard are handled in the same way as the IRQ
assignment process. Select a DMA channel in PCI and PnP configuration section of the BIOS
Setup utility.
Note: To avoid conflicts, reserve the necessary IRQs and DMAs for legacy (old) ISA cards. (In
the PnP and PCI setup section of the BIOS software, select “Yes” in “IRQxx Used by ISA” and
“DMAx used by ISA” for those IRQs and DMAs you wish to give.)
CONNECTION OF CABLES, WIRES AND POWER SUPPLY ON MOTHERBOARD
Connect ribbon cables so that the red stripe is on the Pin 1 side of the connector. The four
corners of the connectors are labeled on the motherboard. Pin 1 is the side closest to the
power connector on hard drives and floppy drives. IDE ribbon cable must be less than 18 in.
(46cm) long, with the second drive connector no more than 6 in. (15cm) from the first connector.
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1. Keyboard Connector (5-pin female)
This connector supports a standard IBM-compatible (or “101 enhanced”) keyboard.
2. Floppy drive connector (34-pin block)
This connector supports the standard floppy drive ribbon cable. After connecting the single
end to the board, connect the two plugs on the other end to the floppy drives. (Pin 5 is sometimes
removed to prevent inserting the cable in the wrong orientation when using ribbon cables with
pin 5 plugged).
3. Parallel Printer Connector (26-pin block)
This connector supports the parallel port ribbon cable and mounting bracket. Connect the
ribbon cable to this connection, and mount the bracket to the computer case on an open slot.
Enable the parallel port and choose the IRQ through Onboard Parallel Port in Chipset Features
of the BIOS software.
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4. Serial Port COM1 and COM2 Connectors (two 10-pin blocks)
These connectors support the provided serial port ribbon cables and mounting bracket. Connect
the ribbon cables to these connectors, and mount the bracket to the case on an open slot.
Enable the serial port and choose the IRQ through Onboard Serial Port in Chipset Features
of the BIOS software.
5. CPU Cooling Fan Connector (FAN)
The Fan connector supports a three-pin CPU cooling fan of 500 mA (6 watts) or less with a
minimum of 3,500 RPM. Depending on the fan manufacturer, the wiring and plug may be
different. The red wire should be positive and the black wire should be ground.
WARNING: These are not jumpers. Do not place jumper caps over these pins, as it will cause
heavy current to flow and the motherboard can be damaged.
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6. Primary / Secondary IDE connectors (two 40-pin blocks)
These IDE interface connectors support upto four IDE hard disk drives. Connect the single
end to the board, then connect the two plugs at the other end to your hard disk(s). For install-
ing two hard disks, the second drive to Slave mode. BIOS now supports SCSI device or IDE
CD-ROM bootup (see “HDD Sequence SCSI/IDE First” and “Boot Sequence” in the BIOS
Features Setup of the BIOS Software). (Pin 20 is removed to prevent inserting in the wrong
orientation when using ribbon cables with pin 20 plugged).
TIP: Two hard disks can be configured to be both Masters using one ribbon cable on the
primary IDE connector and another ribbon cable on the secondary IDE connector. One oper-
ating system can be installed on an IDE drive and another on a SCSI drive, then select the
boot disk through BIOS Features Setup.
7. IDE activity LED (IDE LED)
This connector supplies power to the LED on cabinet showing IDE activity. Read and write
activity by devices connected to the Primary or Secondary IDE connectors do cause the LED
to light up.
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8. USB, PS/2 Mouse (18-pin block)
The external connector set connects to the 18 pin block and is mounted to an open slot on
your computer’s rear side. The system will direct IRQ12 to the PS/2 mouse if one is detected.
If not detected, expansion cards can use IRQ12. Use “PS/2 Mouse Control” in BIOS Features
Setup and “USB Function” in PnP and PCI Setup of the BIOS SOFTWARE.
9. Message LED Lead (MSG LED)
This indicates whether a message has been received from a fax/modem. The LED will remain ON
when there is no signal and blink when there is data transfer or waiting in the inbox.
10. Keyboard Lock Switch Lead & System Power LED (KEYLOCK / PWR LED)
This is a 5-pin connector which connects to the case-mounted keyboard lock switch for locking the
keyboard and also used to connect the system power LED. The system power LED lights when the
system is powered on and blinks in sleep mode.
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11. Speaker Connector (SPEAKER)
This is a 4-pin connector that connects to the case-mounted speaker.
12. Reset Switch
This is a 2-pin connector which connects to the case mounted reset switch for rebooting the
computer, without having to turn off the power switch. This is a preferred method for booting to
prolong the life of system’s power supply.
13. AT Power Connector (12-Pin block)
This connector connects to a standard 5 volt SMPS. To connect the leads from the power
supply, ensure first that the power supply is not plugged. Most power supplies provide two
plugs, each containing six wires. Of these six wires, two are black. Orient the connectors so
that the black wires are together.
Using a slight angle, align the plastic guide pins on the lead to their receptacles on the con-
nector. Once aligned, press the lead onto the connector until the lead locks into place.
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14. ATX Power Supply Connector (20-pin block)
This connector connects to an ATX SMPS. The plug from the power supply will only insert in
one orientation because of the different hole sizes. Find the proper orientation and push down
firmly making sure than that the pins are aligned.
IMPORTANT: The ATX power supply should take at least 10mAmp load on the 5 Volt standby
lead (5VSB). Otherwise, a difficulty in powering on the system without this, will be there.
POWER CONNECTION PROCEDURES
1. After all jumpers and connections are done, close the system case cover.
2. Make sure that all switches are in the off position.
3. Connect the power supply cord into the power supply located on the back of your
system case.
4. Preferably connect the power cord into a power outlet that is equipped with a surge
protector.
5. You may then turn on your devices in the following order:
6. a. Monitor
b. System power. For ATX power supplies, you need to switch on the power supply
as well as press the ATX power switch on the front of the case.
7. During power-on, hold down the <Delete> key to enter BIOS setup.
POWERING OFF THE COMPUTER: First exit or shut down the operating system before
switching off the power switch. For ATX power supplies, press the ATX power switch after
exiting or shutting down the operating system. If using Windows 95, click Shut Down on the
Start menu and then click Shut down the computer? on the Shut down Windows dialog box.
The system will then give three quick beeps after about 30 seconds and power off after
windows shut down. NOTE: The message It’s now safe to turn off your computer will not be
shown in Windows 95 when shutting down with ATX power supplies.
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CHAPTER - 5
KEYBOARD AND MOUSE
GENERAL DESCRIPTION
The IBM PC keyboard was structured in 1980 by West Germany’s Deutsche Industries
Normenausschuss. This is abbreviated as DIN. The DIN specification specifies keyboard
height for angles between 0 and 10 degrees from horizontal plane. It also determines the
duration time of depression for the keys.
The keys of the keyboard have concave top surfaces. The IBM PC keyboard circuitry en-
hances key operation and permit keys to be redefined. This redefinition potential provides
increased programming flexibility. The keyboard connects to the rear of the system unit by
coiled cable usually six feet long.
101 key board generates all 128 characters in ASCII (the American Standard Code for
Information Interchange), as well as special symbol and graphic shapes. The keyboard can
provide a total of 256 characters, shapes, and symbols.
Right side of the keyboard has a numeric key pad. In 101 keys keyboard, there are 12
programmable keys which are mounted on the top side. These can be used to execute se-
lected programs or to initiate special routines (subprograms). The functions of these keys can
be programmed and thus the function of these keys (F1 to F12) vary with the type of software
package or language in use.
There are number of special keys available on the keyboard such as Caps lock, Number
lock, Scroll lock, Shift, Back space, Enter, Home Page down, Page up, End, Delete, Insert
Print Screen, Tab, Control and Alternate. In addition the keyboard has up, down, right and
left arrow keys.
PC KEYBOARD INTERFACE
The keyboard communicates with the CPU through 5 core shielded cable. The scan code is
generated by the keyboard and sent to the computer via a 5 Pin DIN connector. Scan code
is generated by Microcontroller IC (usually 8049) present inside the keyboard. This scan code
is sent to microcontroller IC on the motherboard (usually 8042), this IC translates the scan
code to ASCII code. This ASCII code is further sent to main microprocessor on the motherboard
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for processing.
Signal details are given in table below.
Signal Name 5-Pin DIN 6-Pin Mini-DIN

Data 2 1
Ground 4 3
+5V 5 4
Clock 1 5
Not Connected - 2
Not Connected - 6
Not Connected 3 -
The connector plug at the keyboard side and socket at the motherboard side, details are
shown in following figure.
Fig.:Keyboard, Mouse Connector Details
KEYBOARD BLOCK DIAGRAM
The 87 keys keyboard used an Intel 8048 single chip microcontroller. The 8048 is a 8-bit
parallel single-chip computer that contains a 1K by 8-bit program ROM and a 64 word by 8-bit
RAM data memory. It also has twenty-seven I/O lines including two bi-directional ports, an 8-
bit data bus, an 8-bit timer/counter, on-board oscillator and clock circuits.
The 101 keys keyboard uses an INTEL 8049 single chip micro controller. This is also a 8 bit
parallel single chip microcontroller and contains a 2K by 8 bit ROM. It has 128 word by 8 bit
RAM data memory. It has twenty seven I/O lines including two bi-directional ports, an 8 bit
data bus, an 8 bit timer/counter, and on-board oscillator and clock circuits.
The 101 keys on the keyboard are connected to a two dimensional matrix with 8 Rows by 13
Columns. Figure below illustrates the block diagram of a keyboard which uses the 8049 micro
controller.
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8 Rows by 13 Column Keyboard Matrix Keyboard

Connector
Row
Head +5V
GND
DB0
DATA
Scan BUS
Code
8042
8049 Clock
NC
DB7
P0 P7
Y0 Y3 Y7 Mother
P0 P4
(74LS138) Board
Decoder
COULMN LINE
SELECTION
P5 P7
Block Diagram of IBM Compatible 101 Keyboard interface with IBM PC-AT motherboard
SCAN CODE OPERATION
When the key is depressed, the key switch closes the crossover point (intersection of a row
and column) of an X row and a Y column on the matrix. The signal thus generated is read by
the micro controller and converted into a special code called “Scan Code”.
The 8048/8049 scans the keyboard matrix, every 3 to 5 milliseconds. First one column is
scanned and the status of the key switches in each row in that column are read and stored in
memory. If a key switch was closed the crossover point will be at a zero voltage. The scanning
continues until all 13 columns have been read. Each scan code is stored in a buffer with in the
micro-controller. Thus the buffer reflects the status of the entire keyboard.
The scan continues after all fourteen columns have been read once. Next the array is searched
for the existence of switch condition which is depressed together. If two closed switches are
found in the same column and one of the two rows containing the closed switch then the
unwanted switch condition occurs. Generally these switch conditions are evaluated by the
microcontroller (8049) and ignored. The scan process is performed in 3 to 5 milliseconds and
there is an interval of atleast 20 to 50 milliseconds between key entries. So, the matrix is
scanned at least once for every keystroke and incorrect entry is eliminated.
Each key action generates a unique scan code. By depressing the Shift, Ctrl, Alt keys and
one characters , microcontroller generates the special functions and uppercase characters.
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The scan code is generated by microcontroller (8048, 8049) by depressing a key and releasing
the key. Depressing the key causes the micro controller to generate a hex code which is
different from the Hex code that is generated when the key is released. Once this code has
been sent another different scan code is generated to indicate no key depression.
When the key is held down for more than half a second, the microcontroller generates the
appropriate scan code 10 times each second.
KEYBOARD TO MOTHERBOARD INTERFACE
The 8-Rows by 13-columns matrix circuit of the 101 keyboard is shown in figure. The main IC
in the circuit is 8049 microcontroller. 8049 is a single component 8-bit microcontroller.
Block Diagram of 8049
The pin no.1 output (TO) is directly connected with the system board data pin 2. This is serial
data coming out of the microcontroller.
A 6 MHz crystal oscillator is connected across the pin 2 and 3 to generate the clock frequency
for IC chip operation. This clock signal is on pin 1 (T0) used to clock the serial scan data
coming out pin 27 of 8049 of the keyboard circuit board on to the system board.
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Eight pins of 8049 (DB0-DB7) are connected to rows of keyboard matrix. Microcontroller has
three I/O ports each of eight bits. Of the 13 columns in the keyboard matrix, five columns are
connected to one of the three ports available on microcontroller. Rest of the eight columns are
connected to output lines of a decoder (74138). The input lines of this decoder are connected
to same I/O ports whose 3 pins were left. Usually, output pins (of 8049 IC) 36, 37 and 38 form
three binary inputs to keyboard decoder LS138. These three inputs enter 74LS138 pins 1,2
and 3 where they are decoded to activate a particular output (Y0 through Y7) that connect to
the keyboard matrix. The condition of the decoded line is returned to 8049 IC pin 35 via
74LS138 IC pin 4.
When a key is pressed, this condition can be recognized by reading the data bus lines (DB0
TO DB7) and scanning the ports I/O lines (P0-P7) to determine which intersection point is
active. When a key closure is detected, the event timer program in microcontroller 8049 waits
a few milliseconds to let the key bounce settle down and the key condition becomes stable
before reading the P0 through P7 inputs. Then 8049 stores the fact that a key closure has
occurred in its internal RAM memory as an 8-bit scan code. If a key is held down longer than
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one half second, 8049 causes the same scan code to be generated ten times each second.
Internal RAM in microcontroller IC enables to buffer up to 32 key scan codes permitting
continuous typing ahead for the operator.
MOUSE
The movement of the cursor on the screen is controlled by the mouse. The principle of opera-
tion is shown in fig. 5.5. The mouse has a mechanical ball beneath its body. The ball usually
rests against two rollers, one for translating the X-axis movement and the other for the Y-axis
movement. These rollers are usually connected to small disc with shutters, these shutters
alternatively allow and block the passage of light. Small optical sensors detect movement of
the wheels by catching an internal infrared light blink ON and Off as the shutter wheel rotates
and “chops” the light. These blinks are then translated into movement along the various axes.
This type of arrangement is called an opto-mechanical mechanism. This type of mouse are
very popular now-a-days. Witty-mouse, Dexxa mouse, Logitech mouse, MS mouse all follow
the same principle, the only difference being, their installation driver softwares are different.
CHOPPER WHEEL CHOPPER WHEEL

FOR Y AXIS FOR X AXIS
RUBBER
BALL
Y OUTPUT X OUTPUT
ROLLER FOR ROLLER FOR

Y AXIS X AXIS
LIGHT SOURCES
LIGHT DETECTORS/
OPTICAL SENSORS
Fig.: Principle of operation of (Opto-mechanical operation) mouse
OPTICAL MOUSE
The other type of mouse is Optical Mouse. In this type of mouse, separate beam of infrared
light from two LED’s placed perpendicularly to each other is sent out and it gets reflected back
from the mouse pad having matrix, by which the position of the cursor is decided. There is
only one point at which the light is received back and at this point a light detector is placed,
this point is lying on the axis of the two light sources. Thus the position of the cursor is related
to the position of the mouse on the mouse pad. This type of mouse works with special matrix
mouse pad only. Optical mouse can have the same driver as the opto-mechanical mouse. In
optical mouse as there is no moving ball hence its breakdown is relatively less as compared
to the ordinary mouse.
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MOUSE TROUBLESHOOTING
Problems related to mouse are classified as hardware related and software related. Hardware
related problems are mostly solved by maintenance of the mouse.
Optomechanical Mouse Maintenance
These mouses require occassional cleaning of the moving ball. Cleaning of the sensors.
Wheels and bars cleaning.
For cleaning use either sopy water or mild solvent such as alcohol.
Optical Mouse
Ocassional cleaning of the sensors needs to be done.
Interrupt Conflict
With a mouse, an interrupt is used whenever the mouse has information to send to the mouse
driver. If a same interrupt is used for mouse and some other device or card then an interrupt
conflict occurs. In this case there is possibility that mouse will not work properly or it may not
work at all.
Software Problems
Driver softwares need to be loaded for proper functioning of the mouse. The external drivers
are required to loaded for DOS applications. Typically a driver software is called as Mouse.sys,
this has to be mentioned in CONFIG.SYS file needed for configuring the system at the time of
booting. The proper command that has to be given if the Mouse sys file is present in DOS
directory is
DEVICE=\DOS\MOUSE.SYS
The actual syntax of the command may vary, depending on whether the device driver is to be
loaded into Upper Memory Block (UMB) and where the driver ifile is present on your disk. We
can use command DEVICEHIGH, LOADHIGH or LH commands.
Another version is a MOUSE.COM file which gets loaded in autoexec.bat file. In case of
Windows 95 or Win 98, the setting and menu then control panel, then system then device
manager gives the information of IRQ conflicts regarding any device including mouse. This
should be checked if any mouse problem is there. If IRQ conflict is there, reassign the IRQ the
probelm will be solved.
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CHAPTER - 6
FLOPPY DISK DRIVE
INTRODUCTION
In order to test or service a Floppy Disk Drive one must have a through understanding of the
drive and media parameters that effect reliable operation. The system unit has a space capa-
bility and power connection for one or two floppy diskette drives. A drive can be double sided
with 40/80 tracks or more for each side. The drive is fully self contained, and consist of a
spindle drive system, a head positioning system and a read/write erase system.
PRINCIPLE OF OPERATION OF FLOPPY DISK DRIVES
A FDD works on the same principle as that of any other magnetic media recording like a
cassette recording like a cassette recorder, magnetic tape, etc. It consists of a R/W gap and
a R/W coil along with erase coil/erase gap. When writing, a current (of the order of 8 mA) is
passed through the R/W coil and in case of reading the coil picks up voltage (of the order of 1
to 3 mV). Since there are bandwidth limitations for any system involving an inductance, mag-
netic media, etc. direct recording of digital waveform onto the media and pick up is not pos-
sible. Hence a digital waveform is converted into a sine wave for recording and after pickup it
is converted back to digital form.
Side 0 Head
Mylar Base
Current
Flux
Oxide Layer R/W

Head
Driver
Oxide Layer IC
Flux
Current
Floppy Diskette
Media
(Coated on mylar base)
Fig.: Floppy Drive Recording Principle
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Serial data from the controller is passed through a divide counter, differentiated and recorded
in the form of sine wave impulses on the media. The sinusoidal waveform in turn is picked up,
amplified differentiated, passed through a zero cross detector and thus the serial data is
generated back and output is sent to the FDD controller.
VARIOUS SUB ASSEMBLIES
The FDD consists of following main subassemblies:

READ/WRITE head, Drive motor, Stepper motor, Head carriage Assembly, Sensor, Write
protect sensor, Index sensor, TR 00 sensor, Media sensor, In use LED, Power connector
READ/ WRITE HEAD
> The read/write head contains three coils
> When writing, the head erases the outer edges of the track to ensure data recorded
will not exceed the 0.012 inch track width.
> The read/write head is ceramic.
The read/write head contains three coils. Two read/write coils are wounded on a single core,
center tapped, and one erase coil is wound on a yoke the spans the track being written. The
head assembly showing head construction is as shown in following figure.
Head Assembly
Recording Head
Direction
of
Head
travel
On the
track
Tunnel Erase Heads
Fig.: Typical Floppy Drive Head Construction
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During a write operation, the erase coil is energized. This causes the outer edges of the track
to be trim erased. Therefore, as the track is being recorded, it will not exceed the 0.012 inch
track width. The both sideways erasing allows for minor deviations in read/write head current.
Therefore, as one-track is recorded, it will not splash over to adjacent tracks.
Each bit written will be directed to alternate read/write coils. This results in a change in the
direction of current flow through the read/write head. This produces a change in the flux
pattern for each bit. The current through either of the read/write coils will cause the old data to
be erased , as new data is recorded.
During a read operation, as the direction of flux changes on the diskette surface passing
under the gap, current will be induced into one of the windings of the read/write head. This
results in a voltage output pulse. When the next data bit passes under the gap, another flux
change in the recording surface takes place. This causes current to be induced in the other
coil producing another voltage output pulse.
DRIVE MOTOR
The drive motor which is used in FDD as spindle motor is servo controlled DC motor. The
speed of the motor is 300rpm or 360rpm with the tolerance of 1%. The function of the Drive
Motor is to keep the Floppy diskette revolving at a constant fixed speed when any read or
write operation is being done. The power supply requirement of this motor is + 12V. The drive
has dual speed i.e. 300 rpm and 360rpm and has a jumper on its interface card for selecting
the proper speed.
STEPPER MOTOR
While doing any read or write operation the floppy diskette is running at a constant speed. We
have to move the head for writing at some particular track. For this purpose we use a 4-phase
stepper motor. This motor is also known as head carriage motor. The Floppy drive controller is
sending signal ‘Direction’, this signal tells the motor in which direction i.e. towards the hub
centre or outwards, the head will move. The ‘Step’ signal tell the stepper motor to give number
of steps rotation so that the head reaches the desired track for doing a read or write operation.
The stepper motor generally used is having 1.8 revolution per step i.e. it takes 200 steps for
making a revolution.
HEAD CARRIAGE ASSEMBLY
In FDD a stepper motor is used for driving the head for doing any operation i.e. read/write/
erase. The spindle of the stepper motor is having a circular motion while for head movement
we need linear motion, for this purpose generally a band assembly converts the circular mo-
tion to linear motion. The stepper motor and band assembly uses one-step rotation to cause
a one track linear movement of the magnetic head.
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SENSORS
In FDD four sensors are mainly used. Different sensor used in Drive are namely.
> Write Protect Sensor

> Index Sensor
> TR 00 Sensor
> Media Sensor
Generally Opto-couplers are used as sensor. In these sensors one LED and one photo tran-
sistor is used. Some voltage is applied across the LED and it emits light. If the light is incident
or coming to the base of photo transistor it will start conducting and output voltage (Vout) will
be low level and if something comes in between LED & photo transistor then transistor won’t
conduct, thus output voltage will be high.
Write Protect Sensor
In Floppy diskette there is one notch for write protect. The function of this notch is reverse in 3”
drive and 5-1/4” drive. If we cover this notch with some sticker then the sticker will block the
way of the light incident on photo transistor and the output of the sensor will be low. If this is
done in 5-1/4” drive then we can not do any write operation on the drive. In case of 3” drive the
notch should be covered or closed for write operation.
Index Sensor
The spindle motor is rotating the floppy diskette at a constant speed. There is a sensor near
the hub of spindle that indicates that the head has completed one rotation. There is one index
hole in the floppy diskette through which the light emitted by the opto-coupler passes. An
opto coupler is used as sensor. Whenever the sensor goes low from high with the help of this
index hole, the floppy drive controller IC will issue a index pulse.
TR 00 Sensor
When the floppy drive is given a reset signal or the power is switched ON, the head will move
away from the centre of drive and it will go to the outer-most track of the diskette. The outer
most track which is used for read/write operation is TR00 and the inner most used track is
either track 39 or track 79 depending upon the type of drive.
Media Sensor
This sensor is present in a few makes of drives. Generally it is used in high capacity drive
circuitry. Whenever we insert any diskette in the drive the media sensor senses the diskette.
Thus this sensor also tells the drive adapter that whether diskette has been changed or not.
Whenever we insert or change a diskette the drive motor will start running and head will come
to track 00 after some time the motor will stop.
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IN USE LED
Whenever a floppy drive is selected or some operation is being done then this “In Use LED”
starts glowing. This LED is fixed on the front side of the FDD.
POWER CONNECTOR
The power supply connector on the FDD has 4 connection which are meant for +12V, +5V
and their respective returns (ground).
THEORY OF OPERATION
Drive Select and Head Load
Since the drive may be one of several drives, sharing the same interface signals in a user’s
system, a means is provided to address the selected drive, allowing FDD sole use of the
interface signals while selected. Four DRIVE SELECT lines, numbered 1 through 4, are avail-
able to address up to four drives in a system. Any one of the four lines may be connected
through a jumper (DS1, DS2, DS3, OR DS4) to the input of a DRIVE SELECT gate. A logic
low level signal on the jumper line will select the drive. Once selected, the drive can accept
other input signals and issue output signals. All outputs and inputs are considered active low.
All outputs and inputs on the last drive along a signal cable( flat interface cable) must be
terminated to +5V through 150 ohm resistor. Normally this is done by a resistance pack IC or
a integrated resistance network. In newer drives instead of passive resistors as terminators,
active terminators are used. Jumpers are available for this purpose.
In order to allow reading and writing, the read/write head must be loaded against the surface
of the diskette. The door of the FDD must be closed and a solenoid is activated to enable a
load pad to press the diskette against the head.
Activity light on the door of the drives is activated by an open collector transistor driver. This
driver turns off to allow current to flow from +5V through 75 ohm and the LED to ground. The
activity light will turn on when the drive is selected.
Head Positioning
A stepper motor and head screws, position the read/write head. The head is mounted in a
carriage which moves readily along the diskette. The stepper motor rotates the Axle clockwise
or counterclockwise in small increments. On the Axle is connected a steel band . The steel
band winds or unwinds on the motor axel. To the other end of this steel band is connected the
head carriage assembly. The winding or unwinding of the steel band steps the carriage in
forward or reverse direction track by track. Tracks are numbered 00 through 39 or 79, track 00
being the outermost track. Seeking the read/write head from one track to another is accom-
plish by selecting the desired direction with the DIRECTION line (low to step in, high to step
out), loading the head and then pulsing the STEP line. TR00 sensor prevents the head from
stepping out past track 00.
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After power is turned on, the FDC & drive electronics will recalibrate the drive by stepping out
until the head reaches track 00. Indicated by the TRACK 00, detector (a phototransistor).
When the head is near track 00, the phototransistor turns off, and the voltage falls to ground.
A voltage comparator acts as a Schmitt trigger inverter, squaring up the threshold voltage.
TRACK 00 output will be active only at track 00.
A second voltage comparator acts merely as an inverter to provide the correct polarity for the
drive logic chip input. TRACK 00 output from the drive logic chip is only true when the track 00
detector is active and phase 1 of the stepper is selected internal to the chip. This allows the
track 00 flag to be aligned so that TRACK 00 detector is active at both tracks 00 and 01
providing some mechanical tolerance. However, the
Index and Sector
To provide the user’s system a time mark for controlling reading and writing an index pulse is
issued by the drive once per revolution of the diskette. An index LED and index detector
phototransistor pair are mounted so that light can shine from the LED through a window in the
diskette jacket to the phototransistor. Eachtime a small hold punched in the diskette rotates
round to left light through, the phototransistor. turns on and the +INDEX detector voltage
rises. Since the transition is slow, a voltage comparator connected as a Schmidt trigger in-
verter is used to square up the signal and provide hysteresis. Voltage thresholds are the same
as for the track 00 detector.
The DISK CHANGE output can be connected to the signal interface to alert the user’s system
to the possibility that the diskette has been removed since the drive was last selected. This
output becomes true after the drive is deselected if the door opens.
Read and Write Operations
The write chip forces write current through the read/write coil through either one side of the
coil or the other. As each WRITE DATA pulse is received, the current is switched to the other
side of the coil. The amount of the current is set by a resistor at the current reference input of
the chip (which is by passed by a capacitor to ground to decouble WRITE DATA from write
current), and damping (overshoot) is set by two resistors across the entire coil. Simultaneously,
the erase output will be grounded, allowing 40 mA to flow from the centre taip through the
erase coil to ground. A diode is placed across the erase coil to suppress back emf when the
current is switched off.
Writing will occur whenever WRITE GATE is low, the drive is selected, and the diskette is not
write protected. The write protected LED and write protect detector (phototransistor) sense
whether a slot is covered along with edge of the diskette jacket. If it is covered.
a. The phototransistor turns on.

b. + WRITE PROTECT detector high.
c. The signal is inverted by Schmidt-trigger gate in the drive logic chip.
d. WRITE PROTECT is true on the interface and writing can not occur.
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INTERFACE
The drive contains a 34 pin edge connector, which is a standard from Suggart and accepted
universally.
DIFFERENT TYPES OF PROBLEMS
While working with a Floppy Disk Drive the user face a number of problems which may be any
of the following.
(i) Drive not ready

(ii) TR00 unrecognised
(iii) Sector not found
(iv) Seek Error
(v) Boot Failure
(vi) Read Error
(vii) Write Error
(viii) Files not getting saved
& so on........
The cause may be any of the followings:
(i) Noise
(ii) Drive Motor Rotation
(iii) Drive Head Carriage Assembly
(iv) Damaged Disk
(v) Dirty Collate
(vi) Power Supply Connection Reversed
(vii) Dirty Interface Connector
(viii) Head Carriage Spring
(ix) TR00
(x) Assembly Improper
(xi) Analog Interface Card
(xii) Steel Belt Damage
(xiii) Misalignment
(xiv) Terminator
If the problem is with the drive and not with the media i.e. diskette then first try to clean the
different edge connector and power supply connector with isopropyl alcohol. Head can also
be cleaned and for problem like TR00 unrecognizable, write error or in compatibility in
reading and writing with other drive you have to check the various sensor and alignment.
ALIGNMENT
For checking that whether the drive is properly aligned or not in field you may do some write
operation on the drive and read it on some other drive & vice versa. If this is working all right
then the alignment is with in permissible limit.
(79)
For checking the FDD in repair centre we need equipments called Floppy Drive Exerciser,
C.R.O, and allignment diskette. With some advanced exerciser we don’t require any C.R.O.
In alignment diskette some data is written into some fixed tracks so that while checking the
floppy disk drive, we read the data from the particular track and compare it.
The floppy drive exerciser is an equipment which can completely test the FDD. It has got
various function such as :
(i) Stepping the head to any track

(ii) Controlling the drive motor
(iii) Write data
(iv) Read data
(v) Check TR00
(vi) Check WP sensor
(vii) Check index sensor
In brief it can check the entire electronic circuitry of the FDD.
DO’s AND DON’Ts WITH FDD
1. Do not keep diskette in the open. keep it safe in the envelope when not in use.
2. Refrain from smoking near PC.
3. keep diskette away from dirty environment.
4. Handle FDDs carefully while insertion in PC. Mishandling leads to damages/mal-
functioning
5. Keeping diskette clean. Ensure collect & head are clean.
6. Collect should be cleaned with Johnson bud and isopropyl to prevent misclamping.
7. Head should be cleaned periodically once in 2 weeks with diskette to prevent
accumulation of dust. Frequency of cleaning should be more for dirty environment.
8. Do not put pressure on diskette while closing door lever. Release finger from diskette
after click sound appears. Close door lever after releasing finger from diskette.
(80)
CHAPTER - 7
HARD DISK DRIVE
CONSTRUCTION
The physical construction and components that make up popular hard disk drives are
discussed below.
Drive Components
A hard disk drive is made up of several physical components. All drives have certain compo-
nents same. Some differences do exist in the actual implementations on these components,
as well as in the quality of materials used. All hard disk drives have the following components:
* Disk platters
* Read/Write head
* Head actuator
* Spindle motor
* Disk Drive Electronics
* Configuration items
* Cables & Connector
The platters, spindle motor, R/W heads, and head actuator mechanisms usually are con-
tained in a sealed chamber called the Head Disk Assembly (HDA). The HDA usually is treated
as a single component because it is rarely opened. It should be opened only in a dust free
“clean-room”. The other parts, which are external to the drive, can be disassembled from the
drive itself, these parts include the Disk drive electronics logic board, front panel (bezel),
cables and any other configuration or mounting hardware.
Disk Platters
Hard disks have more than two platters or disk surfaces that usually are found in two diam-
eters, much like floppy drives. The most common types of disks are those with 3.5 inch
platters. Earlier it used to be 5.25 inch platters. Drives with 8-inch or even 14-inch platters
are available but these expensive high-capacity drives typically have not been associated
with PC systems. Also, drive formats that are physically smaller than 3.5 inch have been
developed, but these platters are popular with Laptop and Notebook computers.
(81)
The platters are coated with a magnetic substance or media, which is actually responsible
for storing information. Two popular media are used for hard disk platters: oxide media and
thin film media.
Most earlier drives used oxide media on the drive platters. Oxide media was popular because
it was inexpensive and easy to apply. Oxide media has been used since 1955.
Thin film media is rightly named because the thickness of the media is much less than what
can be achieved by the normal coating method. Thin film media also is known as “platted” or
“sputtered” media. These names reflect the processes of getting thin film of media on the
platters.
Sputtering is the name of a special procedure in which magnetic media is deposited on the
platters in Vacuum. Thin film sputtered disks are created by a process of first coating the
aluminum platters with a layer of nickel phosphorus and then applying the cobalt alloy
magnetic material by a continuous Vacuum deposition process called sputtering.
The surfaces of sputtered platters contain magnetic layers as thin as 2 millionths of an inch.
The surface thus is very smooth, thereby allowing the head to fly close to the disk surface.
With the head closer, the density of the magnetic field can be increased to provide greater
storage capacity. The head can fly over the surface as closely as 6 to 8 millionths of an inch.
The increased intensity of the magnetic field provides the higher signal amplitudes needed for
good signal-to-noise performance.
Read/Write Heads
A hard disk drive usually has one read/write head for each platter side, which gives a usual
range of 2 to 16 heads for any drives. The multiple heads are all mounted together on one
vertical rod having many horizontal arms connected to it. Each horizontal rod has two heads
mounted one on upper side and another on lower side. Thus all heads move in unison across
the platters.
The mechanical aspects of the heads are quite simple. Each head is on an arm that is
spring-loaded to force the heads close to the platter.
Various types of heads are used in the hard disk drive:
* Composite ferrite heads

* Thin Film heads
* Magneto-Resistive heads
The composite ferrite heads are the traditional type of magnetic head design. This type of
head uses an iron oxide core with electromagnetic coils wrapping it.
The Thin Film (TF) heads actually are a specially produced semiconductor chip. These
heads are really a complex circuit. They are produced by the same procedure as any semi-
conductor chip.
(82)
Thin Film heads produce a sharp well defined magnetic pulse that allows extremely high
densities to be written. TF heads are and small and thus can float very close to platter. The
reduced distance between platter and head, enables a much stronger signal to be picked up
and transmitted. This improves accuracy.
Magneto-Resistive Heads are a superior head design and currently popular in drives with 1
GB or higher storage capacities.
Principle of Working of MR Head : Resistance of a conductor changes slightly when an exter-

nal magnetic field is present. MR head senses the flux reversal and changes resistance. A
small current is made to flow through the heads, and the change in resistance is measured by
this sense current.
Head Actuators
Head actuator is the mechanical system that moves the heads across the disk and positions
them accurately above the desired cylinder.
Various types of head actuator assemblies are essentially categorized as :
* Stepper Motor Actuator

* Voice Coil Actuator
Stepper Motor : Stepper Motor is an electrical motor that moves in steps with electrical pulses.
Stepper motor have fixed step positions and cannot position between step positions.
Voice Coil Actuator : It works on electromagnetic force. Its construction is similar to that of a
audio speaker. Hence its name is voice coil actuator.
An audio speaker uses a stationery magnet surrounded by a voice coil connected to the
speaker’s paper cone. Energizing this coil causes the coil to move relative to the stationery
magnet on speaker. This process produces sound from the speaker cone.
In a HDD voice coil mechanism, the electromagnetic coil is attached to the end of the R/W
heads arm and placed near a stationery magnet. No contact is made between the coil and the
magnet. The coil moves by pure magnetic force.
As the electromagnetic coils are energized, they attract or repulse the stationery magnet and
move the R/W heads.
A voice coil actuator has no steps or fixed step positions, and hence can slide the heads in
and out smoothly to any desired position.
Voice coil actuator use “Servo Mechanism” as guidance system for the actuator. It tells the
actuator where the heads are in relation to the cylinders and thus help to place the heads
precisely to desired positions. This positioning is called a “closed loop or feedback loop, servo
controlled mechanism”.
(83)
Closed loop indicates that the servo signal is sent to the head positioning electronics in a
closed-loop system. The feedback from this information is used to position the head accu-
rately on the desired cylinder.
A voice coil actuator with servo control is immune to temperature changes where as stepper
motor actuator gets affected.
Main types of Voice Coil positioning mechanism are:
* Linear Voice Coil Actuator

* Rotary Voice Coil Actuator
A linear actuator moves the head in and out over the platters in a straight line. The coil moves
in and out on a track surrounded by stationery magnets.
Disadvantages of this design are that the actuators are heavy.
A rotary actuator also uses stationary magnets and a movable coil. But in this case the coil is
attached to the end of the actuator arm. As the coil moves relative to the fixed magnet, it
swings the head arm (arm on which the heads are mounted) in and out over the platters.
Almost all voice coil drives, popular today use rotary actuator systems.
Servo Control Mechanisms
Its basic task is that they enable the positioning mechanism to adjust continuously so that R/
W head is precisely placed above a given cylinder on the drive Platter.
Following Servo Control Mechanism are currently in use :

* Embedded Servo (Sector Servo)
* Dedicated Servo
Main difference between these servo controls designs is, where the gray code information is
written on the drive. A special information is only written on the drive when it is manufactured.
This information is in the form of gray code. It is written by a servo writer.
A gray code is a binary system notational code, in which two numbers are represented by a
code that differs in only one bit place or column position.
A servo writer is a machine which mechanically moves the heads to a given reference posi-
tion and then writes the servo information for that position.
Above system makes it easy for the head to read the information and quickly determine its
precise position.
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* Wedge Servo : In this design the servo information is written one time per track. The
servo information is present in each cylinder, immediately preceding the index mark.
The index mark indicates the beginning of each track.
* Embedded Servo : In this design the servo information is written before the start of
each sector. This enables the positioning circuits to receive feed back many times in a
single revolution, making the head positioning much faster and more precise.
* Dedicated Servo : In this design the servo information is written continuously through-
out the entire track. Dedicated servo uses one side of 1st platter exclusively for servo
positioning information. On this platter is recorded a special set of gray code data that
indicates proper track positions.
When the drive is given command to move the heads to a specific cylinder, the disk drive’s
internal electronics use the signal received by the servo head to determine the position of the
heads in respect to the cylinders.
Dedicated servo method is the best as, no additional time is needed to access the servo
positioning information, the information is continuously available at each point. The head on
the 1st platter is always reading and giving positioning information.
In case of wedge of wedge, the positioning is available once at the beginning of the track and
in case of sector servo the positioning information is available at the beginning of each sector.
This is better than wedge method because, there will be several sector on each track so the
servo positioning information is available nearby thus less time is required to access this
information.
When the HDD is low level formatted, Servo positioning information is not erased.
Spindle Motor
The motor that spins the disk drive platter is Spindle Motor. The platters spin around the
spindle that is connected to the spindle motor. The spindle is directly connected to the
Configuration Items
A couple of items must be set to configure a hard disk drive for installation in a particular
system. These configuration items usually is on the bottom side of the drive on the drive
electronics card.
The items that must be sent or configured are similar to those on a floppy drive and perform
the function:
* The drive-select jumper
* The termination resistor
(85)
Drive-Select Jumpers
The drive-select jumper select the “channel” to which the drive is supposed to respond. The
drive controller (either add on card or motherboard) sends control signals on various chan-
nels-one for each drive. We can install a maximum of two HDDs with an Add On Adapter . In
case of enhanced IDE drive controller on a 80486DX motherboard or higher a maximum of
four HDDs can be installed.
In case of two drives the jumper selection on HDDs has to be for:

* Master HDD
* Slave HDD
In case of four drives the jumper selection on HDDs has to be for:

* Primary Master HDD
* Primary Slave HDD
* Secondary Master HDD
* Secondary Slave HDD
In this case the Mother-board has two IDE controllers, one Primary IDE controller and an-
other a Secondary IDE controller. Each controller supports a maximum of two drives as mas-
ter HDD and slave HDD.
In case of older interface ST506, HDD has a control cable in the systems which twists the
drive-select and motor-enable lines to switch the channels for the last drive on the cable. This
procedure is done so that all drives installed in such a system have the same jumper-or
drive-select settings. This makes the installation of a hard disk easier. Both drives con-
nected to such a cable appear to have the same drive-select setting.
The other two cables are smaller 20-pins data cables: one is available for each drive and
is plugged into a single connector for each on the controller. These data cables are not
twisted and are not daisy chained.
In case of IDE interface there is only one cable and this does not have any twist. The cable is
a flat cable that connects to all the drives (Daisy chained). It is jumpers on the HDDs that
distinguish the HDDs as Primary master or slave / Secondary master or slave.
In case of IDE HDD there is no standard jumper selection. Each model has a different type of
jumpers selection and hence installation manual for the HDD needs to be referred.
Terminating Resistors
A hard disk always contains a terminating resistor when manufactured. You must ensure that
the terminator is removed from any drive that is not at the end of the control cable. The
drive at the end of the control cable must have the terminator installed.
(86)
Cables And Connectors
Standard drive interface ST-506/412 or ESDI interfaces always have four connectors:
* Interface control connector

* Interface data connector
* Power connector
* Ground connector
Interface connectors are most important as they carry the drive’s instructions and also carry
data to and form the drive.
TYPES OF HARD DISKS
Differences in HDD exists in data storage capacity, physical size (or from factors), interfaces,
quality, and price.
Interfaces
Several different electrical interfaces are available for hard disk drives.
* ST-506/412
* ESDI
* SCSI
* IDE
Two interfaces, SCSI interface & IDE interface are popular because of their high data transfer
rate and being cheap.
OPERATION OF HDD
Functional Block Diagram
Figure below shows the typical functional block diagram of an intelligent disk-drive system.
(87)
Read/Write
Channel Circuit
(Head Pre-amp, ENDEC, Data Sync.)
Disk data
Controller
Spindle Stepper/ Buffer &
Motor Voice Coil Memory Bus
Interface
Motor Speed & Head Position/

Servo control circuit
System or
Micro-Controller I/O
Fig.: Intelligent Disk Drive block diagram
The path from head-pre-amp to ENDEC (Encoder/Decoder) is commonly called the “read/
write channel”. The basic function of the R/W channel is to communicate data to and from
the disk with instructions from the disk data controller. The R/W channel contains a head-
pre-amp, a pulse detector, a data separator and an ENDEC.
The head reads (or writes) the data serially from (or onto) the HDD platter. The data from the
motherboard (CPU) is received in parallel format at the HDD interfaces, so there is a shift
register (Parallel In Serial Out register) to convert the data from parallel to serial format.
The disk data controller (DDC) interfaces with the microprocessor, memory and main
system bus. The primary function of the DDC is to identify the selected sector on the disk
and then transfer that sector’s data to and from memory.
The microprocessor controls the disk data controller to perform various disk operations. With
an intelligent disk-drive system, the microprocessor is also used to interface with a servo
motor controller, RAMs, ROMs and a spindle motor controller. The position of the disk head
is calibrated using a closed-loop servo system.
Servo patterns are made by servo writer either in the form of dedicated servo (whole disk)
or sector servo (servo pattern between data sectors). The servo demodulator uses servo
patterns to determine the exact position of the head. If the head is off track, the servo
control chip will give an off-track error to reposition the head.
(88)
Reading Data from the Disk
The data is stored in concentric circles (tracks or cylinders) , on the platter of HDD in the
form of magnetic fields. When the head passes over a magnetized region where there is a
change in state (flux reversal), there is a rapid change in the field, resulting in voltage
pulses. The R/W pre-amplifier then amplifies these voltage pulses which are of the order
(amplitude) of micro volts to the order of milli Volts.
To initiate the read operation as shown in fig. 6.2, a command is sent to the disk drive where
the head moves to the specified track on the disk. Finally, the desired sector is identified by
the head ID segment and the various fields are checked, depending on the formatting rules.
Flux reversals are then recorded by the head and amplified by the R/W preamplifier.
The signal from the preamplifier is a series of pulses of alternating polarity that pass through
the pulse detector. The pulse detector (which is a mixed analog and digital device), will accu-
rately locate the time position of the peaks of the pulses.
Because of noise and super position from the read pulses, the data coming out of pulse
detector issues non-synchronized pulses. These non synchronized pulses consists of com-
posite data and clock bits that need to be synchronized before being decoded. The function of
data synchronization is performed by a data synchronizer, which consists of the phase-lock
loop to lock into the incoming bit stream and synchronize it into separate clock and data
signals.
Typical 2,200 Typical 40,000 flux

Tracks per Inch Density Per Inch
Head i in above
Selected track
Read/Write
Amplifier
Pulse Peak
Detector
1st Platter
1 Track
Data Synchronizer
Data (P.L.L)
Separator
DECODER
Clock Data
DDC DISK DATA CONTROLLER
DWA to System
Fig.: Read Process (To begin a read operation a command is sent to the drive where the
head will move the specified disk track)
(89)
The signal is then sent for decoding. Encoded data remove the need for having clock informa-
tion recorded on the track. The selection of the particular code is based on the efficiency with
which the flux reversals are converted to binary 1s and 0s.
In ideal case there should be a minimal number of flux reversals and the code itself must
provide a clock to identify the bit-cell intervals – this may require a separate clock track. These
two requirements seem to be contradictory, and there are different coding methods.
(Note: The above explanation for Read operation is a detailed explanation and is not essential
for the examination.)
The commonly used coding schemes are modified frequency modulation (MFM) and run
length limited (RLL) . In MFM coding, clock bits are used, bits are written only in cases
where data bits are not present in both the preceding and current bit cell where data bits are
written in the middle of the bit cell. As a result, there is a maximum of one flux change per bit
cell. MFM encoding is the most easily implemented encoding scheme and is popular in
floppy disk drives.
The RLL encoding scheme is currently the most popular coding method for hard-disk
drives. It has an excellent coding efficiency of up to 50 percent more than MFM coding in
the same media space. This increased efficiency is achieved without any increase in the
flux changes per inch (FCI) recording density on the media.
RLL codes increase the effective recording density over MFM. This is achieved by eliminat-
ing all the clock bits required in MFM coding and by the scheme of using code words that
minimize the number of 1s at the expense of using more 0s.
Once the disk-drive system receives the command “Read Data”, the head will move to the
specified track. the head pre-amp will then boost the weak signal, which is picked up from
the surface of the disk. The pulse detector output drives a data separator whose phase-
lock loop locks onto the leading edge of the encoded data.
Writing Data to the Disk
The process of writing data to the disk is similar to that of reading from the disk but in
reverse direction, with some minor changes. When the write command is issued, the head
will be positioned over the specified track and sector on the platter where the data will be
written on. Data is written when the R/W head generates a flux change in the media. In case
of reading, a current is induced into the R/W head when a flux change is detected.
(90)
Write
Transmission
Superimposed
Readback
Pulses
(Nominal)
Summation
(Spread)
Read Data
Fig.: Flux change (A negative flux change may appear late when reading back data)
Zone Data Recording
The most common data rate used in drives (under 200MB capacity) is between 10 to 20Mb/
s. The higher the capacity of the drive, the higher the data rate is required.
To further increase the drive’s storage capacity, manufacturers use the zone data recording
(ZDR) technique. ZDR is used in high-performance and high-capacity drives.
Most drives use a single data transfer rate such as 10Mb/s or 15Mb/s. This data rate is
limited by the maximum number of flux transitions that can be placed end-to-end on the
innermost data track of the disc surface. As the length of the circumference of the outer
tracks becomes longer, the data bits will be packed more loosely on the data track.
Thus in above case the recording density is highest on the inner tracks and least on outer
tracks. As a result, a large portion of the disk surface is not used.
If the recording density is maintained highest then maximum data can be recorded.
To make full use of the disk surface, a different number of data bits will be written to different
tracks, depending on the circumferential length. Thus a different data transfer rate is needed
for each track, this requires extra hardware and software.
ZDR technique overcomes the above problem, each track need not have different data trans-
fer rates, instead the hard disk surface is divided into a number of concentric bands, or
zones, with each zone consisting of a number of tracks. The outer-most zone has the
highest data rate(more data bits can be stored) and the innermost zone the lowest.
(91)
By using four zones, the increase in storage capacity is as much as 30- to 40 percent. By
adding more zones, 32 for example, a 50 percent increase in capacity is achieved. If the
disk surface is divided into eight zones, then eight different data rates are needed for the
drives. If more zones are required then equivalent number of data transfer rates would be
required.
These different frequencies can be generated either by using crystals of different frequencies
or by a frequency synthesizer.
In case a number of crystals are used to generate varying data transfer rates, a lot of PCB
space would be wasted and the maximum number of zones would be limited by the number of
crystals used.
By using frequency synthesizer, different data rate frequencies can be generated. A fre-
quency synthesizer, needs only a single external frequency source to generate all
required clocks for data encoding and synchronizing.
Normally, the synthesizer frequency is programmed through the drive’s microcontroller, deter-
mining which zone (frequency) will be accessed.
A way of reducing operating power is, partitioned power down for each functional block.
That is, some of the functional blocks will stay in standby (sleep) mode when the drive is in
the idle state.
SCSI
The SCSI stands for small computer system interface. SCSI is not only a disk interface but a
bus that supports SCSI adapters connected to disk and other device controllers.
SCSI-1 , SCSI-2 are the popular interfaces. The SCSI-2 specification is an improved version
of SCSI-1. SCSI-1 and SCSI-2 devices are normally compatible, but SCSI-1 devices do not
have the additional features of SCSI-2. SCSI-3 is now being defined.
SCSI-1 and SCSI-2 support up to eight devices on the bus where as SCSI-3 supports up to
thirty two devices.
SCSI-2 has following optional features:

* Fast SCSI
* Wide SCSI
Fast SCSI has the capability of high speed synchronous transfer of data. Fast SCSI has a
data transfer rate of 10MB/s on the standard 8 bit SCSI cabling.
Wide SCSI allows for parallel 16 bit or 32 bit data transfer. When Wide SCSI is combined with
Fast SCSI then data transfer rates of 20 to 40 MB per second are achieved.
(92)
CABLES & CONNECTORS
Popularly used cable is of 50 conductor bus configuration. For this there is a 50 pin (unshielded
pin header) connector for Internal SCSI connections. In case of external SCSI connections
the connector is 50 pin shielded D shaped type connector. Both these cables are used in
SCSI-1 & SCSI-2 standards.
The above 50 pin cable is called as A cable in SCSI-2 standards. For 16 bit and 32 bit data
transfers, 68 pin B Cable is used. This B Cable has to be used in parallel with an A Cable. This
combination does not have wide popularity.
In SCSI-3 standard there is a 68 pin conductor cable known as P cable. This cable can be
used alone and hence is better than the previous combination method in SCSI-2 standards.
Thus there are following popular cables :

* A Cable ( Standard SCSI)
* P Cable ( used in 16-bit & 32-bit Wide SCSI)
* Q Cable ( 32-bit Wide SCSI)
SCSI devices can be daisy-chained together using a common, 50-conductor “A” cable and
optionally, a 68-conductor “B” cable, making the signals common to all devices. Terminators
applied at the ends of the cables assure communication signal quality by matching the imped-
ance at the end of the cable to that of the cable itself. In other words, terminators at each end
of the bus must have an impedance equal to that of the cable’s characteristics impedance.
Thus, the pulse energy arriving at the cable termination is completely absorbed and none is
reflected.
SCSI DRIVE CONFIGURATION
Following items need to set to configure a SCSI drive :

* SCSI ID settings ( 0 through 7 )
* Terminator ( Active or Passive)
Each device attached on the SCSI bus must have an unique SCSI ID address. The host
adapter (SCSI controller card) takes one address, and SCSI peripherals attached take the
other addresses.
Normally SCSI host adapters are factory set to ID7, which is the highest priority ID. All other
devices must have unique ID that do not conflict with one another. Some older Adaptec
company’s host adapter required the boot hard disk to be ID-0, newer ones can boot from any
ID.
ID SETTING : ID setting involves changing jumpers on the drive itself. If the drive is an exter-
nal drive then it may have DIP switch setting. If no external switches are present then open the
hard disk or SCSI peripheral and select the jumper settings.
(93)
Particular ID selected is the binary representation of the three jumpers/switches. In this case
observe the most significant bit (MSB), whether it is on right or left.
MSB on Right MSB on Left

SCSI ID Jumper Settings SCSI ID Jumper Settings
0 000 0 000
1 100 1 001
2 010 2 010
3 110 3 011
4 001 4 100
5 101 5 101
6 011 6 110
7 111 7 111
1 Indicates jumper/switch ON
0 Indicates jumper/switch OFF
TERMINATORS
SCSI-1 requires a passive terminator of 132 ohms. This does not support high speeds of
SCSI-2 standards.
SCSI-2 has an active ( voltage regulated) terminator of 110 ohms impedance.
TERMINATION: Termination is required at both ends of the bus, there is no exception to this.
If the host adapter is in the middle of the bus, then host adapter must have its termination
disabled and devices attached at the end of the bus must have terminators installed.
Some devices have internal terminators enabled or disabled through a jumper or by being
physically removed. The devices that do not internal terminators require external terminator
modules for termination.
Termination can be done through :

* Passive terminator
* Active terminator
A Passive Terminator is normally a set of resistance (network of resistance). They are used
over short distances of 2 to 3 feet.
An Active Terminator has one or more voltage regulators to produce the termination voltage.
This ensures that SCSI signals are terminated to the correct voltage level.
Active termination is must for Fast SCSI and Wide SCSI.
(94)
Example:
SCSI RIBBON CABLE
SCSI Host SCSI HDD/

Adapter Peripheral Device
ID-7 ID-7
Terminated Terminated
SCSI RIBBON CABLE
SCSI Host SCSI HDD SCSI CD-ROM /

Adapter Peripheral Device
ID-7 ID-7 ID-7
Terminated UN-Terminated Terminated
Terminators may be connected either internally or externally on to a SCSI device. Internal

terminators are installed on the device’s PCB, while external terminators are built into con-
nectors and encased in a connector shell. The terminator’s connector plug is then inserted or
mated to a second SCSI connector socket on the rear-panel of device.
INSTALLATION OF HDD
Here is an outline of the major steps to follow in the installation of a hard disk for any PC,
XT, AT, or PS/2 system:
I. Drive configuration
a. Drive-select jumpers
b. Terminating resistors
II. Physical installation

III. Machine to disk configuration
IV. Formatting and software installation
a. Low-level format
b. Defect mapping
(95)
2. Interleave selection
a. Partitioning
b. High-level format
These steps are discussed in this section. They are simple to follow and, if done properly,
result in the successful installation of a bootable hard disk. Extra care is taken to ensure
that certain considerations for reliability and data integrity are followed-that this installation
will last a long time and give few problems, for example.
Drive Configuration
Configuring a hard disk drive is similar to configuring a floppy drive, but it actually is much
less complicated. Only two things need to be set: the drive-select jumper and a terminat-
ing resistor.
Drive-Select Jumper Setting
Before a hard disk can be installed, it must be configured properly. The first item to be
configured is the drive-select jumper setting. The drive-select jumper is set so that the drive
and controllers can communicate properly on the same “channel.” resistor.
Cable Types
ST-506
Two cables run from the controller to hard disk drive. These cables consists of a larger 34-
pin control cable and a smaller 20-pin data cable. The control cable is run in a daisy-chain
arrangement to either one or two hard disks. This cable may be wired as a straight-through
design, or it may have a twist in some of the wires before the last physical connector on the
cable (the drive C connector). The data cable is wired straight through. Two data-cable
connector positions are on the controller-one for each of two drives. These cables are
not daisy chained but run from the controller to each drive separately.
If the cable is not twisted, drive C is set to the first drive-select position (DS0 or DS1), and
drive D is set to the second drive-select position (DS1 or DS2).
IDE: 40 Pin single cable used as daisy chain for four devices.
SCSI: 50 Pin A-cable used in daisy chain for eight devices or P Cable for more devices.
HDD INSTALLATION
IDE HDD Auto Detection
The “HDD AUTO DETECTION” utility is a very useful tool specially when you do not know
which kind of hard disk type you are using. You can use this utility to detect the correct disks
type installed in the system automatically. But now you can set HARD DISK TYPE to Auto in
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the STANDARD CMOS SETUP. You don’t need the “IDE HDD AUTO DETECTION” utility. The
BIOS WILL AUTO-detect the hard disk size and model on display during POST.
ROM PCI / ISA BIOS CMOS SETUP UTILITY

AWARD SOFTWARE, INC.
HARD DISK TYPE SIZE CYLS. HEADS PRECOMP. LANDZONE SECTORS MODE
Primary Master 343 665 16 65535 664 63 NORMAL
Primary Slave
Secondary Master
Secondary Slave
HDD Modes
The Award BIOS supports 3 HDD modes: NORMAL, LBA & LARGE
NORMAL mode
Generic access mode in which either the BIOS OR THE IDE controller will make any
transformations during accessing.
The maximum number of cylinders, head & sectors for NORMAL mode are 1024, 16 & 63.
No. of Cylinder (1024)

x No. of Head (16)
x No. Sector (63)
x Bytes per sector (512)
--------------------
528 Megabytes
If user set his HDD to NORMAL mode, the maximum accessible HDD size will be 528 Mega-
bytes even though its physical size may be greater than that!
LBA (Logical Block Addressing) mode
A new HDD accessing method to overcome the 528 Megabyte bottleneck. The number of
cylinders, heads & sectors shown in setup may not be the number physically contained in the
HDD.
During HDD accessing, the IDE controller will transform the logical address described by
sector, head & cylinder into its own physical address inside the HDD.
The maximum HDD size supported by LBA mode is 8.4 Gigabytes which is obtained by the
following formula:
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No.. Cylinder (1024)

x No. Head (255)
x No. Sector (63)
x Bytes, per sector (512)
-----------------------
8.4 Gigabytes
LARGE MODE
Extended HDD access mode supported by Award Software.
Some IDE HDDs contain more than 1024 cylinder without LBA support (in some cases user
do not want LBA). The award BIOS provides another alternative to support these kinds of
LARGE mode:
CYLS. HEADS SECTOR MODE
1120 16 59 NORMAL
560 32 59 LARGE
BIOS tricks DOS (or other OS) that the number of cylinders is less than 1024 by dividing it by
2. At the same time, the number of heads is multiplied by 2. A reverse transformation process
will be made inside INT 12h in order to access the right HDD address the right HDD address!
No.. Cylinder (1024)

x No. Head (32)
x No. Sector (63)
x Bytes, per sector (512)
-----------------------
1 Gigabytes
Note: To support LBA or LARGE mode of HDDs, there must be some software involved. All
these software are located in the Award HDD Service Routine (INT 13h). It may be failed to
access a HDD with LBA (LARGE) mode selected if you are running under a Operating System
which replaces the whole INT 13h. UNIX operating systems do not support either LBA or
LARGE and must utilize the standard mode. UNIX can support drives larger than 528MB.
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CHAPTER - 8
PRINTERS
INTRODUCTION
Printer provide hard copy of data and word processing work. They produce permanent images
of the work done by various application softwares on computers. Printers make use of a ver
wide range of technologies.
Normally, a printer is selected on the basis of print quality, speed and cost. The printing can be
in one color or multi-colors.
Basically, all printers can be classified as impact type and non-impact type. Under these two
broad categories several technologies are employed. The flowchart shows classification of
printers based on their principle of operation.
PRINTERS
IMPACT TYPE NON-IMPACT
Dot Matrix Chain / Bank Inkjet ElectroSensitive

Cylinder Daisy (Laser)
Fig.: Flowchart of printers based on their principle of operation
IMPACT PRINTERS
In impact printer the print head element or part of it actually strikes the ribbon or paper, which
does not happen in non-impact type printers. Impact type printers are slow and are slowly
being phased out.
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Drum Printers
The basic drum impact line printer produces fully formed characters. In this printer, character
images are embossed on the drum. They are transferred to the paper through the ribbon
when a print hammer is actuated. The printer compares the contents of a buffer containing the
data to be printed with the position of the desired characters in each print column. At the
proper time, the corresponding hammers are activated and the line is printed. Drum printer’s
throughput ranges from 10 cps for serial configuration to 1800 lines/min for a line version. The
characters may be embossed on a cylinder ball.
INK JET PRINTERS
Ink-jet printing is noiseless and is capable of printing high-resolution graphics, as well as color
operation, two features that impact printers could not achieve. The power required to operate
ink-jet heads is far less than impact printers which results in smaller power supplies, so ink-jet
printers are small and, are ideal for mobile printing jobs.
Ink-jet printer is composed of four main areas: (1) the print head, (2) the paper transport, (3)
the carriage transport, and (4) the ECU (electronic control unit). This chapter discusses these
subassemblies. As with impact printers, the printer interprets data sent from a host computer’s
main logic (the ECU) and is converted to a series of vertical dot patterns. Carriage motor
moves the carriage and print head moving across the platen. Simultaneously, printer circuits
send each dot pattern to the print head in series. Each dot pattern fires the corresponding
nozzle to leave a permanent mark on the page. This is called serial or moving-head operation.
Drop PAPER
w
Generator
Piezoelectric
Transducer Deflection
Charge Plate
Electrode
Transducer
Driver
Unused Ink
Liquid Ink Pump Charging Character Recycled
Control data
Ink Supply
Filter
Fig.: Principle of operation of Inkjet Printer
THE PRINT HEAD
Ink-jet printing is a non-contact print technology, here the ink is literally spray-painted onto the
page. The systems that control this spraying process make up the ink-jet print head. Three
techniques are used in an ink-jet print head:(100)
(1) continuous flow, (2) piezoelectric pump, and
(3) bubble or thermal pump. Continuous flow printing is typically used for high-volume, low-
quality industrial marking, and hence not used in office automation printers.
DROP ON DEMAND
A series of fine nozzles (each about half as thin as a human hair) are arranged in vertical sets
of 9,12,24, or more on the face of the print head. Nozzles themselves are little more than
microscopic holes drilled into a metal face plate, and are open to the air, but ink’s surface
tension prevents it from spilling. Ink reaches each nozzle through a set of open channels. The
ink comes by gravity from a small ink supply unit reservoir that is built into the head (for
disposable print heads) or located outside to the head in a replaceable ink cartridge (for non-
disposable print heads).
Each ink channel is connected to a series of electrical contacts used to operate the ink pumps
built into each channel. It is these ink pumps that break up ink in the channels and form
individual droplets that are ejected onto the page. The pumps are fired independently by the
printer’s ECU. The control circuitry that interprets data and translates it into dot patterns is
similar to other printers. The color of the print is determined by ink colour, multi-colour cartridges
are also available—each with its own set of nozzles and electrical contacts.
PIEZOELECTRIC PUMPS
In these pumps, a ring of piezoelectric ceramic material is built into an ink channel. When a
high-energy electrical pulse is applied across the ceramic ring, its piezoelectric property causes
ring to constrict and expand in the channel. When the channel contracts, it causes a sudden
displacement of volume that pushes out a single droplet of ink. After the electrical driver pulse
passes, ceramic ring returns to its original shape (expands), and more ink is taken into the
channel to make up the expelled droplet.
BUBBLE PUMPS
Bubble pumps (used in thermal ink-jet or bubble jet printers) also are widely used to generate
ink droplets. This is patented by canon company. As shown, nozzles and channel construction
is very similar to piezoelectric head, but here ring heaters replace ceramic ring. An electrical
driver pulse switches ON a ring heater. This in turn heats ink in the immediate vicinity. As ink
heats up, a steam bubble forms and expands in the channel. When the bubble finally bursts,
it ejects an ink droplet. Ink is drawn in to fill the gap of bubble. Heated ink droplets dry faster on
paper.
Troubleshooting Ink-jet Heads
The replacable cartridge design of most ink-jet heads makes troubleshooting very simple—
print problems can typically be solved by replacing the print head, or by replacing the ECU,
Print head problems are typically indicated by dull print, or by distorted printing. Normal prob-
lem of dull printing can be solved by cleaning print heads.
(101)
Paper Transport Mechanism
Paper handling mechanisms differ slightly from manufacturer to manufacturer. Ink-jet printers
use two distinct types of paper transport: friction feed and tractor feed. Each of these systems
operates in a different manner, and has its own type of problem.
Friction Feed
A friction feed paper transport uses friction to push paper through the printer. Paper is sent
into the printer along a metal feed guide. The guide ensures that paper is sent properly
between the platen and pressure roller(s) and then up in front of the print head assembly. A
set of small, free-rolling rollers press gently against the paper to help keep it flat around
the platen. These free-rolling are ahead of print cartridge. So paper is held in between
two lines of rollers, one line ahead and one line inside the printer feed guide.
In order to allow the free passage of paper, a lever is provided to separate pressure rollers
from the platen. After paper is positioned as required, the lever may be released to re-
apply pressure. From then on, paper can only be moved by hand-turning the platen, or by the
printer’s actual operation.
Square-wave pulses provided by the electronic control unit’s motor drive circuit feed a stepping
motor. Depending on the number of pulses and their sequence, the motor is made to step
clockwise or counterclockwise in required amount. The stepping motor provides force to
drive a set of gears. The primary gear operates a secondary gear attached to the platen.
Gear assemblies are usually used, but pulley systems can sometimes be found.
In some designs a direct drive mechanism is used. In direct drive a stepping motor is used to
operate the platen directly.
The drive assembly offers following useful features:
* The use of gears provides a reliable drive to platen, gears do not stretch or tear with
age, and they do not jam or slip as long as they are kept clean and aligned properly.
* The use of a smaller primary gear provides greater positioning accuracy for the
platen.
Tractor Feed
Tractor feed does not use friction to transport paper. Instead, a set of sprocket wheels are
mechanically linked to the platen drive train. Pegs on each sprocket wheel match perfectly
with specifically made paper. This type of paper (also called continuous - feed or fan-fold
paper) has holes perforated along both sides. Paper is sent into the printer along a metal
feed guide. There is a little resistance from its contact rollers, so paper can easily be fed
through and secured into its sprocket wheels. Most sprocket wheels can slide left or right to
accommodate different paper widths. Bail rollers are included to help keen paper flat
against the platen. Almost all ink-jet printers now-a-days use a friction-feed transport.
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This is optimized for stacked single sheets of paper.
The Print Head (Cartridge) carriage Transport:
Ink-jet printers use serial print heads. Text and graphics are formed by passing a print head
left and right across a page surface. As the head moves, it places (forces out from the
nozzles) series of vertical dots that creates the image. In this way, a complete Line or text can
be generated in a single pass for letter quality text for graphics it requires additional
passes. The high-resolution graphics available from ink-jet printers require great positioning
precision.
Belt drive
Serial print head is moved to left or right by the carriage transport. A print head is mounted
to a holder ( the carriage assembly). Most serial printers make use of belt drive. A
carriage stepper motor is used along with a gear train that drives a primary pulley, which
is connected, to a secondary pulley by a drive linkage. A drive linkage can be a wire, belt,
or chain, depending on the weight of the print head and its desired left-right speed. At one
point, the drive linkage is connected at the carriage, which rides along one or two rails
(carriage rod) having very low friction. Rails keep the carriage totally parallel to the platen at
all points. When the stepping motor turns counter clockwise, the carriage assembly slides
left and vice versa.
Positioning precision for a belt drive (or a direct drive mechanism) is determined by the
stepping motor’s resolution and the pulley diameter. If the primary pulley works through a
gear train, that gear ratio also must be included.
Example: A stepping motor directly drives a pulley 1 inch in diameter. The circumference
of the primary pulley would be 3.14 inches, so one complete motor revolution (thus one
complete pulley revolution) would cause the linkage to travel 3.14 inches. If the stepping
motor works at 200 steps per revolution, each step would turn the pulley of a revolution or
0.0157 inches of linear travel.
LASER PRINTERS
Electro-photographic images are formed by a complex interaction of light, static electricity,

chemistry, pressure, and heat, all guided by a sophisticated ECE (electronic control unit).
Electro-photographic operation
Electro-photographic printing is accomplished through a process and not by a print head as in

the case of Dot Matrix printers. The collection of components that performs the EP printing
process is called an IFS (image formation system). An IFS is made up of Photosensitive
drum, Cleaning blade, Erasure lamp, and fusing rollers. Each of these parts play an important
role in the proper operation of an IFS.
(103)
A photosensitive drum is the core of IFS. An aluminium cylinder is coated with a non-toxic
organic compound that exhibits photo-conductive properties. That is, the coating conducts
electricity when exposed to light. The aluminium base cylinder is connected to ground of the
high-voltage power supply. This drum receives an image from writing mechanism, develops
the image with toner, and then transfers the developed image to paper. Complete image
development is a six-step process and involves all IFS components: cleaning, charging, writing,
developing, transfer, and fusing.
Cleaning
Before a new printing cycle begins, the photosensitive drum is physically cleaned and electrically
erased. The best drum is also not able to transfer all microscopic granule of toner to a page
every time. So rubber-cleaning blade is applied across the entire length of the drum to gently
scrape away any residual toner that might remain from a previous image.
If residual toner is not cleaned, it will adhere to subsequent pages and appear as random
black spots. Toner that is removed from the drum is deposited into a waste toner cavity. Cleaning
must be done without scratching the drum. Any damage to the drum’s photosensitive surface
would become a permanent mark, which will then appear on every subsequent page. Some
EP printer design may return scrap toner back to the supply for reuse. This recycling extends
the life of EP (electrophotographic) cartridge and eliminates the need for a large debris cavity.
Photosensitive
Outer layer
Rubber
Cleaning blade
Waste toner
Collection Box Drum Movement
Used/Waste
toner
Aluminium base
Cylinder (Cross-sectional
Fig. Cleaning EP drum
Images are written to a drum’s surface as horizontal rows of electrical charges, these charges
correspond to the image being printed. A dot of light creates a relatively positive charge at
that point. This corresponds to a visual dot in the completed image. Absence of light allows a
relatively negative charge to remain and no visual dots are generated in the completed image.
The positive charges caused by light must be removed before any new images can be written,
otherwise images would. A series of erase lamps are placed in close proximity to the drum’s
surface. Their light is filtered to allow only effective wavelengths to pass. Erase light removes
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any charges along the drum. Charges are carried to ground through the aluminium cylinder.
After erasure, the drum’s surface contains no charges at all.
Fig.: Erasing all charges from an EP Drum
Charging
A neutral drum surface is not receptive to light from the writing mechanism. New images
cannot be written until the drum is recharged. A uniform electrical charge is applied uniformly
across its entire surface. To recharge (or condition) the drum. Surface charging is achieved by
applying a high negative voltage (often more than –6KV) to a solid wire called a primary
corona located close to the drum. As the drum and high-voltage power supply share common
ground, an electrical field is established between the corona wire and drum.
- 6 KV charging
voltage
Primary Corona - 600V regulating grid

Control Grid voltage
Ionized Air
Photosensitive drum Use of a control grid puts a ve 6 KV
charge on the drums surface
Aluminium base drum
Fig.: Placing a Uniform charge on EP drum
At low voltages, the air gap between a corona wire and drum acts as an insulator. At high
(105)
voltage (-6KV) potential difference, however, the insulating strength of air breaks down and
ionisation of air takes place. The field ionises air molecules surrounding the wire, so negative
charges migrate to the drum’s surface. Ionized gas exhibits a very low resistance to current
flow. Once air ionisation is established, there is effectively a short-circuit between the wire and
drum. This is not good for a high-voltage power supply, as very large currents will flow. To
avoid this a primary grid is placed between the wire and drum. By applying a negative voltage
to the grid, charging voltage and current to the drum can be regulated. This regulating grid
voltage (often -600 to -1000V) sets the charge level actually applied to the drum that is typically
between (-600V to -1000V). The drum is now ready to receive a fresh new.
Writing
In order to form a image on the drum surface; the uniform charge that has conditioned the
drum must be discharged, at the precise points where images are to be produced. Images are
written using light. Points on the drum which are exposed to light get discharged to a very low
level (about -100V), Any areas left unexposed retain their conditioning charge (-600 to -1000V).
The device that produces and directs light to the drum surface is called a writing mechanism.
Images are formed as a series of individual dots, and hence a larger number of dots per area
will allow finer resolution (and higher quality) of the image.
For example, suppose a writing mechanism can place 300 dots per inch along a single horizontal
line on the drum, and the drum can rotate in increments of 1/300 of an inch. This means that
the printer can develop images with a resolution of 300X300 dots per inch (DPI). Current
Now-a-days printers with 600 X 600 DPI are popular.
Developing
Images written to the drum by laser are initially invisible. There are low charges created where
the light strikes, and high charges where the light skips. The image in the form of charge is
developed into a visible image before it is transferred to paper. Toner is used for this purpose.
Toner is an extremely fine powder of plastic resin and organic compounds bonded to iron
particles. Individual granules can be seen under extreme magnification by a microscope.
(106)
Rubber Cleaning blade

Photo Sensitive drum
Aluminium drum
(Cross-section)
Toner supply
Magnet core
Developer Drum
+ AC Booster bias
EP Drum DC bias
Developing latent drum image with toner (a cross-sectional view)
Toner is applied using a toner cylinder (or developer roller). A toner cylinder is a long metal
sleeve containing a permanent magnet. It is mounted inside the toner supply tray. When the
cylinder turns, iron in the toner gets itself to the cylinder. Once attracted, toner acquires a
negative static charge provided by the high-voltage power supply. This static charge level falls
between the photosensitive drum’s exposed and unexposed charge levels (anywhere from -
200 to -500V depending in the intensity control setting). A restricting blade limits toner on the
cylinder to just a single layer.
Charged toner on the cylinder rotates very closely to the exposed drum. Points on the drum
are not exposed to light will have a strong negative charge. This repels toner on cylinder so
that it remains on the toner cylinder and is returned to the supply. Points on the drum that are
exposed to light now have a much lower charge than the toner particles. This attracts toner
from the cylinder (developer roller) to corresponding points on the drum. Thus toner “fills-in”
the latent image to form a visible (or developed) image.
Transfer
The developed toner image on the drum has to be transferred onto paper. Because toner is
now attracted to the drum, it must be attracted away by applying an even larger attractive
charge to the page. A transfer corona wire charges the page. The theory behind the operation
of a transfer corona is exactly the same as that for a primary corona, except that the potential
(107)
is now positive. This places a powerful positive charge onto paper that attracts the negatively
charged toner particles. This is not a perfect process; not all toner is transferred to paper.
Cleaning process is therefore needed.
Photosensitive drum
Toner particles
No net charge on paper
------- ++++++++ Paper

Static change
eliminator
- ve + ve +ve Ionized air particles
Corona assembly
Fig.: Transferring the developed image to paper
Because the negatively charged drum and positively charged paper tend to attract each other,
it is possible that paper could wrap around the drum.
The small-diameter drum and natural stiffness of paper tend to prevent wrapping of paper
around the drum. Also a charge static charge eliminator (static-eliminator comb) is included
to counteract positive charges and remove the attractive force between paper and drum im-
mediately after toner is transferred. Paper now does not have any net charge. The drum is
cleaned and prepared for a new image.
Fusing
Once the toner image has reached paper, it is present on the page by gravity and weak
electrostatic attraction; toner is still in its powder form. Toner has to be fixed permanently (or
fused) to the page before it comes out of printer. Fusing is done with a heat and pressure
roller assembly. A high-intensity quartz lamp heats a non-stick roller to about 2000C. When a
developed page is passed between two rollers, heat from the top roller melts the toner, and
pressure from the bottom roller squeezes molten toner into the paper, where it cools and
becomes permanent. The finished page is then fed to an output tray. Both rollers are called as
fusing rollers, even though only the top heated roller actually fuses. To prevent toner particles
(108)
from sticking to a fusing roller, it is coated with a non-stick material such as Teflon. A cleaning
pad is added to wipe away any toner that may be left. The pad also applies a thin coating of
silicon oil to prevent further sticking.
Fusing temperature is controlled by thermistors, which are used to regulate current through
the quartz lamp, in order to maintain a constant temperature. A thermal switch is also included
as a safety device in the event that lamp temperature rises out of control. If temperature is not
controlled carefully, a failure could result in printer damage, making paper brittle or a fire
hazard.
Fig.: Fusing the toner image to the page.
Writing Mechanisms
After charging, the photosensitive drum contains a uniform electrostatic charge across its
surface. To form a latent image, the drum is discharged at all points that comprise the image.
Light is used to discharge the drum as needed. Writing mechanism is shown in. Images are
scanned onto the drum one horizontal line at a time. A single pass across the drum is called
a trace or scan line. When a scan line is completed, the drum (moves (increments) in prepa-
ration for another scan line. It is the printer’s control circuits that receives an image into indi-
vidual scan lines, then direct the writing mechanism accordingly.
Lasers
The nature of laser light, however, is much different from ordinary light. A laser beam contains
only one wavelength of light (it is monochromatic). Each ray travels in the same direction and
combines in an additive fashion (known as coherence). These characteristics make laser light
easy to direct at a target as a hair-thin beam, with almost no scatter (or divergence). Semicon-
ductor laser diodes are used in all LASER printers.
(109)
Photosensitive drum
Rotation direction
Exposed points
1 1 0 0 1 1 0 1 0 1 1
Digital data from the

electronics control
unit of printer
Fig.: Simplified diagram of writing mechanism
Laser diodes look very similar to ordinary light-emitting diodes. When the appropriate amount
of voltage and current is applied to a laser diode, photons of light are liberated that have the
characteristics of laser light (coherent, monochromatic, and low divergence).
The light beam emitted from LED must be modulated (turned on and off) while being swept
across the drum’s surface. Beam modulation can be done by turning the laser on and off as
(same as in case of diode as a switch). Mirrors are used to alter the direction of the laser
beam, and lenses are used to focus the beam and maintain a low divergence at all points
along the beam path. Figure 32-10 is an illustration of a laser writing mechanism. The weight
of glass lenses, mirrors, and their shock mountings make EP laser printers bulky and expensive.
Alignment is an unavoidable problem in complex optical systems. If any optical component

becomes damaged or fall out of alignment; focus and direction problems may make render a
drum image unreadable. Realignment of optical systems is virtually impossible without special
alignment tools, and is beyond the scope of this course. Finally, printing speed is limited by
the speed of moving parts, and the rate at which the laser beam can be modulated and
moved.
(110)
CHAPTER - 9
DISPLAY CARDS
VIDEO ADAPTER
It is a board that plugs into personal computer to give it display capabilities. The display
capabilities of a computer depends on the logical circuitry (provided in the video adapter) as
well as the display monitor. A monochrome monitor, for instance, cannot display colors no
matter how powerful is the video adapter.
Many different types of video adapters are available for PCs. Video adapters are also called
video cards, video boards, video display boards, graphics cards, graphics adapters or graphic
accelerators. All adapters offer several different video modes. The two basic categories of
video modes are text and graphics. In text mode, a monitor can display only ASCII characters.
In graphics mode, a monitor can display any bit-mapped image. Some monitors also have a
choice of resolutions. At lower resolutions a monitor can display more colors.
Video adapters have screen (video RAM) memory for storing displays. In addition, most
adapters have their own graphics coprocessor for performing graphics calculations. These
adapters are often called graphics accelerators.
Functionally, the video card in a personal computer is an output device. Color Graphics Adapter
(CGA) allow for integration of text with simple graphics. The main disadvantage of the CGA
was, however, its limited resolution for text. A few years later, the EGA card (EGA=Enhanced
Graphics Adapter) was introduced to satisfy more demanding users wishing to work with
high-resolution color screens. But the evolution of the video card did not stop with this, the
introduction of the new series PS/2 computers from IBM called for even higher resolution and
speed, the answer was provided in the form a range of VGA and SVGA cards.
THE MONOCHROME ADAPTER
The Monochrome Display Adapter (MDA) fitted in the earliest of IBM PCs provided only text
display. This card, which is now obsolete, had a screen memory of only 4 Kbyte (4,000
characters), and displayed text as 25 lines of 80 characters. None the less the resolution of
the MDA is relatively high at 720x350 pixels. The character font is 7z11 in a 9x14 raster,
resulting in a clear text display,. The card provided 256 characters, which are stored in an on-
board ROM. No provision is made for the user to define his own characters. The Hercules
(111)
card replaces the MDA, and adds a graphics option in the form a monochrome graphics
interface with a resolution of 720x348 pixels. Text display is basically the same as with the
MDA, and requires no special software. Graphics software, however, can only be run with the
aid of software utility, since IBM, and, therefore, the Disk Operating System (DOS) does not
support the Hercules card.
The CGA Card
The CGA was the first card introduced by IBM that allowed the connection of a color to a PC.
On board the CGA is a 16 Kbyte memory. The card can operate in two modes: text and
graphics. In text ode, two sub-modes are available: 40 or 80 characters per line, at 25 lines per
screen in both cases. The available memory allows 8 or 4 screens to be stored in 40 and 80
character mode, respectively, so that fast scrolling can be achieved. The graphics mode also
affords a member of sub-modes, including one with 640x200 pixels at two colours, and 320x200
pixels at four colours.
The CGA double-scan card is an improved version of the standard CGA. This type of video
adapter is available in the form of an emulated mode on some EGA cards, and enables
software written for the CGA to be run on a display with much higher resolution. This is mainly
by virtue of the double-scan principle, which pro9vides an interface function that effectively
doubles the vertical resolution. Unfortunately, this mode is not available in the form a separate
card.
The EGA Card
The cost of Enhanced Graphics Adapter (EGA) was, for a time, prohibitive for the average
PC user, but that, fortunately changed with the availability of good-quality products from the
Far East. The EGA has a large, 256 Kbyte, on-board memory, and offers a graphics resolution
of 640x350 pixels, at 16 possible colors per pixel (a 256 color extension for the EGA). Pixels
colours selection is from 1 64 x 350 pixels, at 16 possible colors per pixel ( 1 256 color
extension for the EGA). Pixels colours selection is from a 64-color palette. Depending on the
resolution, two or four screens can be held in the memory.
The character set of the EGA is ROM-resident, and uses an 8 x 14 matrix to guarantee
excellent text display capabilities. Provision has been made for the user to shape up to 1024
characters at a height of 8 to 32 pixels. Many manufacturers of EGA cards have come up with
useful extensions to the basic capabilities, often in the form of emulation modes. In many
cases, software is supplied with the card that allows it to switch to the CGA, MDA and CGA
double-scan mode. Some EGA cards take compatibility even further by their ability to adapt
the outputs to the display used. Other EGA can be used in conjunction with a CGA compatible
monitor.
MCGA
In an attempt to put an end to the widespread confusion about videocards in PCs, IBM recently
introduced two new types of display adapter, the Video Graphic Array (VGA) and the Multi
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colour graphics array (MCGA), for use in their series PS/2 computers, Both adapters are
complete, versatile, and expected to stay with us the quite some time. The MCGA is essentially
allow budget’ version of the VGA. It comes as standard with the Model 30 Computer in IBM’s
PS/2 line, and has 64 Kbyte of on-board RAM. The maximum resolution of 640x480 pixels is
achieved in the two-color mode. At the lower resolution of 300x200 pixels, 256 colors are
available from a total of 262, 144 in the color palette. The MCGA can display up to 64 Grey
shades on a monochrome monitor. Downwards compatibility is ensured at least party by a
CGA emulation mode. Other cards such as the EGA or MDA can not be emulated.
VGA Card
VGA can be used with color as well as monochrome monitors with an analogue (linear) input.
Screen memory is 256 Kbyte for standard graphics resolution of 640 x 480 pixels in the text
modes. In the low resolution graphics mode, each of the 320 x 200 pixels can be assigned
one of 256 colours, In the high resolution mode, this is reduced to 16 colors. The number of
available colors in the selected screen mode, upto 8 screens can be held in memory. Characters
are built in a matrix of 9 x 16 pixels in text mode, or 8 x 16 pixels in graphics mode. The VGA
is capable of emulating all previous standards, ensuring software compatibility with MDA,
CGA, EGA and MCGA. Characters in these subsets have a maximum height of 32 pixels.
This card does not have hardware compatibility with previous monitors and cards.
The VGA cards earlier used to come on 16-bit ISA bus. The maximum video RAM
supported on ISA cards was 1 MB. Then PCI VGA card becomes popular. PCI VGA had
design to support upto 2 MB/4 MB of video RAM.
15 PIN D
TYPE
CONNECTOR
Graphic
Accelerator
Coprocessor
RAM
DAC
BIOS
VRAM O
PC-AT 16 BIT ISA
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VIDEO GRAPHICS CHIPSET
All modern video cards are accelerators, which perform various video calculation functions in
addition to just providing the output signal to the monitor. The capabilities of the video card are
due to a function of the internal processor on the card that does the calculating functions. The
logic circuit that controls the video card is referred to as the video chipset. It is sometimes also
called an accelerator or video coprocessor, graphic accelerator coprocessor.
VIDEO BIOS
The video BIOS provides a set of video-related functions that are used by programs to
activate the video hardware. The video BIOS interfaces software to the video chipset in the
same way that the system BIOS does for the system chipset.
The functions in the video BIOS are written to activate the system chipset, however the BIOS
codes can differ for different cards that use the same video chipset.
VIDEO MEMORY (Frame Buffer VRAM)
The screen image that is seen on monitor has many bits of information. For example, a
1600x1200 pixel screen display in true color contains almost 6 MB of data; and this is just for
the displayed image, not for the data itself that the image represents.
RAMDAC
The screen image information is stored in the video memory (RAM) in digital form. Every
value is stored as combination set of ones and zeros. In the case of video data, the patterns
of ones and zeros control the color and intensity of every pixel (dot) on the screen.
The monitor is analog, it doesn't use digital information. To display the image on to the screen,
the information in video memory is converted to analog signals and sent to the monitor. The
IC device that converts this is called the RAMDAC (Random Access Memory Digital-Analog
Converter).
The type and speed of the RAMDAC determines the quality of the screen image, how often
the screen can be refreshed per second, and the maximum resolution and number of colors
that can be displayed.
VIDEO SYSTEM INTERFACES
Video systems have a lot of information that must be moved around, particularly between the
video card, the processor and the system memory. The video system interface is the port or
connection by which the video coprocessor and video memory are connected to the main
processor on motherboard.
The video card requires more I/O bandwidth to the processor and memory than any other
device in the system. Video performance has been the driving factor for the creation of newer
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and faster system buses. Local buses were created to address the bottleneck in data transfer
between the main processor and video card that became acute when graphical operating
systems became the standard. The first local bus was the VESA local bus. (See Motherboard
Buses)
ISA Bus
The ISA bus is the standard (slow) I/O bus still used. Older PCs use ISA-based video cards.
ISA cards have limited acceleration functions and have less memory on board. Thus ISA
cards are almost obsolete now.
VESA Local Bus
VESA Local Bus video cards provide much better performance than ISA cards. This is due to
the fact that the 32-bit local bus is used by VLB cards allows for several times more data
throughput between the card and the processor.
Note: VESA Local Bus video is generally limited to 486 PCs (or other motherboards that use a fourth-generation
processor). The vast majority of Pentiums and later PCs use PCI (or AGP) and do not support VLB at all, although
there are some very old Pentium systems that are VLB-based.
PCI Local Bus
The most popular interface used in current motherboards is the PCI bus. PCI became popular
with the Pentium and is now the standard choice. It offers local bus performance and solves
many of the problems associated with VLB, and gives new features including Plug and Play
and bus mastering.
ACCELERATED GRAPHICS PORT (AGP)
The new enhancement to the PC platform is 3D graphics through AGP. This relieves the
graphics bottleneck by adding a new dedicated high speed bus directly between the chipset
and the graphics controller. This removes bandwidth-intensive 3D and video traffic from the
constraints of the PCI bus. In addition, AGP allows textures to be accessed directly from
system memory during rendering rather than being pre-fetched to local graphics memory.
Segments of system memory can be dynamically reserved by the OS for use by the graphics
controller, this memory is termed as AGP memory or non-local video memory.
The net result is that the graphics controller is required to keep fewer texture maps in local
video memory.
FEATURE CONNECTORS
Many video cards contain what is called a feature connector. This is an additional connector
that is used to connect the video card to other video devices such as 3D accelerators, MPEG
decoders and video capture cards. The reason that these connectors are used is that they
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permit the direct transfer of video information from these devices to the video card, without
having to use the main system bus.
VIDEO CARD RESOURCE USAGE
Video cards do not use many system resources, and device conflicts with video cards are
relatively less. VGA-compatible video cards use the I/O addresses from 3B0-3BBh and 3C0-
3DFh. IRQ 11 or IRQ 12 is used by PCI_VGA card.
PIXELS AND RESOLUTION
The image that is displayed on the monitor screen is made up of thousands (or millions) of
small dots; these are called pixels. A pixel is a "picture element". A pixel represents the
smallest dot on the screen that can be controlled individually. Each one can be set to a
different color and intensity (brightness).
The number of pixels that can be displayed on the screen is called as the resolution of the
image. It is normally displayed as a pair of numbers, such as 640x480. The first is the number
of pixels that can be displayed horizontally on the screen, and the second how many can be
displayed vertically. The higher the resolution, the more pixels can be displayed.
The aspect ratio of the image is the ratio of the number of X pixels to the number of Y pixels.
The standard aspect ratio for PCs is 4:3, but some resolutions use a ratio of 5:4.
Pixel Color and Intensity, Color Depth and the Color Palette
Each pixel of the screen image is displayed on a monitor using a combination of three different
color signals: red, green and blue. Each pixel's appearance is controlled by the intensity of
these three beams of light. When all are set to the highest level the result is white; when all are
set to zero the pixel is black, etc.
The amount of information that is stored about a pixel determines its color depth, which
controls the precise pixel's color. The more bits that are used per pixel, the finer the color
detail of the image. However, increased color depths also require more memory for storage of
the image, and also more data for the video card to process, which makes the card slow.
This table shows the color depths used in PCs today:
Color Number of Bytes of Storage Common Name for

Depth Displayed Colors Per Pixel Color Depth
4-Bit 16 0.5 Standard VGA
8-Bit 256 1.0 256-Color Mode
16-Bit 65,536 2.0 High Color
24-Bit 16, 777, 216 3.0 True Color
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In true color three bytes of information are used, one for each of the red, blue and green
signals that make up each pixel. Since a byte has 256 different values this means that each
color can have 256 different intensities, allowing over 16 million different color possibilities.
This allows for a very realistic representation of the color of images. In fact, 16 million colors
is more than the human eye can distinguish.
REFRESH RATES AND INTERLACING
The RAMDAC is the device in the video card that is responsible for reading the contents of the
video memory, converting the digital values in memory into analog video signals, and sending
them over the video cable to the monitor.
Refresh rate is measured in Hertz (Hz), a unit of frequency. Support for a given refresh rate
requires two things: a video card capable of producing the video images that many times per
second, and a monitor capable of handling and displaying that many signals per second. The
refresh rates are somewhat standardized; common values are 56, 60, 65, 70, 72, 75, 80, 85,
90, 95, 100, 110 and 120 Hz. This is done to increase the chance of compatibility between
video cards and monitors.
FRAME BUFFER MEMORY REQUIREMENTS
The frame buffer is the video memory that is used to store the video image displayed on the
screen. The amount of memory required to store the image depends primarily on the resolution
of the screen image and also the color depth used per pixel. The formula to calculate how
much video memory is required at a given resolution and bit depth is quite simple:
Memory in MB = (X-Resolution*Y-Resolution*Bits-Per-Pixel) / (8*1,048,576)
Horizontal Vertical Video Card Resolution

frequency Frequency (Hz)
15.75 60 CGA 320X200
640X200
18.2 50 EGA mono 640x350
18.4 50 MDA 720x350
18.8 50 Hercules 720x348
21.9 60 EGA 640x350
EGA 1055x352
31 60 EGA+ 640x480
32 60 CGA Double 320X400
Frequency
Table - 1
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The large difference in respect of line and raster frequency between the various videocards
give rise to monitor incompatibility. A standard CGA display, for instance, can not be used in
conjunction with a Hercules card. Some monochrome, Hercules compatible, monitors, however,
are capable of dual frequency operation so that CGA pictures can be displayed by means of
shades of grey. Similar dual-sync color monitors are aimed at users of PCs with a CGA and/
or EGA card. The EGA also requires its own monitor type. Colour SVGA monitor can be used
with VGA card, SVGA card, VL bus VGA card, PCI bus VGA card with 2 MB RAM on board.
Now-a-days AGP Video display adapters are popular with upto 64MB video RAM.
CABLES AND PLUGS
Combining a video card with an appropriate color or monochrome monitor is a problem that is
even further complicated by the cables and plugs needed for each combination. It will be
noted that MDA, CGA and EGA and PGC make use of a 9-pin D-connector, while the new
cards, MCGA and VGA, need more wires and work with a 15-pin connector.
PIN MDA CGA EGA MCGA VGA VGA

mono color
1 Ground Ground Ground R-out -- R-out
2 Ground Ground R G-out M-out G-out

3 - R R B-out -- B-out
4 -- G G -- -- B-out
5 - B B -- Test Ground
6 Intensity Intensity G R-in Key R-Ground
7 Video -- B G-in M-in G-Ground
8. HSYNC HSYNC HSYNC B-in -- B-Ground
9 VSYNC VSYNC VSYNC Key -- --
10 Ground Ground Ground
11 Type 0 -- Ground
12 Type 1 Ground --
13 HSYNC HSYNC HSYNC
14 VSYNC VSYNC VSYNC
15 -- -- --
SIGNAL FLOW FROM KEYBOARD TO MONITOR
When you strike a character on the keyboard, its unique position on the key-board is coded.
That code passes through an I/O chip or microcontroller to the CPU. The microcontroller uses
the keyboard code to read the character ROM. The ROM in turn gives the microcontroller a
byte-sized code called ASCII. The processor CPU on motherboard then stores the ASCII
code into the next available video RAM byte-sized location.
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Meanwhile the processor is also scanning video RAM to constantly update video RAM. Almost
at the same time you hit the key, the character appears in the next display position. The
character has travelled from the keyboard, through an I/O microcontroller chip was stored in
motherboard RAM, sent through all the video circuits, installed in the video display card, sent
into the display monitor and scanned into light on the face of the CRT display.
MONITOR FUNCTIONING
A monitor consists of the display device-the picture tube along with the related circuitry that
converts the signals sent by the computer in a form that can be used by the display. The
picture tube, called a cathode ray tube or CRT, is the core of a monitor.
It has many other elements such as a shadow mask and a phosphor coating that enable it to
display the picture along with the display electronics. The electronics is added to the CRT to
make it a monitor.
The monitor has a stream of electrons that are fired at the monitor screen by CRT’s ‘electron
gun.’ These electrons are filtered through the shadow mask and hit the phosphor-coated
screen to produce images. This process is monitored and controlled by the display electronics.
A colour monitor is capable of displaying many colors, whereas a monochrome monitor can
display only two colors. Color monitors implement the color dot by using three different
phosphors dots that appear red, green, and blue when activated. By placing the phosphors
directly next to each other in a triangle, and activating them with different intensities, color
monitors can create an unlimited number of colors and shades. The real number of colors that
any monitor display is generated and controlled by the video adapter.
Color monitors are based on CRT technology that employs three different techniques to merge
phosphor triplets into pixels:
1. Dot-trio shadow masks place a thin sheet of perforated metal in front of the screen.
Since electrons can pass only through the holes in the sheet, each hole represents a
single pixel.
2. Aperture-grille CRTs place a grid of wires between the screen and the electron guns.
3. Slot-mask CRTs uses a shadow mask but the holes are long and thin. It's sort of a
cross between the dot-trio shadow mask and aperture-grill techniques.
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Subsystems of a Monitor
A computer or video monitor includes the following functional blocks:
1. Low voltage power supply: Most of the lower voltages used here may be derived from
the horizontal deflection circuits, a separate switching power supply, or a combination
of the two. Rectifier/filter capacitor/regulator from AC line provides the positive signal
to the switching power supply or horizontal deflection system. Auto-scan monitors may
have multiple outputs from the low voltage power supply which are selectively switched
or enabled depending on the scan rate.
2. Horizontal deflection: These circuits provide the waveforms needed to sweep the
electron beam in the CRT across and back. It is anywhere from 15 KHz to over 100
KHz depending on scan rate and resolution. The horizontal sync pulse from the sync
separator or the horizontal sync input locks the horizontal deflection to the video signal.
Auto-scan monitors have sophisticated circuitry to permit scanning range of horizontal
deflection to be automatically varied over a wide range.
3. Vertical deflection: These circuits provide the waveforms needed to sweep the electron
beam in the CRT from top to bottom and back. The frequency is anywhere from 50 -
120 or more times per second. The vertical sync pulse from the sync separator or
vertical sync input locks the vertical deflection to the video signal. Auto-scan monitors
have additional circuitry to lock to a wide range of vertical scan rates.
4. CRT high voltage: A color CRT requires up to 30 KV for a sharp bright picture. Most
monitors derive the high voltage (as well as many other voltages) from the horizontal
deflection using a special transformer called a 'flyback' or 'Line OutPut Transformer
(LOPT). Some high performance monitors may use a separate high voltage board or
module which is a self contained high frequency inverter.
5. Video amplifiers: These buffer the low level inputs from the computer or video source.
On monitors with TTL inputs (MGA, CGA, EGA), a resistor network also combines the
intensity and color signals. Analog video amplifiers will usually also include DC restore
(black level retention, back porch clamping) circuitry stabilize the black level on AC
coupled video systems.
6. Video drivers (RGB): These are almost always located on a little circuit board plugged
directly onto the neck of the CRT. They boost the output of the video amplifiers to the
hundred volts or so needed to drive the cathodes (usually) of the CRT.
7. Sync separator: In case of monitors having composite input rather than separate H
sync and V sync, this circuit extracts the individual sync signals. Output is horizontal
and vertical sync pulses to control the deflection circuits. This circuit is not needed in
a monitor that only uses separate sync inputs.
8. System control: Most higher quality monitors use a microcontroller to perform various
user interface and control functions from the front panel . So called 'digital monitors'
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meaning digital controls not digital inputs, use buttons for everything except possibly
user brightness and contrast. Settings for horizontal and vertical size and position,
pincushion, and color balance for each scan rate may be stored in non-volatile memory.
The microprocessor also analyzes the input video timing and selects the appropriate
scan range and components for the detected resolution.
Most problems occur in the horizontal deflection and power supply sections. These
run at relatively high power levels and some components become very hot. Thus both
wear and tear of the components as well as increased chances there is of bad
connections developing from repeated thermal cycles. The high voltage section is
prone to breakdown and arcing as a result of hairline cracks, humidity, dirt, etc.
Video Signal
From Display VIDEO VIDEO
PREAMPLIFIER OUTPUT
AMPLIFIER
Horizontal
Deflection
Vertical
Coil
Deflection
Coil
VSYNC. Signal
VERTICAL VERTICAL
From display
SWEEP OUTPUT
card
OSCILLATOR STAGE
Heater
HSYNC. Signal HORIZONTAL HORIZONTAL

From display SWEEP OUTPUT E.H.T
card OSCILLATOR STAGE
SMPS UNIT 12V, 6V
Fig.: Block diagram of Mono VGA Monitor
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CATHODE RAY TUBE (CRT) TECHNOLOGY
A Cathode Ray Tube (CRT) is a major component in any monitor. It basically is a glass tube
partially evacuated and filled with inert gas at a very low pressure. The cathode (negatively -
ve charged electrode, also called an ‘electron gun’) emits a beams of electrons towards a
positively +ve charged electrode-the anode. At the end of their travel, the electronics strike
into a coating made from phosphor compounds that converts the kinetic energy of the electrons
into visible light-glowing to produce the picture.
Colour CRTs use thousands of triads-triangles painted across the inner surface of the tube.
Every triad consists of three dots of the primary colours red, green blue (RGB) arrayed next to
each other. One triad of dots makes up a ‘picture cell’ called a pixel.
To generate beams that light up the phosphor on the screen, a CRT uses one or more electron
guns. An electron gun is an electron emitter (a cathode) that draws the electrons into sharp,
high-speed beams. There are three separate electron beams, one each for red, green and
blue.
These beams have to go through a shadow mask, which is a layer between the phosphor
triads and the electron gun. The shadow mask causes the three beams to land on the phosphors
in a distinct triangle so that each beam illuminates only the right-coloured dot. Each triad has
a corresponding hole in the shadow mask, which prevents the beam from illuminating the
wrong colour phosphors.
To move the beam across the breadth of the tube face, a group of powerful electromagnets
are arranged around the tube, forming a yoke. They bend the electron beam in the course of
its flight. The magnetic field set up by the yoke is carefully controlled and causes the beam to
sweep each individual display line down the face of the tube. Monochrome CRTs have a
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single electron gun that continuously sweeps across the screen. Most colour tubes have three
guns arranged in a triable. They emit their electrons continuously and the three resulting
beams are steered by the yoke.
SHADOW MASK VERSUS APERTURE GRILL
Most of the CRT-based monitors use a commonly available technology called shadow Mask.
Some manufacturers also refer to them as Fully Square Tube (FST). Basically the shadow
mask is a perforated sheet or metal, usually made of an alloy called Invar, just behind the
glass of the monitor screen. This masks the three separate beams that cause the red, green
and blue screen phosphor to fluoresce. The mask ensures that there is no spill-over of the
beam and that even if the beam is slightly misaligned, a red phosphor dot will not receive the
beam intended for an adjacent green one.
An advancement in the Trinitron screen technology is called the ‘aperture grill’ and the inside
of the screen is painted with Phosphor stripes instead of dots.
The aperture grill is a mesh of vertical wires, although in larger monitors Sony also uses two
horizontal wires to hold the mask steady and thus reduces picture instability. In a Trinitron
monitor, a shimmering wave travels across the screen, due to the vibration of the wire mask.
One of the advantages with a Trinitron screen is that they offer more saturated colour and
better contrasts, which is why they are in favour with the graphics industry. Trinitron screens
are also less prone to glare than mot FST ones because they are cylindrical rather than
spherical.
Colour monitors have longer CRT: In a CRT, the electron beam has to deflect at a very sharp
angle to reach the corners of the screen. Maintaining uniform convergence and focus in a low
deflection angle (Figure A) is easier than in a high deflection angle (Figure B). Convergence
for high angles is very complicated and requires sophisticated and requires sophisticated
electronic design. Obviously, the longer the CRT tube, the lower the deflection angle and the
easier it is to control picture characteristics.
FLAT SCREEN MONITORS
The face of most monitors is a spherical curve. This is because it makes the distance travelled
by the electron beam more consistent across various points on the face of the screen. A truly
flat screen requires the beam to travel further to the edges than to the centre and also means
that the beam will hit the screen obliquely, resulting in image distortion.
Then why are flat screens preferred? Because screen curvature has a negative effect of
distorting the image. Straight lines on the screen appear straight only from one observation
point. Move your head to a different angle and the lines and edges on your drawings and
graphics will warp this way and that.
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Current technology simplifies tube construction and alignment. But even today, the flat-screen
monitors are not truly flat. They are only cylindrically curved and flatter than the older spherically
curved models.
PREVENTIVE MAINTENANCE OF MONITOR
* Place the monitor away from extremes of hot and cold. Avoid damp or dusty locations
if possible.
* Allow good ventilation - monitors use a fair amount of power - from 60 watts for a 12
inch monochrome monitor to over 200 W for a 21 inch high resolution color monitor.
Heat induces a ageing and breakdown.
* Do not put anything on top of the monitor that might block the ventilation grill in the rear
or top of the cover. This is the most urgent need for the convection to cool internal
components.
* Do not place two monitors close to one another. The magnetic fields may cause either
or both to suffer from shaking images. Likewise, do not place a monitor next to a TV if
possible.
* Place loudspeakers and other sources of magnetic fields at least a few feet away from
the monitor. This reduces the possibility of color purity or geometry problems. The
exception is with respect to good quality shielded multimedia speakers which are
designed to avoid magnetic interference problems.
Other devices which may cause interference include anything with power transformers including
audio equipment, AC or DC wall adapters, and laptop power supplies; fluorescent lamps with
magnetic ballasts; and motorized or heavy duty appliances.
PROBLEM : Garbage Display
When the monitor’s display fills up with incoherent characters, dark and light spaces and
other nonsensical figures, it is called a garbage problem. The character you strike on the
keyboard could appear on the screen somewhere or the keyboard could have no effect. Either
way you have garbage.
What is displayed is only the contents of the video RAM. However, the garbage is enough of
a symptom. What’s happening is the processor is running without directions from the operating
system in the ROM. It is filling the video RAM with nonsense.
The trouble could have been bad VRAM or faulty video chip that are involved in getting a
character from the keyboard to the video output circuits. They all interact and a fault in any of
the chips could trigger off the garbage display. The first chip is Video RAM. Any of them could
have faults and cause garbage.
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Another reason could be that the ROM that is running the operation is not getting its control
signals to the processor correctly and the processor is storing just any characters in the video
RAM. Another reason could be that RAM chips won’t store characters correctly and the video
RAM contents are meaningless. The involved chips must be tested one by one until the bad
one is found and replaced.
There is another way garbage can appear. It could be because of faulty keyboard, which is
generating bad or wrong characters. Inside the keyboard structure are circuits. The keyboard
has its own ROM that contains ASCII (or perhaps another type of code). When a key is
struck, the short in the matrix triggers off the ROM. An ASCII code for the key is generated
and transferred to the computer I/O chip or to the processor directly. If trouble starts in the
keyboard circuits, the wrong ASCII bits could be generated. The bits would then be transferred
to the computer, be stored in video RAM and appear as garbage on the screen. In these
cases the keyboard must be replaced or repaired.
Another rare way garbage could appear is when a defect in the video output circuits generates
in-correct character. The ASCII code byte does not produce the character that is displayed.
The ASCII byte typically is used to form an address. The address is found on a character
ROM. In the character ROM, which could be a separate chip or part of a large video output
chip, at the addresses are patterns of the characters to be displayed.
Every character space on the display is made up of scan lines of brightness. Each line
contains dots of light. Each dot of light is controlled by bits. In the character ROM at an
address is a group of bits. The bits are sent to the display and turn the dots on and off
producing the selected character. That is, of the character ROM (wherever it is in the circuit)
fails. Then it is possible that garbage will appear.
PROBLEM : Blank Display Without Border
If there is blank screen, that is there is no display, then the problem can be either within video
card (which is not sending video signals) or the problem can be with the monitor.
In the monitor the problem can be with the video section, (video preamp, amplifier, series
resistance in the video section to the CRT) or the EHT section.
Unless the EHT is generated the raster can not come and hence the screen will be blank.
Thus for this symptom both video and EHT sections need to checked.
PROBLEM : Vertical and Horizontal Sync Troubles
If computer system has any type of synchronization problem, either vertical (picture rolls up or
down) or horizontal (picture flops sideways), try another monitor. If the trouble clears, monitor
needs to be synchronized.
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When the vertical Sync trouble isn’t in the monitor the computer’s video signal, or the vertical
sync. Signal from the video card, needs testing. Horizontal sync troubles are approached in
the same way that vertical sync troubles are. Vertical sync is usually running around a frequency
of 60 Hz.
The horizontal frequency draws the individual lines that make up raster. Horizontal sync.
Frequency is around 18 to 30 Khz. The more the horizontal frequency more number of lines
are there in one frame of raster. The complete raster changes with the frequency of the
vertical sync. The sync. The sync. Signals from the computer simply make the free running
scanning circuits in the monitor get into step with the computer rhythm. They sync. The scanning
circuits of monitor at the computer’s vertical and horizontal rates. That way the character
spaces in the display will always be at the correct place on the screen.
Vertical Deflection PHOSPHORS

Coil
Focus Grid
Horizontal
Screen Grid Deflection
Coil
Control Grid
Shadow
Mask
Red
Green
Blue
CRT VACCUM WITH
AN INERT GAS
Heater
C S F Convergence
Magnet
Purity Magnet
Fig.: CRT of Colour Monitor
The first signal CRT needs is the horizontal sweep. This is the circuit that generates an
electromagnetic saw tooth waveshape. This signal is connected at the neck of the picture
tube, grabs hold of the cathode ray as it passes through the neck, and draw a line of light
from the left side of the screen of to the right.
The companion vertical signal is made in the vertical sweep circuit. It is also connected at the
neck of the CRT, also takes hod of the cathode ray and pulses down and then up a about 60
times a second.
The two sweep signals are the recipients of a horizontal sync and a vertical sync signal from
the computer’s video card. Troubles in the sweep circuits of the monitor are the following :
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* Vertical Sweep
Faults in the vertical sweep signal can produce a display with not enough vertical
sweep producing back areas at the top and bottom of the screen. A faulty signal can
make the sweep be too full and cause a whitish fold over at the bottom of the screen.
A faulty signal can make the sweep be too full and cause a whitish fold over at the
bottom of the screen. The commonest vertical sweep trouble is no vertical sweep.
When this happens the sweep collapse into a bright white line across the center of the
screen. With a no vertical sweep condition you should always turn the brightness level
down so the repeated scanning of the same line of phosphor doesn’t burn a make in
the phosphor.
* Horizontal Sweep
Problems in the horizontal sweep circuits cause similar symptoms but turned 90 degrees.
There can be not enough horizontal sweep with black spaces on either side, too much
sweep that produces a wide nonlinear picture and no horizontal sweep producing a
bright vertical line from top to bottom.
The horizontal sweep circuit has another important duty to perform. It must originate
the signal that will produce the high anode voltage that is applied to the large bell area
of the CRT. The sweep circuit sends a portion of its signal to a flyback high voltage
circuit. There a voltage (about 15,000 volts for a monochrome CRT and more for a
color CRT screen and brightness will disappear. The fourth input the input the monitor
needs is the vide signals from the computer. The signal can be either monochrome or
color. They enter the monitor at a video amplifier stage and then are routed to the
electron gun of the gun of the CRT. In the gun the video signal modulates the cathode
rate or in the case of color CRT, such as 1st Fig. 4.10, the three color cathode rays(
red, green, and blue) that add together to make the color display. Symptoms that appears
when the video signal is in trouble are the following.
* No Video
This is a variation of no video./ When the composite TV signal exits the computer it is
circuits to the electron gun in the CRT, there will be brightness but no display. The
trouble can be found anywhere from the cable between the computer to the monitor,
through the monitor video circuits right through to the CRT. The electron gun in the
CRT is also a suspect.
* Weak Video
This is a variation of no video. When the composite TV signal exits the computer it is
quite weak. In the monitor is a ;complete video amplifier and output circuit. This circuit
amplifies the vide and makes it strong enough to drive the electron gun in the CRT.
Usually a weak video display will be a fault in the video amplifier and output stage.
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* Smeary Video
This is rate type of trouble but when it happens it is easy to diagnose. The picture looks
like a rag has been wiped over it from left to right. The display smears in that direction.
Video is applied to the CRT at much higher frequencies than a signal such as audio.
While audio has a range from 0-20,000 hertz at its best, video ranges from 0-4,000,000
hertz as it changes from back to light. In the video amplifier in Fig. 4.11 are special
resistors and peaking coils to maintain that frequ3ency. In the electron gun the signal
must be applied cleanly to turn the electron gun off and on at those frequencies. If one
of those peaking coils or resistors fail, the frequency response of the video amplifier
drops drastically and the video cannot from back to light at those speeds. This makes
the picture appear to smear. In addition, if the CRT a should develop open electrodes,
the frequency also cannot be made to change the light spots and dark spots on the
screen fast enough, causing the same type of smear.
* Power Supply Symptoms
There are many variations of power supplies in personal computers. The computers
that connect to independent peripherals such as monitor or disk drive have a supply
of their own. The computers that have a built-in display and/or disk derive share the
supply with the display and all the other circuits.
Power supplies that only have to energize a computer and not peripherals such as
displays and disk drives only need to generate small voltages like +or –5 volts and + or
–12 volts. The voltage must be carefully regulated but otherwise are easy to handle
and maintain.
When these supplies fail the symptom you’ll encounter is a completely dead computer.
The off/on switch won’t turn the computer on.
The supply must not only energize the computer but also must provide operating
voltages for the Monitor and the disk drive, the supplies are much lager and more
complicated. When these supplies act up there could be other symptoms besides the
dead set. The following, are two symptoms you could see.
* Shrunken Display
If the supply is energizing the horizontal and vertical circuits and its output voltage falls,
these circuits could lose poser. If the horizontal output circuit loses voltage it could
amplify the horizontal sweep signal less and the picture tube. The some thing could
happen in the vertical circuit and the picture won’t sweep to the top and bottom of the
display. This could make the picture appear to shrink on four sides. A variation of this
is two sided shrinking.
(128)
* Hum (Shaky display with horizontal stripes)
When the reason for HT power supply trouble is a defective filter capacitor, then the
voltage output of the supply is not filtered properly and will contain a form of 50 Hz um.
This hum is visible in the display. It makes the picture bend. The bending might be
accompanied by thick black horizontal stripes.
OTHER PROBLEMS
A completely green screen would result if the beam was ‘off for the red and blue phosphor
dots but ‘on’ for the green ones. The brightness of the green dots would be controlled by the
green dots would be controlled by the brightness of the beam when it was over each of the
dots.
The more complex pictures that we see are a composite result of a mix of this pattern. Our
eyes would not see the individual dots but their composition into an image.
The triads, or triangles of the three dots of elementary colours-red- red, green and blue can
be seen if you see closely at the screen when it is on.
CONVERGENCE PROBLEMS
If monitor is roughly handled during shipment or while installing, it may suffer from a problem
called ‘Convergence.’
The three electron beams must ideally converged on the same point to illuminate a single
triad of phosphor dots. Unless the monitor is designed well, the three beams will not converge
at one point. Poor convergence will thus result in images with rainbow-line shadow and a loss
of sharpness and detail. Since monochrome monitors have only one electron gun, they will
obviously not face this problem.
COLOUR PURITY PROBLEMS
Colour purity means that the colours on the screen are uniform across the image. The simplest
way to check this is to launch a new document in a Windows-based word processing program
such as Microsoft Word. Then change the view to full screen. If the page appears completely
white, everything is fine. If there are patches of colour in places, you have a colour purity
problem.
This could be due to two reasons-a device outside the monitor (such as an audio speaker)
has created a magnetic field that extends into the tube (called incident static or dynamic
magnetic fields). This could happen, for example, if you put a pair of powerful speakers with
their backs close to the monitor. This is because speakers have magnets inside them.
Another reason could be that over time, the shadow mask has become partially magnetised.
In both the cases, the answer is to ‘degauss’ the monitor. Do this by using the Degauss
function provided in many current models.
(129)
In case this feature is not present, degaussing can be done by taking a special degaussing
coil by a technician qualified. If done incorrectly, Monitor may need replacement.
IMPORTANT SERVICE SAFETY INFORMATION
* Operation of the monitor outside of its cabinet or with its back removed involves a
shock hazard. Work on these models should only be performed by those who are
thoroughly familiar with precautions necessary when working on high voltage equipment.
* Excise care when servicing this chassis with power applied. Many B plus and video
input terminals and exposed which, if carelessly contacted, can cause serious shock
or result in damage to the chassis. Maintain interconnecting ground lead connections
between chassis, picture tube dag and power PCB earth when operating chassis.
Certain HV failures can increase X-rays radiation. The monitor should not be operated
with HV levels exceeding the specified rating for their chassis type. The maximum
operating HV specified for the chassis used in these receivers is 12.5 KV+1 – 2KV at
zero beam current with a line voltage of 220 AC. Higher voltage may also increase
possibility of failure in HV supply.
* It is important to maintain spiffed values of all components in the horizontal and high
voltage circuits and anywhere else in the monitor that monitor that could cause a rise
in high voltage or operating supply voltages. No changes should be made to the original-
design of the monitor.
* It is important to maintain specified values of all components in the horizontal and high
voltage circuits and anywhere else in the monitor that could cause a rise in high
voltage or operating supply voltages. No changes should be made to the original-
design of the monitor.
* Components shown in the shaded areas on the schematic diagram and/or identified
by an S in the placement parts list should be replaced only with exact Factory
recommended replacement parts. The use of unauthorized substitute parts may create
a shock, fire, X-radiation or other hazard.
* To determine the presence of high voltage, use an accurate, high impedance, HV

meter connected between seconds anode lead and the CRT dag grounding device.
When servicing the High Voltage System, remove static charge by connecting a 10K
ohm resistor in series with an insulated wire (such as a test probe) between picture
tube dag and 2nd anode lead. (Before AC line cord is disconnected from AC).
* The picture tube used in some monitors employ integral-implication protection. Replace
with tube of the same type number of continued safety. Do not lift picture tube by the
neck.
* Before returning the monitor to the user perform the following safety checks.
(130)
* Inspect all wires & harmful assemblies to make certain that the wires are not pinched
or that any hardware is not lodged between the chassis and other metal parts in the
monitor.
* Replace all protective devices such as non-metallic control knobs, insulating fishpapers,
cabinet backs, adjustment and compartment covers or shields, isolation resistor-capacity
networks, mechanical insulator, etc.
* To be sure that no shock hazard exists, a check for the presence of leakage current
should be made at ;each exposed metal part having a return path to the chassis ( input
terminal, cabinet metal, screw heads, knobs and/or shafts, etc.) in the following manner.
* Plug the AC line cord directly into a 22V AC receptacle. (Do not use an isolation
Transformer during these checks). All checks must be repeated with the AC line cord
plug connections reversed. (If necessary, a monopolarized adapter plug must be used
only for the purpose of completing these checks).
* If available, measure current using an accurate leakage current tester. Reading of 0.35
MA or more is excessive and indicates a potential shock hazard which must be corrected
before returning the monitor to the owner.
* If a reliable leakage current tester is not available an alternate method of measurement

should be used. Using two chip leads, connect a 1.5K ohm, 10 watt resistor in parallel
ground. Use a VTVM or VOM with 1000 ohms per volts sensitivity, or higher to measure
the AC voltage drop across the resistor. Any reading of 0.35 volts RMS or more is
excessive and indicates a potential shock hazard which must be corrected before
returning the monitor to the owner.
(131)
(132)
== APPENDIX ==
CASE STUDY FOR L & T DRIVES
INDEX SENSOR ASSEMBLY
SERVICE CHECK
1. Power up the drive.

2. Without inserting a disk, move the lever to lock position and check for 0 to 0.5 V
between the PWA connector J3 Pin A11 and G(GND). Next, insert a disk and close
the door the voltage at the same points should be 2.5 to 5.25 V.
ADJUSTMENT
1. Loosen the Index Sensor Screws on quarter turn.

3. Connect channel 1 to PWA TP 1A, Channel 2 to TP 1B, connect the external scope
trigger to TP3 and GND to G.
Set the oscilloscope controls as follows:
INPUT COUPLING MODE AC

VERT MODE ADD
INVERT(CH2) ON
TIME/DIV 0.1 ms
VOLTS/DIV (CH1, CH2) 100 mV
4. Insert a CE Disk and turn the front lever to lock position.

5. Load the read/write heads against the disk and step the head/carriage assembly to
track 2. Adjust the sensor position until the timing between the start of the sweep
(index signal from TP3) and the first part of the index burst (TP 1A, TP 1B) is within -
180 to 820 us.
Note: To delay the Index Burst, move the sensor towards the front bezel.
6. Verify that the timing between the start of the sweep and first peak of the index burst
is between -180 to 820 at side 0 and 1, track 68.
7. Tighten Index Sensor screw.
(133)
TRACK 00 SENSOR ASSEMBLY
Service Checks 1, Track 00 Sensor
1. Power up the drive. (Resets memories in main logic card)

2. Step the head/carriage assembly to a position near the inner stop.
3. Check the following:
a. Track 00 lamp:
The voltage across PWA J3-A12 and G (GND) should be between 0 and 0.5.
b. Track 00 Sensor:
The voltage across PWA J3-A13 and G(GND) should be between 0 and 0.5.
Service Check 2, Track 00 Sensor Position Check
1. With power off, move the head/carriage assembly all the way to the outer edge.
2. Power up the drive
3. Power is applied the head/carriage assembly (J1-26) should be at Low level (0 to
0.4V)
4. Move the head/carriage assembly five steps inward and one step outward. The
voltage should change to a High level of 2.4 to 5.25 V.
WRITE PROTECT SENSOR ASSEMBLY
SERVICE CHECK

2. Check the following with no disk in the drive.
(a) Write Protect Lamp:
The voltage across J3-A8 and G (GND) should be between v1.0 and 1.7V.
(b) Write Protect Sensor:
The voltage across J3-A9 and G (GND) should be between 0 and 0.5 V.
3. Check the following with a write protected disk 9a disk with a write protect seal over
the write protect notch) in the drive and the front lever in lock position.
(a) Write protect Sensor:
The voltage across J3-A9 and G (GND) should be between 2.5 and 5.25V.
WRITE PROTECT SENSOR CONFIRMATION
When the write protect sensor has been replaced. It is necessary to carry out the conforma-
tion described in this section.
(1) Insert the medium equipped with the write protect notch. (CE medium etc).
(2) Measure the output of the TP 11 and confirm that the level is high. In this case, move
the jacket by hand to ensure that the level is always more than 3.3 V at any position.
(3) Insert the medium without the write protect notch.
(134)
(4) Measure the output of TP 11 and confirm that level is less than 3V. In this case, the
level should always be less than 3V when the jacket is any position.
(5) If the output level is not the normal level, unscrew the screw which fixes the sensor
and adjust it to obtain the normal level.
MEDIA SENSOR ASSEMBLY
SERVICE CHECK

2. Perform the following with no disk in the drive.
a. Check for 1.0 to 1.7 V across PWA J3-A14 and G (GND).
b. Check for 0 to 0.5 V across J3-A15 and G (GND).
3. Insert a disk and check the following.
a. Check for 2.5 to 5.25 V across J3-A15 and G (GND).
IN USE LAMP ASSEMBLY
SERVICE CHECK

2. Set interference signal DRIVE SELECT to low level, and install a shorting plug on
shorthand pin DS 0.
3. The lamp should light up.
Note: When the lamp is lit, the voltage across J3-A10 and G (GND) should be between 1.0
and 2.0 V.
INDEX LAMP ASSEMBLY
SERVICE CHECK

2. Check that the voltage across the PWA J3-A7 and G (GND) between 1.0 and 1.7 V.
DRIVE MOTOR ASSEMBLY
SERVICE CHECK

2. Insert a disk and move the front lever to lock position.
3. Set the MOTOR ON signal on the interface to Low Level in order the drive motor.
4. Load the read/write heads against the disk.
5. Connect a counter to TP3 and GND on the PWA.
6. Verify that the index pulse period (TP3) is within 166.7 ms +1.5% (164.2 to 169.2 ms).
(135)
HEAD LOAD SOLENOID
SERVICE CHECK
1. Look through the disk inlet on the front bezel to make sure the pad on the bottom of
the bail is normal.
3. Insert a disk and turn the front lever to lock position.
4. Load the read/write heads against the disk.
5. Make sure that there is a gap between the bail and the carriage arm throughout the
carriage travel.
6. Switch off power to the drive.
7. Remove the disk and turn the front lever to lock position .
8. Look through the disk inlet in the front bezel and verify that the gap between the
unloaded read/write heads is within 0.3 to 0.7 mm. If the gap is larger, perform the
adjustment.
ADJUSTMENT
1. Turn the adjustment screw on the read/off plate until the gap between the read/write
heads is within 0.3 to 0.7 mm. Turning the screw clockwise increases the gap,
counter clockwise decreases it.
2. Perform a service check.
FRONT LEVER
REMOVAL AND REPLACEMENT
1. Turn the Front lever to lock position.

2. Remove the front lever screw with a hex wrench and take the crankshaft out via the
front bezel.
3. For reinstallation, reverse the above procedure.
Note:
1. When attaching the front lever, push it in the direction shown in fig. and secure with
the stop-screw.
2. Fix the front lever so that the stop-screw is even with the slot in the crankshaft.
FRONT BEZEL
1. Remove the front lever stop-screw and the front lever.

2. Remove the front bezel screws and pull the front bezel forward to remove.
3. For reinstallation, reverse the above procedure.
(136)
Note:
1) When reinstalling the front baze, make sure that the bosses on the bezel fit correctly
into the matching hold in the frame before securing.
2) Refer to section 6.10 for front lever fixing instructions.
STEPPER ASSEMBLY

2. Check the head/carriage seek operation by applying the Direction and Step signals
to the interface.
Note: When reinstalling, do not tighten the belt clamp and the steel belt assembly screws
completely. Move the carriage forward and backward with your hand, making sure that it
moves smoothly in both directions. If carriage movement is normal, secure the screws.
ADJUSTMENT
1. Perform the position adjustment for the carriage assembly.
HEAD/CARRIAGE ASSEMBLY
Caution:
The head/carriage assembly is factory adjusted and tested. never attempt to adjust or repair
this internal component.
REDIAL ALIGNMENT CHECK
1. Power up the drive(Reset the PWA memories)
2. Set up a dual trace oscilloscope.

- Connect channel 1 to PWA test point 1A.
- Connect channel 2 to PWA test point 1B.
- Connect scope ground to PWA test point G (GND).
- Connect the external scope trigger probe to PWA test point 3.
Set the oscilloscope controls as follows:
INPUT COUPLING MODE AC
VERT MODE ADD
INVERT (CH2) ON
TIME/DIV. 20ms
VOLTS/DIV. (CH2) 20ms
(137)
3. Insert a CE disk and turn the front lever to lock position

4. Load the read/write heads against the disk and make sure the Track 00 signal (J1-26)
is at low level (0 to 0.4 V)
5. Step the head/carriage from Track 31 to 32. Obtain A/B or B/A, the ratio between the
two amplitude lobes on the scope. Convert the ratio to a position on the CE disk
conversion chart. The positioning error should be within +25um.
6. Step the head/carriage from track 33 to track 32 and check the positioning as in step
5 above.
(138)

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Compiled & Published by CFS Documentation Cell

Centre for Electronics Design and Technology of India

First Edition: 1999

Centre for Electronics Design and Technology of India (CEDTI) is an Autonomous

UNIT CHAPTER NAME PAGE NO.

2 Memory: Concept & Troubleshooting 17

5 Keyboard and Mouse 65

6 Floppy Disk Drives 73

7 Hard Disk Drives 81

9 Monitor and Display Cards 111

Appendix - Case of L & T Drives 133

ARCHITECTURE & CLASSIFICATION OF SYSTEMS

THE BASIC PARTS OF THE IBM PC

An IBM PC, computer has five basic parts:

* An arithmetic logic unit

These parts are associated as shown in Fig. 1-1.

INPUT ARITHMATIC OUTPUT

Fig. 1.1 : The five basic parts of IBM PC

Fig.1.2: Memory and I/O Interface

KEYBOARD IBM PC PRINTER

Fig.1.3 : Standard IBM PC Configuration

KEYBOARD IBM PC PRINTER

FDD & HDD

Fig. 1.4 : IBM PC-AT Systems with Additional Drives

* Industry Standard Architecture

* Industry Standard Architecture (ISA)

* Industry Standard Architecture (ISA) ( 16 Bit ISA BUS)

* VESA Local Bus ( 32 Bit VL Bus )

* Enhanced Industry standard Architecture (EISA) Bus

DIFFERENCES BETWEEN PCS/ XTS/ ATS

The abbreviations used in table on next page are given below:

ISA = Industry Standard Architecture

SYSTEM ATTRIBUTES PC OR XT TYPE AT TYPE

MEMORY: CONCEPT & TROUBLESHOOTING

Solid-state memory faults contribute to a large percentage of computer problems. Memory

Data Storage in Memory

EPROMs cannot be programmed in circuit. The programming voltage is normally 21volts or

CONTROL AND DATA CIRCUITS

Typical Memory Speed Parameters

Enhanced Memory Concepts

Memory speed is closely related to the computer system’s performance. Microprocessors

Cache and Tag Memory

LATEST TYPES OF DRAMs USED ON MOTHERBOARDS

BASIC DRAM OPERATION

An asynchronous interface is one where a minimum period of time is determined to be

PAGE MODE ACCESS

FAST PAGE MODE

HYPER PAGE MODE (EDO)

BURST EDO (BEDO)

SYNCHRONOUS OPERATION (in case of DRAMs)

ENHANCED SDRAM (ESDRAM)

SLDRAM is a protocol-based design, just as RDRAM is, it is an open-industry-standard.

Protocol Based DRAM

THE MICROPROCESSOR & COMPATIBILITY

* Reduced instruction-execution time. Instructions in the 486 take an average of only

The 486 Processor Series

Following are the primary versions of the 486:

External (Level 2) Cache : An external secondary cache (Level 2) of up to 512K or more of

POWER MANAGEMENT ARCHITECTURE

A power-management architecture called System Management Mode(SMM) has been

Table shows the Pentium processor specifications.

Maximum rated speeds 60, 66 ; 75, 90, 100 , 133 MHz

External package 273-pin PGA , 296-pin SPGA

PGA = Pin Grid Array

PC & Peripheral Architecture

PC & Peripheral Architecture