a circuit for performing logical operations on input signals.

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store
state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state
by signals applied to one or more control inputs and will have one or two outputs

combinatorial logic, i.e. circuits for which the output depends only on the inputs. In many instances it is
desirable to have the next output depending on the current output. A simple example is a counter, where
the next number to be output is determined by the current number stored. Circuits that remember their
current output or state are often called sequential logic circuits. Clearly, sequential logic requires the
ability to store the current state. In other words, memory is required by sequential logic circuits, which can
be created with boolean gates. If you arrange the gates correctly, they will remember an input value. This
simple concept is the basis of RAM (random access memory) in computers, and also makes it possible to
create a wide variety of other useful circuits

SR flip-flop circuit provides feedback from both of its outputs back to its opposing inputs and is
commonly used in memory circuits to store a single data bit. Then the SR flip-flop actually has
three inputs, Set, Reset and its current output Q relating to it's current state or history

The main difference between a JK flip-flop and an SR flip-flop is that in the JK flip-flop, both
inputs can be HIGH. When both the J and K inputs are HIGH, the Q output is toggled, which
means that the output alternates between HIGH and LOW. Thereby the invalid condition which
occurs in the SR flipflop is eliminated

Case I: When clock is not given, both master and slave are inactive and there will be no
change in outputs.
Case II: For clock=1, master is active, slave inactive. As J=K=0, output of master ie Q
and Q' will not change. As soon as clock goes to 0, slave becomes active, and master
inactive. But since input to slave S and R is same, output of slave will also remain
same.
Case III: For clock=1, master is active and slave is inactive. When J=0 and K=1, outputs
of master will be Q=0, Q'=1, which will be inputs to slave. When clock=0, slave
becomes active and takes inputs 0,1 to give output Q=0, Q'=1. This output will not
change if clock is again made 1and then 0. Hence we get a stable output from master
and slave.
Case IV: For clock=1, master is active and slave is inactive. When J=1 and K=0,
outputs of master will be Q=1, Q'=0, which will be inputs to slave. When clock=0, slave
becomes active and takes inputs 1,0 to give output Q=1, Q'=0. This output will not
change if clock is again made 1 and then 0. Hence we get a stable output from master
and slave.
Case V: When clock =1, J=K=1, master output will toggle. So S and R will invert. But
slave remains inactive all this time since clock is 1. As soon as clock becomes 0, slave
becomes active and master becomes inactive. So slave will also toggle. These changed
outputs are returned through feedback to the master, but master does not respond to
them because clock is now 0 and master is inactive. Thus, in one clock period, master
and slave both toggle only once, avoiding race condition caused by multiple toggling.