Chapter 6.

Operations of
Micro Processor System
• In this chapter:
– General Flow Chart
– Reset operation
– Instruction Fetching and Execution
– Interrupt operation
– Direct Memory Access – DMA operation, and
– Wait State

6.1. General Flow Chart

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 6.2. Reset
• Also called COLD START when reset pin is
activated (low or high logic level when power is on)
• Clear all current states:
– CPU registers, esp. Flag bits
– Mask on interrupt, DMA
– All buses are floated
• Set Program Counter (or CS:IP) with:
– Fix value: reset address, FE x86 start at FFFF0h, or
– Content of a specified memory location: reset vector
• => starting of executing the program stored in ROM
• Student HW: Expl diode, design high active reset

A typical reset circuit

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 80x86 Reset and Clock Circuit

6.3. Fetching and Execution an Instr

• An executable program is a list of binary operational
codes and operand(s) [or instructions], so called
machine language, one by one, no gap.
• An instruction may include:
– one or several bytes – CISC (not RISC)
– one or several machine cycles to operate: OpCode fetch,
MEMR, MEMW, IOR, IOW
– Each machine cycle is divided 4 to 6 clock cycles or T
states

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 Fetching and Execution an Instruction
• After decoding, instruction decoder inside CPU will
give out information:
– Number of bytes of an instruction => increasing PC or
CS:IP to point the next instr.
– Instr group: movement, arithmetic, logic, branch,
control...
– Addressing mode: how can to access to read or write an
operand: immediate, register, direct, register indirect
(base, index, pointer), mem indirect, implied ...
– Data type: bit, byte, word, double word,
• Inc word ptr [bx] and cx,[si]
– Source and Destination operands, often dest. and source
must be same size

Case study 1: MOV AH,7FH instr

• Case study 1:
– mov ah,7fh instruction: move number 7fh to ah
register, immediate addressing mode – 7fh is
constant
• Opcode in binary: B4 7F
• Cycle 1 - Opcode fetching: CPU generates address to
code and –MEMR => B4 code to Inst Reg, after
decoding... some information:
1. How many byte inst? It’s 2 byes => IP+2 points to next inst
2. What is inst group? data movement group!
3. What is type of data? It’s 8 bit data!
4. What is addressing mode? Immediate! ah is destination
Operand

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 MOV AH,7FH instr.

Bus cycles for MOV AH, 7Fh

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Case study 2: MOV CL, [1234h] instr
• Move to CL a contain from data memory is
addressed by DS:1234h:
– 4 byte inst, may in 8 bit/16 bit or 32 bit bus
– Data 16 (or 32 bit): low byte is first, hi byte after
• Mnemonics: mov cl, [1234]
• Machine Language, 4 byte instr: 8A – 0E – 34 - 12
• Fetching:
– Address = E2345 – E2346 – E2347 – E2348
– -MEMR low for 4 times (4 cycles) to read instr.
– Data bus = 8A – 0E – 34 - 12

MOV CL, [1234h] instruction

• Instr. Decoding:
– 4 byte inst => IP + 4 to next instr.
– Group: Data movement
– Data type: byte
– Addressing Mode: direct – address of data is in
instr. clearly, CL is destination operand
• After decoding then executing:
– Address = DS:1234 (in this ex. E3234)
– -MEMR is activated (low) for 1 time (MEMR bus
cycles)
– Data from data mem (E3234) is moved to CL
register
– Student homework: draw timing diagram of
this instr.

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 MOV CL, [1234h]

Case study 3: AND [SI],AL instr.

• Suppose ES was activated only, this instr. reads
content data memory at ES:SI, SI is containing offset
address of dest. op. AL is source operand
• Machine Code Instruction:20 04; AND [SI],AL
– 1st cycle: CS:IP= ADCD:0100, -MEMR=low then reading
1st opcode to Instr Reg. After knowing that this Instr is 2
bytes, then next
– 2nd cycle: CS:IP= ADCD:0101, -MEMR=low then reading
2nd opcode to Instr Reg. After decoding knowing that

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 Case study 3: AND [SI],AL instr.
• That is 2 byte instr, then IP+2
• Instr. Group: Logical Group, AND instr.
• Addressing mode: register indirect, SI (ES was
defined previously instead DS with an prefix
segment override code)
• Data type: byte
• Destination operand: memory location
• Source operand: AL
• Student homework: draw timing diagram
of this instr.

Case study 3: AND [SI],AL instr.

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 6.4. Interrupt
• When CPU is executing a main
program, at the instr. No n, there
is 1 request (interrupt request –
IRQ) from an IO device, suddenly
likes keyboard or mouse, It’ll:
– Continue executing the current instr
– Store context of main prog to Stack
Mem: Flags Reg, CS, IP of instr. No
n+1,
– Load specified address of int.
subroutine ISR), that services
requested IO device and execute
– After finishing ISR, CPU executes
IRET (intr. return), restoring IP, CS
and Flags, and main prog’s
continued

Features of Interrupt operation

• This is a special operation mode of CPU and is
a very effective method, since this checking
takes up substantial processing time.
• For online computer/uP sys. processing:
– Multi-tasks,
– Multi-IO devices management and
– Multi-threads for multi-programs
• IRQ from IO is random and more than an IO in
a system => may be conflicted => resolving
this problem: Interrupt priority

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 How to load address of ISR?
• Specified address, designed by CPU maker:
– Atmega8 (16..256), refer next page
• Interrupt Vector Table – IVT
– A location of RAM contains hundreds of ISR
addresses and their contains may be changed by
system prog or user prog or even virus programs
– An int. vector type was assigned for an IO device
– For Ex. PC has 256 types of int and 256 of 4 bytes
location are mapped in the 1st KiloByte of mem

Case study: X86 IVT

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 Interrupt Priority
• An concept for resolving conflicts when more than an
IO devides need CPU serving. The higher devices
may interrupt the lower ones to obtain service right
• Each IO device was assigned it’s priority level, for ex
0 to 7, often, Zero Level is highest and 7 level is
lowest priority
• If CPU is executing sub program No4 (ISR),
– there’s a request from IO device No5 or bigger (bigger is
lower priority), system will ignore.
– But there’s a request from IO device No3 or less (higher),
system will interrupt Subroutine No4, store it’s context to
stack mem and CPU will execute ISR No3. After executing
IRS No3, system will restore ISR No4 context and continue
– Phrase “System” here include CPU and Intr. Priority
Controller – PIC, Intel 8259A is famous PIC chip

Case Study: PC Interrupt

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 Case Study: PC Interrupt Requests
PC interrupt request signals are listed in priority order,
highest is first and lowest is last.
• NMI: Non maskable Int. for DRAM parity or data
to/from IO error
• IRQ0: 55ms, timer for OS
• IRQ1: Keyboard Int. when a key is pressed
• IRQ2: for extended IO:
– IRQ8: Real time clock (RTC – Dallas 12C887) Alarm
– IRQ9, re-directed for IRQ2, end of a screen scan cycle
– IRQ10; Available
– IRQ11: Available
– IRQ12: for PS/2 Mouse

Case Study: PC Interrupt Requests

– IRQ13: Math Processor request
– IRQ14: Hard disk controller, ISA bus
– IRQ15: Available or Watch Dog Timer
• IRQ3: RS232 port No2
• IRR4: RS232 port No1
• IRQ5: LPT port No2
• IRQ6: Floppy disk Controller, for 4 drivers
• IRQ7: LPT ports No1

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 Case Study 2: AVR interrupt
• Student self study one of interrupt mechanism
of an micro controller and present in front of
class:
– Atmel 89C52 or
– Atmel AT mega 32, or
– PIC 16F877
• Distinguish Interrupt Vector Table and
Interrupt specified Addresses

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6.5. Direct Memory Access - DMA
• Some application of interface to IO device that
system needs speed of data transport very fast,
CPU with software can’t satisfy, the DMA
Controller is designed for those application.
• Notion of DMA: is a type of transportation
data between Central System and an IO device
w/o CPU’s controlling.
• DMA process:
1. Housekeeping: system prog run a procedure for
initializing and preparing DMA operation:
• Where data from/to (mem=>IO or IO=> mem)

DMA
• Load Address of data mem location that will be
transmitted or Received to DMAC’s address register
• Load length of data block to DMAC’s counter, byte or
word
(Case study: IO Read – Mem Write DMA bus cycles)
2. On demands, IOport read data from IO device and
save into IO Port’s data buffer (KBs)
3. IOport send DRQ to DMAController
4. DMAC generates Hold Request HRQ to CPU and
CPU goes to sleep - halted.
5. CPU stops executing current prog at once and
replies HLDA.

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 Block diagram of DMA operation

DMA
6. When receiving HLDA, DMAC will generate signals
simultaneously to execute a DMA bus cycle:
– -DACK (likes chip select) and -IOR => data from IO Port will be read
to system data bus
– Address of Data mem and -MEMW => data will be saved to mem
7. DMAC will:
– Decrease DMAC’s data block counter, if counter = 0 then (8)
– Increase address to point next data mem location,( inc addr reg.)
– Goto (6)
8. finishing DMA operation: -DACK is inactivated => IOport’ll
inactivate DRQ, DMAC’ll inactvate HRQ and CPU’ll
inactivate HLDA, system will continue operation normally
after some (2) clock cycles of delay for stable.

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 Comparison 2 modes Case Study
• Transfer 1KB from Hi Speed IO to Central Sys
– CPU program:
Init: Mov bx, DesAddress; start address of data buffer, to
Mov dx, IOPortAddress; from
Mov cx,400h ; data size
Trans:
in al, dx ; start transferring 2 bytes code, 1 byte Exe
mov [bx],al ; copy al to data buffer, 2 bytes code, 1 byte exe
inc bx ; Increase data buffer pointer, 2 byte code
loop Trans ; cx<= cx-1, if cx=0 then next inst else goto Trans
; 2 bytes code only
– 8 bytes code and 2 byte execution = 10 bytes
– But DMA mode: Initializing phase likes CPU mode, but transfer only 1
bus cycle: IOR-MEMW

6.6. Wait States

• To synchronize between CPU and mem or IO
device with lower speed.
• In these cases, whenever CPU reads or writes,
the Mem controller or IO device has to
generate Ready signal to inform that it’s not
Ready yet and CPU will insert 1 or several
clock cycle(s) to prolong time of all bus
signals, these clock cycles are called Wait
State or TW

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WSes

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