MICROPROCESSOR

AND
ASSEMBLY LANGUAGE

By Bui Quoc Anh

Hanoi University of Technology
1984-2012
(The Confidential Lecture
for HUT’s Adv. Prog ME K54 only)
8/24/2012 1

PART 2
MICRO PROCESSING
TECHNIQUES
• In this part:
– Codes, Numbers and calculation
– Micro processor and micro computer
structures (µP, buses, memories, IO ports...)
– Operation of µP in a system

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 Chapter 4. Number and Code in µP
and computer system
• In this chapter:
– bit, byte, word, double word and quad-byte
numbers
– BCD, Hex numbers
– Signed integer numbers
– Real: fixed and floating point numbers
– ASCII set

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4.1. Natural numbers – counting

numbers:
• What is a bit?
• Definition a (according to Microsoft Macro
Assembler) nybble, a group of 4 bit, form b3 down to
b0
– byte, LSB and MSB, a group of 8 bit, from b7 down to b0:
1011 0100b
– word,
– double word and
– Quad byte
– 80 bit number,
– A number N = bn-12n-1 + bn-22n-2 +... + b121 + b020
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 4.2. Binary Coded Decimal
or 8421 BCD
• Grouping 4 bit (nybble) to describe a 1 digit of decimal
• 0000, 0001, 0010... 1001b ~ 0 to 9d
• Packaged BCD: 4 bit per digit, a byte ~ 2 digits
• Unpackaged BCD: 1 byte for a BCD digit
• Invalid BCD numbers: 1010b to 1111b
• Adding 2 BCD numbers:
– 24+13 = 37 ~ 0010 0100 + 0001 0011 = 0011 0111 OK!
– 15+9 = 24 ~ 0001 0101 + 0000 1001 = 0001 1110 Invalid
add 6 to invalid result: 0001 1110 + 0000 0110 = 0010 0100
http://academic.evergreen.edu/projects/biophysics/technote
s/program/bcd.htm for more calculations of BCD
8/24/2012 5

4.3. Hexadecimal number

• A group of 4 bit describes a range of 16
values, from 0 to 9, A to F, (a to f is available)
• So called: hexa, hex
• Signing: $1C8F, $ABBA, 4CDh, 0abcdh
• Some time look at this number easier than
decimal, especially in cases of hardware
testing, checking...

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 4.4. Calculating with natural numbers
• Addition:
– 2 operands are same size: 8, 16 or 32... bit
– Additioner and additionant are distinguished
– Beside the sumary, the additions may generate a
carry out bit when overflow
• Subtruction:
– Beside the difference, the subtractions may
generate a borrow out bit when negation

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4.5. Calculating with natural numbers

• Multiplication:
– Two 8 bit numbers are multiplied, product is 16 bit
and so on
– The multiplier differs the multiplicant.
• Division:
– The divident size must be twice the divisor,
another word, a 16 bit can divide a 8 bit, quotient
is 8 bit and remainder 8 bit too and so forth.
– The remainder may be more than divisor, Error!
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 4.6. Integral/integer/signed
numbers
• So called signed number,
• Format:
– 8 bit: -128 to +127, short int (depending of individual PL)
language
– 16 bit: -32,768 to +32,767, int,
– 32 long int?
– 80 bit?
• Presenting of an integer:
– MSB is signed bit, if=1 then negative numb, vs, this
method isn’t often used now, weak point: 2 present for zero
+0 and -0
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4.6. Integral numbers/integer

(2’complement numbers)
• All bit is carrying its significance, but the MSB is
negative number
• N = - bn-12n-1 + bn-22n-2 +... + b121 + b020
• the equation A-B = A+(-B) is OK for elect and math.
• Case study, for 16 bit example:
– No -1d: 1111 1111 1111 1111b
– No -32,768d: 1000 0000 0000 0000b
– No +32,767d: 0111 1111 1111 1111b
• What is Integer Overflow?
– -32,768 – 1 =? and +32,767 +1 =?

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 4.7. Real numbers
• What’s a real number?
• Fixed point numbers:
– Using some bits to present the integer field, left of
the dot, and some bit to present the fraction part,
right of the dot.
– Often in a system, these portion format is fixed
– For example: A fixed point format includes 16 bit
integer and 8 bit fraction. How can to present the
number 128.34?

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4.7. Real numbers (Con’t)

• Floating Point number:
– N = 1736.37, can present:
• N=173637*10-2
• N=17.3637*102
• The presentation of N=A * 10B is called
floating point and presented mantissa A and
exponent B only, The num 10 is implied
• In a system, the real number is presented in
format: N=A*2B
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 4.7. Real numbers (Con’t)
• IEEE 754 Standard:
– Preparing from 1982, issuing in 1985 by IEEE
according to US Government’s order
– 3 formats are available: Single (32 bit), Double (64
bit) and Extended Precision (80 bit)
– 3 fields: Sign bit, Power bits and Significant bits
– There are some of weak points but it’s the best in a
dozen of other presentations, calculating more
exactly and suitable for electronic chip designing
8/24/2012 13

4.7. Real numbers (Con’t)

• Case study: IEEE-754 for single precision
format:
– 32 bit, in 3 fields
• MSB: sign bit, iff it’s equal 1, the number is negative,
and vs.
• Exponent/Power: The next 8 bit from the left is power
value, excess 127. Calculate normally and minus to 127
• Significant (not mantissa): remainders

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 4.7. Real numbers (Con’t)
• Significant 23 bits in the most right:
– A hidden bit 0 with value 20=1, always exists in all cases of
calculation, but it is absent in presentation (!)
– Formula to calculate its value:
S = 1+ b12-1 + b22-2 +... + b232-23
• Exercises:
– Convert to decimal: C1E0 0000h
– The biggets, smallest and zero nearest (resolution) values

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4.7. Real numbers (Con’t)

• The double precision format
– Signed bit: MSB
– Power: next 11 bits from the left, excess 1023
– Significant: Remainders, hidden 20

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 4.8. ASCII
• American Standard Code for Information Interchange
• Applied to many types of communication equipment,
peripherals...
• 7 bit, presents 128 codes, divided into
– Control characters: 00-1Fh
– Special characters: symbols, sign, brackets... 20h-2Fh,
3Ah-40h, 5Bh-60h, 7Bh-7Fh
– Arabian number: 30h to 39h ~ 0 to 9
– Upper case characters: 41h-5Ah ~ A to Z
– Lower case characters: 61h to 7Ah ~ a to z
• Refer an ASCII and extended ASCII table as your

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Chapter 5. Introduction of Micro

Processor System
• In this chapter:
– General block diagram
– Micro Processors
– Semiconductor Memories, Mapping and
interfacing
– Controllers, Timers
– InOut ports and mapping
– Peripherals and interfacing
– System and IO buses

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 5.1. A Micro Processor System

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Modern Computer Block Diagrams

An Intel® Core™ Duo Processor An Intel® Core™ i7-3770

T2700 System Processor System
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 5.2. Micro Processor - CPU
• Central Processing Unit and µP name for CPU in an
IC technology or micro computer
• The portion of a system that carries out the instruc-
tions of a program, and is the primary element
carrying out the computer's functions, by the way of
execution of processing binary variables and control
IO devices:
– Instruction fetching from program mem, one by one or PL
– Decoding an instruction to micro instructions and signals
– Fetching operands from data mem or registers,
– Processing and Saving the results (main result and/or
update aux. result - flags)
– Sensing input events for special operation modes
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5.2. Micro Processor - CPU

CPU classifications:
• Number of data bit (of accumulator or ALU that in an
instruction, CPU can process): 4, 8, 16, 32, 64, 128bit
• Capacity of memory management: KBs, MBs, GBs
• Rate of processing:
– Mips, Gips,
– Clock multiplying,
– Subscalar, Pipeline or scalar, superscalar
• RISC vs CISC
• DSP
• Micro controllers – all in one
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 5.2. Micro Processor - CPU
CPU classifications:
• Pinning/Signaling:
– data and address bit or multiplexed
– Status and control bits
• Register set
• Instruction set:
– 1, 2 or 3 operands
– Addressing modes
• Power consumption:
– Slow/sleep modes,
– Mips/Wattage

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5.2. Micro Processor - CPU

CPU classifications:
• Packaging:
– DIP,
– PLCC,
– SOIC,
– FQFP,
– TSOP,
– LGA,
– BGA...

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 5.2. Micro Processor - CPU
Structure of a CPU:
• Control Unit, CU: decoding program instructions and
controlling/creating all signals according to a clock
source:
– Instruction register and queue
– Instruction decoder
• Execution Unit:
– ALU – Arithmetic - Logic Unit:
• Arithmetic: Add, Sub, mul, div, inc, dec, compare,
• Logic: AND, OR, XOR, NOT, shift, rotate. test...

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5.2. Micro Processor - CPU

Structure of a CPU:
• Registers:
– Accumulator: where to keep an operand and result
– Multipurpose Registers for Address, Data, string...
– Status/condition Code [flags] Register: auxiliary result of
process: Zero, Carry, Negative, oVerflow, Parity, Aux
Carry and control bits
• Bus interface unit (BIU), optionally:
– Available in powerful CPU, likes Intel 16/32/64 bit
– For calculation the address of memories (program or data)
or IO
– Segment or page registers to keep hi address bits

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 5.2. Micro Processor - CPU
Structure of a CPU:
• Clock section: to multiply or divide...
• Bus control: Interrupt and DMA management
logic
• Optional: Cache management and memory (for
hi-end only)
• Internal bus

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5.2. Micro Processor - CPU

Famous CPU producers:
– Powerful: Intel, AMD, SPARC, Motorola, IBM
– DSP: Texas Instrument, Motorola
– Micro controllers: AVR, ARM CoreTex (ST,
Microchip, Atmel, Samsung, TI, NXP…)

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 CPU Case Study: Intel 80x86
• History of development of CPU:
– Early 1970s, the first 4 bit microprocessor 4004, then 4040
– 1972-1976: 8008, 8080 and 8085, Intel 8 bit, multipurpose
µP and their IO ports and controllers
– Later of 1978/79: 8086, 8088 the 16 bit CPU introduced; in
this time, the 8bit microcontroller 8031, the precursor of
series of 8x51 and math processor 8087 and IO processor
8089; 8096 the 16 bit µC
– 1982: 80286, 80287, 16 bit 80186;
– 1985/89: 80386DX and 80386SX, 80486DX, 94: 80386EX
– 93: Pentium, 94:80486DX4, 97:P5-MMX,
– 97: PenII, 99:PIII,
– 06: DualCore
– …
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CPU Case Study: Intel 80x86

• 16/32 bit MPU and 64 bit hi-end series
backward compatible
• Control Unit
• Execution Unit
• Bus Interface Unit
• (Later series): 8 of 80 bit Floating Point
Registers

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 x86 Specifications:
• 16/32 bit of ALU and registers
– 8086: 16 data bit, 20 addr bit => 1MB mem space
– 80286: 16 data bit, 24 addr bit => 16MB MS
– 386 and up, 16/32 data bit, 32 addr => 4GB MS
– 16 bit for IO port => 64K IO ports
• 3 status bit S0, S1 and S2 => 8 available bus cycles:
– Opcode fetch: read code from prog mem, -MEMR
– Data Mem Read, read data from data mem, -MEMR
– Data Mem Write, write to data mem, -MEMW
– IO port Read, read from Input port, -IOR
– IO port Write, write to output port, -IOW
– Interrupt Acknowledge, - INTA
– Halt and
– Bus idle
8/24/2012 31

80x86 Main Signals

• AD0 to AD15: 16 addr and • NMI
data bit multiplexed • RESET
• Hi addr. A16-A19 (S3-S6) • CLOCK
• /RD • /BHE and A0
• READY – 00 whole word
• INTR – 01 upper byte at odd add
– 10 lower byte at even add
• /TEST: wait instruction
– 11 non
function as a NOP for test
from 1 to 0 • S4 and S3:
– 00: Alt data, 01: Stack,
– 10: Code or none, 11: Data

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 Main signals
• S0, S1, S2 signals: in max mode, they are
generated out 8 corresponding of bus cycles
– 000: Interrupt Acknowledge
– 001: Read IO Port
– 010: Write IO port
– 011: Halt, wait for external interrupt
– 100: Fetch operational code
– 101: Read data memory
– 110: Write data memory
– 111: Passive

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Internal Block Diagram of x86

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 Internal Block Diagram of x86
• Two functional parts: BIU and EU => speeds
up processing
• What are Flags, Registers, Segment, ALU,
Queue... in the execution unit ?
– Flag: is a flip flops retains sub-result of executions,
will be set (1) or reset (0) and condition of
branching of execution
– Flag register: a 16 bit register, 9 bits are used:
• ZF (Zero) = 1 indicates the previous result is zeroed, f.e.
• CF (Carry) = 1 => result of calculation out of MSB, f.e.
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• OF OverFlow will be set when sumary of 2 positive numbers is

negative one and vs.
• AF – Auxiliary, carry out from 4 lower bit to higher, for BCD
calculations
• SF (Sign), to inform that previous result of calculation is negative
• PF (Parity): number of bit 1 is parity
– 3 control flags:
• IF – interrupt enable (mask) flag, when reset (zero), no interrupt
will be acceptable, except NMI ( later)
• DF: Direction of string processing, set – down, reset – up
• TF: Trap flag is used for single step exec, for debugging
• Write a program segment to move 256 bytes from Source to Dest
with DF=1

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 General Purpose Registers
• 8 GP Regs of 8 bit: AH, AL, BH, ... and DL
• 4 of 16 bit GP Regs, combined from 8 bit regs
– AL: Accumulator, keeping 1 of operands and
result of processing, has some special functions:
• Interfacing to 8 bit peripherals via In/Out ports
• 8 bit multiplicant and quotion of division
• Xlat instruction
• Decimal arithmetic
– AH: byte multiply and divide
– AX: 16 bit IN/OUT, Word multiply and divide
– BX (base): translate, logical 16 bit address bas reg
8/24/2012 37

General Purpose Registers

– CX: counter, for string or loop counting, it’s
content inc or dec after an operation depending to
DF
– CL: number of times of rotation or shifting
– DX: Data:
• Indirect IO port Address, esp. the addr. >= FFh
• Word multiply and divide

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 Segment Registers
• There are 4 (or 6 for later versions) of 16 bit segment
registers, point to a base of memory location: progam
and data.
• Code, Data, Extra and Stack Segments (386- F, G
reserving for data areas).
• Content of a segment will be combined with a
affective addr (logical addr, 16 or 32 bit) to give out
20 (or 32) bit physical address of memory
• (CS*16)+ (IP) => physical addr. of Code Program
– Code Segment – CS: points to the base of program memory
location which being executed by CPU

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Memory Physical Address

• How to create a 20
bit memory address:
– 16 bit segment is left
shift 4 times before
adding
– Suppose offset addr
is 20 bit with 4
higher bits = 0
– Result 20 bit Phy
Addr.
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 Information in Memory
• Program memory: (CS:IP)
– Contains an executing program (code) that is being
processed by CPU, at a moment, only 1 program is
executed, also called code memory.
• Data Memory: DS (or ES) and 1 of 24 modes
– Contains variables of executing program.
– Distinguish variable and constant. Where is a
constant contained?
• Stack Memory: SS:SP
– Modern computers, reserved data memories
(RAM) for each thread or sub programs
8/24/2012 41

Stack Memory and Stack Pointer

• Stack Mem: contains some specified information of
executing prog likes addr of next instruction, flags
and data... (context of main program)
• LIFO: data is stacked (push) or removed (pull/pop)
with mechanism of Last In – First Out
• Stack pointer (SP) always points to Top Of Stack
TOS is lower base)
• Word access: SP auto increment (after popping) and
decrement 2 after pushing,
• Some case of accessing stack mem:
– Branching/Jump/return to sub program from main program:
Auto Inc/Dec, FE: JSB, Call, Ret
– Push or Pop instructions directly, FE push ax

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• Pushing into Stack
Mem:
– 2 byte are pushed in
to Stack mem
– SP=SP-2
• Poping (Pulling)
– Draw a schema to
describe an action of
x86 when poping 2
bytes with numerical
example for SS, SP…
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x86 Memory Map

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 Code, Data and Stack Concuring

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Over-lapping memory

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 Pointers: IP
• Its content points to specified a memory
location, for Code and Stack only:
– Instruction pointer:
• 16 (or 32) bit, points to the next instruction will be
executed. When CPU is executing inst No n, content of
IP, combined to CS, points to inst. No n+1
• It’s content is added number of byte of previous inst.
• When executing main prog, Inst. No n, if there is an
event - interrupt request from outside or jump to
subroutine, CPU will push IP, CS [and Flag] in to stack
mem.
• When return, CPU will execute Istr. No n+1, and main
prog is executed continuously
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CS:IP

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 Pointers: SP
• SP or Stack Pointer:
– SS content is loaded by OS or monitor after
starting, unspecified by CPU maker
– SP content is loaded by OS or monitor after
starting, 0FFFFh usually.
– SP’ll auto-decrease 2 after pushing a word to
Stack Mem: push, call, Int instr. and Ext Int event
– SP’ll auto-increase 2 before popping a word to
Stack Mem: pop, ret, iret instructions
– For Ex. push ax ; content AX is pushed to
Stack and SP decreases 2
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SS:SP

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 Base Pointers : BP
• It’s a 16 bit reg, used likes BX, its content is
combined to a data segment (DS, ES, FS,GS) to
generate out physical address of memory is combined
– For ex.: mov al, [bp] ; copy a byte in data
memory, its addr =
(DS:BP)
– Numerical data for previous instruction: DS=2345h,
BP=789Ah, ((DS)(BP))=4Dh
• It’s an indirect Addressing modes, 1 of 24 addressing
modes of data memory accessing
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Index Registers: Source and

Destination Index Reg.
• 2 x 16 bit registers are used likes BX and BP
• Additional: for string operations
• For Ex:
mov cx, 100h ; Counter = 256
mov si, 3000h ; source mem location at 3000h
mov di, 4000h ; dest mem location at 4000h
cld ; Clear DF SI, DI inc. after copying
movsb ; copy 256 bytes from DS:3000h to
ES:4000h mem location
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 Intel 80386 and later

8/24/2012 53

16 bit Segment Registers

• Memory addressing: (show figure)
• Segment Regs: are 16 bit regs, used to point to the
base of memory locations. Their contents are
combined to ‘an offset address or logical’ in order to
create physical memory address (20/32 bit)
– Code segment (CS) points to base of program mem that
CPU is processing: 64KB (16bit) or 4GB (32 bit),
combined with IP (16/32) to generate full address of prog
mem.
– Data segment (DS) points to base of data memory, that
CPU is reading and writing, 64K or 4G, combined to some
content of reg or data to give out full physical address of
data mem.
– Extra segment (ES) likes DS
– Stack segment (SS)
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 CPU Case Study: Intel 80x86

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MultiCore Processor

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 5.3. Semiconductor Memories
• A device using for storing binary data in some
format: bit or byte or word, even longword.
• Physically: ROMs or RAMs,
• Logically Prog, Data, Stack...
– Why is ROM/RAM ratio difference between computer and
ES?
• Signal and pins:
– Data bit: in/out or out only (ROMs)
– Address bit: capacity of mem, n bit => 2n mem locations
– /Read or Read and -Write (RAM)
– /ChipSelect(s) or –ChipEnable(s)

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5.3.1. Read Only Memory:

• Some types: ROM, PROM, EPROM, EEROM and
EAROM/Flash
• Student difine ROM types?
• For keeping binary information, often in byte
package, it’s content may be kept forever (ROM),
even DC power is lost or dozen years without power
supply (Flash)
• To keep fixed data or fixed/started program likes
BIOS
• Size: KBs to hundreds of KB
• Access time: from 80 to 120 ns

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 5.3.1. ROMs

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ROM
• Some types of ROM:
– Seri 27Cxxx: EPROM, a
crystal window for erasing
by ultraviolet beam
• 27C128: EPROM, 128 K bit
=> 16 KB
• 27C512: EPROM, 512 K bit
=> 64 KB
– Seri 28/29Cxxx: EEROM
or Flash
• 29C512: 64 KB of Flash
• 28C1000: Flash 128KByte
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 A embedded system with ATmega32 and 128KWord
EPROM - by Khuc Truong Son, studt CE47

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Non-volatile memories
• Non-volatile memory, nonvolatile memory,
NVM or non-volatile storage, is computer
memory that can retain the stored information
even when not powered.
• Examples of non-volatile memory include:
– ROM, flash memory,
– Most types of magnetic computer storage devices
(e.g. hard disks, floppy disk drives, and magnetic
tape),
– Optical disc drives, and
– Early computer storage methods such as paper
tape and punch cards.
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 NAND vs NOR Flash Mem
• NAND Flash: small cell size => low cost of
stored data => has been used primarily high
density devices (camera card, USB..)
– Read speed 18..24MB/s, Write speed 2..8MB,
Erase time: 2ms. I/O Indirect access
• NOR Flash: has typically been used for code
storage and direct execution in mobile device
like Mobil-phone, PDA
– Read 100MB/s, Write 0.5MB/s, Erase 900ms

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Comparison of NOR and NAND Flash

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 5.3.2. Static RAM
5.3.2. SRAM: Read or Write Mem
– To store binary temporary information as long as
dc power supply is applied (no exception power
needed – Static). Data’ll be lost when power is off.
– Fast: 5 to 70 ns access time
– Low capacity: KB to hundreds of KB
– Hi Power and expensive
– Easier interface compare to Dynamic RAM
– Using for small, simple systems, often in
embedded system

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SRAM

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 5.3.3. Dynamic RAM
• Keeping data temporary, Read and Write
• Data will be lost in 10ms after writing=> having to
“refresh”
• Refresh: Re-Write after Reading every 6-8 ms. Not
easy for interface, not suitable for small sys. normally
• Cheaper, very high capacity, hundreds Meg or some
Giga bit/chip or 2/4Gbit/chip, even 8Gbit/chip now
• Packaging in bank or bar, n bit address = 22n bit cells
• Always controlled by a dedicated DRAM controller:
– Addr generates, decoding, read/write
– Refreshing: n bit addr, RAS is activated and READ mode
– 1 of 2n groups is refreshed at the moment.
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DRAM

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 DRAM Bank interface

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DRAMs
• SDRAM: Synchronous
interface, wait for clock input
• DDR SDRAM - Double Data
Rate, twice bandwidth, often
64 bit
• DDR2 SDRAM: 4 data per
clock cycle
– Exam: @ 100MHz x 8byte x 2
(clk Mult) x 2 (dual rate) =>
3200MB/s

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 5.3.4. Memory Mapping
• Mem mapping is the techniques of arranging
of mem chips, depend of:
– What CPU type is and it’s signals
– What type, capacity, quantity and total cap of
ROMs and RAMs will be used in the system
– Where ROMs must be located for starting of
executing when power on
– Where RAMs are for re-writeable system’s
variables, interrupt vector table, stack mem...
– Next is example of a x86 system mem mapping
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x86 Mem Map

• 1M Byte DRAM of real mode
– 1st KB for IVT
– 256 bytes next for BIOS data area
– 640 KB for flexible using
– 384 KB for shadow mem or ROM
BIOS. It can’t use 2 zone parallel
at same time
• 384 KB for special uses:
– 64-128 KB for ROM BIOS
– 128 KB for Ext. BIOS
– 128 KB for Disp Page Mem
• Memory shadow: more than 1
mem zones concur address. At
a moment, 1 zone is valid only
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 AT Mega 16 Mem & IO Mapping
• 8 bit RISC micro
controller, All-In-One
• In System Re-
Programmable Mem
Map:
– 16 KB (256KB)
– Program Counter (PC)
13 bit, points to the next
instruction – will be
executed

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AT Mega 16 – Data Map

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 5.3.5.Memory Address Decoding
• Is a technique of gathering higher addess bits from
CPU, then combining them together by logic gates
and decoders to create chip select signals with the
rule: at the moment (1 bus cycle), only 1 of many mem
locations (byte/word/longword) in the system, is
selected, unique.
• In other word, at a machine (bus) cycle, CPU will
read or write only 1 mem location or 1 IO port.
• If above rule isn’t complied, system will be damaged
physically.
• Student explain?

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Procedures of Designing Addr.

Decoder
1. What’s CPU type? Where 7. Deploy address range in
is reset vector/address? binary: min to max
Locate ROM there, 8. Detach higher addr bits,
where’s RAM? which aren’t change in the
2. Nesesary signals to decode given range of map
3. How many ROM and 9. Combine these bits to create
RAM and their capacity? gate signals for decoder
4. How large of Map will be 10. Connect remain bit to
used, how many addr bit? channel select of decoder
5. Create a mem map 11. Test:
6. Design local bus for mem – Generate an addr in map
chips from A0 to Ai, – Generate an addr out of zone
enough for all chips

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 Signals & chips for Address decoding:
• Address bit: number of
address bit are needed
• Data bit: 8, 16, 32 for
schematics => 1, 2 or 4 chip
in parallel
• -RD, -WR, IO/-M or
• -IOR, -IOW, -MEMR,
-MEMW
• ALE: Address Latch Enable
• -PSEN
• 74HC138 (studied), 1 0f 8
• 74HC156, 1 of 8, OC
• 74HC154, 1 of 16
• Logic gates: AND, OR,
NAND, NOR...
• GAL 16V8, 20V8 PLD
chips

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Addr decoding: Case study 1

• The Micro Controller MSC 8051 (w/o internal
mem) has:
– 16 addr bit with ALE signal for demultiplexing 8
lower bit address and data
– /PSEN signal to select program mem
– /RD, /WR.
• Design memory sub system for it with:
– 40KB Flash with 29C64 chips (8KB) each
– 48KB SRAM with 62C64 chips (8KB)
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 Timing diagram Code fetching

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T. D. for data reading

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 Addr decoding: Case study 2
• In a 8088/Min Mode - 8 bit bus system needs:
– 32KB of EPROM, with 27C64 - 8KB each
– 64KB SRAM with 62C512 – 64KB each
– Design the schematics of memory
• Given Signals:
– 20 Address bit, 8 bit data
– /RD, /WR
– IO/-M: 1 => reading/writing IO ports, 0 => Mem

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5.3.6. What types of information are in

memory ?
• Two types of information:
– Program (code), is being executed by CPU
– Data:
• Variables: random access
• Stack Memory, accessed with special way: LIFO
• CMOS RAM:
– Dallas DS12C887 (powered, //), DS1307 (ser)
– Manufactured by CMOS technology: low speed (100ns),
– Very low consumption: under µW, stand by power supply
– Configuration of system, real time clock (RTC)
– ? Where are constants contained?

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 5.3.7. DRAM Parity
• A notion in order to check data for writing,
reading and storing in DRAM chips by the
way adding a 9th bit. This bit is set when the
result contain an even number of bit 1.
• Refer 74HC280: Odd/Even parity Generator
and Checker
– When number of bit 1 from I1 to I9 is even, Sigma
Even is 1, vs.

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74HTC280 in a DRAM Schema

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42
 Case study for parity checking
• Writing: SE (PE) = 1 in same
location in the 9th
• Reading:
– Normal?
– Error, even not data, parity bit is
wrong
• More expensive, 30% => unused
in cheap system now.
• Student homework: design a
schema for 16 bit DRAM parity
generating and checking

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16/32 bit data memories

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43
 5.4. Input – Output Ports
• In/Out or IOs for short are ports to transport
information likes control signal, data,... between
system and wide world. It’s interface layer.
• Classification of ports:
– For transportation between two (or more) micro processor
systems: PC and printer, PC and keyboard
– To control and transport some special devices: CRTs,
HDDs...
– To convert information format with real world: ADC, DAC
– Format of data: parallel or serial ports

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5.4.1. IO mapping
• There are two methods of mapping IO ports:
– Memory mapped IOs: IO ports are mapped into
memory space, likes memory location and chip
• Each port chip has few regiters or ports (1 to 8) => it
takes places of 1 memory zone
• But CPU can process them with all instructions like
memories: Mov, arithmetic and logic instr.
– IO mapped IOs: IO ports are located in their space
• They don’t take place of mem zone, but
• CPU just process them with 2 instructions: Input and
Output only, all other data processes have to exec in
CPU

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 Two types of IO mapping

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5.4.2. Parallel Ports

• To transport data in parallel between system
and other peripheral devices
• Intel PPI 82C55 (Programmable Peripheral
Interface)
– Data format is transported in byte with 3 ports PA,
PB and PC
– 3 modes of operation is specified when initializing
with some types of handshaking signals
– 2 address bit then there’re 4 appropriate registers
or ports
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 Block diagram of a system w PPI

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PPI Operational Modes

• Mode 0 for PA, PB and PC: simple port
– Latched output, unlatched input, usually
• Mode 1: for PA & PC only, strobed Input
Output port. As a Latched buffer when data is
combined with a strobe pulse from IO device.
A IBF (OBF) flag will be set to indicate that
data is available, reset when CPU (IO device)
read this port
• Mode 2: PA only, bi-directional bus with flag
(INTR, -STB, IBF, -OBF, -ACK)

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 Operation of a system w PPI
• 2 address bit => 4 IO locations
– 00: PA, 01: PB, 10: PC and 11 Control Register
– Control Reg: for setting operational modes of PPI
• b7: hi for setting mode
• b6 & b5: for PA operational modes 00 – M0, 01 – M1
10 – M2, 11 – unused
• b4: PA direction: 0 - out, 1 – in
• b3: 4 higher bit PC data direction
• b2: PB mode: 0 - mode 0, 1 – mode 1
• b1: PB data direction
• b0: PC low data direction
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Student homework for PPI

• In a PC system is equipped a PPI 8255 at IO
locations from 60h to 63h.
– Create schematics for address decoding for this
port
– Write a procedure in ASM to initializing: PA
(keyboard in), PB (cassette, speaker...), PC (status
in) mode 0 all and PA, PC are input, PB is output
– Given Signals:
• 10 Address bit from A0 to A9, 8 data bit D0 to D7
• -IOR, -IOW, Reset

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 5.4.3. Serial Ports
• Micro processor processes data in parallel
format as byte, word...
• For reducing price, size... often transmite data
in serial:
– Serializing a byte to stream of bit then
– Deserializing a stream of bit to byte again at that
end.
• Most IO devices are serial interface now a day
(student gives examples)
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Serial standards
• EIA/TIA 232, 485 • Baud rate: bit per second
• USB – 300, 600, 1200, 2400, 4800,
• Ethernet IEEE 802.x 9600, 19200, 38400, 56200 and
115200
• SATA
• Main Signals:
• EIA232 1969 standard: – TxD: Transmit data
– Asynchronous transmission – RxD: Receive data
standard • Modem control and status
– Format of data: signals - Option:
• 1 start bit is low (space) – -RTS, -CTS
• 7 or 8 data bit, b0 first – - DTR, - DSR
• Option parity bit – RI and CD
• 1 or 2 stop bit are hi (mark) • Voltage level and drivers
– Logic 0, space, +3 to +15V
– Logic 1, mark, -3 to -15V
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Serial data format/frame/charcacter

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Modeling of Serial Comm.

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49
 Serial ports: Intel U[S]ART 8250
• Universal Asynchronous Receiver/Transmitter, very
well-know, is equipped in PC as communication or
IED interface ports
• (Motorola; ACIA: Asynchronous Communication
Interface Adaptor)
• Can be set for transmission line and modem operation
modes
– Transceiver registers: Tx and Rx register
– Line Control Reg: set format of character will be sent or
received
– Status Reg: to indicate current state and errors of port.
Software driver must access this reg in order to determine
next decision

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Line Control Register, offset 3

• For determining format of characters will be trans-ceived,
initialized before operating:
• Offset address is 3 of UART port
• Format:
– b1 – b0 : number of data bits: 00 – 5, 01 – 6, 10 – 7 and 11 – 8. But 5
and 6 data bit aren’t use today
– b2: 0 means 1 and 1 means 2 stop bit
– b3: 0 means non and 1 means with parity
– b4: 0 is odd and 1 is even
– b5: if this bit is 1, stuck parity even out, 0 is normal
– b6: 1 means forced space out, normal is 0
– b7: DALB divisor latch access bit, likes a soft switch bit. When it’s 1,
2 offset addresses are divisor latch access, normal is 0

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50
 Line Status Register, offset 5
• b0 = 1 => IBF data received, = 0 when CPU reading Received
Buffer, RxR - xF8h
• b1 = 1 => OE, Overrun Err, last received char is not read by
CPU and overrun by next character
• b2 = 1 => PE, Parity Err, setup even but receive odd parity
• b3 = 1 => FE, Framing Err:
• b4 = 1 => BI, Break Interrupt, t(space)> t(full char)
• b5: THRE: Transmit Hold Reg Empty, you can out next
character
• B6 = 1=> Data Transmitted
• b7: Not Use

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UART Intel 8250

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51
 Case Study: UART 8250 coding
• In PC, Com1 address ;Setting 9600, 8, n, 1:
from 3F8 to 3FFh, mov dx, 3f8h ; base port addr
Com2: 2F8 to 2FFh in al, dx+3 ; import LCR
or al, 80h ; set DLAB hi
• Set format of data for out dx+3, al ; export to LCR
Tx & Rx: 9600, 8, n, 1 mov al, 0ch ; low divisor
out dx, al
xor al, al ; hi divisor is 0
out dx+1, al
mov al, 3 ; 8, n, 1 format
out dx+3, al ; is set

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• Transmitting A and B characters, UART will send

automatically after a char loading to TxReg
mov dx, 3f8h ; Base port Addr of PC’s UART 1
mov al, 41h ; load ASCII char A to AL
out dx, al ; auto send A char in serial
in al, dx+5 ; read LStatusR
X1: test al, 00100000b ; previous char is transmitted yet?
je X1 ; not yet
mov al, 42h ; ASCII char B
out dx, al ; send B char
call delay2 ; delay subroutine for B char sent totally

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• Receiving a byte in Rx Reg to AL
mov dx, 3f8h ; load base UART port addr
in al, dx+5 ; Line Status Register
X2: test al, 00000001b ; data received yet?
jz X2 ; not yet
in al, dx ; copy received byte to AL

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5.4.4. PROGRAMMABLE INTERVAL TIMER

• In order to handle timing applications, one-shot
applications, clock or frequency generation, and
frequency division
• PIT performs timing and counting functions:
– Preset counting, interrupt out when reach to zero
– One shot: generates single pulse with preset width
– Divide by n counter: rate generator, square wave
– Soft/hardware Triggered strobe
• Intel 8253 and 8254 for high lighted example
• Equipped in most micro computer/processor system, in
micro controller.

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 5.4.4. PIT: Case study - Intel 8253/8254
• Description:
– 24 pin IC
– 3 of 16 bit counters/timers T/C0, T/C1 and T/C2,
each includes signals:
• Clock input: event or pulse string input for counting
• Gate: Enabling/disabling T/C
• Out: for programmable pulse output
– System interface signals:
• 8 data bit bus for data/control word reading and writing, A0
and A1 for selecting individual register/counter
• Chip Select (low active), RD, WR: direction of data

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 5.4.4. PIT: Operations
• 6 Operation modes:
– 0. Interrupt on terminal count condition
– 1. Hardware retriggerable one-shot
– 2. Rate generator
– 3. Square wave mode (frequency divider) – the
example mode for this paper
– 4. Software Triggered Strobe
– 5. Hardware Triggered Strobe (retriggerable)

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5.4.4. PIT: Operations

Format of Control word register:

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 5.4.4. PIT: 8254 in PC
• Address 40h to 43h, IO Space
– 40h: T/C0, 16 bit, R/W 2 times, …42h: T/C2...
– 43h: Control Register
• Input clock 1.19 [3.18] MHz (14.31818/3/4[2])
• T/C0: 18.2[26.4] Hz for system clock, IRQ0
• T/C1: 15us generator for refreshing DRAM
• T/C2: beep tone.

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5.4.5. Priority Interrupt Resolve

(Refer 6.4, Intel PIC8259A )
• A device for controlling requests from IO devices
• Many IO ports and controllers in a system, in a moment, if
more than one IO devices request, leading to disputes.
• To resolve disputes, should have priority: each IO device is
assigned a priority index.
• When processing a interrupt service routine (ISR) for
controlling device B, if device A (higher level) requests by a
IRQ signal, system will:
– Stop processing B ISR, save context of B sub into stack mem
– Load address of A sub and execute
– After executing A sub, execute IRET instruction to restore B context
and continue
– All above procedures are resolved by CPU and PIC
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 Priority Interrupt Controller - PIC
• CPU has several IRQs and each IRQ is assigned a
priority level (internal PIC)
• PIC chip: receives all IRQ signals from the IO
devices and create an unique signal (INT) to CPU
corresponding to the priority:
– When CPU’s executing ISR B, if A device (higher level)
requests to PIC, it’ll generates a INT to CPU for
interrupting ISR B and run ISR A,
– When CPU’s executing ISR B, if C device (lower) requests
to PIC, it’ll generates nothing.
– All IRQs should be masked individually by software

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5.4.6. Direct Memory Access Controller

DMAC (Intel DMAC 8237A)

• A device that can transport data with very high

speed, with out CPU’s controlling and
program
• It’s a bus master, can generate address-data-
control signals to read/write data between a IO
device and data memory.
• In DMA mode, DMAC will take to control
system, CPU should be in “sleep” mode to
prevent physical conflict.
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57
 5.5. System Bus
• There are some bus sub-systems in a micro
processing system: System bus (or local bus,
memory bus - front side bus - FSB), IO
buses/IO system
• What is a computer bus?
– It’s group of conductive lines to transport
information of electrical/optical/wireless signals
between a master and multiple of shared slave
devices.
– Critical rule of bus: At a moment, there is only one
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talking, one or more listening to 115

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 Bus classifications: Address bus
• Address bus:
– Form CPU or a bus master pointing – selecting 1
memory or IO port location at a moment with its
combination
– n bit of mem address, a system can manage 2n
mem loc.
– m bit of IO address can manage 2m IO loc. A IO
location may be 4, 8, 16, 32 bit)
– Address bus is often 3 state buffered to broadcast
widely to others
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Data bus
• Data bus: to transport information:
– Operational codes from program memory to CPU
– Data between:
• CPU and Data mem
• CPU and IO ports
• Data mem and IO ports (DMA, w/o CPU)
– Often data bus size is same of ALU and mem (8,
16, 32, 64)
– Data bus is often 3 state buffered when connecting
others
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 Control Bus
• Control signal from a bus master (CPU, DMAC):
– READ, WRITE, Mem/IO,
– Clock, synchronous, busy, bus wide, what segment is being
used...
– Response: INTA, HLDA
• Status from slave devices:
– Ready/Not ready, ACK, Power good
• Request signals from IO devices and ports:
– IRQ, NMI, HRQ, DRQ,

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Serial bus
• Often for interfacing IO devices likes USB,
SATA, Fire-Wire (IEEE1394)…
• Address, data and control information are
serial – time sharing
• Only one master (@ a moment) and multiple
slaves with simple protocol for reducing
architect and price
• Student answer: distinguish between bus and
network?
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 Power Supply
• A part of modern bus system
– Ground (black), Gnd, metalic chassi
– Regulated +5Volt: supplying all Logical ICs (RED)
– Regulated +3.3V (or less) is modulated from +5Volt, to supply to VLSI
chips like modern CPU, FPGA chips with thin junction layer (650nm
and less) technology
– 2.4V, 1.8V, 1.5V…
– Regulated +12 (Yellow) and -12Volt (Blue): is power supply to
• Electro-machanic devices: HDD, FDD, fan...
• Analog boards: Sound, ADC, DAC, OpAmp...
– Power good (yellow) is set when all Voltage values are in available
range

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