Development of a Smart Grid Test Bed and
Applications in PMU and PDC Testing
Saugata S. Biswas, Student Member, IEEE, Jeong Hun Kim, Student Member, IEEE and
Anurag K Srivastava, Senior Member, IEEE
Abstract--The electric power system is moving towards the smart
grid development for improved reliable, secure and economic
operation. Many researchers are now concentrating their
research that is aimed at upgrading the power system by using
state-of-the-art computer based online monitoring and control
tools along with advanced communication facilities.
Implementation of such a system requires enhanced testing and
validation of smart grid technologies as well as development of
new approaches to fully utilize the capabilities of these
technologies. This paper is a modest attempt to present the
summary of the effort to model a smart power grid in real time
by developing a “smart grid test bed”. Additionally, some of the
applications of the developed test bed have been briefly
described, with special emphasis on testing of synchrophasor
devices like PMUs and PDCs.
Index Terms — Smart Grid, Real Time Test Bed,
Synchrophasors, PMU Testing, PDC Testing
I. INTRODUCTION
Implementation of the future smart grid requires
enhancements in the current grid at various levels of operation
and control. One such enhancement involves integration of
Intelligent Electronic Devices (IEDs) and synchrophasor
based devices in the present power grid. In order to efficiently
utilize these devices, it is important to test and validate their
capabilities as well as the accuracy of the data provided by
them. Efforts have been made by researchers wherein several
smart grid algorithms have been developed theoretically, but
they need to be tested and validated before actual
implementation in a real power system. The main aim is to
ensure high accuracy of data obtained from these IEDs and
synchrophasor devices under different operating scenarios and
then make optimum utilization of such data for smart
monitoring and control to make the power systems more
robust and secured. For this purpose, some researchers have
built smart grid test beds in lab environments and are
performing hardware in loop simulations covering various
aspects of a smart grid, as can be seen in [1], [2], and [3].
The test bed in Smart Grid Demonstration and Research
Investigation Lab (SGDRIL), WSU, as reported in this paper,
is a state-of-the-art platform that not only allows testing and
validation of the developed smart grid algorithms in real time,
but also testing the accuracy of synchrophasor devices like
Phasor Measurement Units (PMUs) and Phasor Data
Concentrators (PDCs). Besides this, interoperability of
different hardware devices for power system automation can
978-1-4673-2308-6/12/$31.00 ©2012 IEEE
also be tested. This paper contributes towards providing
details of smart grid modeling and simulation in lab and its
possible applications. Developed lab can be used for smart
grid research and education purposes.
This paper has been divided in the following sections.
Section-II gives an overview of the different hardware devices
and softwares forming parts of the smart grid test bed, along
with their possible applications. Section III describes the
integration of all these devices to form a functional smart grid
test bed and their individual roles in the test bed. Lastly,
section IV mentions one possible application of this test bed,
i.e. synchrophasor device (PMU and PDC) testing.
II. OVERVIEW OF HARDWARE DEVICES AND SOFTWARES
FORMING THE SMART GRID TEST BED
This section gives a brief description of each of the
hardware devices and software used in the test bed, along with
each of their potential applications.
A. Real Time Digital Simulator
Real Time Digital Simulator (RTDS) [4] is a power system
simulator that simulates a power system built in RSCAD user
interface software in real time. The RTDS works on the
parallel processing technology of digital signal processors and
executes the program developed on its processors. The RTDS
not only calculates and shows the electrical output values in
the runtime software, but also produces scaled output signals
(digital as well as analog) through the output interface cards
incorporated into its system.
The RTDS present in the SGDRIL, WSU, consists of one
rack with three Giga Processor Cards (GPCs) – for processing
all computations in real time; one Giga Transceiver
Workstation Interface Card (GTWIF) – for interfacing the
RSCAD user software with the GPC cards of the RTDS; one
Giga Transceiver Digital Input Card (GTDI) – for taking in
input digital signals from external devices like relays; one
Giga Transceiver Front Panel Interface card (GTFPI) – for
taking in input digital signals and giving out output digital
signals from and to hardware devices like relays; three Giga
Transceiver Analog Output Card (GTAO) – for providing
analog output signals to hardware devices like PMUs for
measuring electrical quantities; one Giga Transceiver Analog
Input Card (GTAI) – for taking in analog input signals from
hardware devices; one Giga Transceiver Network Interface
Card (GTNET) – for interfacing a number of different network
protocols with the RTDS simulator; and one Giga Transceiver
Synchronization Card (GTSYNC) – for synchronizing the
RTDS simulation time step to an external time reference like
the GPS clock.
B. GPS Clock
A GPS clock provides the time synchronization signal to
all the synchrophasor devices, so that all these devices are in
time sync with each other and the data time stamping is done
simultaneously irrespective of their geographical location. The
requirement of a GPS clock to send such time signals is that it
must “lock” with 4 GPS satellites through the GPS antenna
(and in case of loss of signal from satellites, the internal
oscillator of the GPS clock maintains the time with an
accuracy of ±1µs until the link with the satellites is re-
established). This kind of precise time synchronization
amongst all the devices is critical for detailed event analysis.
In SGDRIL, there are two GPS clocks – SEL-2407 [5] and
PONOVO PGPSO2 [6]. These devices provide IRIG-B type
time pulse outputs for the synchrophasor device IRIG-B
inputs.
C. Relays / PMUs / DFRs
These are the Intelligent Electronic Devices (IEDs) that
form the heart of the smart grid test bed. Advancements in
high speed and reliable microprocessor based programmable
relays in conjunction with advanced communication
technology embedded in such devices make monitoring and
control tasks much more efficient than their predecessors.
Many of these relays have fault finding feature, which reduces
the fault finding time by about 50%. Many relay
manufacturers also provide the synchrophasor measurement
module (i.e. a PMU) along with the relay module, which
means the monitoring as well as control module, both are in
the same device. Many of these devices have event recording
feature for post event analysis purposes.
In the test bed, there are different kinds of relays, meant for
generator protection, motor protection, transmission line
protection, transformer protection, capacitor bank protection,
reactor protection, etc. Relays/PMUs in the test bed include
SEL-351 [7] (2 nos.) with synchrophasor measurement feature
– for non-directional and directional overcurrent protection,
enhanced breaker monitoring, pilot protection scheme,
autoreclosure control, and under-frequency loadshedding;
SEL-387 [8] (1 no.) – for multi-winding current differential
protection, overcurrent protection, restricted earth fault
protection; SEL-421 [9] (2 nos.) with synchrophasor
measurement feature – for high speed distance protection,
directional overcurrent protection, for pilot protection scheme,
autoreclosure control, and breaker failure monitoring and
control; GE-D60 [10] (1 no. ) with synchrophasor
measurement feature – for 5-zone quad or mho type distance
protection, directional overcurrent protection, multiple
standard pilot protection schemes, single pole or three pole
tripping applications, 4-shot autoreclosure control,
synchronism check for dual breaker operation, out of step
tripping and power swing blocking operations; MICOM
Alstom P847 [11] (1 No.) – mainly for synchrophasor
measurement purpose; and TESLA 3000 Disturbance Fault
Recorder (DFR) from ERLphase [12] (1 No.) with
synchrophasor measurement option – mainly for recording
power system data in three domains: high speed transient
faults (in seconds), low speed dynamic swing (in minutes),
and continuous trend (10 seconds to 1 hour intervals).
D. Current & Voltage Amplifiers
The RTDS produces low level signals at its output ports (as
mentioned earlier in II. A) These low level signals are
inadequate to trigger the functioning of the Relays, PMUs and
DFRs (except for the ones manufacture by SEL, which have a
special low level interface that can accept low level signals for
its operation). Thus these signals need to be amplified to get
the voltage and current within the acceptable range of each
device for it to function properly.
In SGDRIL, WSU, there is one current amplifier and one
voltage amplifier from PONOVO [6]. The current amplifier
has 6 output current channels of range 0-30A with maximum
output power of 210VA, and has a typical current accuracy of
< 0.1%. The voltage amplifier has 6 output voltage channels
of range 0-250V with a maximum output power of > 75VA,
and has a typical voltage accuracy of < 0.1%.
E. Relay / PMU Tester
The Relays and PMUs need to be tested for their accuracy.
In this research work, emphasis is laid on testing of PMUs.
Two alternative devices have been used to test PMU
performance – RTDS (please refer to II. A) and Relay / PMU
Tester from PONOVO.
The GPS compatible PONOVO Relay / PMU Tester
POM2-6143 [6] has 6 nos. current outputs each rated for 15A,
4 nos. voltage outputs rated at 300V. It also has 8 binary
inputs and 4 binary outputs. It is provided with an internal PC
control, along with output monitoring and recording function.
The typical accuracies of this device are as follows – voltage
magnitude: < 0.1%, current magnitude: < 0.1%, frequency: <
1ppm, phase angle: < 0.05°. This device supports testing of all
kinds of devices conforming to the IEC-61850 Standard.
At present in SGDRIL, all the tests on PMUs are being
performed once by using the PONOVO Relay / PMU Tester
and then these obtained test results are validated using the
RTDS, by simulating a power system in real time and
checking the accuracy of synchrophasor measurements
obtained by the PMU (under test), which is stationed at a
particular bus in that system.
F. Phasor Data Concentrator
A Phasor Data Concentrator (PDC) aggregates
synchrophasor data from a number of PMUs and also from
PDCs at the lower tier of data acquisition. Aggregated data
will be correlated with identical time-tags to create a system
wide measurement set and archived to retrieve and use for
future work. PDC has additional functions as well. It performs
real-time data quality checks and calculations involving high
data acquisition rates such as 30 samples per second or higher
like 120 samples per second. Since real-time data quality
checks and calculations should be done before the next data
set arrive, the speed of performance must be very quick. Some
PDCs can down-sample stored data to feed them directly to
applications such as SCADA that use data at slower sample
rates. A PDC is abided by streaming protocol standards such
as IEEE C37.118 for both the phasor data input and the
combined data output stream to interface with data-using
applications. PDCs are available as hardware as well as
software.
The PDC present in the test bed of SGDRIL is of both
types – hardware as well as software. The software PDC is
SEL-5073 [13] with integrated data archiving feature that runs
on Microsoft Windows based computing platform. Data can
be archived on a continuous basis or on the basis of predefined
triggers. This software PDC has the capability of acquiring
synchrophasor data from more than 200 PMUs and supports
message rates of 240 messages per second. It can send
concentrated synchrophasor data to 6 clients at the higher level
of monitoring and control. The hardware PDC in SGDRIL is
SEL-3373 [14] with integrated data archiving feature. There
are two main differences between the hardware PDC and the
software PDC. The hardware PDC allows saving of all PMU
data on the solid-state drive (SSD) in the secure database. This
ensures that no PMU data is lost if communication with the
substation is disrupted. This is a clear advantage over the
software PDC. However, the other point of difference between
the two types of PDCs is that unlike the software PDC, the
hardware PDC can acquire synchrophasor data from up to a
maximum of 40 PMUs at the same message rate of 240
messages per second (specific to SEL PDC).
G. Synchrophasor Visualization Software
Many a times, it becomes important to have a visual
interpretation of the synchrophasor data to see the trends of
the different electrical parameters in real time. SEL
SynchroWAVe Central Software SEL-5078 [15] is used to
translate synchrophasor data into visual information, thus
providing better situational awareness. Synchrophasor data
can also be archived for power system analysis.
H. Synchrophasor Vector Processor
As attempts are being made to make the power grid
“smarter”, a lot of importance is being given to real time
control of power system on the basis of real time system
monitoring. SEL-3378 Synchrophasor Vector Processor (SVP)
[16] is a Programmable Logic Controller (PLC) like real time
control device which takes in synchrophasor data as its input
(either from PDCs, or directly from the PMUs) and outputs
control actions, based on the control algorithm in the SVP (to
the PDCs, Relays or other intelligent control devices) for wide
area protection and control of the power system. The SVP has
the ability to identify power system oscillations with
preconfigured modal analysis; measure voltage, current, phase
angle, real and reactive power; improve the efficiency of the
system by optimizing voltages and minimizing loop flows;
and control circuit breakers, and/or static VAR compensators
based on the control algorithm. Thus, the SVP is a very
powerful tool in detecting and controlling the stability of a
power system. Another application of this device is for
measurement of the states of the power system. It can screen
bad data obtained from a station and then send the true data to
the Energy Management System (EMS). Additionally, it can
also calculate the state vectors of the surrounding stations so
as to provide measurement redundancy. Apart from control,
the SVP can also be used to generate alarms to the system
operators if the set threshold limits of the electrical parameters
are violated.
In SGDRIL, presently the SVP is primarily being used for
identifying and controlling voltage instability in real time at
one or more buses in the test case power system.
I. Real Time Automation Controller
The SEL-3530 Real Time Automation Controller (RTAC)
[17] is a powerful automation device that combines an
embedded real time operating system with microprocessor
based hardware platform and IEC 61131-compliant
programmability. The RTAC can securely communicate with
the different IEDs in a substation (like Relays), gather data
from them, perform high-speed logic processing, and convert
protocols among various built-in client/server protocols. The
RTAC can be used to integrate synchrophasor information
into SCADA data, thus allowing wide area monitoring. The
built-in logic engine also allows users to program control
algorithms in a flexible IEC 61131-3 configuration
environment for real time control of the power system.
In SGDRIL, the RTAC is being mainly used for substation
health monitoring purpose and for automated microgrid
reconfiguration purpose.
J. Substation Automation Computer
SEL-3354 [18] is a robust, computer CPU hardware
designed to operate in the harsh environment of a substation. It
can have either Windows or Linux as the operating system. It
doesn’t have a fan or as such, any moving parts. It is designed
to withstand 15 kV electrostatic discharge, overcurrent,
dielectric strength, radiated emissions, fast transients, and
pulse magnetic field disturbances. It meets IEEE 1613, IEEE
C37.90, and IEC 60255 Protective Relay Standards. A field-
programmable gate array (FPGA) provides an extra level of
computer system reliability with a programmable system
monitor interface and alarm configuration. If this hardware
CPU is connected to a video monitor, keyboard, and mouse, it
can be used to provide a human-machine interface (HMI) for
alarm annunciation, local indication, control, and
configuration. This hardware has a 4GB RAM and a 60GB or
120 GB solid state drive storage and can be connected to
various local peripherals and high-speed network interfaces
with three 10/100BASE-T Ethernet (fiber optional), six USB,
and up to 16 EIA-232/EIA-485 ports. Several software
programs can be installed in SEL-3354 so as to interface it
with the Intelligent Electronic Devices (IEDs) installed in the
substation. This device can thus be used to make relay
settings, gather, view, and analyze event reports generated by
substation relays. It can also be used to forward information to
multiple master data users, such as SCADA.
In SGDRIL, this hardware device has been used to support
various interfacing software programs required for
communication with relays/PMUs, PDC, and SVP.
III. INTEGRATION OF ALL THE SOFTWARES AND HARDWARE
DEVICES IN THE TEST BED
All the hardware and software programs described in the
previous section have been integrated to form a smart grid test
bed, which has the capability of supporting real time
hardware-in-loop simulations and synchrophasor device
testing.
Figure-1 shows the architecture of the interconnections
(communications and hard wired) amongst the various
devices. The computer supports all kinds of softwares
(interfacing and simulation) and is connected to the Ethernet
switch (hub) so as to communicate with all other devices
Figure. 1: Schematic diagram of the architecture of the Smart Grid Test Bed
present in the test bed. The Relays / PMUs, RTAC, SVP are
all connected through Ethernet connections to the Ethernet
switch for communication purpose. The Relays / PMUs are
connected to the analog and/or digital output ports of the
RTDS to receive low level signals obtained during the real
time simulation of the system built in RTDS using RSCAD.
Those relays which cannot operate using low level signals
have been provided with voltage and current Amplifiers,
which amplify the signals suitably. The Relays / PMUs,
RTDS, PDC, SVP and RTAC have all been synchronized to
the UTC using the GPS Clock. The PDC, SVP, and RTAC can
get data from the Relays / PMUs. The test bed has the
Relay/PMU tester for validation of the PMU testing done
using RTDS.
This test bed has been used for different purposes. These
include – synchrophasor device (PMU & PDC) testing, testing
and validation of different kinds of smart grid algorithms like:
real time voltage stability algorithms, substation automation
algorithms, microgrid reconfiguration algorithms, etc.
 Following are some of the results that have been obtained by
IV. PMU AND PDC TESTING USING THE TEST BED performing tests on PMUs using the test bed –
Out of the several applications of the test bed mentioned in
A. Steady State Test on a PMU (Magnitude Change Test)
the previous section, one application that has been described
here is – synchrophasor device (PMU & PDC) testing.
Utilities need the guarantee for reliable and accurate operation
of PMUs and all applications dependent on PMU data as well
as the seamless interchangeability among PMUs from
different vendors before they invest heavily in them. Clause-5
of the revised Synchrophasor standard IEEE C37.118.1-2011
[19] describes the steady state and dynamic tests on PMUs.
This standard has been going through process of revisions and
Case-a: Balanced Conditions
still need more inputs from researchers and industries. With
this motivation, research is being currently performed at
SGDRIL to make PMU and PDC testing more efficient in
reflecting their performance under different system conditions.
Table-1 shows the proposed test conditions used for testing
the PMUs using the test bed.
TABLE-1. PROPOSED PMU TESTS USING THE TEST BED
Main Sub-Category of PMU System Conditions
Category of Testing (Cases) for
PMU Sub-Category of PMU
Testing Testing Case-b: Unbalanced Conditions
Steady State Magnitude Change Balanced, Unbalanced, Figure. 2: %TVE (Y-Axis) v/s P.U. Voltage Magnitude (X-Axis)
Performance Measurement Tests Off-nominal Frequency,
Tests with Harmonics
Phase Angle Change Balanced, Unbalanced, B. Dynamic Test on 2 PMUs (Magnitude Step Change Test)
Measurement Tests Off-nominal Frequency,
with Harmonics
Frequency Change Balanced, Unbalanced,
Measurement Tests with Harmonics

Rate of Change of Balanced, Unbalanced,

Frequency Measurement with Harmonics
(ROCOF) Tests
Harmonic Distortion Tests Balanced, Unbalanced,
Off-nominal Frequency
Dynamic Magnitude Response to Step Balanced, Unbalanced, Figure. 3: Rise Time in secs (y-axis) v/s Test Conditions (x-axis)
Performance Change Tests Off-nominal Frequency,
Tests with Harmonics Cases for System Conditions:
Phase Angle Response to Balanced, Unbalanced, Case-a: Balanced System
Step Change Tests Off-nominal Frequency, Case-b: Unbalanced System
with Harmonics Case-c: System at Off-nominal Frequency
Frequency Response to Step Balanced, Unbalanced, Case-d: System with Harmonics
Change Tests with Harmonics
ROCOF Response to Step Balanced, Unbalanced,
Change Tests with Harmonics Figure. 2 shows the results of the steady state test performed
Modulated Signal Balanced, Unbalanced, on a PMU. The sub-category of PMU test result shown here is
Magnitude Measurement for Off-nominal Frequency, that of ‘voltage magnitude change measurement test’ under
Frequency Modulation Tests with Harmonics two different system conditions (cases – a and b). It can be
Modulated Signal Balanced, Unbalanced,
Frequency Measurement for with Harmonics
clearly seen that the % Total Vector Error (TVE) of the PMU
Frequency Modulation Tests under test is not the same for the two cases, even though %
Modulated Signal ROCOF Balanced, Unbalanced, TVE is < 1% throughout. Figure. 3 shows the results of the
Measurement for Frequency with Harmonics dynamic test performed on 2 PMUs. The sub-category of
Modulation Tests PMU test result shown here is that of ‘voltage magnitude
Magnitude Measurement for Balanced, Unbalanced, response to step change test’ under four different system
Frequency Ramp Tests Off-nominal Frequency,
with Harmonics conditions (cases - a, b, c and d). It can be seen that the rise
Frequency Measurement for Balanced, Unbalanced, time for both the PMUs vary based on the system conditions.
Frequency Ramp Tests with Harmonics Thus it can be said that, these system conditions need to be
ROCOF Measurement for Balanced, Unbalanced, specified along with the subcategory of PMU testing in the
Frequency Ramp Tests with Harmonics future Synchrophasor Standard for better performance analysis
of PMUs.
 Table-2 shows the proposed test conditions used for testing
the PDCs using the test bed.
TABLE-2: PROPOSED PDC TESTS USING THE TEST BED
PDC Tests Description
Data Evaluation of the quality of an input synchrophasor data
Validation using CRC Check
Data PMUs at different substations may send in data at
Re-Sampling different rates, which the PDC needs to up-sample or
down-sample accordingly. This conversion of input data
rate in the PDC needs to be tested for errors
Data Alignment or ordering of synchrophasor data needs to be
Alignment done on the basis of the timestamp on the data. This kind
of data stream should be checked for correct time
sequence (for each data)
Data The PDC should be able to send out the data streams of
Recognition only those PMUs, from which data have been requested
by a client (like Synchrophasor Vector Processor or
Controller) and not from other PMUs due to an error of
recognition
Data While there is data transfer between a PMU and a PDC,
Retrieval some data might be lost. The PDC should be able to
recognize the missing data and send a request to the
concerned PMU/PMUs to resend the missing data. Once
the PDC receives this missing data, it should be able to
reposition this data in correct time sequence based on its
original timestamp.
Data The data sent by different PMUs to a PDC might have
Truncation different number of digits after the decimal place due to
truncation in the PMUs. The PDC should be able to
truncate all the data in the input stream such that all the
data should have the same number of decimal places after
truncation.
V. CONCLUSIONS
In this paper, the motivation and process of developing a
typical smart grid test bed has been discussed. Then, each
component in the test bed has been described along with its
functions. The integration of all these devices has been
explained and the different capabilities of the test bed have
been mentioned. Finally, one application of the test bed i.e.
Synchrophasor device testing has been discussed. These novel
testing methods are being presently investigated in SGDRIL,
and results show their potential in determining the
performance of synchrophasor devices. The developed test
bed can also be used for education and outreach activities
other than research.
VI. ACKNOWLEDGMENT
The authors of this paper would like to thank SEL, GE,
ALSTOM, ERLPhase, PONOVO and RTDS for their help in
building this lab. The authors would also like to extend their
thanks to PSERC for funding this project partially.
VII. REFERENCES
[1] R. M. Reddy and Anurag K. Srivastava, “Real Time Test Bed
Development for Power System Operation, Control and Cybersecurity,”
in North American Power Symposium (NAPS), Sept 2010.
[2] L. Vanfretti, “SmarTS-LAB: a Smart Transmission Grids Laboratory at
KTH,” White Paper, EPS Division, School of Electrical Engineering,
Royal Institute of Technology (KTH), Sweden. Nov, 2010 [Online].
Available:http://www.vanfretti.com/Dr._Luigi_Vanfrettis_Website/Publi
cations.html [May 2012].
[3] Karen Butler-Purry, G. R. Damle, N. D. R. Sarma, F. Uriarte and D.
Grant, “Test Bed for Studying Real-Time Simulation and Control for
Shipboard Power Systems,” in Electric Ship Technologies Symposium
(ESTS), 2007.
[4] RTDS and RSCAD technical information. [Online]. Available:
http://www.rtds.com/index/index.html
[5] SEL-2407 Satellite-Synchronized Clock Instruction Manual, Schweitzer
Engineering Laboratories, Inc., Pullman, WA, 2012.
[6] PONOVO Products technical information. [Online]. Available:
http://www.relaytest.com/product.php
[7] SEL-351-5-6-7Protection System Instruction Manual, Schweitzer
Engineering Laboratories, Inc., Pullman, WA, 2012.
[8] SEL-387-0-5-6 Relay Current Differential Overcurrent Relay Data
Recorder Instruction Manual, Schweitzer Engineering Laboratories,
Inc., Pullman, WA, 2012.
[9] SEL-421-4-5 Protection and Automation System Instruction Manual,
Schweitzer Engineering Laboratories, Inc., Pullman, WA, 2012.
[10] D-60 Line Distance Relay Instruction Manual, GE Multilin, Ontario,
Canada, 2012.
[11] MiCOM P847 Phasor Measurement Unit Technical Manual, ALSTOM
Grid, 2011.
[12] ERL Tesla 3000 Disturbance Recorder User Manual Ver-2.5 Rev-1,
ERLPhase Power Technologies Ltd, 2012.
[13] SEL-5073 SynchroWAVE Phasor Data Concentrator Instruction
Manual, Schweitzer Engineering Laboratories, Inc., Pullman, WA,
2012.
[14] SEL-3373 Station Phasor Data Concentrator Instruction Manual,
Schweitzer Engineering Laboratories, Inc., Pullman, WA, 2012.
[15] SEL-5078 SynchroWAVE Cenral Software Instruction Manual,
Schweitzer Engineering Laboratories, Inc., Pullman, WA, 2012.
[16] SEL-3378 Synchrophasor Vector Processor Instruction Manual,
Schweitzer Engineering Laboratories, Inc., Pullman, WA, 2012.
[17] SEL-3530 Real Time Automation Controller Instruction Manual,
Schweitzer Engineering Laboratories, Inc., Pullman, WA, 2012.
[18] SEL-3354 Embedded Automation Computing Platform Instruction
Manual, Schweitzer Engineering Laboratories, Inc., Pullman, WA,
2012.
[19] IEEE Standard for Synchrophasor Measurements for Power Systems,
IEEE Standard C37.118.1, 2011.
VIII. BIOGRAPHIES
Saugata S. Biswas received his B.E. degree in Electrical Engineering from
Nagpur University, Maharashtra, India, in 2007. He is the recipient of the
Gold Medal award from Nagpur University for his academic achievements
during 2003-2007. He worked in the Design and Development Department of
a Switchgear industry in India from 2007 to 2009. From 2009 to 2010, he was
in the Mississippi State University as a PhD student. From 2011, he is
continuing as a PhD student at Washington State University. His research
interests include synchrophasor device testing, real time voltage stability
monitoring and control using synchrophasor technology, and substation
automation technology for component level diagnostics and prognostics of
substation health monitoring.
Jeong Hun Kim received his B.S. degree in Electrical Engineering from
Pennsylvania State University in 2007. He received his M.S degree in
Electrical Engineering in 2010. Presently, he is a PhD student at Washington
State University. His research interests include synchrophasor device testing
and substation automation technology for system level diagnostics and
prognostics of substation health monitoring.
Anurag K. Srivastava (S’00, SM’ 09) received his Ph.D. from Illinois
Institute of Technology (IIT), Chicago, in 2005. He joined Washington State
University as Assistant Professor in August 2010. He worked as an Assistant
Research Professor at Mississippi State University from 2005-2010. His
research interests include power system model, simulation, operation, control,
security, and stability within smart grid and micro grid. Dr. Srivastava is
member of the IEEE, Power and Energy Society (PES), IET, Sigma Xi, and
Eta Kappa Nu. He is chair of the IEEE PES career promotion subcommittee
and vice-chair of the IEEE PES student activities subcommittee and is active
in several other IEEE PES technical committees.