BASICS OF VLSI

LAB ASSIGNMENT – 1

BY

DAVID JOSE (M100388EC)

N RAMAKRISHNA (M100410EC)
DEVANAND T (M100404EC)
 Exercise 1 Extract threshold voltage, drain induced barrier lowering, body effect,
channel length modulation for different lengths. ( Lmin, 2Lmin, 3Lmin, 4Lmin, 5Lmin)
These exercises are done with W / L ratio = 2.
Threshold voltage - length
485
480
475
470
Length(nm) Threshold voltage(mV)
465
460
180 405.12
455 360 481.72
Vt(mV)

450
445
440
Vt(mV))
540 456.78
435
430
720 431.36
425
420
900 416.1
415
410
405 V DS is kept constant at 1V and I D vs
100 200 300 400 500 600 700 800 900 V GS graphs are used to determine the
DIBL-Length threshold voltage.
-0.01500
-0.01750 Length(nm) DIBL
-0.02000 180 -0.03906
-0.02250
360 -0.01938
DIBL

-0.02500
-0.02750 DIBL
540 -0.02034
-0.03000 720 -0.01356
-0.03250 900 -0.02
-0.03500
-0.03750
-0.04000
I D versus V GS graphs are plotted at two
100 200 300 400 500 600 700 800 900 different V DS to obtain the change in
Length(nm) threshold voltage.

Lambda - Length
0.170
0.160 Length(nm) Lambda
0.150
0.140
180 0.167
0.130 360 0.094
540 0.078
Lambda

0.120
0.110 720 0.059
0.100 Lambda

0.090
900 0.048
0.080 Lambda is evaluated from I D versus
0.070
0.060
V DS graph by noting down the values of
0.050 I D at two different values of V DS .
0.040
100 200 300 400 500 600 700 800 900

Length(nm)
 Gamma-Length
0.3400
length(nm) Gamma
0.3200
180 0.1542
0.3000
0.2800
360 0.2606
0.2600 540 0.3016
Gamma

0.2400
Gamma
720 0.3303
0.2200 900 0.3375
0.2000
0.1800
0.1600
0.1400
Gamma is evaluated by obtaining the values of
100 200 300 400 500 600 700 800 900 V T with V BS =0V and V BS =-0.5V.
length(nm)

Exercise 2 Use the extracted values to plot I D vs V GS

log Id Vs Vgs
1.00E-003

1.00E-004

1.00E-005

1.00E-006
L=180nm
1.00E-007
L=360nm
1.00E-008 L=540nm
L = 720 nm
1.00E-009

1.00E-010

1.00E-011

1.00E-012

1.00E-013
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

These plots are drawn by fixing V DS at 1 Volt and varying V GS from 0 to 1.8V
Exercise 3. Report the minimum and maximum error in percentage(in linear
and saturation regions)

Length 180nm 360 nm 540nm 720nm 900nm

% error in max min max min max min max min max min
I DS
Linear 29.1 0.78 18.74 1.22 27 0.12 33.06 7.35 37.25 13.8
Saturation 17.75 0.37 11.84 0.64 7.99 0.6 16.33 7.87 22.47 14.3

These values are obtained by comparing the the graphs plotted between V DS and I DS
(by maintaining V GS at 1 Volt.) using the theoretical expression and cadence simulator.
V DS is varied from 0V to 1.8V to obtain the I DS versus V DS graph.

Exercise 4. List the reasons for the error.

Reasons for error in Drain current :

In saturation region ,the ideal drain current equation is

I  D SAT =1/2n C ox W / LV GS −V TH 2

In linear region drain current equation is

I  D LIN =n C ox W / LV GS −V TH V DS −V 2DS /2

The graph plotted using the above theoretical equations doesn't consider the effects of
channel length modulation , velocity saturation etc. The graph plotted using the cadence
simulator takes into account the above factors. The theoretical graphs are plotted with a
mobility value of 250 cm2 /Vs . But practically the value of surface mobility is about 10
to 20 cm2 /Vs .
The simulator also takes into account the factors like dependence of bulk depletion charge
on channel voltage and sub threshold conduction.
Exercise 5. Analyze the reasons for the fashion in which results vary with
length.

Reasons for variation of extracted parameters with length.

➢ Threshold voltage ( V T )
Threshold voltage increases slightly with increase in channel length. This is because
gate induced bulk depletion charge increase with increase in channel length. Short-channel
effect leads to the decrease of V T with decrease in L.

➢ Drain Induced Barrier Lowering ( DIBL )

DIBL = - V T /V DS
V T decreases with increase in V DS .Hence (- V T ) is a measure of barrier
lowering. In the graph,we have plotted  V T / V DS .These values are negative. The
values become less negative as L increases .Hence barrier lowering decreases with increase
in L. This is because ,with lower L, drain-body depletion region makes a major share in
charge balance. At higher values of L,the drain-body depletion region width is smaller
compared with L. Hence barrier lowering is low.

➢ Body bias coefficient (  )

=V T −V T0 /  2 F V SB −  2 F 

 is found to increase initially with increase in L and later it remains constant.

But ideally,  should have remained constant throughout. It is given as
= 2 qN A Si /C ox .This initial variation is due to short channel effects etc.

➢ Channel length modulation coefficient (  )

As V DS increases, channel pinch off occurs at the drain end. This change in
length  L is proportional to V DS . Mathematically, = L/ Leff V DS  . Thus ,
for a given V DS , change in channel length (  L ) with respect to original channel
length (L) will be larger for a smaller value of L . Hence lambda decreases with increase in
channel length.
Exercise 6. Comment on the transition frequency for L=.8Lmin to 5Lmin

Transition frequency vs channel length

60
55
Transition frequency(GHz)

50 Length(nm) Transition frequency

45 180 57.06
40 360 19.42
35
540 9.96
30 Transition
25
frequency 720 6.16
20 900 4.3
15
10
5
0
0 200 400 600 800 1000

length(nm)

The transition frequency f T is given as : f T =g m /2 C gs where

C gs =WLC ox .Here C ox =ox /t ox
In order to compute f T , g m value is obtained from the slope of I D −V GS
characteristics.
f T is a measure of the time taken by a charge carrier to move from source to
drain. Hence as channel length (L) increases, time taken for transition increases. So f T
decreases. The transition frequency f T in terms of channel length L is given as :
2
f T =3 n V DSAT /4  L 

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