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AMI-BIOS-Q9D

AMI-BIOS for the DIN-RAIL PC Board


PC7

AMI-BIOS-Q8C
AMI-BIOS for the CompactPCI® Board
CL7

BIOS, Programmer’s & User’s Manual

Revision 0.9

Copyright © 2001 by SBS Technologies


www.sbs.com
PC7 and CL7 BIOS, Programmer’s & User’s Manual

Revision History
Revision By Date Chapter Comments

0.1 BO 2001/11/07 Initial revision for Pre-Release


0.2 BO 2001/04/17 Initial revision revised
0.3 BO 2001/07/18 Initial revision revised
0.4 BO 2002/03/08 Added SMBus devices updated BIOS revisions
0.5 BO 2002/07/01 Added Watchdog / TCO timer chapter
0.6 BO 2002/08/07 Minor corrections
0.7 BO 2002/10/18 Changed contact addresses.
0.8 BO 2003/01/31 Added TCO timer setup description, corrected some Setup
descriptions.
0.9 BO 2003/02/11 Added Parity Check setup entry description

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 2 of 55
AMI-BIOS Setup and PnP Programming

PC7 BIOS Release 2003/01/31


and
CL7 BIOS Release 2003/02/17

User’s Manual

Order No.:M_AMIUSRMANPC7CL7

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 3 of 55
Disclaimer
The information in this document has been carefully checked and is believed to be entirely reliable.
However, no responsibility is assumed for inaccuracies.
SBS Technologies reserve the right to make changes without further notice to any products herein to
improve reliability, function or design. SBS Technologies do not assume any liability arising out of the
application or use of any product or circuit described herein; neither do they convey any license under their
patent rights nor the rights of others. The software described herein will be provided on an "as is" basis and
without warranty. SBS Technologies accept no liability for incidental or consequential damages arising
from use of the software. This Disclaimer of warranty extends to SBS Technologies licensee, to
licensee's transferees and to licensee's customers or users and is in lieu of all warranties whether expressed,
implied or statutory, including implied warranties of saleability or fitness for a particular purpose.
SBS Technologies do not accept any liability concerning the use of their products in life support
systems.

Trademarks
Product and company names listed are trademarks or trade names of their respective companies owners.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 4 of 55
Internet Service (for the latest update information)
The SBS-or Internet information provides you with support and the latest information.

• World Wide Web


Our web site is available at two locations.

http://www.sbs.com

• FTP Server
Here you can find a library of drivers, manuals, error reports, updates, application notes and more.

ftp://ftp.sbs-or.de

• Request Info
If you need more information about a specific product use the following e-mail address or phone
numbers.
SBS Technologies GmbH & Co. KG
Memminger Str. 14
D-86159 Augsburg, Germany
Phone Number: +49 821 / 5034-0
Fax Number: +49 821 / 5034-119

In the US contact
SBS Technologies, Inc.
6301, Chapel Hill Road
Raleigh, NC 27607-5115
Phone Number: +1 919 851-1101
Fax Number: +1 919 851-2844

Request via E-Mail


http://www.sbs.com
Go to the web page Contact Us and complete the e-mail form.

• Support
If you have any questions contact our support engineer in Europe at
SBS Technologies GmbH & Co. KG
Memminger Str. 14
D-86159 Augsburg, Germany
Phone Number: +49 821 5034-170
Fax Number: +49 821 5034-119

In the US contact
SBS Technologies, Inc., Embedded Computers
6301, Chapel Hill Road
Raleigh, NC 27607-5115
Phone Number: +1 919 851-1101
Fax Number: +1 919 851-2844

Support via E-Mail


http://www.sbs.com
Go to the web page Contact Us and complete the e-mail form.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 5 of 55
Table of Contents

Table of Contents
Revision History .....................................................................................................................................2
Disclaimer...............................................................................................................................................4
Trademarks .............................................................................................................................................4
Internet Service (for the latest update information) .................................................................................5
Table of Contents...................................................................................................................................6

1 Introduction ................................................................................................. 8
1.1 Scope..............................................................................................................................................8
1.2 Supported Products ........................................................................................................................8
1.3 Identify Product and BIOS.............................................................................................................8

2 AMIBIOS® Setup ........................................................................................ 9


2.1.1 AMIBIOS Setup Main Menu ...........................................................................................9
2.1.2 Keystrokes ........................................................................................................................9
2.2 Setup Operation............................................................................................................................10
2.2.1 Available Settings tables ................................................................................................10
2.2.2 Specifying a Customized BIOS Setup............................................................................10
2.2.3 Standard CMOS Setup ...................................................................................................11
2.2.4 Advanced CMOS Setup .................................................................................................15
2.2.5 Advanced Chipset Setup.................................................................................................19
2.2.6 PCI / Plug and Play Setup ..............................................................................................25
2.2.7 Peripheral Setup .............................................................................................................28
2.3 Security ........................................................................................................................................34
2.3.1 Setting a Password..........................................................................................................34
2.3.2 Access Restriction ..........................................................................................................34
2.4 Automatic Configuration .............................................................................................................35
2.4.1 Auto-Detect Hard Disk...................................................................................................35
2.4.2 Auto Configuration.........................................................................................................35

3 Using and programming the on board features ..................................... 36


3.1 Plug&Play BIOS Services............................................................................................................36
3.2 Mainboard Feature Control Register (MFCR) Sets .....................................................................36
3.2.1 *SBS1060 – PC7 ............................................................................................................37
3.2.2 *SBS1040 – CL7............................................................................................................38
3.3 Mainboard features ......................................................................................................................38
3.3.1 Mainboard register set ....................................................................................................38
3.3.1.1 Lock/Unlock Register - LOCKR (PC7)...................................................................38
3.3.2 General purpose I/O (PC7).............................................................................................39
3.3.3 CompactPCI PCI ENUM Signal (CL7) .........................................................................40
3.3.4 Status LED (PC7 and CL7) ............................................................................................40
3.3.5 SRAM (PC7) ..................................................................................................................41
3.4 *SBS0001 – Intel i82527 CAN controller ...................................................................................42
3.5 SMBus devices.............................................................................................................................43
3.5.1 Temperature Sensor........................................................................................................43
3.5.2 Serial EEPROM .............................................................................................................43
3.5.3 DIMM SPD EEPROM ...................................................................................................43
3.5.4 CLK Synthesizer ............................................................................................................44
3.6 Watchdog / TCO timer.................................................................................................................44

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 6 of 55
Table of Contents

4 Troubleshooting......................................................................................... 45
4.1 Checkpoint Codes ........................................................................................................................45
4.2 Beep Codes ..................................................................................................................................49
4.3 POST Memory Test .....................................................................................................................51
4.3.1 Displaying Additional AMIBIOS ID Strings .................................................................51

5 Index ........................................................................................................... 52

Error Report Form (Europe) .............................................................................. 54

Error Report Form (US)...................................................................................... 55

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 7 of 55
Introduction

1 Introduction
SBS Technologies mainboard products that are equipped with AMI-BIOS provide the user with
AMIBIOS Setup, a convenient user interface for configuration of system information that is stored in
CMOS RAM. AMIBIOS Setup has an easy-to-use user interface.

1.1 Scope
The first part of this manual describes the general operation and usage of AMI-BIOS Setup, and gives a
detailed description of the system configuration settings, options and features that are available on the
various screens.
Part two explains the onboard peripherals represented by Plug and Play structures complying to PnP
standard.
Part three gives troubleshooting advice for the case that an SBS Technologies mainboard should fail to
boot to the operating system successfully.

1.2 Supported Products


This manual covers the AMI-BIOS PC7 Release 2003/01/31 currently shipping with SBS Technologies
mainboard products PC7 and AMI-BIOS CL7 Release 2003/02/17. Because the same Chipset is used on
these two motherboards the most settings and features are equal, existing differencies are indicated.

1.3 Identify Product and BIOS


BIOS date and revision / version can be observed during bootup in the 4th line on the startup screen, just
below the Product string “SBS Technologies PC7” for the PC7 and “SBS Technologies CL7” for the
CL7 machines. If the monitor used comes up to late to view these lines (they are only displayed a short
time to improve boot up speed) press break button several times to stop the system while detecting IDE
drives, then the strings can be viewed conveniently.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 8 of 55
AMIBIOS® Setup

2 AMIBIOS® Setup
AMIBIOS Setup configures system information that is stored in CMOS RAM. AMIBIOS Setup has an
easy-to-use user interface.

2.1.1 AMIBIOS Setup Main Menu


The AMIBIOS Setup main menu appears as follows. Each menu item is described in this chapter.

AMIBIOS HI-FLEX SETUP UTILITY VERSION 1.18


© 1998 American Megatrends, Inc. All Rights Reserved.

STANDARD CMOS SETUP


ADVANCED CMOS SETUP
ADVANCED CHIPSET SETUP
POWER MANAGEMENT SETUP
PCI / PLUG AND PLAY SETUP
PERIPHERAL SETUP
AUTO-DETECT HARD DISK
CHANGE USER PASSWORD
CHANGE SUPERVISOR PASSWORD
AUTO CONFIGURATION WITH OPTIMAL SETTINGS
AUTO CONFIGURATION WITH FAIL-SAFE SETTINGS
AUTO CONFIGURATION WITH USER SETTINGS
SAVE USER SETTINGS
INVALIDATE USER SETTINGS
SAVE SETTINGS AND EXIT
EXIT WITHOUT SAVING

Standard CMOS setup for changing time, date, hard disk type, etc.

Esc:Exit ↑↓:Sel F2/F3:Color F10:Save & Exit

If BIOS User Defaults are not active, the menu entries “AUTO CONFIGURATION WITH USER SETTINGS”,
“SAVE USER SETTINGS” and “INVALIDATE USER SETTINGS” are not available.
To activate BIOS User Defaults, additional software product, called DOS-SETUP3, provided by SBS
Technologies is necessary. Contact your SBS representative for further information.

2.1.2 Keystrokes
Use the cursor (arrow) keys to navigate through the list of menu items displayed. Press Return or Enter
to open the selected Setup page.
On a Setup page, pressing PgUp, PgDn or the + and – keys on the numeric keypad cycle through the
available settings of the selected item. Press ESC to return to the main screen shown above.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 9 of 55
AMIBIOS® Setup

2.2 Setup Operation


AMIBIOS Setup for PC7/CL7 has five separate configuration screens. Different types of system
configuration parameters are set on each screen.

Type Description Turn to


Standard CMOS Set the time and date. Configure disk page 11
Setup drives.
Advanced CMOS Configure basic system performance page 15
Setup parameters.
Advanced Chipset Configure features specific to the page 19
Setup chipset used in the computer.
PCI/Plug and Play Configure PCI and Plug-and-Play page 24
Setup features.
Peripheral Setup Configure I/O support. page 28

2.2.1 Available Settings tables


On the following pages, there is a table for each option in Setup. The “Optimal” column states the
default setting that is preset from factory. The “Failsafe” column shows the setting that is used whenever
the system needs to recover from a loss of Setup information (e.g. after a loss of backup voltage, or
battery failure). The third column, “User” is there for you to take notes on your own preferred setting.
2.2.2 Specifying a Customized BIOS Setup
SBS Technologies provides, an add-on product and/or manufacturing option to customize versions of
the BIOS releases. BIOS Setup will be preset to “Optimal” default settings that are altered to your
particular application’s requirements. This is especially useful for environments where no onboard
CMOS backup battery can be used, and no external CMOS backup power supply exists either. BIOS
that has been customized for such a system will avoid the “CMOS checksum error” or “CMOS battery
low” messages when no battery is onboard or when onboard battery is low. Instead, BIOS will quietly
restore the specified default settings on every power-up sequence when the CMOS checksum is wrong,
and thus boot to the operating system without requiring the user to restore useful settings manually or
confirm error messages.
For further details see the “DOS-SETUP3” manual.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 10 of 55
AMIBIOS® Setup

2.2.3 Standard CMOS Setup


Select the AMIBIOS Setup options by choosing Standard Setup from the AMIBIOS Setup main menu.
Standard Setup options are described below.

AMIBIOS SETUP-STANDARD CMOS SETUP


(C)1998 American Megatrends, Inc. All Rights Reserved

Date (mm/dd/yyyy): Thu May 28,1998 Base Memory: 640 KB


Time (hh/mm/ss) : 16:05:13 Extd Memory: .62 MB
Floppy Drive A: 1.44MB 3½
Floppy Drive B: Not Installed
LBA Blk PIO 32Bit
Type Size Cyln Head WPcom Sec Mode Mode Mode Mode
Pri Master: Auto 42 40 981 5 981 17 Off Off Auto On
Pri Slave: Not Installed
Sec Master: Auto
Sec Slave: Not Installed
Boot Sector Virus Protection Disabled

Month: Jan – Dec ESC:Exit ↑↓:Sel


Day: 01 – 31 PgUp/PgDn:Modify
Year: 1901 – 2099 F2/F3:Color

All Standard Setup options are described in this section.

Date/Time The current values for date and time are displayed. Month, day and year as well as hour, minute
and second can be altered using the PgUp, PgDn, + and - keys.
Note: These fields do not use default values. On CMOS backup power failure, low battery or
CMOS checksum error, the clock is reset to 1980/01/01 00:00 AM.

Floppy Drive A: and B: Select the type of the connected floppy disk drive(s).
Available Settings Optimal Fail-Safe User
Not Installed B: B:
360 KB 5¼ inch
1.2 MB 5¼ inch
720 KB 3½ inch
1.44 MB 3½ inch A: A:
2.88 MB 3½ inch

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 11 of 55
AMIBIOS® Setup

Primary Master
Primary Slave
Secondary Master
Secondary Slave Select these options to configure the drive named in the option. Press <Enter> or <Return> to
let AMIBIOS automatically configure the drive. The drive’s parameter data fields will then be
filled in with information read from the drive itself. The following table shows how to configure
different drive types.
Type How to Configure
SCSI Select Type. Select Not Installed, SCSI drives are not specified here.
The SCSI drivers provided by the SCSI manufacturer should allow
you to configure the SCSI drive.
IDE Select Type. Select Auto to let AMIBIOS determine the parameters.
Select 32-Bit Mode. Select On to allow 32-bit data transfers.
CD- Select Type. Select ATAPI CDROM. Select the PIO Mode. It is best to
ROM select Auto to allow AMIBIOS to determine the PIO mode. If you
select a PIO mode that is not supported by the IDE drive, the drive
will not work properly. If you are absolutely certain that you know the
drive’s PIO mode, select PIO mode 0 - 4, as appropriate.
ZIP, Select Type. Select ARMD. Select the PIO Mode as described above.
LS120,
MO
Standard Select Type. You must know the drive parameters. Select the drive
MFM type that exactly matches your drive’s parameters. Please see the
below Hard Disk Drive Types table.
Non- Select Type. If the drive parameters do not match the drive parameters
Standard listed for drive types 1 - 46, select User and enter the correct hard disk
MFM drive parameters.

PC7:
Available Settings Optimal Fail-Safe User
One of 1-46 see: page 14
User
Auto Pri/Sec Master Pri/Sec Master
ATAPI CDROM
ARMD
Not Installed Pri/Sec Slave Pri/Sec Slave

CL7:
Available Settings Optimal Fail-Safe User
One of 1-46 see: page 14
User
Auto Pri Master Pri Master
ATAPI CDROM
ARMD
Not Installed Sec Master Sec Master
Pri/Sec Slave Pri/Sec Slave

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 12 of 55
AMIBIOS® Setup

Entering Drive Parameters You can also enter the hard disk drive parameters. The drive parameters are:
Parameter Description
Type The number for a drive with certain identification
parameters.
Cylinders The number of cylinders in the disk drive.
Heads The number of heads.
Write The actual physical size of a sector gets progressively
Precompensation smaller as the track diameter diminishes. Yet each sector
must still hold 512 bytes. Write precompensation circuitry
on the hard disk compensates for the physical difference
in sector size by boosting the write current for sectors on
inner tracks. This parameter is the track number on the
disk surface where write precompensation begins.
Landing Zone This number is the cylinder location where the heads
normally park when the system is shut down.
Sectors The number of sectors per track. MFM drives have 17
sectors per track. RLL drives have 26 sectors per track.
ESDI drives have 34 sectors per track. SCSI and IDE
drives have even more sectors per track.
Capacity The formatted capacity of the drive is the number of heads
times the number of cylinders times the number of sectors
per track times 512 (bytes per sector).

Boot Sector Virus Protection With this feature enabled, AMIBIOS issues a warning when any program (or
virus) issues a Disk Format command or attempts to write to the boot sector of the hard disk
drive. If enabled, the following appears when a write is attempted to the boot sector. You may
have to type N several times to prevent the boot sector write.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

Note: For operating system installation, this feature should be disabled since not all OS
installation procedures allow the messages to appear.
This Virus protection does not work for all known viruses, it just prevents programs (including
viruses) to write or format the harddrive via BIOS INT 13h. Programs which circumvents
INT13h still can manipulate the Harddrive.
Boot Sector Write!!!
Possible VIRUS: Continue (Y/N)? _

The following appears after any attempt to format any cylinder, head, or sector of any hard disk
drive via the BIOS INT 13 Hard Disk Drive Service:
Format!!!
Possible VIRUS: Continue (Y/N)? _

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 13 of 55
AMIBIOS® Setup

Hard Disk Drive Types


Type Cylinders Heads Write Landing Sectors Capacity
Precompensation Zone
1 306 4 128 305 17 10 MB
2 615 4 300 615 17 20 MB
3 615 6 300 615 17 31 MB
4 940 8 512 940 17 62 MB
5 940 6 512 940 17 47 MB
6 615 4 65535 615 17 20 MB
7 462 8 256 511 17 31 MB
8 733 5 65535 733 17 30 MB
9 900 15 65535 901 17 112 MB
10 820 3 65535 820 17 20 MB
11 855 5 65535 855 17 35 MB
12 855 7 65535 855 17 50 MB
13 306 8 128 319 17 20 MB
14 733 7 65535 733 17 43 MB
16 612 4 0 663 17 20 MB
17 977 5 300 977 17 41 MB
18 977 7 65535 977 17 57 MB
19 1024 7 512 1023 17 60 MB
20 733 5 300 732 17 30 MB
21 733 7 300 732 17 43 MB
22 733 5 300 733 17 30 MB
23 306 4 0 336 17 10 MB
24 925 7 0 925 17 54 MB
25 925 9 65535 925 17 69 MB
26 754 7 754 754 17 44 MB
27 754 11 65535 754 17 69 MB
28 699 7 256 699 17 41 MB
29 823 10 65535 823 17 68 MB
30 918 7 918 918 17 53 MB
31 1024 11 65535 1024 17 94 MB
32 1024 15 65535 1024 17 128 MB
33 1024 5 1024 1024 17 43 MB
34 612 2 128 612 17 10 MB
35 1024 9 65535 1024 17 77 MB
36 1024 8 512 1024 17 68 MB
37 615 8 128 615 17 41 MB
38 987 3 987 987 17 25 MB
39 987 7 987 987 17 57 MB
40 820 6 820 820 17 41 MB
41 977 5 977 977 17 41 MB
42 981 5 981 981 17 41 MB
43 830 7 512 830 17 48 MB
44 830 10 65535 830 17 69 MB
45 917 15 65535 918 17 114 MB
46 1224 15 65535 1223 17 152 MB
USER-DEFINED HARD DRIVE - Enter user-supplied parameters.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 14 of 55
AMIBIOS® Setup

2.2.4 Advanced CMOS Setup


Advanced Setup options are displayed by choosing Advanced CMOS Setup from the AMIBIOS Setup
main screen. All Advanced Setup options are described in this section.

Quick Boot Set this option to Enabled to instruct AMIBIOS to boot quickly when the computer is powered
on. The settings are:
Setting Description
Disabled AMIBIOS test all system memory. AMIBIOS waits up to 40
seconds for a READY signal from the IDE hard disk drive.
AMIBIOS waits for .5 seconds after sending a RESET signal
to the IDE drive to allow the IDE drive time to get ready
again. AMIBIOS checks for a <Del> key press and runs
AMIBIOS Setup if the key has been pressed.
Enabled AMIBIOS does not test system memory above 1 MB.
AMIBIOS does not wait for a READY signal from the IDE
hard disk drive. If a READY signal is not received
immediately from the IDE drive, AMIBIOS does not
configure that drive. AMIBIOS does not wait for .5 seconds
after sending a RESET signal to the IDE drive to allow the
IDE drive time to get ready again.

Available Settings Optimal Fail-Safe User


Disabled ●
Enabled ●

Pri Master ARMD Emulated As


Pri Slave ARMD Emulated As
Sec Master ARMD Emulated As
Sec Slave ARMD Emulated As These options specify the type of emulation used for an ATAPI Removable
Media Device attached to the respective IDE controller channel. The settings are Auto
(AMIBIOS automatically determines the proper emulation), Floppy, or Hard Disk.

Available Settings Optimal Fail-Safe User


Auto ● ●
Floppy
Hard Disk

Note: In Auto mode, LS120 drives will be run in Floppy emulation (referred to as ARMD-FDD),
while MO and ZIP drives will be run in Hard Disk (ARMD-HDD) emulation.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 15 of 55
AMIBIOS® Setup

1st Boot Device


2nd Boot Device
3rd Boot Device These options set the type of device for the 1st, 2nd and 3rd boot drive that the AMIBIOS
attempts to boot from after AMIBIOS POST completes.
Available Settings Optimal Fail-Safe User
Disabled
1st IDE-HDD 1st 2nd
2nd IDE-HDD
3rd IDE-HDD
4th IDE-HDD
Floppy 2nd 1st
ARMD-FDD
ARMD-HDD
ATAPI CDROM 3rd 3rd
SCSI (available as 1st or 2nd boot device only)
Network (available as 1st boot device only)
I2O (available as 1st boot device only)

Try Other Boot Devices Set this option to Yes to instruct AMIBIOS to attempt to boot from any other drive in the
system if it cannot find a boot drive among the drives specified in the 1st Boot Device, 2nd Boot
Device, 3rd Boot Device, and 4th Boot Device options.
Available Settings Optimal Fail-Safe User
Yes ● ●
No

Initialize I2O Devices Set this option to Yes to have AMIBIOS initialize any attached I2O-compliant devices.
Available Settings Optimal Fail-Safe User
Yes ● ●
No

Floppy Access Control This option specifies the read/write access that is set when booting from a floppy drive.

Available Settings Optimal Fail-Safe User


Read-Write ● ●
Read-Only

Hard Disk Access Control This option specifies the read/write access that is set when booting from a hard disk
drive.

Available Settings Optimal Fail-Safe User


Read-Write ● ●
Read-Only

S.M.A.R.T. For Hard Disks Set this option to Enabled to permit AMIBIOS to use the SMART (System
Management and Reporting Technologies) protocol for reporting server system information. The
S.M.A.R.T. enables a PC in some cases to predict the future failure of a hard disk drive.
S.M.A.R.T. has to be included in the HDD and appropriate Software has to be used (contact the
HDD manufacturer).
Available Settings Optimal Fail-Safe User
Disabled ●
Enabled ●

Boot Up Num Lock Set this option to Off to turn the Num Lock key off when the computer is booted so you can
use the arrow keys on both the numeric keypad and the keyboard.
Available Settings Optimal Fail-Safe User
Off
On ● ●

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 16 of 55
AMIBIOS® Setup

PS/2 Mouse Support Set this option to Enabled to enable AMIBIOS support for a PS/2-type mouse.

Available Settings Optimal Fail-Safe User


Disabled
Enabled ● ●

System Keyboard This option does not specify if a keyboard is attached to the computer. Rather, it specifies if
error messages are displayed if a keyboard is not attached. This option permits you to configure
workstations with no keyboards.
Available Settings Optimal Fail-Safe User
Absent ●
Present ●

Primary Display This option configures the type of graphics card that is expected to be in the system.

Available Settings Optimal Fail-Safe User


Absent
VGA/EGA ● ●
CGA40x25
CGA80x25
Mono

Note: With Absent chosen, the system will accept any graphics card, or none at all, without error
message or beep code.

Password Check This option enables password checking every time the system boots or when you run AMIBIOS
Setup.

Available Settings Optimal Fail-Safe User


Setup ● ●
Always

If Always is chosen, a user password prompt appears every time the computer is turned on. If
Setup is chosen, the password prompt appears if AMIBIOS Setup is executed. See the Advanced
Setup chapter for instructions on changing a password.

PCI Parity Check (CL7 only) Set this option to Enabled to check the parity on the PCI Bus. If a device on
the PCI Bus detects a parity error and signals it via PERR# PCI-signal, a NMI is generated, the
NMI handler displays a error message, switches the red status LED on and halts the system. The
settings are Disabled or Enabled. The Optimal and Fail-Safe default settings are Disabled.

Available Settings Optimal Fail-Safe User


Disabled ● ●
Enabled

Boot To OS/2 Set this option to Enabled if running OS/2 operating system and using more than 64 MB of
system memory on the motherboard.

Available Settings Optimal Fail-Safe User


No ● ●
Yes

Wait For ‘F1’ If Error Set this option to Enabled to make the system prompt for an <F1> keypress after
displaying any POST error message. With this option set to Disabled, error messages will still be
displayed but the system will continue the boot process if the error was non-fatal.

Available Settings Optimal Fail-Safe User


Disabled
Enabled ● ●

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 17 of 55
AMIBIOS® Setup

Internal Cache This option sets the type of caching algorithm used by the L1 internal cache memory on the
CPU.

Available Settings Optimal Fail-Safe User


Disabled
WriteThru
WriteBack ● ●

System BIOS Cacheable When set to Enabled, the contents of the F0000h system memory segment can be read
from or written to cache memory. The contents of this memory segment are always copied from
the BIOS ROM to system RAM for faster execution.
Available Settings Optimal Fail-Safe User
Disabled ●
Enabled ●

Symbios SCSI BIOS Use this option to decide if the Boot ROM for LSI Symbios SCSI controllers is to be
invoked. This does not alter the boot order that has been defined through the 1st/2nd/3rd boot
device options described above.
The SCSI BIOS must be enabled to allow access to disk drives attached to the SCSI interface.
Available Settings Optimal Fail-Safe User
Disabled
Auto ● ●

Note: This option does not disable the SCSI controller itself. Even with its BIOS ROM disabled,
the SCSI controller is fully functional, and devices attached to the SCSI interface can still be
used after the operating system has loaded the appropriate driver set.
This SCSI BIOS, when enabled, takes control of onboard SCSI controller devices as well as
compatible LSI Symbios SCSI controller devices found in PMC or CompactPCI slots.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 18 of 55
AMIBIOS® Setup

2.2.5 Advanced Chipset Setup


Choose Advanced Chipset Setup on the AMIBIOS Setup main menu. All Chipset Setup options are then
displayed.

USB Function Set this option to Enabled to activate the onboard USB (Universal Serial Bus) controller device.
Available Settings Optimal Fail-Safe User
Disabled
Enabled ● ●

USB Keyboard/Mouse Legacy Support Use this option to enable BIOS support for USB keyboards and mouse
devices in USB-unaware operating systems. USB Function option must be set to Enabled.

Available Settings Optimal Fail-Safe User


Disabled
Keyboard ●
Auto ●
Keyb+Mouse

Note: This feature only works when keyboard and/or mouse are connected to the onboard USB
controller, or if they are connected to a USB hub that is connected to the onboard USB
controller. Devices that are connected to add-on USB controller cards cannot be used for this
purpose.

Port 64/60 Emulation Set this option to Enabled to enable hardware emulation support for USB keyboard and
mouse devices. This allows using USB keyboard and mouse devices in USB-unaware operating
systems that access the keyboard controller through their own drivers rather than BIOS services.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

CPU Latency Timer If set to Enabled the CPU cycle is only deferred after being held in Snoop Stall for 31 clocks
and after another ADS# signal has arrived. If set to Disabled the CPU cycle is deferred
immediately after receiving another ADS# signal.
Available Settings Optimal Fail-Safe User
Disabled
Enabled ● ●

DRAM Page Closing Policy The settings are Closed or Open. If set to Closed, DRAM pages tend to be closed
after use. If set to Open, DRAM pages tend to be left open.
Available Settings Optimal Fail-Safe User
Closed ●
Open ●

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 19 of 55
AMIBIOS® Setup

D-Segment Hole (PC7 only) If set to Disabled, access to the address range 000D8000h – 000DFFFFh is
controlled as set for D000 64K Segment. The D000 Segment setting is done automatically, if no
PCI / PnP-ROM touches this Segment, it remains disabled (all accesses forwarded to HUB Link /
system bus). If a PCI / PnP ROM is loaded in this area it is set to Shadow RAM.- Reads are
directed to system memory DRAM, writes are directed to the HUB Link. If set to D8000-
DFFFF, all accesses to this address range are forwarded to the HUB Link. If set to DC000-
DFFFF, all accesses to this address range are forwarded to the HUB Link. From HUB Link the
transfer is directed to PCI-Bus and ISA-Bus.
On PC7 boards the optional onboard SRAM resides on this address range. To access SRAM
DC000 Hole has to be enabled.

PC7:
Available Settings Optimal Fail-Safe User
Disabled
D8000-DFFFF
DC000-DFFFF ● ●

CL7: not available

Memory Hole (PC7 only)This option specifies the location of an address space to be reserved for use by the ISA
bus.
Available Settings Optimal Fail-Safe User
Disabled ● ●
15MB-16MB

Note: When the 15MB-16MB memory hole is activated, then most operating systems will be
unable to use any memory that resides above it. This limits available extended memory to
14 MB, regardless of the amount physically present.

Graphics Mode Select This option selects the internal graphics device and the amount of system memory to be
used as video memory. The settings are UMA (Unified Memory Architecture) 1 MB or UMA 512
KB. The Optimal and Fail-Safe default Settings are UMA 1 MB. This memory is used for
standard VESA VGA and text modes. The system memory is reduced by this amount of
memory.
Available Settings Optimal Fail-Safe User
UMA 1 MB ● ●
UMA 512 KB

Display Cache Windows Size This option specifies the amount of cache available for the graphics local memory
window (the memory size used in PCI memory space). The settings are 32 MB OR 64 MB. The
Optimal and Fail-Safe default Settings are 64 MB. This establishes a kind of virtual frame buffer
in the PCI memory area, which is used and managed and dynamicaly mapped to DRAM by the
graphics device driver.
Available Settings Optimal Fail-Safe User
64 MB ● ●
32 MB

CPU Freq Select This option selects the method used to set the CPU frequency The settings are Hardware or
Software.
Available Settings Optimal Fail-Safe User
Hardware
Software ● ●

Note: This setting has no effect on standard CPUs, only Intel engineering samples are affected.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 20 of 55
AMIBIOS® Setup

CPU Freq Ratio This option sets the CPU frequency ratio., The settings are 1:2, 1:4, 1:3, 1:5, 2:5, 2:9, 2:7, 2:11,
1:6, 1:8, 1:7, 2:13, 2:15, or 1:2A.

Note: This setting has no effect on standard CPUs, only Intel engineering samples are affected.

ICH Decode Select This option sets the type of ICH decode used. The settings are Subtractive or Positive. To
enable the ISA bridge (Moon ISA Device) this option has to be Positive.

PC7:
Available Settings Optimal Fail-Safe User
Subtractive
Positive ● ●

CL7:
Available Settings Optimal Fail-Safe User
Subtractive
Positive ● ●

Moon ISA Device Enable Set this option to Enabled to enable moon ISA devices. The settings are Enabled or
Disabled. If ICH Decode Select is set to Subtractive this option can not be set to Enabled.

PC7:
Available Settings Optimal Fail-Safe User
Disabled
Enabled ● ●

CL7: not available

Sound Blaster Decode This option specifies the I/O address range used for Sound Blaster devices. The settings
are Disabled, 280h - 293h, 260h - 273h, 240h - 253h, or 220h - 233h. If a device which decodes
in one of these ranges is attached to the LPC-Bus, set this option to the appropriate address.
Otherwise set it to Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
280h – 293h
260h – 273h
240h – 253h
220h - 233h

Microsoft Sound Decode This option specifies the I/O address range used for Microsoft Sound System (MSS)
devices. The settings are Disabled, 530h - 537h, 604h - 60Bh, E80h - E87h, or F40h - F47h. If a
device which decodes in one of these ranges is attached to the LPC-Bus, set this option to the
appropriate address. Otherwise set it to Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
530h – 537h
604h – 60Bh
E80h – E87h
F40h – F47h

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 21 of 55
AMIBIOS® Setup

MIDI Decode This option specifies the I/O address range used for MIDI devices. The settings are Disabled, 330h
- 331h, or 300h - 301h. If a device which decodes in one of these ranges is attached to the LPC-
Bus, set this option to the appropriate address. Otherwise set it to Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
330h – 331h
300h – 301h

Ad Lib Range 388h - 38Bh Set this option to Enabled to allow Ad Lib-compatible sound devices to use the I/O
address range 388h - 38Bh. The settings are Enabled or Disabled. If a device which decodes in
this range is attached to the LPC-Bus, set this option to Enabled. Otherwise set it to Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

Game Port A Set this option to Enabled to enable game port A decode range 200h- 207h on the LPC-Bus. The
settings are Enabled or Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

Game Port B Set this option to Enabled to enable game port B decode range 208h – 20Fh on the LPC-Bus.
The settings are Enabled or Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

ICH Dev31 Func6 Enable Set this option to Auto to allow BIOS to enable ICH AC’97 Modem Controller (PCI
device 31 function 6) if CODEC is present. The settings are Auto or Disabled.
Available Settings Optimal Fail-Safe User
Auto ● ●
Disabled

ICH Dev31 Func5 Enable Set this option to Auto to allow BIOS to enable ICH AC’97 Audio Controller (PCI
device 31 function 5) if CODEC is present. The settings are Auto or Disabled.
Available Settings Optimal Fail-Safe User
Auto ● ●
Disabled

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 22 of 55
AMIBIOS® Setup

DMA-0 Type
DMA-1 Type
DMA-2 Type
DMA-3 Type
DMA-5 Type
DMA-6 Type
DMA-7 Type These options specify the bus that the specified DMA channel can be used on. PC/PCI and LPC
DMA are useful to redirect an LPC DMA channel to a special PCI add-on card that emulates an
ISA device. Actual ISA devices must use PC/PCI, because the ISA bridge is attached to the
PCI-Bus.
Available Settings Optimal Fail-Safe User
LPC DMA All All
PC/PCI

Note: Please make sure that those DMA channels that are used for onboard serial port 2 and
parallel port 1 have their channel set to LPC DMA and onboard parallel port 2 has set it to
PC/PCI. The onboard FDC controller uses DMA-6 which should be set to LPC DMA.

ICH Delayed Transaction Set this option to Enabled to enable ICH delayed transactions. The settings are
Enabled or Disabled.
Available Settings Optimal Fail-Safe User
Disabled ●
Enabled ●

ICH DCB Enable Set this option to Enabled to enable ICH DMA Collection Buffer for PC/PCI and LPC DMA.
The settings are Enabled or Disabled.
Available Settings Optimal Fail-Safe User
Disabled ●
Enabled ●

80 Pin Cable Detection Method Use this option to select the method to detect an 80-pin IDE cable. The available
methods are By GPIO and By Drive. For ATA-66 to work it is necessary to use an 80-pin ATA-
66 cable. If IDE Busmaster (see PCI IDE Bus Master) is enabled, BIOS checks if an 80-pin
cable is present and if the atached drive is ATA-66 capable DMA-66 transfers are used, if not,
ATA-66 is not used.
Available Settings Optimal Fail-Safe User
By GPIO ● ●
By Drive

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 23 of 55
AMIBIOS® Setup

VMEbus System Controller State (CL7 only) In systems with a VMEbus (with SBS-or CVME3/6 PCI to VME
Bridge-Card), this option decides if the VMEbus bridge device on this mainboard becomes the
VMEbus System Controller. In Auto mode, the VME64 System Controller Auto-Detect sequence
will be used, and the outcome will depend on which slot the mainboard is in. Setting to Enabled
or Disabled forces the respective state, and should only be used when the auto-detect sequence
gives incorrect results.

PC7: not available.


CL7:
Available Settings Optimal Fail-Safe User
Disabled
Enabled
Auto ● ●

Note: This setting applies only to CL7 with a separate CPCI-to-VMEbus bridge card (SBS
CVME3/6).

VMEbus Fast DTACK# Filtering (CL7 only) This option determines whether the VMEbus bridge device
shortens the minimum time the DTACK# signal is sampled inactive before initiating a new
access. Normally, this feature should remain Disabled for best line noise immunity. Set to
Enabled for improved performance in low noise VMEbus system configurations.

PC7: not available.


CL7:
Available Settings Optimal Fail-Safe User
Safer ● ●
Faster

Note: This setting applies only to CL7 with a separate CPCI-to-VMEbus bridge card (SBS
CVME3/6).

VMEbus Access Window Size (CL7 only)This option reserves empty local address space for use with VMEbus
applications. VMEbus drivers use this space to map portions of the VMEbus address space into
local address space.

PC7: not available.


CL7:
Available Settings Optimal Fail-Safe User
Disabled
256 MB
512 MB ● ●
1024 MB

Note: This setting applies only to CL7 with a separate CPCI-to-VMEbus bridge card (SBS
CVME3/6).

Spread Spectrum Clock Modulation Set this option to Enabled to enable Clock generator Spread Spectrum
Clock Modulation, wich decreases EMI. The settings are Enabled or Disabled.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 24 of 55
AMIBIOS® Setup

2.2.6 PCI / Plug and Play Setup


Choose PCI/Plug and Play Setup from the AMIBIOS Setup screen to display the PCI and Plug and Play
Setup options, described below.

Plug and Play Aware O/S Set this option to Yes to inform AMIBIOS that the operating system can handle plug
and Play (PnP) devices.
Available Settings Optimal Fail-Safe User
No ● ●
Yes

Note: With this option set to No, BIOS PnP services will still be available to the operating
system. The difference lies in which device classes will be enabled by BIOS, and which ones
remain disabled to be dealt with by the OS. With No selected, BIOS will enumerate and enable
all PnP and PCI devices. Choose Yes to have BIOS enable only those devices that are required to
boot the system.

PCI Latency Timer (PCI Clocks) This option specifies the latency timings (in PCI clocks) for PCI devices
installed in the PCI expansion slots. This controls the amount of time a PCI bus master can burst
data on the PCI bus before allowing other PCI bus masters to gain control.
Available Settings Optimal Fail-Safe User
One of 32 – 248 (in increments of 32) 64 64

PCI VGA Palette Snoop Setting this option to Enabled allows multiple display devices to receive color palette
data, so that all those devices use the same color settings.
VGA Palette Action
Snoop Bit
Disabled Data read and written by the CPU is only directed to the
PCI VGA device's palette registers.
Enabled Data read and written by the CPU is directed to the both the
PCI VGA device's palette registers and the ISA VGA
device palette registers, permitting the palette registers of
both devices to be identical.

This feature is typically required for video multimedia add-on devices that need to know the
system’s color palette in order to provide a correct display.
Available Settings Optimal Fail-Safe User
Disabled ● ●
Enabled

PCI IDE Bus Master Set this option to Enabled to specify that the IDE controller on the PCI bus has bus
mastering capability.
Available Settings Optimal Fail-Safe User
Disabled ●
Enabled ●

Note: The onboard PCI IDE controller is bus master capable.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 25 of 55
AMIBIOS® Setup

DMA Channel 0
DMA Channel 1
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7 These options allow you to specify the type of device that uses each DMA channel. For onboard
peripherals and add-on ISA PnP cards, select PnP. Set those DMA channels to ISA/EISA that are
used by legacy non-PnP ISA cards. BIOS PnP services will only use the channels that are set to
PnP here, so that no PnP compatible device will be assigned a DMA channel that is being used
by a legacy device.
Available Settings Optimal Fail-Safe User
PnP All All
ISA/EISA

Note: Using these options is only necessary when the system configuration contains legacy ISA
add-on devices that remain undetected by BIOS, or when there are devices that are enabled by
the operating system, like PCCard-16 devices or PCI sound cards with a legacy sound card
emulation software. In those cases, those DMA channels that are to be used by these devices
must be set to ISA/EISA here.

IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15 These options specify the bus that the specified IRQ line is used on. Similarly to the DMA
Channel options described above, these options allow you to reserve IRQs for legacy ISA
adapter cards. Onboard I/O and PnP ISA add-on cards are configured by AMIBIOS. All IRQs
used by onboard I/O must be configured as PCI/PnP.
Available Settings Optimal Fail-Safe User
PCI/PnP All All
ISA/EISA

Note: The IRQ lines reserved to ISA/EISA here, plus those occupied by ISA PnP add-ons, plus
the onboard peripherals’ IRQ usage (see next paragraph), must not lead to a situation where all
IRQ lines are taken. At least one IRQ line must remain available for use on the PCI bus. If this is
not the case, BIOS PnP services will not be able to initialize the PCI bus system to an operational
state, meaning that no onboard PCI device and no PCI add-on cards will be usable.
Using these options is only necessary when the system configuration contains legacy ISA add-on
devices that remain undetected by BIOS, or when there are devices that are enabled by the
operating system, like PCCard-16 devices or PCI sound cards with a legacy sound card
emulation software. In those cases, those IRQs that are to be used by these devices must be set to
ISA/EISA here.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 26 of 55
AMIBIOS® Setup

Reserved Memory Size This option specifies the size of the memory area reserved for legacy ISA adapter cards.
Available Settings Optimal Fail-Safe User
Disabled ● ●
16k
32k
64k

The settings are Disabled, 16K, 32K, or 64K. The Optimal and Fail-Safe default settings are
Disabled
NOTE: This setting has no influence to the shadow state, it only prevents BIOS from using this
memory region, while mapping PnP or PCI devices. Also VGA-BIOS is mapped always to
C0000h.

Reserved Memory Address This option specifies the beginning address (in hex) of the reserved memory area.
The specified ROM memory area is reserved for use by legacy ISA adapter cards.
Available Settings Optimal Fail-Safe User
One of C0000h – DC000h (in increments of 4000h) C8000 C8000

Note: The memory region reserved here should also have its Shadowing Control set to Disabled.
Please see the “Advanced Chipset setup” paragraph (D-Segment Hole) for details.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 27 of 55
AMIBIOS® Setup

2.2.7 Peripheral Setup


Peripheral Setup options are displayed by choosing Peripheral Setup from the AMIBIOS Setup main
menu. All Peripheral Setup options are described here.

Important note: BIOS Setup defaults are such that most peripheral devices are set to Auto resource
assignment. However, with this setting, many of the less frequently used peripherals will remain inactive
in favor of assigning as many interrupt lines as possible to the PCI bus. Serial ports 1 and 2 as well as
parallel port 1 will be active. All other peripheral options, such as CAN, ENUM, Monitor External Alert
on IN 1 / 2 etc., do not get an interrupt assigned if set to AUTO.
When a different setup of peripheral devices is required, then all devices listed in the “Peripherals” setup
page (with the exception of the FDC controller) must have their resources assigned manually.

Onboard FDC Set this option to Enabled to enable the floppy drive controller on the motherboard.
Available Settings Optimal Fail-Safe User
Auto (enable unless add-on FDC is present) ● ●
Disabled
Enabled (uses IRQ6 and DMA2)

Drive and Port Interface (PC7 only) Use this option to define what floppy disk drives (FDD) are connected.

CL7: only effective with hardware revisions obove V4.0


PC7:
Available Settings Optimal Fail-Safe User
A:FDC, B:FDC ● ●
A:FDC, B:LPT
A:LPT, B:LPT

Note: The swapping is done on hardware level, and is effective even in operating systems that
use their own drivers to access the FDDs.
The external FDD provided by SBS Technologies connects to drive B: signals. For this device,
this option should be set to Yes even if it is the only FDD in the system, thus making it drive A:.

Swap Floppy Drives (PC7 only) When two FDDs are connected, set this option to Yes to make the A: drive
appear as B: and vice versa.
Available Settings Optimal Fail-Safe User
No ● ●
Yes

Note: The swapping is done on hardware level, and is effective even in operating systems that
use their own drivers to access the FDDs.
Also note that the drive type settings on the “Standard CMOS Setup” page list the drive letters as
they appear to the operating system (i.e. after swapping), while the above Drive and Port
Interface option refers to the actual unswapped drive connections on the FDC.
The external FDD provided by SBS Technologies connects to drive B: signals. For this device,
this option should be set to Yes even if it is the only FDD in the system, thus making it drive A:.

To use SBS-Technologies parallel port floppy drive set Drive and Port Interface to A:FDC,
B:LPT and Swap Floppy Drives to Yes.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 28 of 55
AMIBIOS® Setup

Onboard Serial Port1 This option specifies the base I/O port address of serial port 1.
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on serial ports) ● ●
Disabled
3F8h, IRQ4
2F8h, IRQ3
3E8h, IRQ4
2E8h, IRQ3

Onboard Serial Port2 This option specifies the base I/O port address of serial port 2.
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on serial ports) ● ●
Disabled
3F8h, IRQ4
2F8h, IRQ3
3E8h, IRQ4
2E8h, IRQ3

Onboard Parallel Port This option specifies the base I/O port address of the 1st parallel port on the motherboard.
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on parallel ports) ● ●
Disabled
378h
278h
3BCh (EPP mode not available)

Parallel Port Mode This option specifies the parallel port mode. Set this option to the mode recommended for the
connected peripheral.
Setting Description
Normal The normal parallel port mode is used.
EPP The parallel port can be used with devices that adhere to the
Enhanced Parallel Port (EPP) specification. EPP uses the existing
parallel port signals to provide asymmetric bidirectional data transfer
driven by the host device.
ECP The parallel port can be used with devices that adhere to the
Extended Capabilities Port (ECP) specification. ECP uses the DMA
protocol to achieve data transfer rates up to 2.5 Megabits per second.
ECP provides symmetric bidirectional communication.

Available Settings Optimal Fail-Safe User


Normal
EPP
ECP ● ●

EPP Version This option specifies the Enhanced Parallel Port specification version number that is used in the
system. This option only appears if the Parallel Port Mode option is set to EPP. Please consult
the manual of the connected peripheral for information on which version to choose.
Available Settings Optimal Fail-Safe User
1.7
1.9 ● ●

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 29 of 55
AMIBIOS® Setup

Parallel Port IRQ This option specifies the IRQ used by the parallel port. This option can only be set when the
Onboard Parallel Port setting is not Auto.
Available Settings Optimal Fail-Safe User
Auto (while Onboard Parallel Port is set to Auto) ● ●
7
5

Parallel Port ECP DMA Channel This option sets the DMA channel used by the parallel port. It is only available
if the setting for the Parallel Port Mode option is ECP.
Available Settings Optimal Fail-Safe User
Auto (while Onboard Parallel Port is set to Auto) ● ●
3
1

Onboard Serial Port 3 (PC7 only) This option specifies the base I/O port address of serial port 3.

PC7:
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on serial ports) ● ●
Disabled
3F8h, IRQ11
2F8h, IRQ10
3E8h, IRQ11
2E8h, IRQ10

Onboard Serial Port 4 (PC7 only) This option specifies the base I/O port address of serial port 4.

PC7:
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on serial ports) ● ●
Disabled
3F8h, IRQ11
2F8h, IRQ10
3E8h, IRQ11
2E8h, IRQ10

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 30 of 55
AMIBIOS® Setup

Onboard Parallel Port 2 (PC7 only) This option specifies the base I/O port address of the 2nd parallel port on the
motherboard.

PC7:
Available Settings Optimal Fail-Safe User
Auto (steer around detected add-on parallel ports) ● ●
Disabled
378h
278h
3BCh (EPP mode not available)

Parallel Port 2 Mode (PC7 only) This option specifies the parallel port mode. Set this option to the mode
recommended for the connected peripheral.
Setting Description
Normal The normal parallel port mode is used.
EPP The parallel port can be used with devices that adhere to the
Enhanced Parallel Port (EPP) specification. EPP uses the existing
parallel port signals to provide asymmetric bidirectional data transfer
driven by the host device.
ECP The parallel port can be used with devices that adhere to the
Extended Capabilities Port (ECP) specification. ECP uses the DMA
protocol to achieve data transfer rates up to 2.5 Megabits per second.
ECP provides symmetric bidirectional communication.

PC7:
Available Settings Optimal Fail-Safe User
Normal
EPP
ECP ● ●

EPP Version(PC7 only) This option specifies the Enhanced Parallel Port specification version number that is
used in the system. This option only appears if the Parallel Port Mode option is set to EPP.
Please consult the manual of the connected peripheral for information on which version to
choose.

PC7:
Available Settings Optimal Fail-Safe User
1.7
1.9 ● ●

Parallel Port 2 IRQ (PC7 only) This option specifies the IRQ used by the parallel port. This option can only be
set when the Onboard Parallel Port setting is not Auto.

PC7:
Available Settings Optimal Fail-Safe User
Auto (while Onboard Parallel Port is set to Auto) ● ●
5

Parallel Port 2 DMA Channel (PC7 only) This option sets the DMA channel used by the parallel port. It is only
available if the setting for the Parallel Port Mode option is ECP.

PC7:
Available Settings Optimal Fail-Safe User
Auto (while Onboard Parallel Port is set to Auto) ● ●
1

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 31 of 55
AMIBIOS® Setup

Onboard IDE This option specifies the IDE channel used by the onboard IDE controller.

PC7:
Available Settings Optimal Fail-Safe User
Disabled
Primary (uses IRQ14)
Secondary (uses IRQ15)
Both (uses IRQ14 and IRQ15) ● ●

CL7:
Available Settings Optimal Fail-Safe User
Disabled
Primary (uses IRQ14) ● ●

Onboard CAN (PC7 only) This option specifies the IRQ used by the onboard CAN controller. This option
is only available if the controller device is physically present and the Moon ISA Device is
enabled (see Moon ISA Device Enable page 21). Otherwise, the option will show as N/A. With
No IRQ selected, the controller will still be usable for polled operation.

PC7:
Available Settings Optimal Fail-Safe User
Auto
No IRQ ● ●
One of IRQ 3-5,7,9-12,14,15

With No IRQ selected, the controller will still be usable for polled operation.

Monitor External Alert on IN 1 / 2 (PC7 only) This option selects which Interrupt is triggered if IN1 or IN2
changes from the inactive to the active state. Choose a IRQ number, or No IRQ for polled
operation or if IN1 and IN2 is not used at all.

PC7:
Available Settings Optimal Fail-Safe User
Auto
No IRQ ● ●
One of IRQ 3-5,7,9-12,14,15

PCI ENUM# signal (CL7 only) This option selects whether CompactPCI Hot Plugging events trigger a Hardware
Monitoring interrupt. Choose an IRQ number to do so, or No for polled operation of Hot Plug
drivers or no Hot Plug support at all.

CL7:
Available Settings Optimal Fail-Safe User
Auto
No IRQ ● ●
One of IRQ 3-5,7,9-12,14,15

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 32 of 55
AMIBIOS® Setup

TCO Timer Timeout This option selects the timeout for the TCO Timer (Watchdog) at the first timeout the
timeout register in the TCO registers is set. At the second timeout a reset is generated. To use
this feature special operating software is necessary to prevent rebooting while the operating
system is running. See also: 3.6 *SBS0040 - Watchdog / TCO timer on page 44.
Don’t enable this feature if you are not sure what you are doing.
Available Settings Optimal Fail-Safe User
Disabled ● ●
One of 2s – 36s (this times are rounded values)

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 33 of 55
AMIBIOS® Setup

2.3 Security
The Supervisor and User passwords activate two different levels of password security: Supervisor and
User. Depending on the security level, setup screens may or may not be available to the operator.
In addition, BIOS may be prepared so that all users must enter a password every time the system boots
or when AMIBIOS Setup is executed.
2.3.1 Setting a Password
From the main AMIBIOS screen, select “Change Supervisor Password”, and enter the new Supervisor
Password (twice). If there was a password set before, you must first enter the existing password before
being prompted to type the new one.
Once a supervisor password has been set, the “Change User Password” item becomes available as well.

If You Do Not Want to Use a Password just press <Enter> when the password prompt appears.

Remember the Password! Keep a record of the new password when the password is changed. If you forget the
password, you must erase the system configuration information in NVRAM (Non-Volatile
Random Access Memory). A method to do this is to hold down the <Ins> key while powering up
the system. See the Hardware Manual for information about other methods of erasing system
configuration information.

2.3.2 Access Restriction


On the Advanced CMOS Setup screen, the option “Password Check” is used to set the desired level of
access restriction. Available choices restrict access to Setup (“Setup”) or any usage of the computer
(“Always”) to be available to password owners only.

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AMIBIOS® Setup

2.4 Automatic Configuration


The menu items in this category permit you to select a group of settings for AMIBIOS Setup options.
Not only can you use these to quickly set system configuration parameters, you can choose a group of
settings that have a better chance of working when the system is having configuration-related problems.

2.4.1 Auto-Detect Hard Disk


Selecting this item from the AMIBIOS Setup main screen will enter the Standard CMOS Setup page,
and automatically detect all the IDE drives attached. Devices attached to the Floppy connectors cannot
be detected. Their type must always be set manually.
Please verify that the detection results match the connected IDE hardware, and correct the settings
manually as required.
Note: In general, using this menu item is not recommended. For optimal system behavior with fully IDE
and/or ATAPI compliant devices, please set the IDE drive type to Auto on those channels where a
device of any type is connected, and to Not Installed for the others.

2.4.2 Auto Configuration


These two main menu items provide a quick way of reverting the system configuration to a factory
predetermined set of well working defaults.
Note that the settings on the Standard CMOS Setup page will not be changed, in order to avoid losing
the IDE drive parameters that have been set manually or gained through auto-detection.

Optimal Load the Optimal default settings for the AMIBIOS by selecting the “Auto Configuration with
Optimal Settings” item on AMIBIOS Setup main screen. The Optimal default settings are best-
case values that should optimize system performance. If NVRAM is corrupted, the Optimal
settings are loaded automatically.
The Optimal set of defaults (including the settings from Standard CMOS Setup) is also loaded
when the <End> key is held down at system hard-reset or at powerup, or at every powerup if this
particular BIOS has been prepared for use on systems that don’t have a battery backed NVRAM.
In the latter case, changes made in Setup will not be permanent. However, these changes will be
retained across hardware reset or software reboot sequences.

Fail-Safe Load the Fail-Safe settings by selecting the “Auto Configuration with Fail-Safe Settings” item on
AMIBIOS Setup main screen.
The Fail-Safe settings provide far from optimal system performance. These settings have been
carefully chosen to allow booting an operating system and run diagnostic software even if some
undetermined component in the system would make it fail with “Optimal” settings chosen. Use
this option as a diagnostic aid if the system is behaving erratically.

Please note that using these two menu items will also alter internally used settings that are not visible in
the Setup pages. In order to return from a test in Fail Safe mode to settings suitable for normal operation,
it is therefore recommended to first use the “Optimal” preset and then change settings from there.

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On Board Features

3 Using and programming the on board features

3.1 Plug&Play BIOS Services


The general steps in detecting and using the Plug&Play device interface offered by system BIOS
are described in Microsoft’s Plug&Play Specification 1.0A (see:
http://www.eu.microsoft.com/hwdev/PlugnPlay). Sample code is available from SBS
Technologies on request.
Plug&Play BIOS device support follows the concept of representing a device’s logical function
block in a device node. Such a node has a unique identification number, and several tags
describing the resources used by the device (I/O ports, memory, interrupts, DMA channels). A
single hardware device may contain more than one logical function, and thus be represented by
several device nodes. The opposite may also be true, where a logical function is formed by
several hardware devices and thus is represented in a single device node.
SBS Technologies has registered the Plug&Play manufacturer ID code “SBS” with Microsoft.
The implemented device node types divide into two main classes. While the *SBS0xxx range
classifies actual I/O hardware, the *SBS1xxx range includes the unique sets of mainboard feature
control registers. Chapter 3.2 gives a summary of the feature sets that are present on each of the
mainboard models covered in this manual, while chapter 3.3 describes those mainboard features
in detail. The I/O hardware devices that are optionally available on various models are
documented in chapter 3.4 *SBS0001 – Intel i82527 CAN controller.
Since some of the mainboard features are also useful, or even required, for handling those I/O
devices, a common approach to using those onboard devices is to first determine which set of
mainboard features is present, and then find and use the desired I/O device.

3.2 Mainboard Feature Control Register (MFCR) Sets


Any SBS Technologies mainboard model combines a certain choice of the features described in
the previous chapter in a feature set. In order to safely use one of these features, software must
first determine which feature set is currently present.
To achieve this, software will normally implement access methods suitable for the range of SBS
Technologies mainboards on which it is to run, and then use the appropriate one depending on
which one of the feature sets known to the software has been detected. If no known feature set is
found, or none at all, the software is required to stop operation and alert the user of incompatible
hardware.
The actual detection of mainboard feature control register sets is done by scanning PnP BIOS
device nodes for those node IDs in the *SBS1xxx range that are used on mainboards relevant to
the software. PnP BIOS services will never report more than one node from this range. The
following pages describe the sets that are currently found on PnP-capable SBS Technologies
mainboards.
Once a matching device node has been retrieved, its contents can be analyzed. Behind the node
header, a sequence of tags describes the resource used by a certain function. The usual approach
for programmers that want to use a certain mainboard feature is to first scan the list of PnP
device nodes for the mainboard type(s) to be supported, then determine the resources that belong
to that feature.
It is guaranteed that the implementation underlying a given device node ID never changes; both
the actual hardware and the sequence of tags are guaranteed to be the same. Even the slightest
change in register map or behavior from an existing feature set will lead to the definition of a
new, unique ID code.
Device ID codes actually consist of three parts, a three-letter manufacturer ID, a three-digit
device ID, and a one-digit revision count. When a new feature gets added to an existing set,
without altering any of the existing ones, the device ID will remain the same, and the revision
counter will increase. In that case, additional tags may be appended to the otherwise unchanged
device node.

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On Board Features

Software should be written with forward compatibility regarding this revisioning scheme in
mind. The device node structure allows to do this by use of the Compatible Device ID list of
tags. For the initial revision of a given device, this list is empty; further revisions list the full
device node ID of the previous ones. For example, software that wants to use features from
*SBS1000 should inspect all nodes that ID as *SBS100x, and accept a node that either identifies
as *SBS1000 directly, or those with device IDs *SBS1001 through *SBS100F that have a
Compatible Device ID tag *SBS1000 in their device node structure.
Please refer to Microsoft’s Plug&Play ISA Specification, Chapter 6, for detail information on the
device node structure definition and tag substructure usage.

3.2.1 *SBS1060 – PC7


The PC7 mainboard implements the following features:

 Mainboard register set


– Lock/Unlock register (only with on board CAN option)
 General Purpose I/O (PC7)
– External Alert input lines IN1 and IN2 with possible, hardware monitoring interrupt
– External Signal output lines OUT1, OUT2, OUT3 and OUT4
– Status LED Control
– Hardware Monitoring interrupt on External Alert input lines IN1 and IN2
 128 KB battery powered SRAM
– Enable / Disable SRAM register
– 16 KB SRAM access window
– Bank select register to select 16KB SRAM bank.

These features are represented in the device node data structure as follows:

Node ID *SBS1060 (6010534Ch)


Tag Type Symbol Contents
1 FPORT register set Mainboard register set
2 FMEM32 SRAM window 16 KB Memory window used to access 128 KB on board SRAM
3 PORT GPIO1 General Purpose I/O ports (part 1), GPIO base
4 PORT GPIO2 General Purpose I/O ports (part 2)
5 XIRQ HWMON IRQ Hardware Monitoring event IRQ line

To eliminate the need for future software updates when the mainboard feature set is enhanced,
drivers that use tag information that is now contained in *SBS1060 shouldn’t do a device node
search for *SBS1060 only. Instead, inspect any found device node from the range *SBS1060
through *SBS106F. If *SBS1060 is found, accept it; *SBS1061 through *SBS106F should have
their tag list scanned for a Compatible Device ID tag with *SBS1060 in its data field and be
accepted if this is found.
In reverse, software that requires one of the additional tags from later revisions must not accept
and use data from an earlier revision’s device node ID.

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On Board Features

3.2.2 *SBS1040 – CL7


The CL7 mainboard implements the following features:

 General Purpose I/O


– Status LED control
– CompactPCI ENUM signal
 CompactPCI ENUM interrupt

These features are represented in the device node data structure as follows:

Node ID *SBS1040 (4010534Ch)


Tag Type Symbol Contents
1 PORT GPIO1 General Purpose I/O ports (part 1), GPIO base
2 PORT GPIO2 General Purpose I/O ports (part 2)
3 XIRQ ENUM IRQ CompactPCI Hot Plugging event IRQ line

To eliminate the need for future software updates when the mainboard feature set is enhanced, drivers
that use tag information that is now contained in *SBS1040 shouldn’t do a device node search for
*SBS1040 only. Instead, inspect any found device node from the range *SBS1040 through *SBS104F.
If *SBS1040 is found, accept it; *SBS1041 through *SBS104F should have their tag list scanned for a
Compatible Device ID tag with *SBS1040 in its data field and be accepted if this is found.
In reverse, software that requires one of the additional tags from later revisions must not accept and use
data from an earlier revision’s device node ID.

3.3 Mainboard features

3.3.1 Mainboard register set


This register set is only used if PC7 is equipped with onboard CAN option. On PC7 boards
without CAN option this register set is not available. If mainboard register set is not available the
size of the used ressources of tag descriptor one is zero (the order and presence of descriptor tags
is not changed). This register set contains several registers which are reserved, the only one used
is LOCKR which is described in the next chapter.

3.3.1.1 Lock/Unlock Register - LOCKR (PC7)


To protect the mainboard feature control registers from unwanted access by unrelated software,
most of the register set is normally hidden. A certain bit pattern must be written to LOCKR Lock
Bit Pattern (LBP) bits before accessing these registers. Actual I/O hardware devices as described
later in chapter 3.4*SBS0001 – Intel i82527 CAN controller may also be affected.
The register set base address must be obtained from the mainboard’s feature control register set
Plug&Play device node described in chapter 3.2.
I/O port: (register set base)+9h
Size: 8 bit
Bit Name Write Read
7-0 LBP 05h to unlock extended registers F8h if extended regs unlocked
04h to lock extended registers FFh if extended regs locked

Before accessing the onboard CAN Controller described in chapter 3.4, the register set must be
made visible by writing 05h to the LBP bits. Writing 04h hides the register set from both writing
and reading. The current state of the LOCKR register can be determined by reading LBP. Bit

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On Board Features

pattern F8h means that all the lockable features are unlocked (visible); a read value of FFh means
they are locked (invisible).
It is recommended that the register set is hidden again immediately after the software has
finished using that mainboard feature’s registers. However, software must take into account that
LOCKR may have been operated by concurrently running other software.
It is thus mandatory that either a centralized handler operate the LOCKR using lock/unlock
counters, or that every piece of software that uses LOCKR accounts for this situation. In the
latter case, software may never assume that the locked/unlocked state remains the same over a
period of time. Instead, LOCKR must be operated before and after the actual feature register
accesses, and this must be done by first reading and memorizing the current state of LOCKR,
then unlocking, and, when finished accessing feature registers, restoring the memorized state.

3.3.2 General purpose I/O (PC7)


PC7 provides two general purpose opto isolated inputs which can be used to trigger an interrupt.
This interrupt is selected in the BIOS Setup (see Monitor External Alert on IN 1 / 2 page 32
Tag descriptor 3 and 4 defines an I/O address space where the registers, to read and write the I/O
ports, are located. Descriptor Tag 5 (type XIRQ) defines the IRQ used.
WARNING: Regard any bit in this space, not described in this document, as reserved. It is
possible that some vital board functions depend on values programmed in them. Actually the
whole I/O address space described by descriptor tag 3 and tag 4 is writeable, so be aware not to
change any undocumented bit.
The 3rd tag descriptor defines the base address of the GPIO programming register I/O space. The
offsets given in this chapter refer to this base.
GPIO base + 04Bh:
Bit Name Function Description
0 OUT1 Output Value OUT1 Set this bit to program the OUT1 port level to high
1 OUT2 Output Value OUT2 Set this bit to program the OUT2 port level to high
2 OUT3 Output Value OUT3 Set this bit to program the OUT3 port level to high
3 OUT4 Output Value OUT4 Set this bit to program the OUT4 port level to high
4 BSEL0 Bank select 0 See SRAM page 41
5 BSEL1 Bank select 1 See SRAM page 41
6 BSEL2 Bank select 2 See SRAM page 41
7 Res Reserved

GPIO base + 04Dh


Bit Name Function Description
0-4 Res Reserved
5 IN1 INPUT 1 Read input level on INPUT 1
6-7 Res Reserved

GPIO base + 04Ch


Bit Name Function Description
0-2 Res Reserved
3 IN2 INPUT 2 Read input level on INPUT 2
4-7 Res Reserved

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On Board Features

3.3.3 CompactPCI PCI ENUM Signal (CL7)


PCI ENUM signal is used in CompactPCI systems that support hot plugging. A “1” state
indicates that a hot plugging event has occurred, meaning that at least one CompactPCI device is
currently requesting either insertion or extraction.
Using BIOS Setup, this signal can be assigned an IRQ line. The contents of a device node XIRQ
tag (ENUM IRQ) reflect this assignment; it is controlled through a system BIOS setup item.
Depending on user selection and system wide resource availability, the tag might contain an
empty bitmap (all zero) indicating that no IRQ line was assigned to CompactPCI hot plugging
events. The ENUM# signal can still be used under these conditions, but only in polled operation.
If software cannot operate in polled mode, the user must be notified of the situation and software
operation then ceased, so that the user can reboot the system and enter BIOS setup to take
whatever steps are necessary to assign an IRQ line. Details on how to do this can be found in the
chapter AMIBIOS Setup: PCI ENUM# signal.
Tag descriptor 1 and 2 (of *SBS104x device node) defines an I/O address space where the
registers, to read and write the I/O ports, are located. Descriptor Tag 3 (type XIRQ) defines the
IRQ used.
WARNING: Regard any bit in this space, not described in this document, as reserved, it is
possible that some vital board functions depend on values programmed in them. Actually the
whole I/O address space described by descriptor tag 1 and tag 2 is writeable, so be aware not to
change any undocumented bit.
The 1st tag descriptor defines the base address of the GPIO programming register I/O space. The
offsets given in this chapter refer to this base.
GPIO base + 04Dh
Bit Name Function Description
0-3 Res Reserved
4 ENUM PCI ENUM signal 1: CompactPCI hot-plugging event
level 0: normal condition
5-7 Res Reserved

3.3.4 Status LED (PC7 and CL7)


The status LED, used at Powerup to indicate the system status, can be used for any customer
purpose. With the LEDPOW register the LED is switched on and off. With LEDCTRL the
behaviour of the LED can be changed. GPIO base is described by tag descriptor 1 for CL7 (node
ID *SBS104x) and by tag descriptor 3 for PC7 (node ID *SBS106x).
GPIO base + 050h
Bit Name Function Description
0 Res Reserved
1 LEDPOW LED Power To switch LED on, set this bit to 1.
2-7 Res Reserved

GPIO base + 05Eh


Bit Name Function Description
0:1 LEDCTRL Reserved 00 = On
01 = Blink at 1 Hz rate with 50% duty cycle (0.5s on 0.5s off)
10 = Blink at ½ Hz rate with 75% duty cycle (1.5s on 0.5s off)
11 = Off
2-7 Res Reserved

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On Board Features

3.3.5 SRAM (PC7)


PC7 provides optional 128KB battery buffered SRAM which is accessed through a 16KB
memory window. Tag descriptor 2 (type fmem32) of SBS1060 PnP node provides the address
where this memory window is located. The memory shadow / cache setting for this range has to
be disabled (not shadowed / cached). Currently this memory range is fixed at DC000h, therefore
it is usefull to enable DC000-hole (see D-Segment Hole) in the BIOS Setup to enable access to
the SRAM window, even if BIOS sets the D000 segment to shadow, because of some PCI / PnP
ROM. Software should not make any assumptions on this address, it should always use the Plug
and Play mechanism to determine the address of the SRAM memory window.
The SRAM with its decode logic is placed on the ISA Bus, therefore MOON ISA Device (see
Moon ISA Device Enable page 21) has to be enabled in BIOS Setup.
To make SRAM visible / accessible to software the SRM_EN bit has to be set. Setting this bit to
0 disables access to SRAM, the contents of SRAM is not affected. With the BSEL0 to BSEL2
bits the desired 16 KB bank of SRAM is selected. These three bits can be programmed with
values between 0 and 7, which are eight 16 KB banks forming together 128KB SRAM memory.
The contents of SRAM can be read or written through the SRAM memory window with normal
memory operations. GPIO base is described by descriptor Tag 3 and 4 (see 3.3.2 General
purpose I/O).

Note: BIOS SRAM detection uses the first two words of SRAM. The values contained in the
SRAM are restored after detection, however if system fails in exactly this moment (a few micro
seconds), the first two words (or a part of them) may be destroyed.

GPIO base + 04Eh:


Bit Name Function Description
0-2 Res Reserved
3 SRM_EN Enable SRAM Set this bit to 1 to make SRAM window accessible to software
4-7 Res Reserved

GPIO base + 04Bh:


Bit Name Function Description
0-3 OUT 1, 2, 3, 4 See General purpose I/O page 39
4 BSEL0 Bank select 0 least significant bit of SRAM bank number
5 BSEL1 Bank select 1 first bit of SRAM bank number
6 BSEL2 Bank select 2 most significant bit of SRAM bank number
7 Res Reserved

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On Board Features

3.4 *SBS0001 – Intel i82527 CAN controller


SBS Technologies PC7 optionally can be equipped with an Intel i82527 CAN controller device.
The CAN controller is attached to the ISA bus, mapped into 256 bytes of contiguous I/O port
space and using a single interrupt request line. Such an implementation of onboard CAN is
represented in a PnP device node with the ID code *SBS0000. Currently on PC7 this node is
revision 1 and reads SBS1001.
While the actual implementation of I/O address decoding and interrupt routing toward the i82527
may differ among the various types of motherboards, these differences are taken care of by
system BIOS. The programming model visible to application or driver software remains
constant, allowing those implementations to be handled all the same under the *SBS0000 device
ID.
Once software has successfully searched the PnP device nodes for this ID, and thus retrieved the
node data structure, it is safe to assume that an i82527 is actually physically present. System
BIOS does not create a device node if the device is physically absent. There is no system BIOS
Setup option to fully disable the entire device1. If no matching device node has been found,
software must quit operation immediately after notifying the user of the fact that no known
i82527 implementation has been found.
While the presence of the device node always means that the i82527 is present, an interrupt
request line may or may not have been assigned; please see below for details.
The resources assigned to the i82527 are represented in the device node data structure as follows:

Node ID *SBS0001 (0100534Ch)


Tag Type Contents
1 PORT Fixed I/O Port, base (base1), size 10h.
2 PORT Fixed I/O Port, base (base2), size F0h.
3 XIRQ Interrupt Request Line Bitmap

While the i82527 actually uses one single contiguous I/O port range 100h bytes in size, a
limitation in the Fixed I/O Port tag structure requires representing this one I/O port range in two
tags. Although in this representation, i82527 register index 00h..0Fh are contained in tag #1,
while registers 10h..FFh are in tag #2, software need not account for these two subranges
separately. It may be assumed that the two ranges are contiguous, i.e. (base2) always is
(base1)+10h, and all accesses may be performed using (base1) and offsets 00h..FFh.

On most boards the resources described by tags #1 and #2 hide behind the motherboard
Extended Register Set Lock/Unlock function. In order to gain access to this I/O port range,
software needs to operate the motherboard feature control register LOCKR. This implies that, in
order to use the *SBS000x device, software must also implement the handling of the feature
control register sets (MFCR) that are present on the motherboard types on which the software is
to be used. Currently, *SBS000x is implemented only on motherboards that have MFCR-set.
These MFCR sets currently are: *SBS1000 through *SBS1003, *SBS1030 (PC5 with AMI
BIOS) and *SBS1060 (PC7).
The contents of the XIRQ tag #3 are usually controlled through a system BIOS Setup item (see
Onboard CAN page 32). Depending on user selection and system-wide resource availability, the
tag might contain an empty bitmap (all zero) indicating that no IRQ line was assigned to the
i82527. The device can still be used under these conditions, but only in polled operation. If
software cannot use the device in polled mode, the user must be notified of the situation and
software operation then ceased, so that the user can reboot the system and enter BIOS Setup to

1
On PC7 it is possible to disable the complete ISA Bus leading to any ISA device being not accessible, this looks like the
device is actually not present.

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On Board Features

take whatever steps are necessary to assign an IRQ line to the i82527. Details on how to do this
can be found in the SBS Technologies AMIBIOS User’s Guide.
As the i82527 never uses more than one IRQ line, the tag normally contains one single bit set to
1 referencing a successfully assigned IRQ line.

3.5 SMBus devices


The PC7 and the CL7 using a I2C bus like 2-wire serial bus (SMBus) to communicate with
several onboard devices. The SMBus is a subset of I2C bus. To access the SMBus there is a
SMBus Controller within the chipset. See the intel ICH (I/O Controller Hub) manual on how to
program the SMBus controller. (Intel document 2906550x.pdf where x is the revision; 3 was
recent while writing this manual. see: http://developer.intel.com ).
On SMBus a read or write cycle is distinguished by the least significant bit (LSB) of the address.
To read a device set the LSB to one. For writing this bit is set 0. The table below shows the
device addresses used on PC7 and CL7. The ‘X’ is a placeholder for read/write bit.

SMbus Devices and their SMbus addresses.


Device SMB address (binary)
CLK Synthesizer * 0101111X
DIMM SPD EEPROM * 1010000X
Serial EEPROM (24C04) 1010100X
Temperature sensor (LM75) * 1 1001111X
Temperature sensor (MAX1617A) * 1 0011000X
*
: Access to devices marked by * is done by BIOS . It is strongly recommended not to write to these
devices by user software.
1
: LM75 is used on boards revision 0.x and 1.x. MAX1617A is used on boards revision 2.x and later.

3.5.1 Temperature Sensor


A National Semiconductors LM75 or a MAX1617A temperature sensor is implemented on the
PC7/CL7 board with its interface connected to the SMBus controller. The sensor is located
below the CPU and shows the air temperature between board and CPU. The sensor contains an
over-temperature output, which can be used to take actions like reducing the CPU speed.
For programming information please see the the manuals for the respective temperature sensor.
More information about LM75 can be found in the datasheet from National Semiconductors.
(see:http://www.national.com). More information on the MAX1617 can be obtained from the
datasheet from MAXIM. (see: http://www.maxim-ic.com).

3.5.2 Serial EEPROM


For storage of user data a serial EEPROM is implemented on the board. It is a standard 24C04
type EEPROM with 512 bytes. More information about writing and reading the contents can be
found in the datasheets from the manufacturer (e.g. Microchip Technology, SGS Thomson,
Atmel, Catalyst and many others). See http://www.st.com for instance.
If the DOS-SETUP3 user default option is used, the upper 128Bytes (beyond address 180h)
of this EEPROM are reserved.

3.5.3 DIMM SPD EEPROM


The SPD (serial presence detect) EEPROM resides on the DIMM and is a standard EEPROM
used for SPD data. Don’t change any data in this ROM!

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On Board Features

3.5.4 CLK Synthesizer


The Clock synthesizer is programmed by the BIOS. Don’ t change any values. Programming
improper values may even damage some board components.

3.6 *SBS0040 - Watchdog / TCO timer


The Intel 810 ICH (I/O Controller HUB) LPC interface device (D31:F0) contains a timer called
TCO timer, which has the functionality of a watchdog.
Please find the detailed description of the TCO timer in the Intel document 2906550x.pdf where
x is the revision; 3 was recent while writing this manual. see: http://developer.intel.com ).
The resources assigned to theTCO timer are represented in the device node data structure as
follows:

Node ID *SBS0040 (4000534Ch)


Tag Type Contents
1 PORT Fixed I/O Port, base, size 20h.

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Troubleshooting

4 Troubleshooting
Should an SBS Technologies mainboard fail to boot into the operating system, the troubleshooting
process is assisted by diagnostic data. This chapter describes how to obtain these codes and messages,
and explains the technical details behind them.

4.1 Checkpoint Codes


During the initial phase of power-up, there is no screen output available that would allow displaying
messages to the user. Instead, checkpoint codes are output to I/O port 80h/81h and LPT1 connector’s
data lines in binary form. A simple piece of hardware that displays the states of the eight LPT data lines
can be connected to this port to assist tracking potential problems or hardware failures.
The below tables describe the sequence of checkpoint codes, and the actions that are taken after each
particular checkpoint has been passed.

On a cold boot sequence (like when the system is first powered on), the following actions are performed
from BIOS ROM.

Checkpoint Description
Code
D0h The NMI is disabled. Power on delay is starting. Next, the initialization code
checksum will be verified.
D1h Initializing the DMA controller, performing the keyboard controller BAT test,
starting memory refresh, and entering 4 GB flat mode next.
D3h Starting memory sizing next.
D4h Returning to real mode. Executing any OEM patches and setting the stack next.
D5h Passing control to the uncompressed code in shadow RAM at E000:0000h.The
initialization code is copied to segment 0 and control will be transferred to
segment 0.
D6h Control is in segment 0. Next, checking if <Ctrl> <Home> was pressed and
verifying the system BIOS checksum.

If either <Ctrl> <Home> was pressed or the system BIOS checksum is bad,
next will go to checkpoint code E0h.

Otherwise, going to checkpoint code D7h.


D7h Passing control to the interface module next.
D8h The main system BIOS runtime code will be decompressed next.
D9h Passing control to the main system BIOS in shadow RAM next.

Should this initial sequence detect that the main BIOS is damaged (usually due to a previous FlashROM
update failure), a special recovery procedure is initiated. Users can recognize this situation as follows:
The floppy disk drive’s activity LED comes on, and the computer continuously tries to access the floppy
disk while beeping in a certain pattern. Please see the below table and the beep code description in Beep
Codes chapter 4.2 for details.

This procedure allows flashing an intact BIOS image into the FlashROM from an attached floppy disk
drive. Should this procedure activate, please ask SBS Technologies support for assistance. A failed
attempt in using this emergency procedure may require the mainboard to be sent in for physical
replacement of the FlashROM chip.

Checkpoint Description
Code
E0h The onboard floppy controller if available is initialized. Next, beginning the
base 512 KB memory test.
E1h Initializing the interrupt vector table next.
E2h Initializing the DMA and Interrupt controllers next.
E6h Enabling the floppy drive controller and Timer IRQs. Enabling internal cache
memory.
EDh Initializing the floppy drive.
EEh Looking for a floppy diskette in drive A:. Reading the first sector of the
diskette. (single beep on every retry)
EFh A read error occurred while reading the floppy drive in drive A:.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 45 of 55
Troubleshooting

Checkpoint Description
Code
F0h Next, searching for the BIOS image file in the root directory.
F1h The BIOS image file is not in the root directory. (two beeps)
F2h Next, reading and analyzing the floppy diskette FAT to find the clusters
occupied by the BIOS image file.
F3h Next, reading the BIOS image file, cluster by cluster.
F4h The BIOS image file is not the correct size.
F5h Next, disabling internal cache memory.
FBh Next, detecting the type of flash ROM.
FCh Next, erasing the flash ROM.
FDh Next, programming the flash ROM.
FFh Flash ROM programming was successful. Next, restarting the system BIOS.
(four beeps)

When the initial boot sequence has finished successfully, and the main system BIOS has been copied
from ROM to Shadow RAM, execution continues there. This is also the entry point for a system restart
after a software initiated reset. The sequence from this point onward is as follows:

Checkpoint Description
Code
03h The NMI is disabled. Next, checking for a soft reset or a power on condition.
05h The BIOS stack has been built. Next, disabling cache memory.
06h Uncompressing the POST code next.
07h Next, initializing the CPU and the CPU data area.
08h The CMOS checksum calculation is done next.
0Bh Next, performing any required initialization before the keyboard BAT command
is issued.
0Ch The keyboard controller input buffer is free. Next, issuing the BAT command to
the keyboard controller.
0Eh The keyboard controller BAT command result has been verified. Next,
performing any necessary initialization after the keyboard controller BAT
command test.
0Fh The initialization after the keyboard controller BAT command test is done. The
keyboard command byte is written next.
10h The keyboard controller command byte is written. Next, issuing the Pin 23 and
24 blocking and unblocking commands.
11h Next, checking if the <End or <Ins> keys were pressed during power on.
Initializing CMOS RAM if the Initialize CMOS RAM in every boot AMIBIOS
POST option was set in AMIBCP or the <End> key was pressed.
Subcode Port 81h: 01 check 32kHz clock running
Subcode Port 81h: 02 32kHz clock checked
12h Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2.
13h The video display has been disabled. Port B has been initialized. Next,
initializing the chipset.
14h The 8254 timer test will begin next.
19h The 8254 timer test is over. Starting the memory refresh test next.
1Ah The memory refresh line is toggling. Checking the 15 second on/off time next.
23h Reading the 8042 input port and disabling the MEGAKEY Green PC feature
next. Making the BIOS code segment writeable and performing any necessary
configuration before initializing the interrupt vectors.
24h The configuration required before interrupt vector initialization has completed.
Interrupt vector initialization is about to begin.
25h Interrupt vector initialization is done. Clearing the password if the POST DIAG
switch is on.
27h Any initialization before setting video mode will be done next.
28h Initialization before setting the video mode is complete. Configuring the
monochrome mode and color mode settings next.
2Ah Bus initialization system, static, output devices will be done next, if present.

After checkpoint 2Ah, the system’s I/O hardware has been fully initialized. This implies that the LPT1
port has now been set to its original purpose and will no longer show diagnostic information. However,
the system’s display controller has also been activated, allowing the user to observe the rest of the boot
process on the attached display unit.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 46 of 55
Troubleshooting

If an error occurs after the system display has been initialized, the error messages are displayed as
follows:
ERROR Message Line 1
ERROR Message Line 2
Press <F1> to continue
and the system halts. The system does not halt if Wait for <F1> If Any Error in Advanced Setup is
Disabled.
RUN SETUP UTILITY.
can also appear. Press <F1> to run AMIBIOS Setup if this message appears.

Error Message Explanation


8042 Gate-A20 Gate A20 on the keyboard controller (8042) is not working. Replace
Error the 8042.
Address Line Short! Error in the address decoding circuitry.
C: Drive Error No response from drive C:. Run the AMIDiag Hard Disk Utility.
Check the C: hard disk type in Standard Setup.
C: Drive Failure No response from hard disk drive C:. Replace the drive.
Cache Memory Bad, Cache memory is defective. Run AMIDiag.
Do Not Enable
Cache!
CH-2 Timer Error An AT system has two timers. There is an error in timer 2.
CMOS Battery State CMOS RAM is powered by a battery. The battery power is low.
Low Replace the battery.
CMOS Checksum CMOS RAM checksum is different than the previous value. Run
Failure AMIBIOS Setup.
CMOS System The values stored in CMOS RAM have been destroyed. Run
Options Not Set AMIBIOS Setup.
CMOS Display The video type in CMOS RAM does not match the type detected.
Type Mismatch Run AMIBIOS Setup.
CMOS Memory The amount of memory found by AMIBIOS is different than the
Size Mismatch amount in CMOS RAM. Run AMIBIOS Setup.
CMOS Time and Run Standard Setup to set the date and time.
Date Not Set
D: Drive Error No response from drive D:. Run diagnostic software. Check the hard
disk type in Standard Setup.
D: drive failure No response from hard disk drive D:. Replace the drive.
Diskette Boot The boot diskette in drive A: cannot be used to boot the system. Use
Failure another boot diskette and follow the screen instructions.
Display Switch Not Some systems require a video switch be set to either color or
Proper monochrome. Turn the system off, set the switch properly, then
power on.
DMA Error Error in the DMA controller.
DMA 1 Error Error in the first DMA channel.
DMA 2 Error Error in the second DMA channel.
FDD Controller AMIBIOS cannot communicate with the floppy disk drive controller.
Failure Check all appropriate connections after the system is powered down.
HDD Controller AMIBIOS cannot communicate with the hard disk drive controller.
Failure Check all appropriate connections after the system is powered down.
INTR1 Error Interrupt channel 1 failed POST.
INTR2 Error Interrupt channel 2 failed POST.
Invalid Boot AMIBIOS can read the diskette in floppy drive A:, but it cannot boot
Diskette the system with it. Use another boot diskette and follow the screen
instructions.
Keyboard Is The keyboard lock on the system is engaged. The system must be
Locked...Unlock It unlocked to continue to boot.
Keyboard Error The keyboard has a timing problem. Make sure a Keyboard
Controller AMIBIOS is installed. Set Keyboard in Advanced Setup
to Not Installed to skip the keyboard POST routines.
KB/Interface Error There is an error in the keyboard connector.
No ROM BASIC Cannot find a proper bootable sector on drive A:, C:, or CD-ROM
drive. AMIBIOS cannot find ROM Basic.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 47 of 55
Troubleshooting

Error Message Explanation


Off Board Parity Parity error in memory installed on an adapter card in an expansion
Error slot. The format is:
OFF BOARD PARITY ERROR ADDR = (XXXX)
XXXX is the hex address where the error occurred. Run diagnostic
software to find and correct memory problems.
On Board Parity Parity error in motherboard memory. The format is:
Error ON BOARD PARITY ERROR ADDR = (XXXX)
XXXX is the hex address where the error occurred. Run diagnostic
software to find and correct memory problems.
Parity Error ???? Parity error in system memory at an unknown address. Run
diagnostic software to find and correct memory problems.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 48 of 55
Troubleshooting

4.2 Beep Codes


Beep codes are used in situations when the checkpoint code on its own wouldn’t provide enough
information to track down the problem precisely, or to prompt the user for intervention.

There are three classes of beep codes. The first class of beep codes is generated by the memory detection
procedure. These consist of a number of short beeps followed by one single long beep, and always occur
during the memory initialization after checkpoint D3h. Such a beep sequence is repeated infinitely.

# of short Description
beeps
0 No memory in system.
1 Mixed memory types. In systems with DIMM sockets, both sockets must contain
SDRAM memory of matching type specifications. DIMMs of different sizes are
acceptable.
2, 3 or 4 100 MHz system with no SDRAM. EDO DIMMs are not accepted when the
DRAM bus is running at 100 MHz.
5 Invalid SPD data. In systems with DIMM sockets, the SDRAM DIMMs used
must follow the PC100 specification, meaning that the Serial Presence Detect
EEPROM on the DIMM must contain a PC100 specification compliant set of
configuration data.

The second class of beep codes is generated by the emergency BIOS flash procedure that gets invoked
whenever the BIOS image contained in the FlashROM chip appears to be damaged. These beep codes
occur immediately after powerup while the floppy disk drive activity light is on. They are meant to
guide the user through this emergency procedure (there is no display at that time).

# of short Description
beeps
1 Insert disk in drive A:
2 No suitable file on disk
4 Flash procedure successful – restarting system now
5 Read error on floppy disk
7 Incompatible flash hardware
8 Floppy disk controller error
10 Flash erase error
11 Flash program error
12 BIOS file is wrong size
13 BIOS file is not compatible

The last class of beep codes is for generic error situations. These may occur anytime during POST, and
consist of a number of short beeps that are not followed by any long beeps. Some of these beep codes
are fatal, and are also repeated infinitely. Others just alert the user, and allow the system to continue
normal operation after the situation has been resolved. In the latter case, the system should have been
able to initialize the display beforehand, and will display an error message.

Beeps Error message Description


Short (none) Normal condition at checkpoint D1:
Click System has been powered up and begins
boot sequence
Contin. (none) At checkpoint D1: Unable to initialize
short keyboard controller. Usually caused by a
Beeps shorted line in the Keyboard or Mouse
connection, or a blown keyboard power
supply fuse.
1 Refresh Failure The memory refresh circuitry is faulty.
2 Parity Error Parity error (or unrecoverable ECC error
in ECC systems) in the base memory (the
first 64 KB block) of memory.
3 Base 64 KB Memory Memory failure in first 64 KB.
Failure
4 Timer Not Operational A memory failure in the first 64 KB of
memory, or Timer 1 is not functioning.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 49 of 55
Troubleshooting

Beeps Error message Description


5 Processor Error The CPU generated an error.
6 8042 - Gate A20 Failure Cannot switch to protected mode.
7 Processor Exception The CPU generated an exception
Interrupt Error interrupt.
8 Display Memory The system video adapter is either
Read/Write Error missing or its memory is faulty. This is
not a fatal error.
9 ROM Checksum Error The ROM checksum value does not
match the value encoded in AMIBIOS.
10 CMOS Shutdown The shutdown register for CMOS RAM
Register Read/Write Error has failed.
11 Cache Memory Bad — The cache memory test failed. Cache
Do Not Enable Cache memory is disabled.

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 50 of 55
Troubleshooting

4.3 POST Memory Test


Normally, the only visible POST (Power On Self Test) routine is the memory test. The screen that
appears when the system is powered on is shown below.

AMIBIOS (C) 1995 American Megatrends Inc.


XXXXX KB OK

Hit <DEL> if you want to run SETUP

(C) American Megatrends Inc.


XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-ROMID-X

An AMIBIOS Identification string is displayed at the left bottom corner of the screen, below the
copyright message. Press <Ins> during system boot to display two additional AMIBIOS Identification
strings. Note that doing so will also erase CMOS storage, so that a CMOS checksum error will be
displayed.
AMIBIOS Identification Strings show the options installed in AMIBIOS. This information might be
needed on inquiries to SBS-or Industrial Computers Technical support.

4.3.1 Displaying Additional AMIBIOS ID Strings

In order to obtain the information from a system with a customized BIOS prepared for operation without
CMOS battery or other backup, the system must be brought to a forced error prompt by following the
steps below.

Step Action
1 If that setting is available, Enable Wait for <F1> If any Error in
Advanced Setup to Enabled before freezing the screen.
2 When a problem occurs, freeze the screen by powering on the system
and holding a key down on the keyboard to cause a Keyboard Error
message.
3 Copy the three lines and report this information to SBS Technologies.
Press <F1> to continue the boot process.

The following appears after POST completes:

Hit <DEL> if you want to run SETUP

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 51 of 55
BIOS User’s Manual Index

5 Index
DMA #2 Error ........................................................47
1
DMA Channel 0 .....................................................26
1st Boot Device ......................................................16 DMA Channel 1 .....................................................26
DMA Channel 3 .....................................................26
2 DMA Channel 5 .....................................................26
2nd Boot Device.....................................................16 DMA Channel 6 .....................................................26
DMA Channel 7 .....................................................26
3 DMA Error .............................................................47
3rd Boot Device .....................................................16 DMA-0 Type ..........................................................23
DMA-1 Type ..........................................................23
8 DMA-2 Type ..........................................................23
80 Pin Cable Detection Method .............................23 DMA-3 Type ..........................................................23
8042 - Gate A20 Failure.........................................50 DMA-5 Type ..........................................................23
8042 Gate-A20 Error..............................................47 DMA-6 Type ..........................................................23
DMA-7 Type ..........................................................23
A DRAM Page Closing Policy...................................19
AC97 Audio ...........................................................22 Drive and Port Interface .........................................28
AC97 Modem.........................................................22 D-Segment Hole .....................................................20
Ad Lib Range 388h - 38Bh ....................................22 E
Address Line Short! ...............................................47
Advanced Setup....................................................15 ENUM signal.........................................................40
AMIBIOS Identification string ..............................51 EPP Version .....................................................29, 31
B F
Base 64 KB Memory Failure .................................49 Fail-Safe BIOS Setup Settings ...............................35
BIOS Password Support.........................................34 FDD Controller Failure ..........................................47
Boot To OS/2 .........................................................17 Fixed Memory Hole ...............................................20
BootUp NumLock..................................................16 Floppy Access Control ...........................................16
C G
C: Drive Error ........................................................47 Game Port A...........................................................22
C: Drive Failure......................................................47 Game Port B ...........................................................22
Cache Memory Bad, Do Not Enable Cache!..........47 GP I/O....................................................................39
CAN controller .....................................................42 Graphics Mode Select ............................................20
CD-ROM drive Configuring ..................................12 H
CH-2 Timer Error...................................................47
Chipset Setup........................................................19 Hard Disk Access Control ......................................16
Clock Modulation...................................................24 Hard Disk Drive Capacity ......................................13
CMOS Battery State Low ......................................47 Hard Disk Drive Parameters...................................13
CMOS Checksum Failure ......................................47 Hard Disk Drive Type D: .......................................12
CMOS Display Type Mismatch .............................47 Hard Disk Drive Types...........................................14
CMOS Memory Size Mismatch .............................47 HDD Controller Failure..........................................47
CMOS Shutdown Register Read/Write Error ........50 Hit <DEL> if you want to run SETUP ...................51
CMOS System Options Not Set .............................47 I
CMOS Time & Date Not Set .................................47
CPU Freq Ratio ......................................................21 ICH DCB Enable....................................................23
CPU Freq Select.....................................................20 ICH Decode Select .................................................21
CPU Latency Timer ...............................................19 ICH Delayed Transaction .......................................23
ICH Dev31 Func5 Enable ......................................22
D ICH Dev31 Func6 Enable ......................................22
D: Drive Error ........................................................47 IDE drive Configuring............................................12
D: drive failure .......................................................47 IN1/IN2 ..................................................................32
Default....................................................................35 Internal Cache.........................................................18
Diskette Boot Failure .............................................47 INTR #1 Error ........................................................47
Display Cache Windows Size ................................20 INTR #2 Error ........................................................47
Display Memory Read/Write Error........................50 Invalid Boot Diskette..............................................47
Display Switch Not Proper.....................................47 IRQ10 .....................................................................26
DMA #1 Error ........................................................47 IRQ11 .....................................................................26
SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 52 of 55
BIOS User’s Manual Index

IRQ14.....................................................................26 PCI/PnP Setup ......................................................25


IRQ15.....................................................................26 Peripheral Setup ...................................................28
IRQ3.......................................................................26 Plug and Play Aware O/S .......................................25
IRQ4.......................................................................26 POST Memory Test................................................51
IRQ5.......................................................................26 Pri Master, Pri Slave, Sec Master, Sec Slave .........12
IRQ7.......................................................................26 Primary Display......................................................17
IRQ9.......................................................................26 Processor error........................................................50
Processor Exception Interrupt Error .......................50
K
PS/2 Mouse Support...............................................17
KB/Interface Error .................................................47
Q
Keyboard................................................................17
Keyboard Error ......................................................47 Quick Boot .............................................................15
Keyboard Is Locked...Unlock It .............................47
R
L
Refresh Failure .......................................................49
Landing Zone .........................................................13 Reserved Memory Address ....................................27
Reserved Memory Size...........................................27
M
ROM Checksum Error............................................50
Microsoft Sound Decode........................................21
S
MIDI Decode .........................................................22
Monitor...................................................................17 S.M.A.R.T. For Hard Disks....................................16
Moon ISA Device Enable ......................................21 SCSI drive Configuring..........................................12
Setup Types...........................................................10
N
SMBus ...................................................................43
No ROM BASIC ....................................................47 Sound Blaster Decode ............................................21
Number of Cylinders..............................................13 Spread Spectrum.....................................................24
Number of Heads ...................................................13 SRAM ....................................................................41
Number of Sectors..................................................13 Status LED ............................................................40
Swap Floppy Drives ...............................................28
O System BIOS Cacheable.........................................18
Off Board Parity Error ...........................................48 System Keyboard ...................................................17
On Board Parity Error ............................................48
T
Onboard CAN ........................................................32
Onboard FDC .........................................................28 TCO Timer / Watchdog..........................................33
Onboard Floppy Controller ....................................28 Timer Not Operational ...........................................49
Onboard IDE ..........................................................32 Try Other Boot Devices..........................................16
Onboard Parallel Port.......................................29, 31
U
Onboard Serial Port..........................................29, 30
Optimal default settings .........................................35 Un/Lock register ...................................................38
USB Function .........................................................19
P
USB Keyboard/Mouse Legacy Support .................19
Parallel Port Address........................................29, 31
V
Parallel Port ECP DMA Channel .....................30, 31
Parallel Port IRQ ..............................................30, 31 VMEbus Access Window Size...............................24
Parallel Port Mode ...........................................29, 31 VMEbus Fast DTACK# .........................................24
Parity Error.............................................................49 VMEbus System Controller State...........................24
Parity Error ????.....................................................48
W
Password Check .....................................................17
PCI ENUM.............................................................32 Wait for <F1> If any Error .....................................51
PCI IDE BusMaster................................................25 WINBIOS Setup .....................................................9
PCI Latency Timer (PCI Clocks) ...........................25 Write Precompensation ..........................................13
PCI Parity Check....................................................17
PCI VGA Palette Snoop.........................................25

SBS Technologies – PC7 / CL7 BIOS, Programmer’s and User’s Manual V 0.9 Page 53 of 55
Error Report

Error Report Form (Europe)

SBS Technologies GmbH & Co. KG Company Name

Memminger Str. 14 Department

86159 Augsburg Contact Person

Mailing Address

Phone Number:+49 821 5034-170 Phone Number

Fax Number +49 821 5034-119 Fax Number

Email Address

Part. N. __________ Revision: V _._ Date _ ___ Serial N. ________

Error Description:

Hardware Environment:

Operating System/Software:

Warranty repair:  YES  NO (Please see section ‘Warranty’)


Error Report

Error Report Form (US)

SBS Technologies, Inc. Company Name

6301 Chapel Hill Road Department

Raleigh, NC 27607-5115 Contact Person

Mailing Address

Phone Number: +1 919 851-1101 Phone Number

Fax Number +1 919 851-2844 Fax Number

Email Address

Part. N. __________ Revision: V _ . _ Date _ ___ Serial N. ________

Error Description:

Hardware Environment:

Operating System/Software:

Warranty repair:  YES  NO (Please see section ‘Warranty’)