EE115C - Tutorial 5 28/06/11 10:38 a.m.

EE115C: Digital Electronic Circuits Cadence Tutorials Electrical Engineering

Prof. Dejan Markovic #5: Hierarchical Design and Post-Layout Verification Winter
2007

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This tutorial will demonstrate hierarchical design of a simple chain of gates using simple layout instantiation and also layout of a ring
oscillator circuit using VXL. The process of post-layout extraction and simulation with wire RC model is demonstrated on the ring
oscillator example.

Bigger Designs and Hierarchy (Warm-up Example)

Now let's use our NAND gate and inverter cell to build something a little more complex.
In the Library Manager, create new cell named row.

You should now be editing layout view of row cell. Instantiate NAND four times and inverter once to form an array of cascaded cells.

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Your layout will look something like the figure above unless you selected to view all the internal layers.

Layout Editing: Show/Hide Internals (Review from Tutorial 3)

You may now want to see what's inside of the NAND2X1 cells and the inverter.
To do this, hit hotkey “e” and set Display Levels from 0 to 10, for example.

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This will show all the layers inside the cells as shown below. Alternatively, you can press Shift-f to display (Ctrl-f to hide) all
underlying layers – up to level 32 in this process.

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Layout Editing: Push, Pop, and Edit in Place

OK, now that we are here, let's say our boss comes over and says "sorry but you need to reduce the number of substrate/well
contacts". First, select the leftmost NAND2X1 cell and hit hotkey “x” (for Design > Hierarchy > Edit In Place).

After you hit “x”, notice that your edit cell is now NAND2X1 (check the top banner of the layout window which says:
Virtuoso® Layout Editing: ee115c NAND2X1 layout).

Select one of the substrate contacts for deletion as shown below.

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Notice that all four instances will be updated – this is expected since you modified NAND2X1 cell from your library. You can open your
NAND2X1 cell to check this out.

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Removing contacts seems like a bad idea in this case, so undo this exercise by using hotkey “u”. Save the cell and type “B” (capital!)
to get back up.

Now, just for grins, let's wire up two of the gates. Since we want to wire them up in row and NOT in NAND2X1 or INVX1, we must first
make sure row is our edit cell. Now that row is your edit cell, simply use wiring strategy you learned in Tutorials 3 and 4 to hook up a
couple of wires. Figure below shows a zoomed in view to show two gates wired up within row cell.

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Now when you zoom to fit and press Ctrl-f to hide the internal layers, you will see only the top level wire you just made.

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Save and close the layout.

Schematic-driven Layout Hierarchy: Ring Oscillator Example

Create layout view for cell Ring_OSC from Tutorial 2. From the Virtuoso Layout Editing window, invoke Tools > Layout
XL. In the VXL dialog window (review Tutorial 3 if needed), uncheck the option of creating I/O pins (because we still don’t know how
many VDD and GND pins we would need in the final design). Your initial cell placement should look like this:

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Click on the cells to see their connectivity in the schematics. Now, we are going to place the cells in row-like fashion similar to that in
the schematic. As you keep dragging the cells into the bounding box, you should observe flylines and objects in the schematic. Your
layout/schematic windows should look as follows as you are dragging the gates:
Layout, third gate is being moved corresponding cell in the schematic

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Continue with the second and third row (notice that the cells in the second row are flipped, just like they are in the schematic). When
you are done placing the rows, your layout should look similar to this:

Now, we are going to share VDD and GND rails. Make sure the cells are aligned and move the rows such that the prBoundaries meet.
Sharing of the GND rail for the first two rows should look like this:

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Notice that the substrate contacts have nicely overlapped (all that symmetry in cell design is finally paying off!). Overlap the VDD rails of
the second and third rows and re-size the top-level cell boundary. Your layout should now look like this:

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Wire up the internal signals inside the rows first. Notice that when you use Create Path and click on the source node (e.g. pin Z), the
destination node (e.g. pin A) gets highlighted to as a guide for wiring up the circuit (you can imagine that this gets quite useful for large
design which may not be as regular as the ring oscillator). Here’s the layout screen capture to illustrate the highlighting of the path
(both pins Z and A are highlighted in green):

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Wire up the output of the first row and the input of the second row etc. using Metal2 layer. The layout should look like this (notice
Metal2 wires in red):

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Design Verification: DRC check

Now is a good time to run intermediate DRC check. If you placed M2/M1 and M1/Poly close, then you might run into M1 spacing error
like the one illustrated below:

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You can cover both contacts with a Metal1 polygon to fix this error.

Layout Editing: Adding Power Rails and Labels

Now we are going to add power rails in Metal3 layer that span the entire height of the layout. We will use five vertical stripes, three for
VDD and two for GND, in alternating order.

You can hide all internal layers to see only your top-level routing:

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Create contact stack to connect GND signals. The stack should include:
- M2/M1 contact (power rails are wide, so put 2 contacts)
- M2 rectangle over the M1 GND rail and under M3
- M3/M2 contact (again, put 2 contacts)

This is top-level mapping of the ground signal (contact stack highlighted):

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Repeat this process for the VDD lines. Hint: once you create a contact stack, you can copy it as many times as needed or select
multiple copies as shown below:

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Once you are finished placing VDD contacts, they should be positioned as highlighted:

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Finally, add VDD and GND pins to the power rails. Create a shape pin (shortcut: Ctrl-p) in Metal3 layer.

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Specify VDD! as pin name.

Select Display Pin Name.

I/O type should be inputOutput.

Click Hide to create the pin.

Place the VDD! pin at the bottom of your layout and copy if over to other VDD lines (since M3 stripes are not connected, you have to put
pin on each as a way of logically connecting them). Note: for larger designs, all the power/gnd rails will be connected at the top level.

Your VDD! pins should be distributed as follows (check the bottom edge of the layout):

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Place GND! pins on top of the two gnd lines and your layout is finished. Your top-level routing and pin distribution should finally look like
this:

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Save your (hopefully final) layout!

Final Verification: DRC Check

Let’s run final DRC check to make sure our layout meets all the design rules. Start Assura > Run DRC…

Click Yes to see the final DRC report.

Error Layer Window pops up showing few DRC erros:

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This indicated Metal2 spacing problem. Click on arrows above to see the errors in layout. It looks like Metal2 wires are too close to
Metal2 from the contact stack as highlighted below:

For more details, in the Error Layer Window you can click View > Explain, and then click on the highlighted shape above.
Following window will appear:

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This is the marker text window that provides details about the DRC errors. You can also find this information in the manual (may
also review Tutorial 3):
/usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/docs/gpdk090_DRM.pdf

Since we want to fix only Metal2 spacing errors, we can select to display only this layer. Go over to the LSW window.

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Select Metal2 drw and click NV.

You will see that only Metal2 remains active.

Now, go to the layout editor and refresh the window using Window > Redraw (hotkey Ctrl-r). Only Metal2 will be visible in layout
as shown below:

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DRC violations are indicated with white lines (also circled for better emphasis). The easiest way to fix these errors is to shrink the
Metal2 area in the contact stack. Use ruler to measure 0.2µm away from the signal lines and shrink the Metal2 from the contact stack
accordingly. This process is illustrated below:

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Layout Editing: Stretch Command

You can resize the object by stretching (Edit > Stretch). After you enter stretch mode (hotkey: “s”), left-click and sweep over the
edge you would like to stretch, that edge will become highlighted, left-click to take the edge and stretch the object. The stretching is
illustrated below:

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Click the AV button in the LSW window and press Ctrl-r to refresh the layout. Now, let’s run DRC one more time (if you haven’t
closed previous run, first select Assura > Close Run).

Your design should be DRC clean!

Close the run: Assura > Close Run.

Final Verification: LVS Check

The next step in the verification process is LVS (review Tutorial 3 for LVS basics). Start the LVS run from the layout window by invoking
Assura > Run LVS…

Nice feature of VXL is that your layout is schematic-driven. In other words, you are doing LVS on the fly as you are constantly checking

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your schematic during the layout design. That extra effort pays off in the end: your designs typically end up being LVS correct (unless
you mix up some labels in the layout or introduce some bug of that nature). Upon completing the LVS run, following window appears:

Click No since no debugging is needed.

Final Verification: Extraction

We are now going to introduce another step in the verification chain: layout extraction and post layout simulation. Copy Assura
technology file to your cadence-labs directory:

> pwd
> /w/fac.01/ee/dejan/ee115c/cadence-labs
> cp /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/assura/assura_tech.lib .

Modify the assura_tech.lib file to read as follows:

DEFINE gpdk090 /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/assura

Set up Assura > Technology:

Click OK.

To start the extraction, go to Assura > Run RCX… (note: if you previously did Assura > Close Run, this menu won’t show up, so
you need to do Assura > Open Run…).

Following window will pop-up:

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In the Setup tab, choose Extracted View for Output. Make sure Setup Dir is the following:
/usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/assura/rcx

Click on the Extraction tab.

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Choose RC as the Extraction Mode (both resistance and capacitance) and Schematic Names as the Name Space (since we didn’t
label any nodes in the layout). Also type TP as the Ref Node.

Walk through other tabs just for exercise, but don’t change anything. Click OK.

When the Assura run is complete, the following window pops-up:

Click Close.

This will be part of the run report (sitting in your cadence-labs directory):
rcx.Ring_OSC.log

Summary for ee115c/Ring_OSC/av_extracted

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instance count totals:

lib cell view total

analogLib pcapacitor symbol 167
analogLib presistor symbol 322
gpdk090 nmos1v ivpcell 15
gpdk090 pmos1v ivpcell 15

extracted view creation completed

cpu: 0.27 elap: 2 pf: 57 in: 55 out: 88 virt: 55M phys: 0M

Finished /usr/apps/cadence/ASSURA315/tools/assura/bin/rcxToDfII

Run ended: Thu Dec 28 01:16:41 2006

***** Assura terminated normally *****

Now let’s go to the Library Manager window and open av_extracted cell view. Zoom in to the top left corner and you will see
layout annotated with transistor symbols indicating extracted components:

Similarly, you can zoom in to see parasitic resistances:

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Design Verification: Post Layout Simulation

In post layout extraction, we are verifying our design against conceptual schematic model. Now, we are going to compare delay
numbers obtained from the schematic (Tutotial 2) with the post layout simulation data. For reference, schematic: T = 400ps (oscillation
period).\

From the extracted view, start Analog Environment and set up simulation the same way you did in Tutorial 2, section Ring
Oscillator Delay Simulation.

In the Setup > Environment, add av_extracted to the switch view list.

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Your final setup should look as follows:

Net 5:net19 is the output of the last inverter in the first row (corresponds to TP from the schematic). Any other point can be chosen,
of course, because the objective is to simulate period of the ring oscillator. Save this state as state_Ring_OSC_ext.

If you get stuck at around 500mV, you can set initial condition on a node to help the simulation converge. To do so, choose
Simulation > Convergence Aids > Initial Condition and select the node you would like to initialize as shown below:

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After the simulation is complete, following graphs appears:

Now, we measure period from the first falling edge to the second falling edge:

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The delay is evaluated at: 495ps

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So, the post-layout delay is about 20% longer!!!

Layout effects could contribute to this. A slightly different layout achieves 509ps period:

Overall, 20% is a good rule of thumb for performance degradation. Message for your project: it is a good idea to over-design your
circuit in schematic by about 20%, so that the final post layout design meets the specs…

Hope you have fun with Cadence!

Last Modified on December 27, 2006 by Dejan Markovic

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