EEE5026; 943/U0280

Physical Design for Nanometer ICs

張耀文
Yao-Wen Chang
ywchang@ntu.edu.tw
http://cc.ee.ntu.edu.tw/~ywchang
Graduate Institute of Electronics Engineering
Department of Electrical Engineering
National Taiwan University
Spring 2018

Administrative Matters
․ Time/Location: Thursdays 2:20 pm--5:30 pm; BL-114
․ Instructor: Yao-Wen Chang
․ E-mail: ywchang@ntu.edu.tw
․ URL: http://cc.ee.ntu.edu.tw/~ywchang
․ Office: BL-428. (Tel) 3366-3556; (Fax) 2364-1972
․ Office Hours: Wednesdays 4-5pm; other times by appointment
․ Teaching Assistant: Yu-Sheng Lu (yslu@eda.ee.ntu.edu.tw); office
hours: 12:30-1:30pm, Wednesdays
․ Prerequisites: data structures, algorithms, and logic design
․ Required Text: Either of the following two books:
 Wang, Chang, and Cheng (Ed.), Electronic Design Automation:

Synthesis, Verification, and Test, Morgan Kaufmann, 2009

 Sait and Youssef, VLSI Physical Design Automation: Theory and

Practice, World Scientific Publishing Co., 1999

․ References: Selected reading materials from recent publications
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 Teaching Assistant
․Yu-Sheng Lu 呂祐昇
․Email: yslu@eda.ee.ntu.edu.tw
․Office: BL-406; Tel: 3366-3700 # 6406
․Office Hours: 12:30-1:30pm, Wednesdays.
․2nd-year Ph.D. student

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Course Objectives
․Study techniques/algorithms for physical design
(converting a circuit description into a geometric
description) and their comparisons
․Study nanometer process/electrical effects and their
impacts on the development of physical design tools
․Study problem-solving (-finding) techniques!!!

solution S1
S2
S3
S4
S5
P1 P2 P3 P4 P5 P6 problem
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 Course Contents
․ VLSI design flow/styles and technology roadmap
․ Physical design processes
 Partitioning
 Floorplanning
 Placement
 Routing (global, detailed, clock, and power/ground routing)
 Post-layout optimization
․ Timing: timing modeling, performance-driven design
․ Signal/power integrity: crosstalk, IR drop
․ Design for manufacturability
 Process variation, optical proximity correction (OPC), chemical
mechanical polishing (CMP), multiple pattering, e-beam, extreme
ultraviolet (EUV), directed self-assembly (DSA), nanowire, etc.
․ Design for reliability: antenna effect, redundant via,
electromigration, thermal, etc.
․ Machine learning based layout optimization
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Grading Policy
․Grading:
 Homework assignments + quizzes: 25%
 Programming assignments + lab: 25%
 One in-class open-book, open-note exam: 30% (June 28)
 Final project + presentation + demo: 20% (due June 21)
 A 1-page project proposal is due in-class on May 24

 Could be research work, implementation, and/or literature

survey
 Default project: Problem B, C, or E of the 2018 IC/CAD Contest at
http://iccad-contest.org/tw/ (E for domestic undergraduate students)
 Teamwork is permitted (1--3 persons; preferably 2 persons)

 Bonus for class participation

․Homework: 30% per day penalty for late submission
․WWW: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/pd.html
․Academic Honesty: Avoiding cheating at all cost
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 2018 CAD Contest @ ICCAD
․Default project: Problem B, C, or E of the 2018 IC/CAD
Contest at http://iccad-contest.org/tw/
․Teamwork is permitted (1--3 persons; preferably 2
persons)

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Unit 1: Introduction
․Course contents:
 Introduction to VLSI design flow/styles
 Introduction to physical design automation
 Semiconductor technology roadmap
․Readings
 W&C&C: Chapter 1
 S&Y: Chapter 1

physical
design fabrication

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 IC Design & Manufacturing Process

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IC Design & Manufacturing Process (cont’d)

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 From Wafer to Chip
2, 4, 6, 8-inch wafers

12-inch wafer
8-inch vs. 1-inch ignot

Apple A11 die (iPhone 8)

TSMC 10nm FinFET; Wafer dicing
4.3B transistors; 87.66 mm2 18-inch wafer

Wire
bonding

chips
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Die, Package, and Board

Apple A9 die for iPhone 6s
(1.85GHz; 5B+ transistors)

TSMC Samsung
16nm FinFET 14nm FinFET packages
104.5 mm2 96 mm2

packages boards
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 IC Design Considerations

․Several conflicting considerations:

 Complexity: large number of devices/transistors
 Power: low-power consumption
 Performance: high-speed requirements
 Cost: die area, packaging, testing, etc.
 Time-to-market: about a 15% gain for early birds
 Others: manufacturability, reliability, testability, etc.
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“Moore’s” Law: Driving Technology Advances

․Logic capacity doubles per IC at a regular interval (say, 18 months).
 G. Moore: Logic capacity doubles per IC every two years (1975).
 D. House: Computer performance doubles every 18 months (1975)

4Gb

Itanium 2

Intel uP

4004 8086 80386 PentiumPro Pentium 4 Itanium 2

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 Design Productivity Crisis
Logic transistors per chip

Productivity in transistors
10,000M 100,000K

1,000M 10,000K

per staff-month
58%/yr compound
100M Complexity 1,000K
complexity growth rate limiter
10M 100K

1M 10K
0.1M 21%/yr compound
1K
productivity growth rate
0.01M 0.1K

1980 1985 1990 1995 2000 2005 2010 2015

․Human factors may limit design more than technology.

․Keys to solve the productivity crisis: CAD (tool &
methodology), hierarchical design, abstraction, IP
reuse, platform-based design, etc.

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“Old” (1997) Technology Roadmap for Semiconductors

․ Source: International Technology Roadmap for Semiconductors (easier to

see the past & trend with the older version; for more recent update, see
http://www.itrs2.net/).
․ Deep submicron technology: node (feature size) < 0.25 m.
․ Nanometer Technology: node < 100 nm.
․ 14/16 nm technology was in production in 2015; 10 nm in 2016/2017
(5nm in 2020 by EUV?)

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 Nanometer Design Challenges
․Apple A11 (iPhone 8): technology node: 10 nm FinFET,
 P frequency  2.39 GHz, die size  87.66 mm2,
transistor count per chip  4.3B, wiring level  10+ layers,
supply voltage < 1.0 V, power consumption < 16 W (?)
 Feature size↓ : sub-wavelength lithography (impacts of
process variation)? reliability? noise? wire coupling?
 Frequency ↑, dimension ↑ : interconnect delay?
electromagnetic field effects? timing closure?
 Chip complexity ↑ : large-scale system design
methodology?
 Supply voltage ↓ : signal integrity (noise, IR drop, etc)?
 Wiring level ↑: manufacturability? yield? 3D layout?
 Power consumption/density ↑: power & thermal issues?

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Design Complexity Increases Dramatically!!

Mixed-size Placement

Routing & interconnect

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 High IC Complexity

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Power Is a Key Limiting Factor for IC Design!

․Power density increases exponentially!

1000
Power doubles every 4 years
5-year projection: 200W total, 125 W/cm2 ! Rocket
Nozzle
Nuclear Reactor
100 Pentium® 4
2
Watts/cm

Itanium 2
Pentium® III Itanium 2-DC
Hot plate
Pentium® II
10
Pentium® Pro Power & Performance
i386 Pentium® trade-off!!
i486
1
         

Fred Pollack, “New Microarchitecture Challenges in the Coming Generations of CMOS

Process Technologies,” 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel.
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 Interconnect Dominates Circuit Performance!!
70 Worst-case
interconnect
60
delay due
to crosstalk
50
Delay (ps)

40

30
Interconnect
20 delay

10
Gate delay
650 500 350 250 180 150 100 70 (nm)

Technology Node Source: Synopsys

In ≦ 0.18μm wire-to-wire
CS CW
capacitance dominates (CW>>CS)

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Manufacturing with Optical Lithography

․Patterns on a mask are transferred onto a wafer
Light source
Illumination
Lens

Mask

Projection Lens

Immersion Wafer
(water)
R = k1λ / NA 0.25 * 193 nm / 1.35 = 36 nm
R: resolution; k1: resolution constant (>= 0.25); λ: wavelength
NA: numerical aperture = f(lens, refractive index)
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 Sub-Wavelength Lithography Gap
․Sub-wavelength lithography: use light of larger
wavelength (193nm) to print features of smaller sizes

EUV
E-beam

[S. Borkar, MICRO’04]

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Technology Roadmap [Aitken, 2014]

EUV + DSA

eNVM NEMS CNT

EUV LELE Opto
Patterning VNW monolithic
SAQP TSV EUV + DWEB

Interconnect
Log (complexity)

MLG, CNT
LELELE
III-V EUV
Transistors SADP HNW
FinFET
LELE
HKMG We Are Here
Strain
Planar CMOS Strong RET
PMOS NMOS
LE, <
LE, ~
CU wires
AI wires
10nm 7nm 5nm 3nm

1975 1985 1995 2005 2015 2025

Source: R. Aitken @ ISPD’14 Keynote & S. Segars @ 2014 Kaufman Award dinner
(with revision by Y.-W. Chang)
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 Most Expected Patterning Technologies

Multiple patterning Extreme ultraviolet

lithography (MPL) lithography (EUVL)

Electron beam Directed Self-

lithography Assembly (DSA)
(EBL)
Each technology has different difficulties and
requires solutions for a breakthrough
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Litho-Etch-Litho-Etch (LELE) Double Patterning

․Pro: Simpler layout decomposition into masks
․Con: Overlay error with misalignment between masks
40nm 20nm 80nm
80nm
20nm 20nm

= +
mask 1 mask 2
1st exposure-etching process
mask 1
photoresist
mask
Target film
substrate

2nd exposure-etching process

mask 2

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 Extreme Ultraviolet Lithography (EUVL)
․EUVL is the most invested next-generation lithography
technology
 Its wavelength is only 13.5 nm
 Reflective optical components and masks are used

Reflective
mask
Reflective illuminator
optics (mirrors)

EUV source Reflective projection

optics (mirrors)

Wafer

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Electron Beam Lithography (EBL)

․EBL is a maskless next-generation lithography technology
 Maskless: no more diffraction limitation of light
 Can define very fine patterns

Mapper Lithography

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 Directed Self-Assembly (DSA)
․Block copolymer DSA for contact/via patterning
 Groups of contacts/vias are patterned by guiding templates
with traditional 193i lithography

Self-assembly Topographical and

block copolymer chemical patterns

Mask Template Contacts

Smaller and denser patterns Contact patterning with DSA

Contact patterns formed by various DSA templates

[Xiao, et al., ASP-DAC’15]
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Cut/Via Pattering with DSA

․A large template can be used to pattern multiple close
contacts even for sub-7nm nodes

Layout Vias
close vias

Templates
22nm
7nm

[Xiao, et al., DAC’14]

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 Reliability Becomes a 1st-Order Effect!!
․Reliability with 10-layer metal?
m5
+
++
m4

m3
m2 + +++
m1

sgd sgd
Si substrate

[Courtesy: Dr. Patrick Groeneveld]

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“3D” Integration Adds Complexity!

3D IC device heat sink

thermal TSV
signal TSV tier3
TSV
inter-layer dielectric
tier2
metal layer
device layer tier1
substrate TSV-IO
substrate
dielectric routing region

2.5D interposer
(Xilinx Virtex-7
FPGA)

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 臺大演講網
3D Transistor: FinFET 胡正明院士
․Lower leakage power
․Performance gain at
lower voltage
․Higher drive current

3 fins

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Traditional VLSI Design Cycles

1. System specification
2. Functional design
3. Logic synthesis
4. Circuit design
5. Physical design
6. Fabrication
7. Packaging
․ Other tasks involved: verification, simulation, testing, etc.
․ Design metrics: area, speed, power dissipation,
manufacturability, reliability, testability, design time, etc.
․ Design revolution: interconnect (not gate) delay dominates
circuit performance in deep submicron era.
 Interconnects are determined in physical design.
 Shall consider interconnections in early design stages.
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 Traditional VLSI Design Cycle

& verification

& verification

& simulation

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Traditional VLSI Design Flow (Cont'd)

design

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 Physical Design (PD)

physical
design fabrication

․ PD converts a circuit description into a geometric description.

․ The description is used to manufacture a chip.
․ Physical design cycle:
1. Partitioning
2. Floorplanning
3. Placement
4. Routing (clock, power/ground, signal nets)
5. Post-layout optimization (buffering, sizing, etc.)
• Others: circuit extraction, timing verification and design rule
checking
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Physical Design Flow

B*-tree based floorplanning system

Routing system
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 Floorplan Examples

Apple A5 Intel
with dual
ARM cores Pentium 4

A floorplan
with
interconnections

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VLSI Placement
․Place objects into a die s.t. no objects overlap with each
other & some cost metric (e.g., wirelength) is optimized

chip

ISPD98 ibm01

842K cells 12,752 cells

247 macros
646 macros
Amax/Amin = 8416
868K nets

wirings among cells/macros are not shown here!!

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 Routing Example
• 0.18um technology, two layers, pitch = 1 um, 8109 nets.

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Modern EDA & Circuit Design Challenges

Scalability Multi-dimension

Heterogeneity Technology

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 Example: Modern Placement
․High complexity 2.5M
 Millions of objects placeable
objects
Scalability mixed-size
․Placement constraints design
 Blockage, routability,
density, timing, region, etc. Macros have
revolutionized
Multi-dimension SoC design
․Mixed-size placement
 Thousands of big macros
with millions of small cells
device
Heterogeneity TSV TSV
․ More: 3D IC, datapath, FPGA,
etc. dielectric
routing region
Technology substrate
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Design Styles

Power Others

Structure ASIC FPGA SPLD

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 SSI/SPLD Design Style

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Full-Custom Design Style

• Designers can control the shape of all mask patterns.
• Designers can specify the design up to the level of individual
transistors.

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 Terminology
․Cell: a logic block used to build larger circuits.
․Pin: a wire (metal or polysilicon) to which another
external wire can be connected.
․Nets: a collection of pins which must be electrically
connected.
․Netlist: a list of all nets in a circuit.
nets

pin cells

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Standard-Cell Design Style

• Selects pre-designed
cells (typically, of the same
height) to implement logic

• Over-the-cell routing is
pervasive in modern
designs

• Modern designs often

contain cells of different
row heights (esp. with
FinFET transistors)

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 Standard Cell Example

• Over-the-cell routing is pervasive in modern designs

Courtesy of Newton/Pister, UC-Berkeley

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Gate Array Design Style

• Prefabricates a transistor array
• Needs wiring customization to implement logic

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 FPGA Design Style

․Logic and
interconnects are
both prefabricated.

․Illustrated by a
symmetric array-
based field-
programmable
gate array (FPGA)

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FPGA/CPLD Examples
Xilinx XC4413 FPGA (0.35 um)

Altera Stratix IV FPGA

(40 nm)

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 FPGA Design Process
․Illustrated by a symmetric array-based FPGA
․No fabrication is needed

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Comparisons of Design Styles

Full Standard Gate FPGA
custom Cell array
Cell size variable fixed height fixed fixed
Cell type variable variable fixed programmable
Cell placement variable in row fixed fixed
Interconnection variable variable variable programmable

Full Standard Gate FPGA

custom Cell array
Fabrication time --- -- + +++
Packing density +++ ++ + ---
Unit cost (large quantity) +++ ++ + ---
Unit cost (small quantity) --- -- - +++
Easy design & simulation --- -- - ++
Easy design change --- -- - +++
Timing simulation accuracy -- - - ++
Chip speed +++ ++ + ---
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 Design Style Trade-offs
4
10 full
custom

3
10 semi-
Turnaround custom
Time
(Days) 2
10

FPGA
SPLD CPLD
10

SSI optimal
solution
1
2 3 4 5 6 7 8
1 10 10 10 10 10 10 10 10
Logic capacity (Gates)

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Appendix:

Structured ASIC

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 Structured ASIC
․ A structured ASIC consists of predefined metal and via layers, as
well as a few of them for customization.
․ The predefined layers support power distribution and local
communications among the building blocks of the device.
․ Advantages: fewer masks (lower cost); easier physical extraction
and analysis.
․ Popular for engineering change orders (ECO’s)

A structured ASIC Faraday’s 3MPCA structured ASIC

(M5 & M6 can be customized) (M4--M6 can be customized)
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Comparisons of Design Styles

Full Standard Gate Structure FPGA
custom Cell array ASIC
Cell size variable fixed height fixed fixed fixed
Cell type variable variable fixed fixed programmable
Cell placement variable in row fixed fixed fixed
Interconnection variable variable variable variable/fixed programmable

Full Standard Gate Structure FPGA

custom Cell array ASIC
Fabrication time --- -- + ++ +++
Packing density +++ ++ + - ---
Unit cost (large quantity) +++ ++ + - ---
Unit cost (small quantity) --- -- - + +++
Easy design & simulation --- -- - + ++
Easy design change --- -- - + +++
Timing simulation accuracy -- - - + ++
Chip speed +++ ++ + - ---
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