FPGA BASIC STRUCTURE AND

CONCEPT OF SYNTHESIS
1 Ehsan Yazdian
CONCEPT OF SYNTHESIS
 FPGA has Large Number of Logic Block ‘Islands’ in a ‘Sea’ of Interconnects
 Example: Designing a Full Adder

Full Adder

 We can implement this design in FPGA using FPGA

programming softwares.
 We can put these blocks together to design multi-bit adders.
Real projects are much more complex
than this simple adder. 2
HARDWARE DESIGN LANGUAGES
 Behavioural codes instead of gate level design.
 Verilog, VHDL, ....
 Example of verilog code for adder:
module fulladder (
input a,
input b,
input c_in,
output out,
output c_out
);
assign {c_out,out}=a+b+c_in;
Endmodule

 Synthesis tools convert behavioural codes to

gates which can be implemented on FPGA.
3
POPULARITY OF VERILOG HDL
 Verilog HDL
 General-purpose
 Easy to learn, easy to use
 Similar in syntax to C
 Allows different levels of abstraction and mixing them
 Supported by logic synthesis tools and simulators.
 Not all constructs are synthesizable
 Example of non synthesizable Command
module useless;
initial
$display(“Hello World!”);
endmodule
4
Compare to printf() in C
…. BACK TO FPGA STRUCTURE
 Look-Up Tables
 FPGA uses SRAM memory instead of
A
Combinatorial logic. B Z
 Capacity is limited by the number of inputs, not C LUT
by the complexity D

 Benefit: Delay through the LUT is

constant and is simpler to design. A B C D Z
0 0 0 0 0
0 0 0 1 0
Combinatorial Logic 0 0 1 0 0
0 0 1 1 1
A
0 1 0 0 1
B
Z 0 1 0 1 1

C . . .

D 1 1 0 0 0
1 1 0 1 0
5
1 1 1 0 0
1 1 1 1 1
BASIC COMPONENTS OF FPGA
 Simplified Slice Structure
Slice 0
PR
LUT Carry DE Q
CE
CLR

 Flip-Flops are used to LUT Carry D PR

CEE Q

implement sequential CLR

logics.

6
 CONNECTING LOOK-UP TABLES

 FPGA has Large Number

of CLBs (Configurable Logic
block) and
Interconnections.

A typical CLB

COUT COUT
 Local routing provides
feedback between slices in Slice S3
the same CLB, and it
provides routing to Slice S2
neighboring CLBs Switch
Matrix
SHIFT

Slice S1

7
Slice S0

Local Routing
CIN CIN
CLB INTECONNECTIONS
 A switch matrix provides access to general routing resources
 The mapping of logical connections to these physical routing
resources is entirely managed by the router software.

8
FPGA STRUCTURE
 Basic components
 Configurable Logic (CLBs)
 Contain combinatorial logic and register
resources

 Programmable Interconnection

 Programmable Input/Output circuit

 Interface between the FPGA and the outside
world

 Each I/O supports 40+ voltage and protocol

standards, including
 LVCMOS, LVDS, LVPECL, SSTL, HSTL, …

 Each pin can be input, output and 3-state.

 Each pin can be individually configured.

9
FPGA STRUCTURE
 Programmable Clock Generator
 Global clock buffers
 Macro components
 Multiplier ( large combinational logic)
 Random Access Memory (Large Density)
 Read Only memory (Large Density)
 CPU
 Rocket IO
 DSP blocks

10
FPGA STRUCTURE (COMMON BLOCKS)

Block SelectRAM™ I/O Blocks (IOBs)

resource

Programmable
interconnect
Dedicated
multipliers
Configurable
Logic Blocks
(CLBs)

11
Clock Management
 SOME NEW FEATURES
RocketIO™
Multi-Gigabit Smart RAM
New block RAM/FIFO
Transceivers
622 Mbps–10.3 Gbps

Xesium Clocking
Advanced CLBs Technology
200K Logic Cells 500 MHz

Tri-Mode
Ethernet MAC
XtremeDSP™ 10/100/1000 Mbps
Technology Slices
256 18x18 GMACs
1 Gbps SelectIO™
PowerPC™ 405 ChipSync™ Source synch,
with APU Interface XCITE Active Termination
450 MHz, 680 DMIPS 12
EXAMPLE OF RESOURCES ON VIRTEX-7

Each 7 series FPGA slice contains four LUTs and eight flip-flops;

Number of slices corresponding to the number of LUTs and flip-flops supported in the
device. 13