MODFIED GLITCH-FREE AND CASCADABLE

ADIABATIC LOGIC CIRCUITS

Thesis submitted in partial fulfillment

of the requirements for the degree of

Master of Science (by Research)

in
VLSI

by
Prashanth Paramahans M.
200742003
manik@research.iiit.ac.in

International Institute of Information Technology

Hyderabad,India
June -2010
 INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY
Hyderabad, India

CERTIFICATE

It is certified that the work contained in this thesis titled “Modified Glitch-Free and
Cascadable Adiabatic Logic Circuits” by Prashanth Paramahans , has been carried out under
my supervision and has not been submitted elsewhere for a degree

____________ _______________________________
Date Advisor: Professor Satyam Mandavilli
 Acknowledgement

I would like to thank my advisor , Prof. M Satyam for his support,

guidance , motivation, and immense knowledge which played a great
role during the development of ideas in the thesis.I could not have
imagined having a better advisor and mentor for my Master’s study.I
thank my fellow labmates in CVEST for the stimulating discussions we
had,and for all the fun we have had in the last few years.
Last but not the least, I would like to thank my family for their
continued support through out my study.
 Abstract

Conventional CMOS logic circuit design approaches rely on charging

the output capacitive nodes to the power supply Vdd or discharging
it to ground.This design approach has been widely used.For Low
power applications, although there are many techniques both at cir-
cuit level and system level, a very fundamental source of energy
dissipation is the discharge of the capacitor to ground.Every time
a capacitor is discharged to ground, an amount of energy = 12 CV 2
stored in the capacitor is lost.This loss of energy can be prevented
if instead of discharging the capacitor to ground,the charge or en-
ergy stored can be recycled. Another way of reducing the power
consumption is to design the circuit in such a way that the charg-
ing of the capacitive node takes place very slowly.It has been ob-
served that slowly charging the capacitor requires lesser energy than
abrupt charging.Adiabatic circuits use the above two methods viz.
slow charging and discharging, and charge recycling to minimize
the power consumed.Several Adiabatic designs have been proposed
in literature.Most of them achieve significant power savings in com-
parision to conventional circuits.Drawbacks of these circuits include
complex circuit design for achieving simple operations,requirement
of multiple clocks and/or requirement of complimentary input sig-
nals for controlling the charging/discharging process.The Current
work is based on an existing adiabatic logic style known as GF-
CAL (Glitch Free and Cascadable Adiabatic Logic )which is simple
and doesnt require complimentary signals or complex clocking.The
GFCAL has a drawback that it uses junction diodes for controlling
the charging and discharging of output nodal capacitance.Junction
diodes are difficult to fabricate in a CMOS process and they are re-
sponsible for power dissipation due to the cut-in voltage drop across
them.
This work improves the circuit by replacing the diodes with tran-
sistors that control the charging and discharging process.The effi-
ciency has gone up from 50% for GFCAL to about 60% for the mod-
ified circuit in comparison to conventional CMOS logic circuits.The
modified design is found to work satisfactorily, is cascadable and
simple block level implementations like adders have been demon-
strated and verified to work with lower power consumption than
conventional CMOS circuits.
Contents

Chapter 1. Basics of Low Power Design . . . . . . . . . . . . . . . . . 3

Need for Low-Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1. Sources of Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 4
1.2. Low Power Design techniques . . . . . . . . . . . . . . . . . . . . . 4
1.2.1. Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2. Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . 6
1.3. Active power Reduction . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1. Activity Reduction . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2. Supply voltage reduction . . . . . . . . . . . . . . . . . . . . 7
1.4. Leakage reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.1. Leakage reduction using dual Vt technology . . . . . . . . . 8
1.4.2. Stacking technique . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.3. Supply gating . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.4. System and architecture level power reduction . . . . . . . 9
1.5. Adiabatic or charge recovery based circuit design . . . . . . . . . . 10

Chapter 2. Adiabatic Architectures . . . . . . . . . . . . . . . . . . . . 11

2.1. RC circuits and related Energetics . . . . . . . . . . . . . . . . . . . 11
2.2. Previous Adiabatic Circuit techniques . . . . . . . . . . . . . . . . . 13
2.2.1. Adiabatic Dynamic Logic (ADL) . . . . . . . . . . . . . . . 14
2.2.2. Split Level Charge Recovery Logic (SCRL) . . . . . . . . . 14
2.2.3. 2N-2P logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.4. 2N2N-2D logic . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.5. Quasi Static Energy Recovery Logic (QSERL) . . . . . . . 17
2.2.6. Efficient Charge Recovery Logic (ECRL) . . . . . . . . . . . 18
2.2.7. Glitch-Free and Cascadable Adiabatic Logic (GFCAL) . . . 19
2.2.8. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 3. Modified GFCAL Logic . . . . . . . . . . . . . . . . . . . . 21

3.1. Operation of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2. Simulation of the basic transistor based adiabatic inverter . . . . . 23
3.3. Qualitative discussion on the output waveforms . . . . . . . . . . . 25

1
 3.4. Effect of variation of Device parameters . . . . . . . . . . . . . . . . 25
3.4.1. Effect of Variation of transistor widths . . . . . . . . . . . . 25
3.4.2. Variation with Load capacitance . . . . . . . . . . . . . . . 27
3.4.3. Varying the clock power Frequency . . . . . . . . . . . . . . 29
3.4.4. Varying the input data frequency . . . . . . . . . . . . . . . 30
3.4.5. Delay characteristics and input output relations . . . . . . . 31
3.5. Cascadability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 4. Mathematical model of the adiabatic inverter circuit . 34

4.1. Charging process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.1. Energy during charging . . . . . . . . . . . . . . . . . . . . 35
4.2. Discharge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.1. Energy consumed during the discharge cycle . . . . . . . . . 37
4.3. Performance Variation with Circuit Parameters . . . . . . . . . . . 39
4.4. Efficiency estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 5. Logic design based on MGFCAL . . . . . . . . . . . . . . 43

5.1. NAND function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2. NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3. Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1. Estimating the power consumption by simulation . . . . . . 46
5.4. Further application-an 8-bit adder circuit. . . . . . . . . . . . . . . 48
5.5. Implementation of sequential blocks using Modified GFCAL gates . 50
5.5.1. A JK Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Appendix A. The MOS transistor and CMOS based circuits . . . 55

Appendix B. Linear Feedback Shift register . . . . . . . . . . . . . . 59

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 1

Basics of Low Power Design

Need for Low-Power Design

With increased scaling in CMOS technology, todays designs are capable

of performing very high speed computations as the complexity and number
of devices on a given IC is no longer an issue. Much of the research efforts
in the recent decades have been dedicated to improving the speed of digital
systems.Thus, high speed computation has become an expected norm for
average users.Along with this, there is a growing desire to have access to
computation at any location without being limited to a given space with a
wired network.This requirement for portability of the computational device
places restrictions on the size, weight and power.Most of the times, it is
observed that the heaviest component in any such portable system is the
battery.A typical Ni-Cd battery provides only 20 Watt-hours of energy per
pound of weight.Battery efficiency has not improved at the same pace as the
complexity and power requirement of the recently developed designs.
Previously, portability was mostly associated with low throughput devices
like calculators and wrist-watches.But with the growing use of portable de-
vices capable of performing computations comparable to desktop computers,
it has become necessary to adopt design methodologies that would work with
low-power and give high throughput.This issue of low power is becoming more
important even in non-portable applications where power is available.Until
recently, these non-portable systems did not have any concern for low power
due to availability of cooling systems like heat sinks and fans.But with in-
creasing device densities, the amount of heat radiated by such systems is
increasing and there is a need to adopt low power design approaches in such
applications to minimize the amount of heat radiated and to keep the cost
of cooling systems to a minimum.

3
 Thus it is evident that methodologies for design of low power systems are
needed.We will examine the sources of power dissipation in digital circuits
and later discuss briefly the existing techniques that are used to achieve low
power designs.

1.1. Sources of Power Dissipation

The three major sources of power dissipation in CMOS circuits can be

expressed using the equation given below

Ptotal = Pswitching + Pshort−circuit + Pleakage (1.1)

Ptotal = α.V.Vdd .fclk .Cload + Isc .Vdd + Ileakage .Vdd (1.2)

In equation (1.2), the first term represents power dissipation due to switch-
ing. V is the voltage swing, Cload is the load capacitance and fclk is the
switching frequency. The factor α is the activity factor which represents the
fraction of the circuit that is switching. In most cases the voltage swing for
V is same as the supply voltage Vdd in such cases the term V becomes Vdd .
The second term in the equation represents short-circuit power dissipation
which occurs when both the pull-up and pull-down paths in a CMOS circuit
are momentarily ON. In such a condition, a short-circuit current Isc flows
from Vdd to the ground and causes power dissipation . Apart from these
two terms viz. the switching power and short-circuit power, there is always
present the component due to leakage currents. Leakage currents depend
upon various fabrication technology related factors like threshold voltage Vth
, device dimensions, substrate-injection etc. Previously, a dominant portion
of the power dissipated in a CMOS circuit was due to switching and as such
many techniques for low power design tried to minimize switching, but with
advanced technology nodes,leakage power is becoming a concern in modern
IC designs and as such techniques for minimizing the leakage power have
been developed.

1.2. Low Power Design techniques

Low power design can be attained by either following a circuit based

approach or an architectural approach or at a higher level where the pro-
gramming is optimized.In most cases a combination of one or more of theses

4
 Figure 1.1. Energy,delay Vs. Voltage

methods is used to optimize the power consumption of a design. At circuit

level, the main task is to minimize any one of the components of equation
1.2.In the following sections a brief discussion on different methods used to
obtain low power design are given
For a given technology , the energy per operation can be reduced by
lowering the supply voltage.Since capacitance and threshold voltage are still
constant, the speed of the circuit will be slower.It has been shown in [25]that
delay is related to the threshold voltage and output capacitance as

CV
td = k (1.3)
(V − Vth )2
Figure 1.1 shows a plot of energy-per-operation, delay and energy-delay
as the supply voltage is scaled.At large voltages, reducing the supply voltage
reduces the energy with very small change in delay.But at voltages near the
threshold voltage of the device , even a small change in supply causes a large
change in delay with modest change in energy. At Vdd = 3Vth a minima is
observed and as such at this point , changing the supply voltage does not
affect the energy-delay product strongly and thus allows for trading delay
for energy.From the point Vdd = 1.5Vth to Vdd = 6Vth there is a factor of 8
variation of energy that can be traded for delay without much change in the
energy-delay product.

1.2.1. Transistor Sizing

Power consumption can also be reduced by scaling down the devices in a

circuit. Since the capacitance due to gates of the transistors get reduced with
reduced dimensions, the power consumed decreases.But the sizing reduces the
current drive of the logic gates and thus reduces the speed of operation.This
can be understood by taking the example of a chain of inverters. Figure

5
 Figure 1.2. Energy,Delay Vs. Transistor Width

1.2 shows the delay, energy,Energy-delay of a single stage in the inverter

chain as a function of the transistor’s capacitance contribution to the total
load. In case of smaller transistors, the load will be due to load capacitance
of next stage and for larger transistors, the gate capacitance will also be
present and comprises a major portion of the load capacitance. For smaller
devices, energy is dominated by switching of the load capacitance and delay
is inversely related to the device width and as such increasing the transistor
width improves the energy-delay product.For large devices the self loading
due to gate terminal comes into picture and it is observed that decreasing
the transistor size improves energy-delay product.The optimum operating
point is when the transistor self loading is same as the loading due to next
stage.In complex circuits this same method of optimizing will hold good.
The transistors in the critical path should be sized accordingly.But as in
[25], using minimum-sized devices can lead to low power design but it does
not lead to an energy efficient design.

1.2.2. Technology Scaling

Another way to improve the energy-delay product is to improve the tech-

nology.A mentioned in [21] & [26]in ideal scaling, all voltages and linear
dimensions are reduced by a scaling factor of γ(<1). As the electric field
in the devices and wires remains the same, the device current and wire ca-
pacitances also scale as γ.Since the voltages also scale by γ,the switching
energy per transition (CV 2 )term scales as γ 3 . The delay of each logic gate
improves by gamma (td ≈ CV i
) . The energy-delay product decreases by γ 4 .
This means that if a scaling of 0.7 is introduced, then a chip can give the
same performance at (0.7)4 ≈ 0.25 of the previous power consumption. But

6
in ideal scaling , the threshold voltage Vth does not scale in tune with the
supply voltage.Static power dissipation caused by leakage current through
the OFF transistors will limit how low the threshold voltage can be scaled.
Even with constant voltage scaling, the reduced capacitance improves both
the energy and delay, so their product scales as γ 2 .

1.3. Active power Reduction

There are two methods of reducing active power or dynamic power. They
are

1.3.1. Activity Reduction

Energy consumption is proportional to the frequency at which signals

change state from 0 to 1 or vice-versa and to the capacitance on the signal
line. This is true for every signal path in a system, whether it is a clock
signal, a data pin, or an address line. This implies that power consumption
can be reduced by carefully minimizing the number of transitions. So a
correct choice of the number representation can have a significant impact on
the switching activity. For example, program counters in processors generally
use a binary code. On average, two bits are changed for each state transition.
Using a Gray code in which only single bit changes occur from one count to
another, can give significant energy savings.Many such coding techniques
have been reported in literature that yield different power savings.[4, 25]
To reduce activity in synchronous logic, clock gating[28] is employed.
Clock signal to a logic block is gated by a control signal, disabling clock
when the particular logic block is not in use, thereby reducing the clock
signal activity and thus the overall active power consumption. Since clock
accounts for substantial activity in the logic, it results in considerable power
savings.This technique can be applied to signal other than clock that have
large effect on the active power.

1.3.2. Supply voltage reduction

Since power consumption reduces quadratically with supply voltage, sup-

ply voltage reduction can result in substantial power savings. There are
two ways to employ supply voltage reduction without compromising perfor-
mance—static and dynamic.
In dynamic supply voltage scaling[3], the chip is designed to deliver max-
imum performance at highest supply voltage.When the performance demand

7
is low, the chip is operated at lower voltage, delivering lower performance but
with substantial (quadratic) power reduction.The logic chip may also detect
the performance demand and adjust frequency and supply voltage accord-
ingly [6]. A mobile microprocessor for example may detect peaks in perfor-
mance requirement and accordingly adjust supply voltage and frequency to
deliver the necessary throughput, thereby saving power and energy.
In static supply voltage reduction, multiple supply voltages are used.
Figure 1.3 shows such a scheme using two supply voltages. Higher supply
voltage is used for performance critical blocks which run at higher speed and
consume higher power and lower supply voltages are used for blocks that
have less performance demand.There are several issues with multiple supply
voltages that need careful evaluation. When a logic signal that emerges from
a slow block is connected to the fast block, the signal levels are closer to the
threshold voltages of the transistors, and could consume excessive leakage
power and reduce noise margin. This scheme also requires additional power
supply grid, and associated support such as decoupling capacitors, to ensure
error free operation.

1.4. Leakage reduction

Even when a CMOS circuit is idle there will be a leakage component

of current that will always be present.This contributes significantly to the
power dissipation of the circuit.Leakage power is becoming a major part of
the total power dissipation with newer technologies.Some of the methods of
reducing leakage power are discussed here.

1.4.1. Leakage reduction using dual Vt technology

Dual Vt design technique[2] can be used to reduce the subthreshold leakage

power.In this , the process technology provides two types of transistors viz.

high supply voltage

low supply voltage

slow fast slow

low supply voltage

high supply voltage

Figure 1.3. static voltage scaling using multiple supplies

8
High threshold voltage (High Vt ) and low threshold voltage ( Low Vt ). The
high Vt transistors give slower logic with lower leakage whereas the Low
Vt transistors yield faster logic, but higher ( about 10 times the slower ones )
leakage.Thus a selective usage of low and high Vt transistors will yield higher
performance with lower leakage.

1.4.2. Stacking technique

This method is used to reduce the standby leakage power.It uses the fact
that and “off” transistor stack has an order of magnitude lower subthresh-
old leakage than the individual transistors.To exploit stack effect in standby
mode, the logic block needs to be placed in a state where all stacked transis-
tors are turned off. This can be done manually, however, future design tool
developments may automate this process.A 1.5X to 2.5X reduction has been
reported using this technique[10] .

1.4.3. Supply gating

Supply gating or “sleep transistor” is another method used to reduce both

active and standby leakage power[18].The concept is similar to clock gating,
where power supply is “gated” using a high Vt transistor, to cut off the power
to a logic block .This method can reduce the leakage currents by 1000X;
however there are several issues. First, the high Vt transistor in series with
the supply causes performance degradation.Second, the virtual supply rails
could couple to noise, reducing noise immunity. Third, the virtual supply
rails require a careful local power grid design such that the logic state is not
lost when the virtual supplies are collapsed.

1.4.4. System and architecture level power reduction

The above mentioned circuit design methods of power reduction try to

minimize any one or more components of power dissipation as shown by equa-
tion 1.2.There are power reduction methods adopted at system level where
along with the above mentioned circuit design methods, system power dissi-
pation is reduced by careful design of algorithms and data encoding[9].Though
software does not consume energy, the storage and execution of the software
by the underlying hardware consumes energy.Execution of software involves
power dissipation for computation, storage and communication.The energy
requirement for storage is less compared to that required for execution. Thus
much of power reduction using software deals with minimizing power in ex-
ecution of the code.For example reading a data block from the memory re-

9
quires signals to be sent from the CPU to the main memory.This signaling is
reduced by using algorithms and employing cache memory structures which
try to get the data as far as possible from the CPU registers or from the cache.
Other methods include use of a simplified instruction set for simple decoding
and execution, selective shut-down of unused blocks during the operation of
the design etc.

1.5. Adiabatic or charge recovery based circuit design

Apart from the above mentioned circuit level techniques, one particularly
interesting technique is the Adiabatic Circuit design technique[1].Here the
main concern is the recycling of the charge that has been stored on the
capacitive nodes at the outputs.Usually in conventional CMOS circuits, the
output capacitive nodes of any logic gate are either charged to power supply
level or discharged to ground to get a logic ’1’ and logic ’0’.The discharging of
these capacitive nodes when switching from logic ’1’ to logic ’0’ represents a
wastage of energy.Every time a capacitive node of capacitance C is discharged
to from voltage V to Ground, an energy equal to 12 CV 2 is lost.Adiabatic cir-
cuits try to recycle this stored charge so that instead of discharging to ground,
the stored charge is sent back to the power supply.Adiabatic logic circuits and
the related power supplies are designed accordingly so that charge recycling
is possible.Another important parameter that determines the efficiency of
these circuits is the way the capacitance at the output charges.The charging
process and the charge recovery process are efficient only when the charging
voltage is slowly varying one.
In the next chapter the basics of adiabatic circuits viz., The charging and
discharging process of a capacitor in RC circuit and the energy calculations
are discussed.Later a brief discussion on the already existing adiabatic logic
styles with their merits and demerits is given.
Chapter 2

Adiabatic Architectures

Adiabatic Circuits are based on recovering the energy stored in nodal

capacitances.For a given amount of energy stored in nodal capacitance, the
energy drawn from the source depends on the rate of drawing the charge
from the source.Lower the rate of charging, less is the power drawn from the
source.In other words, the efficiency of charging depends on how slowly the
capacitance is charged.In adiabatic circuits, one would like to take advantage
of this process and increase the efficiency by charging the capacitance slowly
in addition to pumping the stored energy back into the supply.

2.1. RC circuits and related Energetics

This section is a review of the charging and discharging processes occur-

ring in RC circuits.The energy stored in a capacitor when it is charged to a
voltage V in a series RC circuit is explained.
Consider a simple RC circuit as shown in the figure 2.1 .Assume that
initially the charge on the capacitor is 0 and it starts charging at time t=0
and that the voltage source is a step voltage source V u(t).At any instant of
time the voltage on the capacitor is v(t) .In order to charge the capacitor,
the battery has to do work. The work done in transporting a small amount
of charge dq to the capacitor requires an amount of work dW given by

dW = v(t)dq (2.1)

The total work done in charging the capacitor from 0 to Q coulombs is

ˆQ
W = v(t)dq (2.2)
0

11
 At any instant, the voltage across the capacitor is related to the charge
q(t) as v(t) = q(t)
C
.Thus equation 2.2 becomes

ˆQ
q(t) 1 2 (CV )2 1
W = dq = Q = = CV 2 (2.3)
C 2C 2C 2
0

R
C
V(t)

Figure 2.1. A simple series RC circuit

Note that the energy stored in the capacitor is the work done in charging
it and it is independent of the series resistance R.The energy supplied by the
battery is

Ebattery = Q.V = (CV ).V = CV 2 (2.4)

This implies that the energy dissipated by resistor is

1
ER = Ebattery − W = CV 2 (2.5)
2
.
Now consider the same capacitor charged using a ramp voltage instead of a
step voltage.Let the voltage source be Vs (t) = VTt .Where V is the peak voltage
reached by the supply over a period T .The differential equation describing
the charging of the capacitance is given by
ˆ
1
Vs (t) = i(t).R + i(t)dt
C

di(t) 1 V
+ i(t) =
dt RC T
Solving this linear differential equation with the initial condition i(0) = 0
gives i(t) = VTC (1 − e−t/RC ).Using this value for i(t), the Energy dissipated
across the resistor during the entire duration of charging is
ˆ T
ER = i2 (t).Rdt
0

12
 ˆT  2
CV
ER = R(1 − e−t/RC )2 dt
T
0

Evaluating the above integral gives

 2  
CV RC −2T −T
ER = R T− (e RC − 1) + 2RC(e − 1)
RC
T 2
For T ≫ RC, the exponential terms can be neglected and the above
expression can be approximated to
 2  
CV RC
ER = R T− (−1) + 2RC(−1)
T 2
2
CV 2

CV 3RC
ER = RT (1 − )u RC
T 2T T
Thus the power dissipated across the resistor is approximately
 
RC
ER = CV 2 (2.6)
T
Compare equation 2.6 with equation 2.5.The energy dissipated by the
resistor can be reduced by choosing T ≫ RC.
Thus it is observed that a ramp charging waveform can charge a capacitor
optimally by dissipating lesser energy across the resistor.This is the reason
why most of the adiabatic circuits reported in literature use a Ramp type or
a trapezoidal type of power clock waveform.

2.2. Previous Adiabatic Circuit techniques

Many adiabatic/charge recycling circuits for digital logic applications

have been proposed in literature.An adiabatic circuit in strict sense must
follow two rules viz.
— Never turn on a transistor when there is a voltage potential between the
source and drain.
— Never turn off a transistor when current is flowing through it.
Theses 2 rules are observed generally to make sure that step variations
of current are not present and thereby unnecessary energy dissipation is
avoided[8].Most of the adiabatic circuits in literature don’t follow these rules
strictly.All the charge recycling type of circuits are generally referred to as
adiabatic circuits.In this section we take a look at some of the prominent

13
 out out out out

in

out
phi1 phi2 /phi1 /phi2

in Q1 C
D1
phi1
phi2
phi

Figure 2.2. ADL inverter

circuit techniques and analyze their various aspects like complexity, power
consumption , draw-backs if any etc.

2.2.1. Adiabatic Dynamic Logic (ADL)

Adiabatic Dynamic logic was proposed by Dickinson & Denker[7] .An

Adiabatic Dynamic Logic inverter circuit is shown in figure 2.2.It consists
of a diode D1 with cut-in voltage Vγ and a transistor M with threshold
voltage Vt . The capacitor represents the implied load due to subsequent
stages.The power supply is a time varying clock φ. There are two basic
stages of operation of this circuit, precharge and evaluate.In the precharge
state, the power-clock ramps up from 0 to Vdd , precharging the output node
through the forward biased diode D to a value of Vdd − Vγ .In the evaluate
stage, the clock supply ramps down from Vdd to 0.Now if the input is logic ’1’,
then M is ON, so the output is driven low and Vout = 0.If the input is logic ’0’,
then the output remains at high level and Vout = Vdd − Vγ .So logic inversion
is taking place at the output .For cascading this kind of gate, different clocks
are required.If an inverter is driving a second inverter then the clock for the
second inverter should be in phase quadrature as shown in figure 2.2.Thus a
four phase clocking is required for proper cascadable operation.

2.2.2. Split Level Charge Recovery Logic (SCRL)

The Split Level Charge Recovery Logic (SCRL) was reported by Younis
and Knight[30][?].
A good understanding of the working of this logic can be obtained by
analyzing a full cycle of the inverter gate circuit shown in figure [2.3]. It is
similar to a conventional CMOS inverter with the exception of added trans-
mission gate at the output .The inverter is driven by two complimentary
power clocks φ and φ̄ rather than Vdd and ground terminals.φ varies between

14
 Ø
Vdd
P
Ø
Vdd/2

input x output
0

P /Ø Vdd/2
/Ø
0

Figure 2.3. SCRL inverter

Vdd and V2dd whereas φ̄ varies between V2dd and 0 .The transmission gate at the
output is controlled by clocks P and P̄ . Initially, the clocks φand φ̄ are at
Vdd
2
,the transmission gate is turned OFF by the clocks P and P̄ and output
is also V2dd .After a valid input logic level is applied, the transmission gate at
the output is gradually turned ON by swinging P and P̄ to Vdd and ground
respectively.Then the clocks φ and φ̄ swing to Vdd and ground respectively.If
the input to the gate is Vdd then the node marked x and the output will
follow φ̄ to ground and if the input was at ground then the node x and
output follow φ to Vdd . The fact that both φand φ̄ start at V2dd and split
towards Vdd and ground is the reason this family is called Split-Level Charge
Recovery Logic. After the output is sampled by a later gate, the transmission
gate is turned off and the clocks φand φ̄ are gradually brought to V2dd and
the gate is ready to accept a new input.Although this leads to lesser power
consumption compared to conventional CMOS, the circuit is very slow due
to the additional time lost in gradual switching of the nodes from V2dd to Vdd or
ground and vice-versa.

2.2.3. 2N-2P logic

This circuit topology was proposed by Denker et. al[13] . The name comes
from the number of transistors in a gate as each input requires 2 NMOS and
the overhead for each complete gate is 2 PMOS transistors. This circuit
uses differential input and output, so each input to a gate requires both
polarities to be represented and each gate computes both a logic function
and its complement. The basic circuit for a inverter-buffer is shown in figure.
Each NMOS input gets the corresponding positive and negative polarity
inputs and the cross-coupled PMOS are connected to the power clock. The
timing and logical operation of the gate is as follows .The circuit operation
can be divided into 4 phases based on the clock and input conditions. In

15
the reset phase the inputs are low, the outputs are complementary and the
power supply ramps down. The high output, because its PMOS is held in
ON state by the low output, will follow the clock down so that at the end
of the reset phase both outputs will be low. In the wait (second) phase the
power-supply stays low, maintaining the outputs low (the necessary condition
for the next logical gate, which is delayed by a quarter cycle, to perform its
reset phase) and the inputs are evaluated. Because the gate is “powered
down", the evaluation of the inputs will have no effect on the state of the
gate. In the evaluate phase, the power supply ramps up and the outputs will
evaluate to a complementary state. The half-gate with its input high will
have its output held low while the half-gate with its input low will follow
the ramp up. At the end of evaluate phase, the outputs will always be
complementary. This condition is guaranteed by the inverse logic of the two
half gates and their cross coupled PMOS’s (this is the reason that 2N-2P
logic must be differential). In the hold phase the power supply clock stays
high while the inputs ramp down to low. Gate outputs remain valid for
the entire phase.Because there are four phases to the timing, there must
be four quadrature clocks in a complete system, each clock 90 degrees in
advance of the previous clock. In this way, each logic phase in the system
holds its outputs valid while its successor is evaluating (ramping up) and its
predecessor is resetting (ramping down) and waits with its outputs both low
while its successor is resetting (down) and its successor is evaluating (up).

2.2.4. 2N2N-2D logic

This logic family was proposed by Denker et. al .This logic uses differ-
ential signaling and hence each signal is represented by itself and its com-
plement.A logic 0 is represented by a downward pulse on c and a logic 1
is represented by a downward pulse on d.This design requires a four stage
clock cycle as shown in figure [2.4].At the beginning of the cycle the clock is
high at Vdd and the diodes ensure that the outputs are high. The evaluate
phase begins when the clock ramps down to 0V from Vdd .During this phase
the inputs have to be valid.Assume that a=0 and b=1.Since a=0, no current
flows in that branch and the output c remains high.However, all transistors in
the right evaluation branch are on because b = c = 1 . Hence signal d follows
the clock down. The evaluation phase is followed by the hold phase when
the output is valid logic signal and can be sampled by other logic gates.The
input does not have to be valid at this time since both the clock and signal
dare low at this time and turning the right evaluation branch on or off does

16
not affect the output.Similarly just because signal d is low, the left evaluation
branch is off, and the output d remains at logical 1 irrespective of the inputs.
The last phase is the recharge phase when the clock ramps up to Vdd and
because of the diodes, whichever output was low follows the clock to a logical
high.Cascading such logic gates requires the second gate to be operated from
a different clock because the output is valid only during the hold phase while
the inputs are required to be valid during the evaluation phase.

2.2.5. Quasi Static Energy Recovery Logic (QSERL)

QSERL proposed by K.Roy [29] [22]is based on conventional CMOS ap-

proach with two additional diodes as shown in figure 2.5. One diode con-
trols the PMOS tree charging path while the other controls the NMOS tree
discharging path.Compared to the 2N2N-2D and 2N-2P, this logic circuit
requires only two complimentary sinusoidal clocks. QSERL gates are based
on the conventional CMOS logic gates. The diode on the top of PMOS block
controls the charging path.The diode on the top of PMOS block controls the
charging path,while the diode below the NMOS block controls the discharg-
ing path.The power clock consists of two stages.The evaluation phase and
the hold phase.During evaluation phase the clock phi swings up and phi-bar
swings down.One of the two paths, the PMOS pull-up path or the NMOS
pull down path ,is turned ON.Based on the present state of the gate we have
four cases which determine the output for next state.
1. The output node X is LOW and the PMOS tree is turned ON.Then X
follows phi as it swings HIGH
2. The output node X is LOW and the NMOS tree is ON.X remains LOW
and no transition occurs.
3. The output node X is HIGH and PMOS tree is ON.X remains HIGH and
no transition occurs.

c c

d
d

Figure 2.4. 2N2N-2D inverter/buffer

17
 phi

PMOS
block

in out

NMOS
block

phibar

Figure 2.5. QSERL logic block

phi

Mp1 Mp2
out outb

in Mn1 Mn2 inb

Figure 2.6. ECRL inverter/buffer

4. The circuit node X is HIGH and the NMOS tree is ON. X follows phi-bar
down to LOW.

2.2.6. Efficient Charge Recovery Logic (ECRL)

Efficient Charge Recovery Logic or ECRL was proposed by Yong Moon et.
al[16][17] .A simple inverter circuit using ECRL is shown in the figure.This
gate uses differential signaling i.e both input and its compliment are required
for proper functioning.If we assume ’in’ is HIGH and ’inb’ is LOW, at the
beginning of a cycle,when the clock phi rises, ’out’ remains at ground level
because ’in’ turn on MN2. ’outb’ follows phi1 though Mp1.When phi1 is
high, the outputs hold valid logic levels.These values can be used in the next
stage. While phi1 falls down to a ground level, charge on outb’ returns its
energy to phi1.This logic gate avoids usage of any diodes but still requires a
4 phase clocking for proper pipelining( cascading ) of multiple stages.

18
2.2.7. Glitch-Free and Cascadable Adiabatic Logic (GFCAL)

This was proposed by N.S Reddy [20][19] and is based on a modification

of QSERL already discussed above. Instead of using two complimentary
clocks, φ1 and φ¯1 , a single clock is used.More specifically the logic makes use
of a single triangular clock waveform .The load capacitance represents the
capacitance due to input of the next stage. The charging and discharging are
controlled by two diodes D1 and D2 .The operation of this logic is explained
here using an inverter shown in figure 2.7. Similar to QSERL, four cases
arise based on the input and output conditions at the beginning of any cycle.
1. Rising Vclk and input LOW.In this case the transistor M1 is ON , M2 is
OFF and the path M1-D1 allows the capacitor to charge to Vclk producing
logic HIGH at the output.
2. Falling Vclk and input LOW. In this case the capacitor remains charged
due to the presence of diode which does not allow the discharge process.
Thus a LOW input is still giving a HIGH at the output
3. Rising Vclk and input HIGH. Here the transistor M2 is ON and M1 is
OFF and the path M2-D2 allows discharging of the capacitor only when
the output is higher than Vclk (t) at any point. This discharge happens
only for a small duration and may not produce much change at output.
4. Falling Vclk and input HIGH. In this case, the output capacitor gets dis-
charged in-case it was previously charged.Thus a logic LOW is obtained
for a logic HIGH as input.

Vclk
Vdd

Vclk
in
M1 M2 0
Vin
D2
D1
Vout

out

Figure 2.7. GFCAL inverter

2.2.8. Overview

The above discussed logic approaches have their own advantages and
disadvantages.SCRL for example consumes lower power but requires many

19
devices for a logic gate.The SCRL inverter requires 4 transistors, a SCRL
NAND requires 8 transistors.In genera ll more devices are required per logic
function compared to conventional CMOS design approach.Another draw-
back is the requirement of multiple clock phases required for larger circuits.
The 2N-2P and its modified versions like 2N2P-2D,2N2P-2N etc consume
less power but have requirements like differential inputs, multi-phase clock
inputs.The ECRL logic requires four-phase clocking.Multi-phase clocking in-
creases the design complexity of the clocking circuit and also increases the
power dissipation of the clocking circuit. Further the number of transis-
tors per logic gate is more. For a M-input logic gate, the 2N2P-2N ap-
proach requires 6M transistors, thus these gates are inefficient in terms of
chip area. Adiabatic Dynamic logic (ADL) gates have simple gates with
minimum number of transistors among all adiabatic circuits. But still the
gates require a four-phase clocking for cascading.The load capacitor in these
gates is charged irrespective of the input .The output logic levels are valid
only during a particular phase of the clock cycle and this may produce
unwanted outputs and limits the cascadability of this circuit.In addition
to the above, there are several other architectures proposed for adiabatic
operation[15][14][23][5][27][24].However most of them are very complex and
need several clocks for their operation.The advantage one gets in reducing
the power dissipation is more than compensated by the use of several clocks
and increase in number of transistors.However, GFCAL gates proposed by
N.S reddy seem to be more simple with a single clock.The design is cascad-
able and uses less number of devices than other adiabatic circuits other than
ADL. For a logic gate of M inputs, it requires 2M transistors and 2 Diodes.It
makes use of diodes to control the charging or discharging of the load ca-
pacitor. This has a small drawback. The voltage drop ac cross the diode
due to cut-in voltage Vγ causes a power dissipation when current flows across
it. The reported efficiency of 50% compared to conventional CMOS can be
further improved by an alternative technique which consumes relatively less
energy.An attempt has been made to replace the diodes by switching MOS
devices and the outcome of this investigation forms the basis of this thesis.In
the next chapter a modified GFCAL inverter is discussed.
Chapter 3

Modified GFCAL Logic

The GFCAL logic discussed in the previous section has its own draw-
backs.The presence of diodes in the charging and discharging path results
in a loss of energy when current flows across the diodes.Even.From a simple
point of view , if a charge q flows through a forward biased diode having a
cut0in voltage of Vγ ,then an energy of qVγ is expended.If this diode path for
current flow is modified, significant energy reduction can be obtained.Based
on this idea, a modified form of the GFCAL circuit has been proposed. Fig-
ure 3.1 shows the proposed modified GFCAL inverter.The transistors M1 and
M3 form the charging path and M2,M4 form the discharging path.For any
applied logic input, either the charging path or the discharging path will be
valid.Note that in a given stable logic state, only one branch will be valid.The
power supply is a trapezoidal waveform varying between 0 and Vdd .Hereafter
this circuit will be referred to as MGFCAL circuit. In order to highlight the
modification made in this circuit, the original GFCAL circuit is also shown
in the figure 3.1.In the next section, the operation of the circuit is discussed
with step-by step discussion of various states the circuit might be in. Along
with this ,the situation of the GFCAL circuit is also considered for the same
states.

3.1. Operation of the circuit

The working of this circuit can be understood by considering different

cases as follows

Case-1:Output capacitor initially uncharged & input is logic ’0’ In

case of the GFCAL inverter, the transistor M1 will be ON and the diode
D1 will conduct when the clock transitions from 0 to Vdd . This causes the
capacitor to charge and an output of logic ’1’ is obtained.

21
 For the Modified GFCAL,first let’s consider that the load capacitor is in
uncharged state and input is logic ‘0’.In this case, the transistor M1 turns
ON and when the clock goes from 0 to Vdd ,at some point where the power
clock voltage exceeds the threshold voltage Vthn of the transistor M3, it turns
ON and starts charging the capacitor. So a logic ’0’ gives a logic ’1’ at the
output.

Case-2:Output capacitor initially uncharged & input is logic ’1’ For

GFCAL circuit, this means, the transistor M2 is ON and M1 is OFF, and
the diode D2 allows discharging only when the clock transitions from Vdd
to 0.Thus a ’1’ at input gives ’0’ at output.For the modified GFCAL, the
transistor M2 will be ON but M4 will be OFF when the clock waveform is
transitioning from 0 to Vdd .When the clock goes from Vdd to 0, M3 turns
OFF at some point and thus prevents discharging.So the capacitor remains
uncharged. Note that a small amount of charging may still take place initially
due to the leakage currents .But still this is very small and doesn’t increase
the output level much.Thus a logic ’1’ at the input gives a logic ’0’ at the
output.

Case-3:Output capacitor initially charged & input is logic ’0’ The

transistor M1 will be ON and M2 will be OFF in GFCAL gate and only
charging path is available through M1 and D1 when the clock transitions
from 0 to Vdd .Thus the capacitor can only charge and the cannot discharge
thus keeping the output at logic ’1’.
In case of the modified GFCAL, when the output is ‘1’ or charged to
some initial voltage level, and input is ‘0’, the circuit remains in the same
state as before.This can be explained as follows.For input being logic ’0, the
transistor M3 is ON and allows charging through M3 when power clock goes
from 0 to Vdd .So the output is logic ’1’.When power clock goes from Vdd to 0,
the transistor M3 is OFF and thus discharging is prevented. So a ‘0’ at the
input gives a ‘1’ at the output.

Case-4:Output capacitor initially charged & input is logic ’1’ For

GFCAL , this is same as case-2 with capacitor being initially charged.The
transistor M2 will be ON and the charge through the capacitor discharges
through the diode D2 and M2 when the clock transitions from Vdd to 0.In the
modified GFCAL circuit,M3 is ON and M3,M4 will allow the discharge of
the capacitor while the power clock goes from Vdd to 0.M1 will be OFF and
further charging will not take place when power clock goes from 0 to Vdd .So
a logic ’1’ at input gives a logic ’0’ at the output.

22
 Vclk
Vclk

in
in
M1 M2
M1 M2

D2
D1
M3 M4

out
out

CL C

Figure 3.1. Modified GFCAL (left) along with the original GFCAL inverter circuit

From the above discussion it is seen that in modified GFCAL the tran-
sistors M2 and M4 which switch alternatively are seen to allow only either
charging or discharging at a given time.Further these switching transistors are
controlled by the power clock signal which controls this charging/discharging
process.So it is evident that the modified circuit can work satisfactorily as
an inverter.In order to evaluate the performance of this modified inverter,
simulations of the circuit on Hspice has been carried out which is described
below.

3.2. Simulation of the basic transistor based adiabatic

inverter

The circuit shown in figure 3.1 is designed using MOS models of TSMC
180nm CMOS technology .The device length and width are taken as L =
0.18µm and W = 4µm for both PMOS and NMOS transistors.A load ca-
pacitance of 200f emtoF arads is chosen.The power clock is a trapezoidal
waveform varying between 0 and 3.3V.The rise time and fall time have both
been chosen as 20nanoSeconds. A time period of 100 nanoSeconds has been
chosen for the power clock as depicted in figure 3.2.The input waveform is
chosen as a series of alternate 1s and 0s with a rise time of 1picoSecond and
a pulse width of 1 µsec.
The output waveform shown in 3.3 represents broadly the inverted input
waveform.However there appears in the output waveform a ripple superim-
posed on the actual waveform.This ripple is due to the coupling of the power

23
 Graph1
(V) : t(s)
4.0
v(vdd)

2.0
(V)

0.0

-2.0

0.0 100n 200n 300n 400n 500n 600n

t(s)

Figure 3.2. Power Clock waveform

Output waveforms
(V) : t(s)
4.0
output
3.0
(V)

2.0

1.0

0.0
(V) : t(s)
4.0
input

3.0
(V)

2.0

1.0

0.0

0.0 2u 4u 6u 8u 10u

t(s)

Figure 3.3. Input and Output waveforms obtained from HSPICE simulation

clock waveform on the output waveform.This is due to the MOSFET ca-

pacitance coupling the power clock waveform with the output waveform.The
reasons for this are discussed in the next section.In general it is possible to
minimize this ripple by choosing a very large load capacitor but this will
lead to a reduction in the speed of the circuit.This clearly shows that the
proposed inverter circuit replacing diodes by switched transistors seems to
work satisfactorily.Further one may note, there are no unwanted outputs like
glitches.However it is necessary to evaluate its performance from the point
of view of power consumption, effect of clock frequency, effect of load capac-
itance and effect of load capacitance and effect of input frequency.All these
aspects have been investigated and have been described below.

24
3.3. Qualitative discussion on the output waveforms
The output waveform for the inverter circuit with a square wave input
is shown in figure 3.3The output waveforms for the inverter circuit show
a ripple. This is due to the power clock frequency getting coupled to the
output voltage due the gate-source capacitance and drain-source capacitance
of the bottom transistors.The amount of this ripple depends on the relative
values of capacitance cgs & cds of the transistor and the load capacitance.If a
large width transistor is taken with the assumption that better charging may
take place, there may be increased device capacitance which can lead to a
increased ripple.The amount of ripple depends on the values of capacitance of
load and the gate capacitance of the switching NMOS transistor that controls
charging.A discussion of this is given in the next chapter.
As far as the voltage levels at the output are concerned, they are not
the same as in a regular CMOS gate (0, Vdd ).The maximum value i.e logic
’1’ is less than Vdd − Vtn and logic ’0’ is Vtp .The Vtn term is the threshold
voltage of the bottom NMOS transistor.When the capacitor gets charged,it
has to charge through a series connected PMOS and NMOS transistors. An
NMOS transistor cannot pass a good ’1’.With a Vgs > Vtn the output for
NMOS transistor with V at drain gives a value of V − Vtn at the source termi-
nal.Thus the output voltage level is less than Vdd − Vtn for logic ’1’. Similar
explanation goes for the observed logic ’0’ of Vtp due to the bottom PMOS
transistor.Further dependence of the output waveform on various factors like
Device Width,Load Capacitance etc. is discussed in the next section.

3.4. Effect of variation of Device parameters

In this section a discussion is given of the effects of different parameters on
the output waveforms of the inverter circuit.The output waveform has been
observed to depend on parameters like the threshold voltages Vth of NMOS
and PMOS transistors, the width of the transistors, the load capacitance
etc.These trends are discussed below

3.4.1. Effect of Variation of transistor widths

Increasing the width of a transistors allows the circuit to charge or dis-
charge the capacitive nodes faster.This is due to the fact that, a larger width
allows more current to pass through the transistors and thus lesser time is
required to charge the capacitors to a required voltage level.Although the
charging and discharging processes are accelerated,there are other effects of

25
increasing the device width.One effect is that large device dimensions means
that large capacitance of gate-source and drain-source junctions.As seen from
the circuit diagram in figure 3.1, the power clock is connected to the gate
of the controlling transistors and the time varying clock is imposed on the
output waveform due to this coupling.

Graph4
(V) : t(s)
3.0
v(7)

2.0
(V)

1.0

0.0

1u 1.5u 2u

t(s)

Figure 3.4. Output waveform ripple with different device Widths.The minimum
ripple in the figure is with width of 2µm and maximum ripple waveform is with a
device width of 32µm.

Graph0

1.5u

Power dissipation : width of transistor

avg_pwr
1.4u
Power dissipation

1.3u

1.2u

1.1u

0.0 5u 10u 15u 20u

width of transistor

Figure 3.5. Power dissipation with device width

26
 This creates ripples in the output waveform which become prominent as
the device junction capacitance approaches the value of load capacitance.This
is verified by direct simulations on the circuit. Other parameters like power
dissipation are also affected by device widths.An increase in device width
increases the power dissipation of the circuit due to increased current flow
through the charging and discharging branches.This is shown in figure 3.5

3.4.2. Variation with Load capacitance

As the load capacitance takes time to charge or discharge based on its

capacitance value, a large capacitance will lead to slow charging and dis-
charging and small capacitance values will give very fast charge discharge
times.However, a disadvantage of using smaller capacitance is the increased
ripple observed in the output waveform.

Vapplied Vapplied
Vin

Cgs

output
output

Cload
Cload

Figure 3.6. Capacitance model to explain the ripple effect

A circuit model to explain this effect is given in figure 3.6 which consists
of two capacitances connected in series where the top capacitance represents
the coupling capacitance due to both controlling transistors and the bottom
capacitance is the load capacitance.

27
Figure 3.7. Variation in observed ripple for Logic ’1’ output for different capaci-
tances

It is seen that at any point of time the applied voltage Vapplied is dis-
tributed among the two capacitors in an inverse ratio of their capacitance.A
smaller coupling capacitance(device capacitance) gives a very small ripple
and a large coupling capacitance gives a large ripple.

Figure 3.8. Variation in observed ripple for logic ’0’ output for different capaci-
tances

So a trade-off is made in selecting the device width and load capacitance.A

higher capacitance will give a smoother waveform but with reduced speed of
operation..Thus an optimum value of capacitance is chosen in such a way
that it is higher than the cgs of the switching transistors and the ripple
is kept at minimum with optimal operating speed.For the TSMC 180µm
technology, the coupling capacitance due to devices is found to be about

28
 Figure 3.9. Power dissipation for various capacitance..

9.59f F.If the load capacitance is chosen as 200f F , then amount of ripple
will be 9.59f F
200f F
× Vdd = 0.15V .
As far as power dissipation is concerned, the power dissipation is expected
to be constant with respect to load capacitance.Since energy is being recy-
cled from the load capacitance, the load capacitance should not have much
effect on the power dissipation except for a small increase in the power with
increasing capacitance.This small increase is due to the dissipation across the
switches.

3.4.3. Varying the clock power Frequency

The power clock is primarily responsible for efficient charging of the load
capacitance.Theoretically, the power dissipation across the resistive switch i.e
the transistor, depends on how fast the charging or discharging waveform is
varying.An increase in power clock waveform frequency tends to increase the
power dissipation.The voltage level up to which the load capacitance charges
also depends on the power clock frequency.If an extremely slow power clock
is used, the output capacitance charges till Vdd as the clock rise time and fall
time are made larger.Figure shows simulated average power consumption for
different rise-time,fall-time values of power clock.It can be seen that for larger
time periods or slower frequencies, the power dissipation decreases.However
there is a limit on the time period of the power clock.It can be at most equal
to the input data pulse width.Even for this case, the input data and power
clock have to be synchronized for proper logic operation.

29
Figure 3.10. Average Power dissipation for different power clock time periods mea-
sured for 8µsec for 1µsec pulse width input data

Varying the power clock frequency (Time period) shows that as the fre-
quency increases, there is a slight fall in the maximum voltage (Logic ’1’)
reached by the capacitor.The minimum voltage (Logic ’0’ ) also increases with
clock frequency.For clock frequencies very close to the input data frequency
, the output may not be satisfactory.The transmission delay between input
and output will depend on the clock frequency .The delay characteristics and
their dependence on the frequency of power clock is discussed later.

3.4.4. Varying the input data frequency

Input frequency determines how often the logic switches between 1 and
0 and thus influences the power consumption of the gate.The variation of
power consumed for various input data pulse widths is shown in figure 3.11
.It is observed that lower input frequencies(higher time periods )give a low
power input.The minimum time period of the input signal can be equal to
the time period of the power clock.This gives the lowest power consumption
but the input signal and clock should have a 1800 phase difference in order
to get proper logic inversion.Thus usually the input signal and clock signal
are chosen such that time period of clock is about 10 to 15 times that of the
input signal pulse width.This has two advantages.First, the clock and data
need not be synchronized and second the transmission delay between input
and input will not cause appreciable change in output pulse width.
The output voltage levels do not change with input data frequency.The
output levels are decided by the power clock voltage levels and threshold
voltage of the switching transistors. Delay between input and output is

30
 Graph0
(−) : toni(−)
1.5u
avg_pwr

1u
(−)

500n

0.0

0.0 1u 2u 3u 4u 5u

toni(−)

Figure 3.11. Variation of power consumption with different input signal pulse
widths

also not affected by changing input data frequency.Delay characteristics are

dependent on the clock frequency used.This is discussed in next section.

3.4.5. Delay characteristics and input output relations

Transmission delay is defined as the time difference between the input

and output signals measured at the instant they are at their 50% levels.In
the present adiabatic inverter circuit, this delay depends on the power clock
frequency and also on the instant of time at which the input is switching
with respect to the power clock signal.From the circuit operation it is clear
that the output capacitive node can switch i.e charge or discharge only when
the power clock is switching from high to low or vice-versa.Thus if the input
signal switches at the instant when the power clock is not switching , then
the output has to wait till the power clock signal switches.Varying the delay
between the power clock switching instant and the input signal, it is observed
that the delay varies from a minimum of 0nanoSeconds to a maximum of
one period of the power clock signal i.e 20nanoseconds.This variation in
transmission delay with respect to the offset between input signal and power
clock is shown in figure 3.12.
Note that for offsets of more than one clock period, the the input will be
aligned to the next clock switching instant and the delay again decreases to
a minimum.This is because if the switching input and the power clock are

31
Figure 3.12. Delay characteristics with different offsets between input and power
clock

separated in time, then they can be at the maximum , one clock frequency
apart.Keeping in view this delay characteristics, it is suggested to keep the
power clock cycle period small with respect to the input signal.

3.5. Cascadability

The essential requirement for a digital logic gate to be cascadable is that

the input voltage levels and the output voltage levels be same.But in spite of
this requirement not being met in this logic approach, the circuit is cascad-
able.For one stage the outputs are degraded from 0,Vdd to Vtp, Vdd − Vtn .But
this voltage level depends on the supply levels.If the inverter circuit is given
Vtn and Vdd − Vtp as input for logic ’0’ and logic ’1, then it is observed that
output logic levels are also the same as input.The inverter circuit is tested for
cascadability by connecting 100 such inverters in a pipeline.It is observed that
even at the 100th stage output, the same voltage levels are maintained.Figure

32
3.13 shows some waveforms taken from some random stages of the 100 stage
pipeline.

Graph0
(V) : t(s)
3.0
v(n_92)

2.0
(V)

1.0

0.0
(V) : t(s)
3.0
v(n_11)

2.0
(V)

1.0

0.0
(V) : t(s)
3.0
v(n_10)

2.0
(V)

1.0

0.0

500n 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u

t(s)

Figure 3.13. Some output waveforms taken from random stages

In this chapter, the modified GFCAL circuit has been introduced and
its elementary characteristics like voltage levels, power consumption and de-
lay characteristics have been discussed.In the next chapter an approximate
analysis of the inverter circuit is taken considering the MOSFETS as ideal
switches and having a ON resistance of R in the charging and discharging
path.
Chapter 4

Mathematical model of the adiabatic

inverter circuit

The charging and discharging pattern of the adiabatic inverter and the
variation of the waveform with different parameters is further investigated by
considering the charging and discharging branches as composed of resistors
when the corresponding branch is active. Assuming that the combination
of PMOS and NMOS in series acts as a resistor of value R when both the
transistors are ON, it can be seen that both the charging and discharging
branch present the same resistance path.Although the transistors are not
completely ON for the whole charging or discharging process, we assume this
to simplify our analysis.

4.1. Charging process

During charging, when the input is logical ’0’, the MOSFET M1 is ON

and as Vclk increases from 0 to Vdd , the capacitor is charged through the
transistor M3. The clock voltage reaches its peak value Vdd in a time T.The
equation for clock waveform can be written as

Vdd t
Vclk (t) =
T
The clock reaches a value Vth the threshold voltage of the MOSFET M3
at time Tth .The voltage Vc across the load capacitor C after Tth is given by

Vdd t dVc
= RC. + Vc
T dt

dVc 1 1 Vdd t
+ .Vc = ( )
dt RC RC T
dy
This is a linear differential equation of the form dx + P (x)y = Q(x) for
´ ´ ´
which the complete solution is of the form ye P (x)dx = Q(x)e P (x)dx dx + K
The solution becomes

34
 Vdd Vdd
Vdd
in
R
0
== Vdd T
out
C C
0
T
Figure 4.1. simplified model of the charging path

ˆ
t 1 Vdd t
Vc(t) e RC = te RC dt + V0 (4.1)
RC T
which gives
 
−t 1 Vdd t
Vc(t) = e RC RC.e RC (t − RC) + V0
RC T
So the complete solution after simplifying is

Vdd −t
Vc (t) = (t − RC) + V0 e RC
T
The equation for current is obtained by differentiating 4.1 as ic (t) = C dV
dt
c

which gives

Vdd V0 −t
ic (t) = C − e RC
T R

4.1.1. Energy during charging

The energy consumed by the circuit during charging process is evaluated

as
ˆ  
Vclk (t) − Vc
Echarging = Vclk (t) dt
R
which is equal to
ˆ ˆ
1 2 1
Vclk (t) − Vclk (t)Vc dt
R R
In the above expression, the first term becomes

35
 ˆ   2 3
1 Vdd Vdd t
t2 =
R T RT 3
The second term is
ˆ   
1 Vdd t Vdd −t
(t − RC) + V0 e RC dt
R T T

ˆ  2 ˆ  2 ˆ −t
! !
1 Vdd Vdd Vdd V0 te RC
= t2 dt − RC tdt + dt
R T T T

2
t3 V 2 t2 Vdd V0

1 Vdd −t
= − C dd2 − Ce RC (t + RC)
R T 3 T 2 T
So the complete expression for Echarging is

2
2t3 2 2

1 Vdd Vdd t Vdd V0 −t
Echarging = −C 2 − Ce RC (t + RC) (4.2)
R T 3 T 2 T

Equation 4.2 should be evaluated between the limits T1 and T2 which are
the times between which the charging path is valid.i.e
h 2 2
iT2
1 Vdd 2 2t3 Vdd t Vdd V0 −t


Echarging = R T 3
− C T 2 2 − T Ce (t + RC)
RC

h iT1

2 3 V2 2 −t
− R1 VTdd 2t3 − C Tdd2 t2 − VddTV0 Ce RC (t + RC)

4.2. Discharge Cycle

The equation of clock voltage during discharge is

−Vdd
Vclk (t) = t + Vdd
T
 
t
Vclk (t) = Vdd 1 −
T
where the coordinates have been shifted to the origin to simplify the
derivation.
When the input is logical ’1’, the transistor M2 is ON and when the clock
voltage Vclk (t) is falling, the load capacitor discharges through M4 and M2.
The differential equation in this case is
 
dVc 1 1 t
+ Vc = Vdd 1 −
dt RC RC T

36
This again is a linear differential equation as in the case of charging.The
voltage across the capacitor then is
ˆ  
t 1 t t
Vc (t)e RC = Vdd 1 − e RC + V1
RC T
ˆ  
Vdd t t
= 1− e RC + V1
RC T

t
!
Vdd e RC RC t
= 1 − e RC (t − RC) + V1
RC RC
T
( t
! )
−t Vdd e RC RC t
Vc (t) = e RC
1 − e RC (t − RC) + V1
RC RC
T

Vdd −t
Vc (t) = Vdd − (t − RC) + V1 e RC (4.3)
T
The equation of current through across capacitor can be obtained as C dV
dt
c

which gives  
−Vdd V1 −t
ic (t) = C − e RC
T RC

4.2.1. Energy consumed during the discharge cycle

The equation for Energy during discharge is

ˆ  
Vclk (t) − Vc
Edischarge = Vclk (t) dt
R
ˆ
1 2


= Vclk (t) − Vclk (t)Vc dt
R
ˆ  2 ˆ
1 2 t 1
Vdd 1− dt − Vclk (t)Vc dt
R T R
In the above expression, the first part is
ˆ  2 2
 3
1 2 t −Vdd T t
= Vdd 1− dt = 1−
R T 3R T
The second part is
ˆ
1
Vclk (t).Vc (t)dt
R
ˆ  
1 Vdd t Vdd −t
Vdd − (t − RC) + V1RC
dt
R T T

37
 2 2 2
t3 t2
 
Vdd t 1 Vdd 1 Vdd −t
− − RC − V1 RCe RC (t + RC)
RT 2 R T2 3 2 R T
So the complete expression is

2
3 2 2 2
 3
t2
 
−Vdd T t Vdd t 1 Vdd t 1 Vdd −t
Edischarge = 1− + − − RC − V1 RCe RC (t+RC)
3R T RT 2 R T 2 3 2 R T

3 !
t2 t3 t2
  
V2 dd T t 1
V1 −t
Edischarge = − 1− + − 2 − RC
RCe RC (RC + t)
R 2T 3 T T
T Vdd 3 2
(4.4)
Equation 4.4 should be evaluated between T3 and T4 which are the times
between which the discharge path is valid.So the actual power dissipation is
evaluated as

" 3 !#T4
t2 1 t3 t2
  
V2 dd T t V1 −t
Edischarge = − 1− − 2 − RC + RCe RC (RC + t)
R 2T 3 T T 3 2 T Vdd

h   iT3
V2 dd t2 T t 3 1 t3 2 V1 −t
RC t2


− R
− 1−
2T 3
− T
− T2
+ 3
+ t) T Vdd
RCe RC (RC
Combining equation 4.2 and 4.4 one may obtain the energy dissipated as
Echaring − Edischarging . Each of these quantities are to be evaluated for their
respective periods of charging and discharging.The instant T1 at which the
charging takes place can be evaluated as

Vdd T1
= Vth
T
so
Vth T
T1 =
Vdd
T is the rise-time of the power clock . T2 can be calculated as

Vdd T2
= (Vdd − Vth )
T

(Vdd − Vth )T
T2 =
Vdd
Assuming that the capacitance value is small so that charging of the
capacitor closely follows the rise-time.In case the charging and discharging
time constants are large compared to rise time, one has to find out the value

38
 x 10
4 Plot of energy vs power supply of inverter
2.5

Energy (pJ)
1.5

0.5

0
1 1.5 2 2.5 3 3.5
Vdd (volts)

Figure 4.2. Variation in Energy per Cycle of charging and discharging with Vdd

of the output voltage at the peak of the power clock.Further the charging
continues during the flat portion of the power clock till the voltage on the
capacitor is Vdd −Vth .Similar procedure is to be adopted for finding the T3 and
T4 .Using these values of T1 ,T2 ,T3 and T4 , Echarging and Edischarging can be
calculated.The difference between these two gives the energy dissipation in
one charge discharge cycle. The typical numerical calculations carried out to
check the accuracy is discussed later.

4.3. Performance Variation with Circuit Parameters

Using the equations for voltages and energies obtained in the above sec-
tion, it can be seen how the different measurements like voltage levels, energy
etc vary with parameters like load capacitance,Rise-time and fall time of
power clock signal and so on.
It can be observed from the equations of the charging and discharging en-
2
ergies that the energy is directly related to Vdd term.So an increasing supply
level will increase the energy dissipation.The dependence of energy on other
components like path resistance, frequency of power clock etc. is not directly
evident from the expressions.In order to get a clearer view of the dependence
of energy on resistance, the equations 4.2 and 4.4 are evaluated and plotted
for varying path resistance.It is seen that with decreasing resistance, the en-
ergy consumption increases.This is in agreement with figure 3.5 where larger
device width i.e smaller resistance devices have high power dissipation than
small width devices.

39
 3

2.5

Energy per cycle in pJ

2

1.5

0.5
1000 2000 3000 4000 5000
Resistance in Ohms

Figure 4.3. Variation in Energy per cycle with resistance of charging path

A similar approach is followed to determine the dependence of energy

consumption on the frequency of power clock.The power clock is a trapezoidal
waveform with equal rise time, fall time and ON time.Thus the expressions
for energy are plotted by varying a single parameter T which represents both
the rise time and fall time and also represents the clock frequency. Figure
shows that with increasing rise time i.e with slower frequencies the power
dissipation comes down.This is in agreement to the basic idea of adiabatic
design i.e slower the charging lesser the power dissipation.Figure shows the
dependence of energy on the load capacitance.Although, ideally there should
not be any change in energy consumption for different capacitances, a small
increase is observed.Looking at the equations 4.2 and 4.4, one may realize
that there is a small component of extra energy dissipated due to the last
−t
term containing e RC .Normally this value is so small that it may be ignored.

4.4. Efficiency estimation

In order to estimate the efficiency of the MGFCAL circuit, the above

mathematical model is used assuming the ON resistance of the MOS switches
to be R in the charging and discharging paths.The ON resistance is estimated
using a setup where a capacitor of known value is charged through two series
connected NMOS and PMOS transistors. A step voltage is applied at one end
to this combination and the output charging characteristic is considered.From
this exponential charging characteristics, the rise-time is estimated as

40
 5000

4000
Energy per cycle in fJ

3000

2000

1000

0
10 20 30 40 50 60 70 80
Risetime , Fall time of clock T

Figure 4.4. Energy per cycle with varying T (Rise Time, fall Time)

Tr = 2.2R.C

where the values of C and Tr are known from simulations and R is cal-
culated.Such calculation although may not be accurate but gives a simple
method of approximating the non-linear resistance characteristics of the MOS
transistor.For series connection of NMOS and PMOS transistors of 180µm
technology with dimensions of L = 180nm and W = 4µm, the resistance
approximated using this method is approximately 5KΩ.The power clock has
a maximum value of 3.3Volts and C = 200f F.Using these values in the ex-
pressions for energy obtained in the previous sections,the energy values are
obtained as

Echarging = 26.2 × 10−12 J

Edischarging = 15 × 10−12 J

From these values, the percentage of energy lost is calculated as

Echarging − Edischarging 26.2 − 15

%Lost = × 100 = × 100 ≈ 42%
Echarging 26.2

41
 0.0

Energy in pJ ( Yrange -50pJ to 50pJ)

0.0
0 0.0 0.0 0.0 0.0
capacitance 200fF to 2pF

Figure 4.5. Variation in Energy per cycle of charging discharging for different ca-
pacitive loads

In other words an efficiency of 58% is obtained.

It may be seen from this description given here that the estimated en-
ergy recovered is about 58%.In conventional CMOS circuits the entire energy
drawn is dissipated.Thus this circuit may be considered as 58% more effi-
cient.From the result reported in [20] , the GFCAL circuit consumes about
50% of energy that CMOS consumes.Thus the present modified GFCAL con-
sumes 8% less energy than GFCAL circuit and 58% less energy than CMOS
circuit.
Chapter 5

Logic design based on MGFCAL

The inverter design is used as basis for the design of other logic blocks
such as NAND and NOR gates.Any logic gate can be designed in theory
using this approach of two paths,one for charging and other for discharg-
ing.The paths should have the appropriate,pull-up and pull-down circuitry
to provide required logic operation.In this chapter ,the NAND and NOR gates
are discussed and some of the circuit properties are studied.Finally in order
to characterize the power consumption of the gates, the gates are subject to
pseudo-random input bit streams and the average power consumed is mea-
sured for comparison with conventional CMOS gates.As a further extension
a combinational block of 8-bit ripple carry adder has been designed.It is also
shown that , implementation of sequential blocks is also possible.

5.1. NAND function

The NAND function can be obtained by using the circuit shown in figure
5.1.The operation of this gate is similar to that of the inverter i.e the charging
and discharging of the output transistor is controlled by the pull-up and
pull-down paths and the controlling transistors.In order to realize a NAND
operation, consider the truth table for NAND gate.It is required that the
output should be logic ’0’ when both inputs are logic ’1’. For this case we
can have a series connection of two NMOS transistors in the discharge path
.For the logic ’1’ output, the inputs can be any of the three combinations i.e
01, 10, 00.These three cases can be taken care by using a parallel combination
of two PMOS transistors in the charging path.The controlling transistors at
the bottom remain as it is in all logic gates.It can be seen that output can
charge from rising Vclk if the pull-up path comprising of M1,M2 and M5 is
conducting.This occurs for inputs of A=0 , B=0 or A=B=0.So the output
for this is 1.The output capacitor discharges to Vclk if A=B=1 and Vclk is

43
 Vclk

A B M3 A
M2
M1

M4 B

M5 M6
out

Cload

Figure 5.1. NAND gate

falling from Vdd to 0.Thus a NAND operation is realized.A NOR gate can be
realized in a similar manner.

5.2. NOR gate

The NOR function is obtained by using the circuit shown in figure 5.2 .The
operation of this gate is similar to that of the NAND gate above.The output
can charge from rising Vclk if the pull-up path comprising of M1,M2 and
M5 is conducting.This occurs for inputs A=B=0.So the output for this will
be 1.The output capacitor will discharge to Vclk if A=1 or B=1 or A=B=1
and Vclk is falling from Vdd to 0.Thus a NOR operation is realized.It can
be observed from the circuit diagrams of both NAND and NOR gates that
their pull-up and pull-down paths resemble the conventional CMOS gate
structures.Thus any logic function can be realized by having the appropriate
pull-up and pull down paths in the basic inverter configuration.

5.3. Simulation results

The NAND and NOR gates circuits are simulated using HSPICE.Figure
5.3 shows the input and output waveforms for NAND gate.It is observed
that the output shows levels similar to the inverter circuit.An explanation
of the observed voltage levels was already given in section 3.3.The output
levels are lesser than Vdd and 0 due the presence of the switching transistors
M5 and M6 . The pull-up path comprising of M1,M2 and M5 has to pass a

44
 Vclk

A
A M3 B
M1 M4

B M2

M5 M6
out

Cload

Figure 5.2. NOR gate

Adiabatic NAND
(V) : t(s)
4.0
v(b)
(V)

2.0

0.0
(V) : t(s)
4.0
v(a)
(V)

2.0

0.0
(V) : t(s)
3.0
v(out)

2.0
(V)

1.0

0.0

0.0 2u 4u 6u 8u 10u

t(s)

Figure 5.3. NAND gate simulation waveforms

good logic ’1’ but allows a voltage less than Vdd − Vth due to the presence of
M5.Similarly the pull-down path comprising of M3,M4 and M6 passes Vth as a
logic ’0’.The amount of ripple in the output waveform shows a dependence on
the load capacitor as discussed earlier.A larger capacitance will lead to slower
circuit but smoother outputs and a smaller capacitance gives faster circuit
with a considerable ripple due to clock waveform.In any case , for optimum
performance, the load capacitor should be chosen to be considerably larger
than the gate capacitance of the switching transistors as the amount of ripple
depends on the ration of Cload and Cgs as explained earlier.
Since logic circuits with two inputs have been considered,the power con-
sumed in a given time depends on the input bit pattern and how many times

45
 Window No. Power Consumed ( µW atts)
1 0.2913
2 0.3142
3 0.3091
4 0.3501
5 0.2960
6 0.3116
7 0.3530
8 0.3342
9 0.3262
10 0.3333
11 0.3231
12 0.3037
13 0.3482
14 0.3391
15 0.3515
Table 5.1. Average Power measurements for adiabatic NAND gate at various
50µsec duration windows.

the load capacitor charges or discharges.Therefore, in order to better estimate

the power consumption of the circuits, they are fed with two pseudo-random
bit sequences of large length and the average power consumed is measured
during different time slots of equal duration.

5.3.1. Estimating the power consumption by simulation

A pseudo-random sequence is a bit sequence that appears to be random

for small duration of observation but is periodic after a certain length.Pseudo-random
binary sequence are usually generated using a Linear Feedback Shift Register
(LFSR).(Refer Appendix B)
Two bit sequences obtained from same LFSR with different seed values are
given as input to the NAND and NOR gates.Two seed values ’1’ and ’2’ have
been used to obtain different sequences which are applied to the inputs A and
B of the gate.Here for a bit width of 1µSec ,time windows of 50µSec duration
has been chosen and the average power consumed in this windows at various
times is measured and a average is calculated from these values.This average
measurement gives a better estimate of the average power consumption of
the gates. Tables 5.1 and 5.2 show these measurement results. A similar
measurement is made on conventional CMOS gates for comparison purpose.
Tables 5.3 and 5.4 show the measurements for corresponding Conventional
CMOS gates.It is observed that the efficiency of the MGFCAL depends on
the input data used.In general NOR based circuits for MGFCAL have less

46
 Window Power Consumed ( µW atts)
1 0.2111
2 0.2658
3 0.3078
4 0.2795
5 0.2668
6 0.3023
7 0.2651
8 0.3103
9 0.2888
10 0.3102
11 0.3028
12 0.2870
13 0.3001
14 0.2707
Table 5.2. Average Power measurements for adiabatic NOR gate at various 50µsec
duration windows.

Window No. Average Power(µW )

1 0.6188
2 0.6949
3 0.6989
4 0.7851
5 0.6441
6 0.6998
7 0.6879
8 0.7582
9 0.7296
10 0.7559
12 0.7293
13 0.6742
14 0.7868
15 0.7588
Table 5.3. Average Power measurements for Conventional CMOS NAND gate at
various 50µsec duration windows.

47
 Window Average Power (µW )
1 0.5255
2 0.5033
3 0.3369
4 0.3055
5 0.4214
6 0.3638
7 0.4756
8 0.3112
9 0.4169
10 0.3081
12 0.3597
13 0.4790
14 0.3626
15 0.4472
Table 5.4. Average Power measurements for Conventional CMOS NOR gate at
various 50µsec duration windows.

efficiency and this can be attributed to the number of times switching takes
place.the average efficiency of MGFCAL NAND with respect to conventional
CMOS is 57.67%. For NOR , the efficiency is less at 44.78%.This depends
on the number of times charging or discharging of the capacitor is occurring
at the output.
Using the above discussed gates any combinational logic can be imple-
mented.As an example to this, an 8-bit ripple carry adder is designed as
discussed next.

5.4. Further application-an 8-bit adder circuit.

The NAND and NOR gates being universal gates are sufficient to design
any combinational logic circuit.To test the effectiveness of these gates a sim-
ple 8-bit Ripple carry adder is designed.The other gates used for this adder
like Ex-OR have been derived using combination of NAND gates discussed
above. Using such Ex-Or gates a full adder is realized.Figure 5.4shows the
implementation of Ex-OR gate and figure shows typical waveforms for a full
adder using this Ex-OR gate.

48
 A B

A B
Figure 5.4. XOR gate realized using NAND gates

Figure 5.5. Typical waveforms for a full-adder module

A 8-bit ripple carry adder was designed and the performance of this adder
circuit is tested by applying known bit pattern to the two inputs.A schematic
for the 8-bit ripple adder is shown in figure 5.6. A 11001100 and 10101010
pattern was applied and the circuit has been observed to work satisfacto-
rily.Power measurement on the MGFCAL adder circuit and conventional
CMOS adder circuit for this combination are shown in Table 5.5 .

49
 carry
A
B
A
sum
B FA
==
C carry
sum C

B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 C_in B0 A0

FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0

C_out S7 S6 S5 S4 S3 S2 S1 S0

Figure 5.6. A 8-bit ripple carry adder derived using the available NAND gates

Architecture Power measured

Conventional CMOS 8-bit adder 4.75mW
MGFCAL based 8-bit adder circuit 1.85mW
Table 5.5. Power measurements for ripple carry adder

Along with a combinational logic sequential logic is also possible but the
strict requirements on clocks and delays may not be achievable due to device
constraints and power constraints.A JK latch implementation is discussed
for this purpose.

5.5. Implementation of sequential blocks using Modified

GFCAL gates
In the previous sections, combinational blocks using MGFCAL were pre-
sented. Any logic design style will be useful if it is possible to implement
both combinational as well as sequential blocks with it. In order to show that
the present adiabatic style viz. MGFCAL can be used to design sequential
blocks, a latch implementation is shown.

5.5.1. A JK Latch

Conventionally a latch is a clocked gateway for data. The data at the

output of the latch changes according to the input only when the clock is

50
 J Q

Clk

K Qb

Figure 5.7. JK Latch

Circuit Average power (µW )

JK latch conventional CMOS 5.643
MGFCAL based JK latch 1.979
Table 5.6. Power measurements for JK Latch

enabled. When the clock is disabled, the data at the output remains ’latched’
to the previous value it had when clock was valid.Figure 5.7 shows a JK
latch.It makes use of NAND gates. When the clock signal clk is logic ’1’,the
outputs Q and Q̄ will change as the inputs J and K change.When clock is
logic ’0’ , the outputs Q and Q̄ remain latched to the previous values. This
same circuit can be used as the basis for design of a MGFCAL based JK
flip-flop. The NAND gate discussed in the previous section can be used in
place of the conventional NAND gate and required latch functionality can be
obtained.Power measurement for this latch in comparison to a conventional
CMOS version are given in table 5.6
Typical waveforms for the JK latch are shown in the figure.The power
measurements show that MGFCAL based latch consumes about 64% less
power than the conventional circuit.
Thus the MGFCAL logic can be used to implement combinational blocks
as well as sequential blocks.
It has been shown that the MGFCAL based logic design style is efficient
and power saving is up to the tune of 60% for various simple logic blocks.This
is a significant improvement over the GFCAL circuits which gave power sav-
ings of 50% compared to conventional CMOS circuits.The replacement of
diode from the original GFCAL logic circuits with switching transistors that
emulate a diode action and don’t form a diode like potential barrier for
current flow has indeed lowered the power consumption.In addition to power
savings, the architecture follows the simplistic design process of GFCAL with
minimal number of components compared to other adiabatic logic styles like
the 2N2P-2D,2N-2P2N etc.
Figure 5.8. Typical waveforms for the JK latch

52
Chapter 6

Conclusion

This thesis deals with a method of cutting down the wastage of energy
in conventional CMOS circuits.In CMOS circuits the energy stored in the
nodal capacitance is wasted by discharging that energy to ground depending
on the signal that is present .This thesis reports ways of pumping the energy
stored in the capacitor back to the power supply thus reducing the energy
dissipated or energy wasted.Such circuits are referred to as adiabatic circuits.
There have been several approaches reported for recycling the energy and
it has been shown that GFCAL[20] approach generally results in a saving of
50% of what is normally dissipated in similar CMOS circuits.GFCAL cir-
cuits make use of diodes to limit the direction of current in the circuits.It
is not only difficult to realize diodes in CMOS technology but they also
contribute to considerable power dissipation.This thesis reports a method
replacing these diodes by MOSFETS which can be easily fabricated with
CMOS technology.This approach not only simplifies the technology needed
to realize these adiabatic circuit but increases the power saving to about
60% compared to CMOS circuits.It has been clearly demonstrated by carry-
ing out the performance characteristics like the logic level variations,effect of
the characteristics of input signal, power clock signal etc., that these circuits
can be used in large cascadable circuits and systems without any loss of
performance.Simple circuits like logic gates and block level implementations
like adder have been realized.The adiabatic circuits that have been investi-
gated are with a technology of 0.18µm with BSIM3V3 model parameters.The
present day technologies are with much smaller feature sizes and the device
models also are much more complicated.It is quite likely that further modi-
fications in the circuit topology may be needed if one wants to optimize the
performance with advanced technologies.
It may further be noted that these circuits are to be fabricated and effect
of parasitics on the performance is to be finally evaluated before they find

53
their way in real life electronic gadgets.It is believed that future low power
electronic systems should not use not only lower currents and lower voltages
but the wastage of energy must be reduced through the use of adiabatic
approach.
Appendix A

The MOS transistor and CMOS based

circuits

This section is a brief introduction to the Metal Oxide Semiconductor

Field Effect Transistor (MOSFET) which is the most common type of tran-
sistor in use in modern Integrated Circuit (IC) Design.The basic structure
of a MOSFET is shown in the figure.It consists of a doped semiconductor
substrate in which two regions of opposite doping are diffused.These regions
are called Source and Drain.An insulating layer (usually SiO2 ) separates the
metal or poly silicon gate terminal from the semiconductor.Thus the name
Metal Oxide Semiconductor.Based on the kind of substrate and the kind of
implants for source and drain and the kind of carriers responsible for current
flow between source and drain terminals, there are two kinds of transis-
tors in MOS technology.They are n-channel NMOS(having p-type substrate
and n-type source and drain regions) and p-channel transistor PMOS(having
n-type substrate and p-type source and drain regions).A simplified view of a
n-channel MOS transistor is shown in figure A.1.A positive voltage applied
to the Gate terminal first causes a depletion if mobile charge carriers in
the substrate under the oxide layer.A further increase in the applied gate
voltage leads to a formation of region with excess electrons thus making
it n-type.Since the substrate is p-type for n-channel transistor, the n-type
layer formed below the oxide layer is referred to as an inversion layer.The
gate-to-source voltage at which the inversion layer becomes as much n-type,
as the substrate is p-type is commonly called the threshold voltage.When
the gate to source voltage vgs is more than vth the device conducts current
from source to drain on applying a voltage and when it is less than vth
the device conducts practically no current.This property of controlling the
conducting path with the help of applied gate voltage is used in realizing
different circuits in both analog and digital domain.The dependence of the
drain to source current on the drain to source voltage for different values of
gate voltages is shown in the figure A.2.
The current voltage relationship is mostly non-linear.There is a small

55
 G

D S

n+ n+
p-substrate

Figure A.1. n-channel MOS transistor

region in which linearity is observed and this region is called the triode region
of operation.This occurs for vds < vgs − vth .The equation of drain source
current in this region is given by
 
0W Vds
Id = k (Vgs − Vth )Vds −
L 2
where k 0 is a parameter depending on the process technology and W and L
are the length and width of the conducting channel in the transistor.Beyond
vds = vgs − vth , the drain current is essentially independent of vds .This region
is called saturation region.The current in this region is given by the equation

W
Id = k 0 (Vgs − Vth )2
2L

For vth < 0 the transistor is in cut-off mode and no current flows.In all above
cases, the proper operation of the device requires the source-substrate and
drain-substrate junctions to be reverse biased so that no current flows from
source or drain to substrate.This condition is met by connecting the substrate
to the most negative potential available in a design which is usually ground
terminal.
The above discussion is equally applicable for a p-channel transistor or
PMOS.In most of the circuits a combination of PMOS and NMOS transistors
is used and this design methodology is called CMOS (Complimentary Metal
Oxide Semiconductor) design. A simple example of such design is a Inverter
or NOT gate as shown in figure A.3.
Usually the threshold voltage of NMOS devices is positive and that for
PMOS devices is negative.If the two devices are connected as shown in the
figure, then an input voltage of 0 makes the PMOS ON and the output node
is pulled up to Vdd . If a voltage of Vdd is applied at input then NMOS is
ON and output node is pulled down to 0.Thus a logic inversion is taking
place.Note that the pull-up and pull-down processes have to charge or dis-

56
 Graph0
(A) : VOLTS(V)
2.0m
-i(vd)

1.0m
(A)

0.0

0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0

VOLTS(V)

Figure A.2. NMOS current voltage characteristics

Graph0
Vdd 2.0
(V) : t(s)

v(out)

1.0
(V)

0.0

in out -1.0

2.0
(V) : t(s)

v(in)

1.5
(V)

1.0

0.5

0.0

0.0 20n 40n 60n

t(s)

Figure A.3. CMOS Inverter with typical output waveforms

57
 A B NAND out A B NOR out
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Table A.1. Truth tables for NAND and NOR gates

Vdd Vdd

A
A B
out
B out
A

B A B

Figure A.4. CMOS NAND and NOR gates

charge the output nodal capacitance.In general any logic gate can be realized
with appropriate combination of PMOS and NMOS devices.A simple NAND
implementation is discussed here to demonstrate this. A NAND gate has
the truth table as given in A.1 . Thus it is required that output be logic
’0’ only when both inputs are logic ’1’. To get this functionality we want
the output node capacitance to be pulled up for combinations of 00, 01 and
10.The output should be pulled-down for the combination of 11. This can
be achieved by using the circuit shown in figure A.4.A NOR gate can also be
obtained in a similar way.
Appendix B

Linear Feedback Shift register

In order to estimate the average power consumed by logic gates or circuit

with multiple inputs, random input bit sequences are required.One way to
produce such sequences is to use a Linear Feedback Shift Register.An LFSR
is a shift register whose input is a linear function of two or more previous
bit positions( also called taps). Ex-OR and Ex-NOR are the only linear
combinations of single bits possible.There are many possible configurations
and the length of the bit sequence produced depends on the position of the
taps.Only some combination of taps will generate a maximal sequence with
a period of 2n − 1.A simple example of an LFSR with taps at 3rd and 4rd
positions is shown in figure B.1.

1 2 3 4

1 0 0 1

Figure B.1. A 4-bit LFSR

The value of the shift register before start of the sequence is called a
seed.When using a Ex-OR based LFSR, a seed of all 0’s is invalid.Similarly
a seed of all 1’s is invalid for a Ex-NOR based LFSR.
The arrangement of taps for feedback in an LFSR can be expressed as a
polynomial mod 2. This means that the coefficients of the polynomial must
be 1’s or 0’s. This is called the characteristic polynomial.For the LFSR of
figure B.1, the characteristic polynomial is

x4 + x3 + 1 (B.1)

59
 The 1 at the end in the characteristic equation is the input bit to the
LFSR at the beginning of the sequence.The length of this LFSR is 15 (i.e
24 − 1)which means it goes through all the possible 15 states before returning
to initial state.For the purpose of giving inputs to the NAND and NOR gates,
an LFSR of length 1023 has been chosen.This requires a 10-bit shift register
with taps at positions 7 and 10.The characteristic polynomial is

x10 + x7 + 1 (B.2)

Thus the output sequences obtained from such an LFSR can be used as
a input to digital circuits to gauge their power dissipation characteristics.
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1
List of Figures

1.1. Energy,delay Vs. Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2. Energy,Delay Vs. Transistor Width . . . . . . . . . . . . . . . . . . . 6
1.3. static voltage scaling using multiple supplies . . . . . . . . . . . . . . 8

2.1. A simple series RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2. ADL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. SCRL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. 2N2N-2D inverter/buffer . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5. QSERL logic block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6. ECRL inverter/buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7. GFCAL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1. Modified GFCAL (left) along with the original GFCAL inverter circuit 23
3.2. Power Clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3. Input and Output waveforms obtained from HSPICE simulation . . . 24
3.4. Output waveform ripple with different device Widths.The minimum
ripple in the figure is with width of 2µm and maximum ripple
waveform is with a device width of 32µm. . . . . . . . . . . . . . . . . 26
3.5. Power dissipation with device width . . . . . . . . . . . . . . . . . . . 26
3.6. Capacitance model to explain the ripple effect . . . . . . . . . . . . . 27
3.7. Variation in observed ripple for Logic ’1’ output for different capacitances 28
3.8. Variation in observed ripple for logic ’0’ output for different capacitances 28
3.9. Power dissipation for various capacitance.. . . . . . . . . . . . . . . . . 29
3.10. Average Power dissipation for different power clock time periods
measured for 8µsec for 1µsec pulse width input data . . . . . . . . . 30
3.11. Variation of power consumption with different input signal pulse widths 31
3.12. Delay characteristics with different offsets between input and power
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.13. Some output waveforms taken from random stages . . . . . . . . . . . 33

4.1. simplified model of the charging path . . . . . . . . . . . . . . . . . . 35

4.2. Variation in Energy per Cycle of charging and discharging with Vdd . 39
4.3. Variation in Energy per cycle with resistance of charging path . . . . 40

64
4.4. Energy per cycle with varying T (Rise Time, fall Time) . . . . . . . . 41
4.5. Variation in Energy per cycle of charging discharging for different
capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1. NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2. NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3. NAND gate simulation waveforms . . . . . . . . . . . . . . . . . . . . 45
5.4. XOR gate realized using NAND gates . . . . . . . . . . . . . . . . . . 49
5.5. Typical waveforms for a full-adder module . . . . . . . . . . . . . . . . 49
5.6. A 8-bit ripple carry adder derived using the available NAND gates . . 50
5.7. JK Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.8. Typical waveforms for the JK latch . . . . . . . . . . . . . . . . . . . 52

A.1. n-channel MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . 56

A.2. NMOS current voltage characteristics . . . . . . . . . . . . . . . . . . 57
A.3. CMOS Inverter with typical output waveforms . . . . . . . . . . . . . 57
A.4. CMOS NAND and NOR gates . . . . . . . . . . . . . . . . . . . . . . 58

B.1. A 4-bit LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

List of Tables

5.1. Average Power measurements for adiabatic NAND gate at various

50µsec duration windows. . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2. Average Power measurements for adiabatic NOR gate at various
50µsec duration windows. . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3. Average Power measurements for Conventional CMOS NAND gate at
various 50µsec duration windows. . . . . . . . . . . . . . . . . . . . . 47
5.4. Average Power measurements for Conventional CMOS NOR gate at
various 50µsec duration windows. . . . . . . . . . . . . . . . . . . . . 48
5.5. Power measurements for ripple carry adder . . . . . . . . . . . . . . . 50
5.6. Power measurements for JK Latch . . . . . . . . . . . . . . . . . . . . 51

A.1. Truth tables for NAND and NOR gates . . . . . . . . . . . . . . . . . 58

66