172 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO.
1, JANUARY 2015
A BL-CSC Converter-Fed BLDC Motor Drive
With Power Factor Correction
Bhim Singh, Fellow, IEEE, and Vashist Bist, Student Member, IEEE
Abstract—This paper presents a power factor correction
(PFC)-based bridgeless canonical switching cell (BL-CSC)
converter-fed brushless dc (BLDC) motor drive. The pro-
posed BL-CSC converter operating in a discontinuous in-
ductor current mode is used to achieve a unity power
factor at the ac mains using a single voltage sensor. The
speed of the BLDC motor is controlled by varying the
dc bus voltage of the voltage source inverter (VSI) feed-
ing the BLDC motor via a PFC converter. Therefore, the
BLDC motor is electronically commutated such that the VSI
operates in fundamental frequency switching for reduced
switching losses. Moreover, the bridgeless configuration
of the CSC converter offers low conduction losses due to
partial elimination of diode bridge rectifier at the front end.
The proposed configuration shows a considerable increase
in efficiency as compared with the conventional scheme.
The performance of the proposed drive is validated through
experimental results obtained on a developed prototype.
Improved power quality is achieved at the ac mains for
a wide range of control speeds and supply voltages. The
obtained power quality indices are within the acceptable
limits of IEC 61000-3-2.
Index Terms—Bridgeless canonical switching cell
(BL-CSC) converter, brushless dc (BLDC) motor, disconti-
nuous inductor current mode (DICM), power factor correc-
tion (PFC), power quality.
I. I NTRODUCTION
B RUSHLESS DC (BLDC) motor drives have gained im-
portance in the last decade due to power quality im-
provements that have also resulted in exceptional performance
compared with other conventional drives [1]. The advantages
of high efficiency, high reliability, high ruggedness, low elec-
tromagnetic interference (EMI) problems, and excellent perfor-
mance over a wide range of speed control have made this motor
popular in the industry [2], [3]. The BLDC motor is suited
to many low- and medium-power applications ranging from
household appliance; medical equipment; position actuators;
heating, ventilation and air conditioning; motion control; and
transportation [4]–[7]. BLDC motors are synchronous motors
having permanent magnets on the rotor and three phase wind-
ings on the stator. Electronic commutation based on the rotor
position sensed by Hall-effect sensors is used, which eliminates
the problems associated with conventional dc motors, such as
sparking, noise, EMI, and maintenance problems [8].
Manuscript received July 28, 2013; revised November 17, 2013 and
February 5, 2014; accepted March 22, 2014. Date of publication May 30,
2014; date of current version December 19, 2014.
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology Delhi, New Delhi 110 016, India (e-mail: bsingh@
ee.iitd.ac.in; vashist.bist@gmail.com).
Digital Object Identifier 10.1109/TIE.2014.2327551
0278-0046 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
A diode bridge rectifier (DBR), followed by a high value of
the dc link capacitor feeding a voltage source inverter (VSI)-
based BLDC motor, draws peaky current from supply and
injects a high amount of harmonics in the supply system [9].
This results in a poor power factor (as low as 0.7) and high total
harmonic distortion (THD) of supply current (as high as 65%)
at the ac mains. Such power quality indices are not acceptable
by international power quality standard IEC 61000-3-2 [10].
Therefore, power factor correction (PFC) converters are used
for improving the power quality at the ac mains. Many con-
figurations of single-stage power conversion with and without
isolation have been reported in the literature [11], [12]. These
converters have less number of components and, thus, have
low losses associated with them. The cost of these converters
becomes an important parameter, which is primarily decided
by the amount of sensing requirement, which depends on the
mode of operation of the PFC converter. A current multiplier
approach is used for the PFC converter operating in continuous
conduction mode (CCM), which offers low stresses on the PFC
converter’s switch but requires three sensors, whereas a single
voltage sensor is required for the PFC converter operating
in discontinuous conduction mode (DCM) using the voltage
follower approach, but at the cost of high stresses on the PFC
converter’s switch. Therefore, the choice of operating mode
is a tradeoff between the cost and the permitted stress on the
switch [12].
Many configurations of PFC-converter-based BLDC mo-
tor drives have been reported in the literature [1], [13]–[18].
Ozturk et al. [13] and Wu and Tzou [14] have used a conven-
tional boost PFC converter for feeding a BLDC motor drive.
This topology uses constant dc link voltage and pulsewidth
modulation (PWM)-based control of VSI for speed control of
BLDC motor. This suffers from high switching losses in six
solid-state switches of the VSI due to the higher switching
frequency of PWM pulses. Cheng [15] has proposed an active-
rectifier-based BLDC motor drive fed by a three-phase VSI,
which requires a complex control and is suitable for higher
power applications. Lee et al. [16] have explored the possibili-
ties of various reduced part configurations for PFC operation,
which also uses a PWM-based VSI and therefore have high
switching losses in it. A buck chopper operation as a front-end
converter for feeding a BLDC motor drive has been proposed by
Barkley et al. [17]. It also has high switching losses associated
with it due to high frequency switching.
These switching losses are reduced by using a concept of
variable dc link voltage for speed control of BLDC motor [19].
This utilizes the VSI to operate in low frequency switching
required for electronic commutation of BLDC motor, and it
SINGH AND BIST: BL-CSC CONVERTER-FED BLDC MOTOR DRIVE WITH POWER FACTOR CORRECTION
Fig. 1. Conventional PFC-based CSC converter.
reduces the switching losses associated with it. A front-end
single-ended primary-inductor converter (SEPIC) feeding a
BLDC motor using a variable voltage control has been pro-
posed in [18], but at the cost of two current sensors for the
operation of BLDC motor. This paper presents the development
of a reduced sensor-based BLDC motor drive for low-power
application.
In the last decade, bridgeless PFC converters have gained
importance due to low conduction losses at the front end [20]–
[30]. This is achieved due to partial or complete elimination
of the DBR, thereby reducing the conduction losses associated
with it [20]. Many configurations of bridgeless converter are
reported in the literature, each having their peculiar character-
istics [20]–[30]. A bridgeless buck [20] and a bridgeless boost
[21], [22] converters suffer from a limited voltage conversion
ratio (< 1 for buck and > 1 for boost) and therefore cannot be
used for a wide voltage control. To overcome this, a bridgeless
buck–boost converter has been proposed in [23], but it has high
switching losses corresponding to three switches. A two-switch
bridgeless buck–boost PFC converter is proposed in [24], which
has low losses compared with [23]. Higher order PFC bridge-
less Cuk [25]–[27], SEPIC [28], [29], and Zeta [30] converters
have been widely used but have a high number of components.
However, no attention has been paid to the canonical switch-
ing cell (CSC) converter, although it has excellent performance
as a power factor preregulator, a small component count (com-
pared with the nonisolated Cuk converter), and good light
load regulation [31]–[34]. Fig. 1 shows the conventional PFC-
based CSC converter. In this, a combination of a switch (Sw ),
a capacitor (C1 ) and a diode (D) is known as a ‘canonical
switching cell,’ and this cell, combined with an inductor (Li )
and a dc link capacitor (Cd ), is known as a CSC converter. With
proper design and selection of parameters, this combination
is used to achieve PFC operation when fed by a single phase
supply via a DBR and a dc filter.
This work aims at the development of a bridgeless config-
uration of a CSC converter, which offers partial elimination
of DBR at the front end for reducing the conduction losses
associated with it. Moreover, the application of this converter
for feeding a BLDC motor drive is discussed to develop a low-
cost solution for low-power application.
II. PFC BL-CSC C ONVERTER -F ED
BLDC M OTOR D RIVE
Fig. 2 shows the proposed BL-CSC-converter-based VSI
fed BLDC motor drive. As shown in this figure, the DBR
173
is eliminated in this BL-CSC converter, thereby reducing the
conduction losses associated with it. This BL-CSC converter is
designed to operate in a discontinuous inductor current mode
(DICM) such that the currents flowing through inductors Li1
and Li2 are discontinuous, whereas the voltage across the
intermediate capacitors C1 and C2 remains continuous in a
switching period. An approach of variable dc link voltage for
controlling the speed of the BLDC motor is used, and it is elec-
tronically commutated for reduced switching losses in the VSI.
The operation, design, and control of this BL-CSC converter-
fed BLDC motor drive are explained in the following sections.
Performance of the proposed drive is verified with test results
obtained on a developed prototype with improved power quality
at the ac mains for a wide range of speeds and supply voltages.
A brief comparison of the proposed configuration with the
existing bridgeless converter configurations is tabulated in
Table I. It shows the total number of components (Switch—
Sw , Diode—D, Inductor—L, and Capacitor—C) and the com-
ponents conducting during each half-cycle of supply voltage.
The bridgeless buck [20] and boost converter [21], [22] con-
figurations are not suitable for the required application due to
requirement of high voltage conversion ratio (i.e., voltage buck-
ing and boosting) for controlling the speed over a wide range.
As compared with the various bridgeless configurations of Cuk
[25]–[27], SEPIC [28], [29], and Zeta converters [30], the
proposed BL-CSC converter has the relatively lower number
of components and least number of conducting devices during
each half-cycle of the supply voltage, whereas the proposed
configuration exhibits the minimum conduction losses due to
the conduction of minimum number of components during each
half line cycle.
III. O PERATING P RINCIPLE OF THE
PFC BL-CSC C ONVERTER
The operation of the BL-CSC converter is classified into two
major categories.
A. Operation in Positive and Negative
Half-Cycles of Supply
This bridgeless converter is designed such that two switches
operate for positive and negative half-cycles of the supply
voltage.
Fig. 3(a)–(f) shows the operation of the proposed BL-CSC
converter for positive and negative half-cycles of the supply
voltage, respectively. As shown in Fig. 3(a)–(c), during the
positive half-cycle of the supply voltage, the input side current
flows through switch Sw1 , inductor Li1 , and a fast recovery
diode Dp . Similarly, switch Sw2 , inductor Li2 , and diode Dn
conduct for a negative half-cycle of the supply voltage, as
shown in Fig. 3(d)–(f).
Fig. 4(a) shows waveforms of supply voltage with inductor
currents (iLi1 and iLi2 ) and intermediate capacitor voltages
(VC1 and VC2 ). The proposed converter is operating in DICM,
i.e., the inductor currents (iLi1 and iLi2 ) are discontinuous, and
the voltages across the intermediate capacitor (VC1 and VC2 )
remain continuous with a permissible amount of voltage ripple
in a complete switching period.
174 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015
Fig. 2. Proposed BL-CSC converter-fed BLDC motor drive.
TABLE I
C OMPARATIVE A NALYSIS OF THE P ROPOSED BL-CSC
C ONVERTER W ITH E XISTING C ONFIGURATIONS
B. Operation During Complete Switching Period
The proposed BL-CSC converter is designed to operate in
DICM such that current in inductors Li1 and Li2 becomes
discontinuous for a switching period. Fig. 3(a)–(f) shows dif-
ferent modes of operation during a complete switching period
for positive and negative half-cycles of the supply voltage,
respectively. Fig. 4(b) shows the associated waveforms during
the three modes of operations.
Mode I-A: As shown in Fig. 3(a), when switch Sw1 is
turned on, the input side inductor Li1 starts charging via
diode Dp , and current iLi increases, whereas the intermediate
capacitor C1 starts discharging via switch Sw1 to charge the
dc link capacitor Cd . Therefore, the voltage across intermedi-
ate capacitor VC1 decreases, whereas the dc link voltage Vdc
increases.
Mode I-B: When switch Sw1 is turned off, the energy stored
in inductor Li1 discharges to dc link capacitor Cd via diode D1 ,
as shown in Fig. 3(b). The current iLi reduces, whereas the dc
link voltage continues to increase in this mode of operation.
Intermediate capacitor C1 starts charging, and voltage VC1
increases, as shown in Fig. 4(b).
Mode I-C: This mode is the DCM of operation as the current
in input inductor Li1 becomes zero, as shown in Fig. 3(c).
The intermediate capacitor C1 continues to hold energy and
retains its charge, whereas the dc link capacitor Cd supplies the
required energy to the load.
The similar behavior of the converter is realized for the other
negative half-cycle of the supply voltage. An inductor Li2 , an
intermediate capacitor C2 , and diodes Dn and D2 conduct in a
similar way, as shown in Fig. 3(d)–(f).
IV. D ESIGN OF THE PFC BL-CSC C ONVERTER
The proposed PFC converter is designed to operate in DICM
such that the current flowing in inductors Li1 and Li2 be-
comes discontinuous, whereas the voltage across intermediate
capacitors C1 and C2 remains continuous in a switching pe-
riod. A 424-W BLDC motor (full specifications are given in
Appendix A) is selected for experimental studies. Therefore,
a front-end converter of 500 W (Pmax ) is designed to feed a
BLDC motor drive. For a wide variation of speed, the dc link
voltage is controlled from a low value of 70 V (Vdc min ) to the
rated voltage of 310 V (Vdc max ).
The input voltage VS is applied to the PFC converter as
√
VS (t) = Vm Sin(2πfL t) = 220 2Sin(314t)V (1)
√
where Vm is the peak input voltage (i.e., 2VS ), and fL is the
line frequency, i.e., 50 Hz.
SINGH AND BIST: BL-CSC CONVERTER-FED BLDC MOTOR DRIVE WITH POWER FACTOR CORRECTION 175

Fig. 3. Different modes of operation of the proposed BL-CSC converter. (a) Mode I-A. (b) Mode I-B. (c) Mode I-C. (d) Mode II-A. (e) Mode II-B.
(f) Mode II-C.

instantaneous duty ratio D(t) is obtained by substituting (2) in

(3) and rearranging it as
Vdc Vdc
D(t) = = . (4)
Vin (t) + Vdc |Vm Sin(ωt)| + Vdc
Since the speed of the BLDC motor is controlled by varying
the dc link voltage of the VSI, therefore, the instantaneous
power Pi at any dc link voltage Vdc is taken as a linear function
of Vdc as
 
Pmax
Pi = Vdc (5)
Vdc max
where Vdc max represents maximum dc link voltage, and Pmax
is the rated power for the PFC converter.
Using (5), the minimum power corresponding to the mini-
mum dc link voltage of 70 V (Vdc min ) is calculated as 113 W
Fig. 4. Waveforms in different modes of operation of the proposed
converter. (Pmin ).

Now, the instantaneous value of voltage appearing across any A. Design of Input Inductors (Li1 and Li2 ) in
of the switch and inductor combination is given as Discontinuous Current Conduction
 √ 
  The critical value of input inductor Lic is expressed as [12]
Vin (t) = |Vm Sin(ωt)| = 220 2Sin(314t) V (2)
 2
Vin (t)D(t) Rin D(t) VS D(t)
Lic = = = (6)
where  represents the modulus function. 2Iin (t)fS 2fS Pi 2fS
The output voltage Vdc of the CSC converter is given as [9]
where Rin represents the input resistance, fS is the switching
D frequency, and Pi is the instantaneous power.
Vdc = Vin (3)
(1 − D) The selection of switching frequency is a tradeoff between
the permitted losses in the PFC converter switches and the size
where D represents the duty ratio. of the input inductor. A high switching frequency reduces the
The instantaneous value of duty ratio D(t) depends on the size and the value of the input side inductor. However, it also
input voltage Vin (t) and the required dc link voltage Vdc . The increases the switching losses of the solid-state devices and
176 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015

therefore requires a large size of heat sink. Moreover, a low must have low ohmic losses, i.e., low equivalent series resis-
value of inductance increases the current stress on the PFC tance and low equivalent series inductance, which makes them
converter switch in DICM operation. Therefore, the switching suitable for operating at high-surge-current and high-frequency
frequency is selected as 20 kHz such that the losses and current applications. Therefore, the film capacitors (with polypropylene
stress of PFC converter switches are low, and it also meets the dielectric) are used for this application.
desired performance.
The minimum critical value of input inductance (Lic ) is
calculated at the lowest possible value of supply voltage, i.e., C. Design of the DC Link Capacitor (Cd )
85 V, for its operation at universal ac mains (85–270 V). The The value of dc link capacitor is calculated as [11]
value of Lic min is calculated as  
 2  Idc Pi 1
VS min D(t) Cd = = (10)
Lic min = 2ωΔVdc Vdc 2ωκVdc
Pmax 2fS
where κ represents the permitted ripple in dc link voltage.
 2
85 0.7206 The worst case design occurs for the minimum value of dc
=
500 2 × 20 000 link voltage i.e., 70 V, and is expressed as
 
≈ 260 μH (7) Pmin 1
Cd =
Vdc min 2ωΔVdc min
 
where D(t) is the duty ratio calculated at dc √ link voltage of 113 1
310 V and peak value of supply voltage of 85 2 V. =
70 2 × 314 × 0.02 × 70
To achieve a discontinuous current conduction, the value ≈ 1836 μF. (11)
of input inductors Li1 and Li2 must be selected lower than
Lic min [35]. Therefore, the values of Li1 and Li2 are selected Therefore, the dc link capacitor with a nearest possible
around one third of Lic min , i.e., Li1 = Li2 = 70 μH to achieve value of 2200 μF is selected for this application. A capacitor
discontinuous current conduction. required for this application must have a large capacitance per
unit volume due to the high value of the capacitance and its
B. Design of Intermediate Capacitors (C1 and C2 ) for operation at relatively high current and low frequency switching
Continuous Conduction (reflection of second-order harmonic). Therefore, electrolytic
capacitors are best suited for this application.
The expression for intermediate capacitance (C1 and C2 ) is
given as [11]
D. Design of Filter Parameters (Lf and Cf )
Vdc D(t)
C1 = C2 = A low-pass LC filter is used to avoid the reflection of higher
ΔVC (t)fS RL
order harmonics in supply system. The maximum value of filter
Vdc D(t) capacitance is given as [36]
= (8)
η {Vin (t) + Vdc } fS RL Im
Cmax = tan(θ)
ωL V m
where η is the permitted ripple voltage across intermediate √
capacitors (C1 and C2 ), VC is the intermediate capacitor’s (Po 2VS )
= tan(θ)
voltage, and RL is the emulated load resistance and is given ωL V m
2 √
as RL = Vdc /Pi . (500 2/220)
The value of intermediate capacitor is calculated at the = √ tan(1◦ )
314 × 220 2 V
maximum value of intermediate capacitor ripple, which occurs = 574.27 nF. (12)
at rated dc link voltage of 310 V and maximum supply voltage
of 270 V, i.e., Thus, a filter capacitor Cf of 330 nF is selected.
Vdc max D(t) The value of filter inductor is designed by considering the
C1 = C 2 = √  source impedance (LS ) of 4%–5% of the base impedance.
η 2VS max (t) + Vdc fS RL
Hence, the additional value of inductance required is given as
310 × 0.4481   2 
= √ 1 1 VS
0.1{270 2 + 310}20 000 × 192.2 Lf = Lreq + Ls ⇒ = L req + 0.05
4π 2 fc2 Cf ωL Po
  
= 0.522 μF (9) 1 1 (220)2
Lreq = 2 −0.05
4π ×(2000)2 ×330×10−9 314 500
where the amount of permitted voltage across intermediate = 3.77 mH (13)
capacitor (η) is taken as 10% of VC .
Thus, the value of intermediate capacitors (C1 and C2 ) is where fc is the cutoff frequency, which is selected such that
selected as 0.66 μF. The capacitors required for this application fL < fc < fS . Therefore, fc is taken as fS /10.
SINGH AND BIST: BL-CSC CONVERTER-FED BLDC MOTOR DRIVE WITH POWER FACTOR CORRECTION
Fig. 5. Control of the PFC BL-CSC converter feeding BLDC motor
drive.
This LC filter with inductance Lf and capacitance Cf is
selected as 3.77 mH and 330 nF, respectively. The capacitor
selected for this filter is also a film capacitor with polypropylene
dielectric to sustain high frequency switching current ripples
present in this converter.
V. C ONTROL OF THE PFC BL-CSC C ONVERTER -F ED
BLDC M OTOR D RIVE
The control of the proposed PFC based BL-CSC converter-
fed BLDC motor drive is divided into two parts. This includes
the control of the PFC converter for dc link voltage control and
the electronic commutation of BLDC motor.
A. Control of the Front-End PFC Converter
A voltage follower approach is used for the control of the
BL-CSC converter operating in DICM. A single voltage sensor
is required for controlling the dc link voltage for speed control
of BLDC motor, and inherent PFC is achieved at the ac mains
[12]. Fig. 5 shows a complete block diagram for the control of
dc link voltage.
This control scheme consists of a ‘reference voltage gen-
erator,’ a ‘voltage error generator,’ a voltage controller, and
a PWM generator. A reference voltage generator generates a
∗
reference voltage Vdc by multiplying the reference speed ω ∗
with the motor’s voltage constant kv as
∗
Vdc = kv ω ∗ . (14)
The voltage error generator compares this reference dc link
∗ sition to achieve electronic commutation of BLDC motor. A
voltage (Vdc ) with the sensed dc link voltage (Vdc ) to generate
an error voltage (Ve ), which is given as
Ve (k) = Vdc (k)∗ − Vdc (k) (15)
where ‘k’ represents the kth sampling instance.
This error voltage Ve is given to a voltage proportional–
integral (PI) controller to generate a controlled output voltage
Vcc , which is expressed as
Vcc (k) = Vcc (k − 1) + Kp {Ve (k) − Ve (k − 1)} + Ki Ve (k)
(16)
where Kp and Ki are the proportional and integral gains of the
PI controller, respectively.
Finally, the PWM signals are generated by comparing the
output of PI controller (Vcc ) with the high-frequency sawtooth
177
Fig. 6. Three-phase VSI feeding a BLDC motor.
TABLE II
S WITCHING S TATES FOR E LECTRONIC C OMMUTATION OF BLDC M OTOR
BASED ON H ALL -E FFECT P OSITION S IGNALS
signal (md ), which are given as
 
if md < Vcc then Sw1 = ‘ON’
for VS > 0;
if md ≥ Vcc then Sw1 = ‘OFF’
 
if md < Vcc then Sw2 = ‘ON’
for VS < 0; (17)
if md ≥ Vcc then Sw2 = ‘OFF’
where Sw1 and Sw2 represent the gate signals to PFC switches
Sw1 and Sw2 , respectively.
The modeling and stability analysis of the proposed converter
is given in Appendix B.
B. Control of BLDC Motor
Hall-effect position sensors are used to sense the rotor po-
standard commutation technique is used for this trapezoidal
back electromotive force (EMF) BLDC motor, where only two
stator phases conduct at any given instant of time. With the
help of rotor position information, the switches in the VSI
are switched ON and OFF to ensure proper direction of flow
of current in respective windings. Hall-effect position sensors
(Ha , Hb , and Hc ) are used for sensing the rotor position on a
span of 60◦ for electronic commutation. The conduction states
of two switches (S1 and S4 ) are shown in Fig. 6. A line current
iab is drawn from the dc link, whose magnitude depends on
the applied dc link voltage Vdc , back EMFs (ean and ebn ),
resistances (Ra and Rb ), and mutual and self-inductances (M
and La and Lb ) of the stator windings. Table II shows the
different switching states of the VSI feeding a BLDC motor
based on the Hall-effect position signals (Ha −Hc ).
178 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015
Fig. 7. Performance of the proposed drive at rated condition with
supply voltage as 220 V and dc link voltage as (a) 310 V and
(b) 70 V.
VI. R ESULTS AND D ISCUSSION
The performance of the proposed drive is experimentally
validated on a developed hardware prototype of the proposed
BLDC motor drive. A digital signal processor (DSP) TI-
TMS320F2812 is used for the development of the proposed
drive. Optoisolation is provided between the DSP and the gate
driver of the VSI and PFC switches using 6N136 optocouplers.
The necessary protection and scaling circuits are developed to
scale the output of voltage sensor to 0–3 V (CMOS level) for
making it compatible with the analog-to-digital converter of
the DSP. Hall signal filtering and power circuitries are also
developed for the Hall-effect position sensors. Moreover, a
DSP-based moving average filter is also designed for Hall
signal filtering for obtaining improved sensing of rotor posi-
tion for satisfactory operation of the BLDC motor [37]. Test
results of the proposed BLDC motor drive are discussed as
follows.
A. Steady-State Performance
Fig. 7(a) and (b) shows test results of the proposed drive
operation at rated load on the BLDC motor with supply voltage
of 220 V and dc link voltages of 310 and 70 V, respectively. As
shown in these figures, the dc link voltage is maintained at the
Fig. 8. Waveforms of (a) inductors’ currents and (b) intermediate
capacitor voltage with supply voltage at rated load on the BLDC motor
with dc link voltage as 310 V and supply voltage as 220 V.
desired reference value with different magnitude and frequency
of the stator current demonstrating the BLDC motor operation
at different speeds. A sinusoidal supply current in phase with
supply voltage is obtained, which shows a near unity power
factor at both the values of dc link voltages.
B. Performance of the PFC BL-CSC Converter as Power
Factor Preregulator
Fig. 8(a) shows the discontinuous inductor currents (iLi1 and
iLi2 ) with supply voltage to verify the DICM operation of the
BL-CSC converter. As shown in these figures, inductors Li1
and Li2 conduct for the positive and negative half-cycles of the
supply voltage, respectively. Moreover, a continuous voltage
across the intermediate capacitor (VC1 and VC2 ) is obtained,
as shown in Fig. 8(b). The template of voltage and current
of the PFC converter switches Sw1 and Sw2 and its enlarged
waveform are shown in Fig. 9(a) and (b), respectively. A peak
voltage and a current stress of 580 V and 37 A, respectively, are
observed, as shown in Fig. 9(b), which are acceptable for a PFC
converter of 0.5 kW operating in DICM.
Since the converter has been designed to operate in DICM,
a high current stress has been observed on the PFC converter
switch. However, the root-mean-square (RMS) value of the
SINGH AND BIST: BL-CSC CONVERTER-FED BLDC MOTOR DRIVE WITH POWER FACTOR CORRECTION 179

Fig. 9. Stress on PFC converter switches and its enlarged waveforms

during its operation at rated conditions.

current flowing in the PFC converter switches is on the order

of half the value of input RMS current (i.e., ≈ 2.2 A at rated
condition). Hence, the conduction losses in switch correspond-
ing to a relatively reduced RMS current are low. Therefore, a
smaller size of heat sink is required for this application.

C. Dynamic Performance of the Proposed

BLDC Motor Drive
The dynamic performances of the proposed drive during
different values of supply voltage and dc link voltage are shown
in Fig. 10. Fig. 10(a) shows the starting of the BLDC motor
during step change in dc link voltage from 0 to 50 V at a supply Fig. 10. Recorded dynamic performance of the proposed drive at rated
load on the BLDC motor during (a) starting at Vdc = 50 V, (b) speed
voltage of 220 V. A limited inrush in stator current and supply control during change in dc link voltage from 100 to 170 V, and
current is observed, and the increasing frequency of the stator (c) sudden change in supply voltage from 250 to 180 V.
current shows an increase in the speed of the BLDC motor.
Fig. 10(b) shows the dynamic performance of the proposed motor drive. A brief analysis with regard to the system stability
drive during speed control corresponding to the step change in is given in Appendix B.
dc link voltage from 100 to 170 V. A smooth control of dc link
voltage is obtained with limited overshoot in supply and stator
D. PFC and Improved Power Quality at AC Mains
current. Fig. 10(c) shows the dynamic behavior of the proposed
drive during a step change in supply voltage from 250 to 180 V. This section deals with the obtained power quality indices
The dc link voltage is maintained constant, which shows a at the ac mains for the operation of the proposed BLDC motor
satisfactory closed-loop performance of the proposed BLDC drive at different values of dc link voltages and supply voltages.
180 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015
Fig. 11. Recorded power quality indices of the proposed drive at rated
load on the BLDC motor for (a)–(c) Vdc=300 V, VS = 220 V; (d)–(f) Vdc =
70 V, VS = 220 V; (g)–(i) Vdc = 300 V, VS = 259 V; and (j)–(l) Vdc = 300 V,
VS = 170 V.
A ‘Fluke’-made power analyzer is used for the measurement
of quality indices. Information on various parameters and
power quality indices is obtained from three different types of
recorded waveforms. The first set of waveform of four different
cases [see Fig. 11(a), (d), (g), and (j)] shows the RMS value,
the frequency, and the crest factor (CF) of supply voltage and
supply current, respectively. The second set of waveforms [see
Fig. 11(b), (e), (h), and (k)] shows the active, reactive, and
apparent powers; the power factor (PF); and the displacement
power factor (DPF) at ac mains; whereas the third set of
waveforms [Fig. 11(c), (f), (i), and (l)] shows the harmonic
spectra and the obtained THD of supply current at ac mains.
Fig. 11(a)–(f) shows the performance of the proposed drive at
rated condition of supply voltage with dc link voltages of 310
and 70 V, respectively. A near unity power factor is achieved
at the ac mains in both cases, as shown in Fig. 11(b) and (e),
respectively. Moreover, Fig. 11(g)–(l) shows the performance
at rated dc link voltage and rated load on the BLDC motor with
supply voltages as 259 and 170 V, respectively. An improved
power quality operation is achieved with near unity power
factor and low THD of supply current at ac mains within the
limits of IEC 61000-3-2 [10].
Fig. 12. Comparative analysis of (a) losses and (b) efficiency of the
proposed drive with the conventional scheme.
E. Comparison of Efficiency of the Proposed Drive With
the Conventional Scheme
The losses in a BLDC motor drive consist of the losses in
the BLDC motor, VSI, and PFC converter. These losses are
separately measured in three different parts of the proposed
BLDC motor drive. The losses in the BLDC motor consist of
the fixed (core and windage) losses and the variable (copper)
losses. The core and windage losses are fixed, whereas the cop-
per losses depend on the current flowing in the stator windings.
These losses are measured by using the standard method of no-
load test by coupling it with a dc machine. The losses in the
PFC converter are estimated by measuring the output and input
powers using dc link voltage, dc link current, supply voltage,
and supply current, respectively. The losses in the VSI are
estimated by measuring the losses in the complete drive system
and subtracting them from the combined losses of the BLDC
motor and the PFC converter.
In a conventional scheme of a DBR-fed BLDC motor drive,
the losses in VSI are very high due to PWM-based switching of
six switches in a VSI. The switching frequency of the solid state
switches, which are usually insulated-gate bipolar transistor,
is kept on the order of 20 kHz for proper operation. Such
high switching frequency causes high switching losses in the
VSI and, thus, poor efficiency, as shown in Fig. 12(a) and (b),
respectively.
The conventional scheme of a PFC converter-fed BLDC
motor drive uses a constant dc link voltage at the VSI. This
scheme also utilizes PWM-based switching of VSI; thus, it
SINGH AND BIST: BL-CSC CONVERTER-FED BLDC MOTOR DRIVE WITH POWER FACTOR CORRECTION 181

Fig. 14. Circuit configuration of the CSC converter with parasitic

resistances.

A PPENDIX B
Fig. 13. Percentage of losses in different parts of the proposed BLDC M ODELING OF THE P ROPOSED C ONVERTER
motor drive.
The CSC converter is modeled in DCM of operation. Fig. 14
has high switching losses corresponding to high switching shows the circuit configuration of the CSC converter with
frequency, as shown in Fig. 12(a). The efficiency achieved in parasitic resistances as rL , rc1 , and rcd of the input inductor,
this case is lower than the conventional scheme of DBR-fed intermediate capacitor, and dc link capacitor, respectively. The
BLDC motor drive due to extra losses of the PFC converter, as state-space model of the proposed converter is developed where
shown in Fig. 12(b). The proposed scheme uses a fundamental the state-space parameters are the inductor current iLi , the
switching operation of VSI, i.e., the switching losses in VSI intermediate capacitor voltage VC1 , and the dc link voltage Vdc .
are significantly reduced. Moreover, there are low losses in The state-space equations are given as [38]
a PFC converter due to elimination of DBR at the front-end
converter. Therefore, a significant increase in efficiency on the Ẋ = An X + Bn Vin , Vo = CX (18)
order of 4%–5% is achieved in the proposed configuration.
Fig. 13 shows the percentage of losses obtained in different where X is the state vector, An is the state matrix, Bn is the
parts viz., BLDC motor, VSI, and the PFC converter of the input matrix, and C is the output matrix.
proposed BLDC motor drive. The equations corresponding to the three modes of opera-
tion viz., switch turn on (X = A1 X + B1 Vin ), switch turn
off (X = A2 X + B2 Vin ), and the DCM of operation (X =
VII. C ONCLUSION A3 X + B3 Vin ), are respectively given in
A PFC-based BL-CSC converter-fed BLDC motor drive has ⎡ ⎤ ⎡ rL ⎤⎡ ⎤
i̇Li − Li 0 0 iLi

been proposed with improved power quality at the ac mains. A ⎣ V̇C1 ⎦=⎣ 0 b1 1 + rRcd b1 ko ⎦⎣ VC1 ⎦
bridgeless configuration of a CSC converter has been used for V̇dc 1 R−r Vdc
0 a1 Ra1
c1
achieving reduced conduction losses in the PFC converter. The ⎡ ⎤
1
speed control of BLDC motor and PFC at ac mains has been Li rcd 
achieved using a single voltage sensor. The switching losses in ⎣
+ −b1 1 + R ⎦ Vin (19)
the VSI have been reduced by the use of fundamental frequency − a11
switching by electronically commutating the BLDC motor. ⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ 1 ⎤
Moreover, the speed of the BLDC motor has been controlled by i̇Li k3 k4 k5 iLi Li
⎣ V̇C1 ⎦=⎣ k1 b2 k2 ⎦⎣ VC1 ⎦ + ⎣ 0 ⎦ Vin
controlling the dc link voltage of the VSI. The proposed drive rc1 1 1
rc1

has shown an improved power quality at the ac mains for a wide V̇dc a2 a2 a2 1 + R Vdc 0
range of speed control and supply voltages. The obtained power (20)
quality indices have been found within the acceptable limits ⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤
i̇Li 0 0 0 iLi 0
of IEC 61000-3-2. A satisfactory performance of the proposed ⎣ V̇C1 ⎦=⎣ 0 Cd
k6 ⎦⎣ VC1 ⎦ + ⎣− aCCd ⎦Vin
drive has been obtained, and it is a recommended solution for a2 C1  2 1
V̇dc 0 1 1
1+ rc1 Vdc − a1
low-power applications. a2 a2 R 2

(21)
A PPENDIX A where various parameters, i.e., a1 , a2 , and ko −k6 , are de-
BLDC M OTOR R ATING fined as
4 pole, Prated (Rated Power) = 424.11 W (0.5 hp), Vrated  rc1 rcd  Cd
(Rated DC Link Voltage) = 310 V, Trated (Rated Torque) = a1 = − Cd rc1 + rcd + b1 = (22)
R a1 C1
1.35 N · m, ωrated (Rated Speed) = 3000 rpm, Kb (Back
EMF Constant) = 78 V/krpm, Kt (Torque Constant) = Cd
a2 = − Cd (rc1 + rcd ) b2 = (23)
0.74 N · m/A, Rph (Phase Resistance) = 14.56 Ω, Lph a2 C1
(Phase Inductance) = 25.71 mH, J (Moment of Inertia) =  rc1   rc2  1
1.3 × 10−4 N · m/s2 . ko = 1 − 1+ + (24)
R R R · b1
182 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015

By putting these values of different parameters in (30), the

plant transfer function is obtained as
1.205 × 104 s2 + 7.799 × 106 s − 3.718 × 1012
G(s) = .
s3 + 4.565 × 107 s2 + 7.102 × 109 s + 4.282 × 1012
(31)
The transfer function of the PI controller is given as
Ki
Gc (s) = Kp + (32)
s
where Kp and Ki represent the proportional and integral gains
of the PI controller and their values selected as 0.3 and 0.001,
respectively.
Using the plant and compensator transfer functions as given
in (31) and (32), the Bode plots of the complete system with and
without compensator have been plotted, as shown in Fig. 15. A
positive and a high value of gain and phase margins are obtained
on the order of 70 dB and 105◦ , respectively, which shows good
stability of the proposed system [38].

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Bhim Singh (SM’99–F’10) received the B.E.
degree in electrical engineering from the Uni-
versity of Roorkee, Roorkee, India, in 1977 and
the M.Tech. and Ph.D. degrees from the Indian
Institute of Technology (IIT) Delhi, New Delhi,
India, in 1979 and 1983, respectively.
In 1983, he joined, as a Lecturer, the Elec-
trical Engineering Department, University of
Roorkee, where he became a Reader in 1988.
In December 1990, he joined, as an Assistant
Professor, the Electrical Engineering Depart-
ment, IIT Delhi, where he became an Associate Professor in 1994
and has been a Professor since 1997. His areas of interest include
power electronics, electrical machines and drives, renewable energy
systems, active filters, flexible ac transmission systems, high-voltage
direct current, and power quality.
Prof. Singh is a Fellow of the Indian National Academy of Engineering;
The National Academy of Sciences, India; the Indian Academy of
Sciences; The Institution of Engineering and Technology, U.K.; The
Institution of Engineers (India); and the Institution of Electronics and
Telecommunication Engineers and a Life Member of the Indian Society
for Technical Education and the System Society of India.
Vashist Bist (S’13) received the Diploma and
B.E. degrees in instrumentation and control en-
gineering from Sant Longowal Institute of Engi-
neering and Technology, Punjab, India, in 2007
and 2010, respectively. He is currently working
toward the Ph.D. degree in the Department of
Electrical Engineering, Indian Institute of Tech-
nology Delhi, New Delhi, India.
His areas of interests include power electron-
ics, electrical machines, and drives.