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+ Ip L
A B
Fig.1 gives the main circuit of the full bridge with a Vi
- T
zero voltage transition design. S1, S2, S3 and S4 are
controlled switching devices, MOSFETs. D1, D2, S3 D3 C3 S2 D2 C2
VA-B
Ts/2 The minimum turn on delay and the effective duty
Vi DTs/2
DoTs/2 DeTs/2 cycle can be easily taken into account in the design
of a digital controller.
t0 t1 t2 t3 t4 t5 t6 t7 t8 t10 t13 t
0
slope = Vi / ( Lc + Lt )
3. DESIGN OF THE DIGITAL CONTROLLER
-Vi
-Ipa 500 W Model Converter
-Iap slope = Vo / Lf
slope = ( Vi - Vo ) / ( Lc + Lt + Lf )
Vs
A 500 W, 400/40 V FPZVS power converter has
0
t been designed in this study, however, design details
are beyond the scope of this paper, parameters of
the converter are listed bellow instead:
Fig.2 Gate timing and typical waveforms.
MOSFET device IRF840;
switching frequency = 500 kHz;
Responses associated with the voltage and current
at the primary terminals of the transformer, VA-B commutating inductor Lc = 14 µH;
and Ip, are given as two middle traces of Fig.2 output filtering inductor Lf = 6.2 µH;
respectively. Please note that the finite slope of the output filtering capacitor Cf = 6.5 µF;
rising and falling edges of the primary current, IP, load resistance Ro = 3 Ω;
results in the loss of the duty cycle Do. The fixed individual switching duty cycle = 48%;
effective duty cycle De is therefore reflected from maximum phase shift duty cycle = 88%;
the pulse width of the secondary voltage, Vs, shown minimum turn on delay = 40 ns
as the bottom trace of Fig.2. The difference
between D and De is thus 3.1 The software programming
6. REFERENCE
Fig.5 Switching patterns versus voltage of primary
side. [1] M. Marx and D. Schroder ‘Analysis of a Zero-
Voltage-Transition DC-DC Full-Bridge
To confirm the zero voltage transition achieved by Converter’, IEEE Transactions on Power
this design, the gating signals versus the steady Electronics, pp. 298-303, 1995.
state response of the primary voltage, VAB, are [2] W. Chen, F.C. Lee, M. M. Jovanovic and J. A.
given in Fig.5, results are compared with the ZVS Sabate, ‘A Comparative Study of a Class of
conditions. Full Bridge Zero-Voltage-Switched PWM
Converters’, IEEE Transactions on Power
Regarding the ZVS conditions, with the switching Electronics, pp. 893-899, 1995.
sequence as shown, the leg A (left one in Fig.1) is [3] M. M. Walters and W. M. Polivka ‘A High-
the A-P leg, this means that immediately before and Density Modular Power Processor for
after the turn-on of S1 or S3, the converter is in a Distributed Military Power Systems’, Proc,
passive state when it is freewheeling, resulting in APEC 1989, pp. 403-412, 1989.
VAB of zero. That ZVS conditions are [4] R. Redl, N.O. Sokal and L. Balogh, ‘A Novel
Soft-Switching Full-Bridge DC/DC Converter:
Prior to the turn-on of S1, VS1=0 and VAB = 0; Analysis, Design Considerations, and
Prior to the turn-on of S3, VS3=0 and VAB = 0; Experimental Results at 1.5 kW, 100 kHz’,
IEEE Transactions on Power Electronics,
The leg B is the P-A leg, immediately before and Vol.6, No.3, pp.408-418, 1991.
after the turn-on of S2 or S4, the converter is in a [5] L.H. Mweene, C. A.Wright and M.F. Schlecht,
active state and the power is transferred to the ‘A 1 kW 500kHz Front-End Converter for a
transformer secondary. Thus VAB is equal to the Distributed Power Supply System’, IEEE
input supply VI, gives the ZVS conditions as below Transactions on Power Electronics,
Vol.6.NO.3.pp.398-407, 1991.
Prior to the turn-on of S2, VS2=0 and VAB =Vi; [6] P. F. Kocybik and K. N. Bateson, ‘Digital
Prior to the turn-on of S4, VS4=0 and VAB = -Vi Control of a ZVS Full-Bridge DC-DC
Converter’, IEEE Transactions on Power
Although VDS is not shown in Fig.5, it can be Electronics, pp.687-693, 1995.
derived from VAB which satisfy above ZVS [7] B. Andreycak, ‘Phase Shifted, Zero Voltage
conditions as depicted in Fig.5. This means that Transition Design Considerations and the
VSi =0 for i= 1, 2, 3 & 4 is met at the instant of turn UC3875 PWM Controller’, Product &
on of each MOSFET, the ZVS operation is thus Applications Handbook 1995-96, Unitrode
achieved. Integrated Circuits Corporation.
[8] Louis Baker, ‘VHDL Programming with
5. CONCLUSION Advanced Topics’, John Wiley and Sons, Inc.,
1993.
The design example of the FPGA digital controller [9] Jayaram Bhasker, ‘A Guide to VHDL Syntax’,
and simulation results for both the controller and Prentice-Hall, Inc., 1995.
the converter are presented. The current mode [10] Simon S. Ang, ‘Power-Switching Converters’,
control is applied which is ready to be replaced by Marcel Dekker, Inc., 1995.
an advanced control algorithm during the software
programming. The control loop time is found
approximate to the A/D conversion time, this