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Design of a FPGA Controller for Full Bridge Phase-Shifted Zero Voltage

Switching DC/DC Power Converters


Hao Li and Qin Jiang

School of Communications and Informatics


Victoria University, P.O. Box 14428,
Melbourne City MC 8001, Vic. Australia
Email: jq@cabsav.vu.edu.au
Abstract
The paper describes the development of a FPGA (Field Programmable Gate Array) digital
controller for the control of a full bridge phase-shifted zero voltage switching (FPZVS) dc/dc
power converter. The merits of the FPGA technology are its flexibility, intelligence and a
much faster speed than that of a DSP type digital controller. The design details are presented
in this paper based on a 500 W, 500 kHz model converter. The simulation results of both the
controller and the converter are presented using the Xilinx Foundation Series environment and
the PSpice software respectively.

1. INTRODUCTION implemented with hardware only, it takes a long


design cycle and lacks flexibility and intelligence.
The switching mode power supply (SMPS)
operating at a high frequency can provide small The application of digital controllers using digital
size and weight, as the filtering inductance and signal processor to the control of FPZVS converters
capacitance are reduced and power density is was reported [6]. Where the control law is software
increased. However, a high switching frequency programmed, this allows for advanced control
results in high switching losses which reduce the algorithm such as predictive and adaptive controls
efficiency of the converter. To overcome this to be implemented. Also the non-linear dependence
dilemma the soft-switching techniques were of the desired duty factor on the input and output
introduced [1-5], such as the Zero Voltage voltages of the converter can be easily taken into
Switching (ZVS) techniques which can be used to account in the software programming. This is not
increase the converter efficiency at high switching possible with the analog controllers. However,
frequencies [3-5]. In this technique, effects of the given the switching frequencies 500 kHz plus for
parasitic circuit elements are used advantageously the ZVS technology, the speed of DSP may be not
to facilitate the resonant transitions as opposed to sufficiently high to implement advanced control
being dissipatively snubbed. The resonant tank algorithms.
functions to position zero voltage across the
switching device prior to turn-on, eliminating any In this paper, the application of the latest PLD
power loss due to the simultaneous overlap of (Programmable Logic Device) technology into the
switch current and voltage at each transition [4]. control of the FPZVS power converter is explored.
Not only the switching losses but also the Radio The technology features combined merits of both
Frequency Interference (RFI) and the Electro- analog and DSP controllers, in that its design
Magnetic Interference (EMI) are significantly process is that of computer programming using C-
reduced. The requirement of power MOSFET like high level language. Whereas its speed is
switches dissipation is reduced as well and the much faster than DSP. The throughput time of the
conversion efficiency is increased significantly. PLD controller is found approximate to the
conversion time of Analog/Digital converters in
Most of FPZVS converters on the market use the use.
analog controller of integrated circuit from
companies like Unitrode, Motorala and etc [1-5]. In what follows, the operation principle of the
Typically two ICs are used, for instance, UC3875 FPZVS converter is described first, features to be
IC generates the gate drive signal to the MOSFETs, taken into account in the design process of the
and the TL074 IC implements the control loop digital controller are highlighted. The design
regulators [4]. Analog controllers can provide the example of the FPGA digital controller based on a
fastest control loop update compared with digital model converter is then discussed. Finally the
controllers. However, as they are designed and simulation results are presented.
2. OPERATION PRINCIPLE OF THE FPZVS
CONVERTER S1 D1 C1 S4 D4 C4

+ Ip L
A B
Fig.1 gives the main circuit of the full bridge with a Vi
- T
zero voltage transition design. S1, S2, S3 and S4 are
controlled switching devices, MOSFETs. D1, D2, S3 D3 C3 S2 D2 C2

D3 and D4 are body diodes of the MOSFETs. C1,


C2, C3 and C4 are the equivalent parasitic output
D5
capacitance of the MOSFETs. T is the isolation Lf
+

transformer. The inductance L equals Lc + Lt, D6


Cf Ro Vo

where Lc is the commutation inductance and Lt is -

the leakage inductance of the transformer.


Fig.1 Topology of the full bridge phase shifted ZVS
Zero voltage transition requires each MOSFET to converter.
be turned on and off when the voltage across its
drain and source terminals, VDS, is zero. Turn-off Minimum turn-on delay time
with a zero voltage is achieved by the existence of
Ci (i = 1, 2, 3, 4) as shown in Fig.1. When the In principle, to ensure loss-less transitions, the
MOSFET Si is conducting, Ci is short-circuited, i.e. MOSFET must be turned on only when current
VDSi is zero. As the voltage across the Ci cannot flows in its body diode, i.e. after its parasitic output
change instantaneously, the MOSFET is always capacitance is completely discharged and the output
turned off with a zero voltage. Turn-on with a zero capacitance of the other MOSFET of the same leg
voltage however, requires a resonant process, is charged up. The time it takes to complete the
during which Ci of the incoming MOSFET’s Si above process is referred to as the minimum turn-
discharges until its anti-parallel diode conducts on delay time, Ton-min, which if associated with the
prior to turn on, VDSi of the incoming switch is then P-A leg transition is greater than that of the A-P leg
clamped to the diode’s conducting voltage [7]. transition. Also it is proportional to Vi and inversely
proportional to the load current. To minimize the
Power is only transferred to the output section conduction loss, the designed turn-on delay time
during the ON time of the diagonal switches, S1/S2 should be based on the Ton-min corresponding to the
or S3/S4 of Fig.1. This is similar to a conventional specified load condition.
full bridge converter, which alternately places the
transformer primary across the input supply Vi for The effective duty cycle
some period of time. This duration is termed active
state. The FPZVS converter works at a fixed switching
frequency, its operating duty cycle, D, is
During the freewheeling period, either the top two proportional to the on-pulse overlap between two
or the bottom two MOSFETs (S2/S3 or S1/S4 ) are diagonal MOSFETs. Normally, one gating signal is
on, termed as the passive state. The load and fixed as a reference one, while the other is phase
magnetizing currents can therefore continue to flow shifted so that the duration of the on-pulse overlap
in the primary winding. In fact, their commutation of the two devices is varied. At the maximum
to the secondary side is resisted by the leakage output, the overlap is maximum and vice versa.
inductance, and the total resistance of the
transformer, the MOSFETs, and the diode rectifier In Fig.2, the gating signals (top four traces) S1
is not large enough to force a significant through S4 over one power transfer cycle are
commutation during the freewheeling period [5]. illustrated, where the turn-on time delays between
two pair of diagonal switches S1/S2 and S3/S4 are
In Fig.1, the two legs of the bridge, leg A and leg B (t13 – t10) and (t5 – t2) respectively, corresponding
operate under significantly different conditions. to the amount of the phase shift implemented.
Depending on the switching sequence of S1 through
S4, switching one of the legs moves the converter
from the active state to the passive state. While
switching the other leg moves the converter from
the passive state to the active state. The former is
termed A–P leg and the latter the P–A leg.
S1
voltages of the converter. To realize this control
S2
law with an analog controller would be
S3
complicated. While the digital control offers the
S4
possibility to program the equation in software.
Ip

VA-B
Ts/2 The minimum turn on delay and the effective duty
Vi DTs/2
DoTs/2 DeTs/2 cycle can be easily taken into account in the design
of a digital controller.
t0 t1 t2 t3 t4 t5 t6 t7 t8 t10 t13 t
0
slope = Vi / ( Lc + Lt )
3. DESIGN OF THE DIGITAL CONTROLLER
-Vi
-Ipa 500 W Model Converter
-Iap slope = Vo / Lf
slope = ( Vi - Vo ) / ( Lc + Lt + Lf )
Vs
A 500 W, 400/40 V FPZVS power converter has
0
t been designed in this study, however, design details
are beyond the scope of this paper, parameters of
the converter are listed bellow instead:
Fig.2 Gate timing and typical waveforms.
MOSFET device IRF840;
switching frequency = 500 kHz;
Responses associated with the voltage and current
at the primary terminals of the transformer, VA-B commutating inductor Lc = 14 µH;
and Ip, are given as two middle traces of Fig.2 output filtering inductor Lf = 6.2 µH;
respectively. Please note that the finite slope of the output filtering capacitor Cf = 6.5 µF;
rising and falling edges of the primary current, IP, load resistance Ro = 3 Ω;
results in the loss of the duty cycle Do. The fixed individual switching duty cycle = 48%;
effective duty cycle De is therefore reflected from maximum phase shift duty cycle = 88%;
the pulse width of the secondary voltage, Vs, shown minimum turn on delay = 40 ns
as the bottom trace of Fig.2. The difference
between D and De is thus 3.1 The software programming

The block diagram of the FPGA controlled FPZVS


D = De + Do (1)
converter is given in Fig.3. The design of the
controller is a process of computer programming
The effective voltage gain of the converter can be using the C-like VHDL code. There are 3
expressed based on the effective duty cycle De. concurrent processes embedded in the program, the
control cycle, the reference gating signal generation
Vo N s and the phase shift implementation respectively.
= ⋅ De (2) They are to be detailed in what follows.
Vi Np
where Np and Ns are turns of the primary and the Control Cycle
secondary windings of the transformer respectively.
The expression of D can be derived from Fig.1 and The command phase shift duty cycle at ith sampling
Fig.2 as follows cycle, Di, is calculated based on the feedback
signals Vo and If as shown in Fig.3. The current
( Lc + Lt ) control mode is implemented with a band-band
N 2 ⋅ Vo − ⋅ Vo + 4 ⋅ ( Lc + Lt ) ⋅ f s ⋅ I o
Lf control algorithm as follows:
D=
( L + Lt )
N ⋅ Vi − c ⋅ Vo If (Im – If) > 0, Di = Di-1 + k1× sign (Vref – Vo)
Lf
(3) Otherwise Di = Di-1 + k2 × sign (Im – If)
1 Where k1 and k2 are control constant representing
where f s = – the switching frequency and the step change in Di-1, Vo is the output voltage, Vref
Ts is the reference of Vo, If is the filter inductor current
Np and Im is the upper limit of If.
N= – the transformer turns ratio.
Ns
The last equation indicates that the duty cycle D
depends non-linearly on the input and output
XC4005XL switching duration, which is 25 clock cycles in this
Digital
S1 – S4 design. If the diagonal pair, say S3 and S4, is turned
Clock FPZVS on and off simultaneously, then the max Di is 96%
Controller
(25MHz) Converter (24/25), however, the zero voltage switching is lost
(FPGA)
ACT22025 Vo If and MOSFET’s experience a hard switching
D0 – D7 process.
A/D
Converter
Sensor To ensure the ZVS process, there must be two
transitions, the freewheeling and resonant
MAX113
respectively, between the turn-on of S3 and S4, both
takes time to complete. During the freewheeling
Fig.3 The block diagram of the FPGA controlled period, S2 and S3 are conducting immediately
system. before and after the turn-on of S3. Followed by a
resonant interval prior to turn-on S4. Referring to
On the calculation of the duty cycle Di, it is Fig.2 for the corresponding time (t5 – t2). In this
changed division by division at each control cycle. design one clock cycle is allowed for each
In this way the soft start-up is automatically transition respectively, gives the minimum phase
ensured. The controller also provides total device shift of two clock cycles and thus the maximum Ton
and system overload protection due to its inherent of 22 clock cycles. The maximum Di is therefore
current limitation. While the control algorithm 88% (22/25).
employed is simple in this study, any upgrade is
ready to be implemented by reconfiguring logic 3.2 Design of the FPGA controller
functions in the present system with a PC or other
device through the standard X-Checker Adapter After programming, the compilation, synthesis and
socket. implementation of the written program are carried
out under the Xilinx Foundation Series
Reference Gating Signal Generation Process environment. A series of reports are produced by
the software in different aspects at different stages.
Fixed gating signals S1 and S3 are generated in this One report is issued after a successful compilation
process. They are used as the reference waveforms and synthesis of the VHDL program. Up to 8
for gating signals S2 and S4 respectively. reports are issued on successful implementation at
different stages. By analyzing these reports, one
Unlike the hard switching method where the can know whether or not the program achieves the
individual gating signal is symmetrical with a duty design specifications before finalizing the hardware
cycle of 50%, in the case of the soft switching, to implementation. For instance, from the Map
ensure a zero voltage switching of the converter, Report, the 2nd implementation report, it indicates
the minimum turn-on delay time, Ton-min, between that total number of logic gates up to 2604 are
two switches of the same leg needs to be considered required. Consequently, the chip XC4005X with
and is set at 40 ns in this design, corresponding to up to 5000 logical gates available is selected for
one cycle of the external clock frequency of 25 this design.
MHz (refer to Fig.3). This means that the turn-on
duration takes 24 clock cycles against a turn-off From the Post Layout Timing Report, the 7th
duration of 26 ones, given a total clock cycles of implementation report, it is found that the
50 to cover one switching cycle of 500kHz. Thus propagation delay at the longest route formed in the
the individual switching duty cycle is 48% (24/50), device of the digital controller is 33.6 ns,
and is fixed for all four gating signals. corresponding to the maximum allowable
frequency of 29.76 MHz. This is greater than the
Phase Shift Implementation Process selected external clock frequency of 25 MHz for the
XC4005X chip and is therefore satisfactory.
During this process gating signals S2 and S4 are The chip can run at synchronous system clock rates
phase shifted with respect to S1 and S3 respectively. of up to 80 MHz, and internal performance can
The amount of phase shift is based on the command exceed 150 MHz. However, the device only
duty cycle Di determined at each sampling cycle. supports 12-mA Sink Current Per Output, which is
not sufficient high to drive the power MOSFET’s
The maximum Di needs to be specified for the gate at the fsw of 500kHz, due to the MOSFET’s
controller. Generally, Di is defined as 2Ton /Tsw. high input capacitance of 1300 pF. Therefore, a
Where Ton is the on-pulse overlap of the two Totem Pole buffer of low output impedance is
diagonal switches, and Tsw /2 is one half of the necessary to obtain required gate drive current.
The throughput time of the controller is found
approximate to the conversion time of the A/D
converter, that is 193.8 kHz using the device
MAX113 with two sampling channels in parallel
operation. The control loop update can be
significantly reduced by update the A/D converter
to MAX1003, a dual device with a sampling rate of
90 MHz.

A circuit schematic is translated from the program


by the software. The circuit will actually be formed
in a PLD. With the circuit schematic, the program
can be debugged on the component level [8-10]. Fig.4.(a) The post layout timing simulation results
at 88% duty cycle.
4. SIMULATION OF THE CONTROLLER
AND THE CONVERTER

4.1 Controller simulation

Simulation of the FPGA controller is carried out at


real time situation using Xilinx Foundation series
environment, and results are given in Fig. 4(a).
Where the top trace shows the input to the
controller, that is the clock signal at 25 MHz,
followed by four output gating signals S1 through
S4 respectively. It can be seen that waveform of the
gating signals are asymmetrical with a constant on-
pulse duration of 48% of the switching duration as
expected. Fig.4(b) Step response up to 100 µs.

4.2 Control system simulation

Responses of the voltage and current of the model


converter to the gating signals of Fig.4(a) are
simulated using the simulation package MicroSim
DesignLab, a PSpice type circuit simulator. Due to
the limitation of the package, only the responses of
the open-loop system is simulated. Nevertheless,
both steady state and transient responses of the
converter can be analyzed based on this work, and
results are given in Fig.4(b) and (c) respectively.

Fig.4 (b) gives the step response of the model


converter up to 100 µs. From the top trace
downwards, it shows waveforms of the primary
voltage VAB, primary current Ip, secondary voltage Fig.4(c) Steady state portion of Fig.4(b)
Vs and output voltage Vo respectively.
The steady-state portion of Fig.4 (b) is extended in
Fig.4 (c) for 95µs ≤ t ≤ 100µs to give a clear view
of waveforms. The output voltage ripple of 1MHz
with a peak to peak value less than 50mV can be
observed. This implies that the voltage error
window, Vref – Vo of the controller should be set
greater than 25 mV.
means that if the complexity of the control
algorithm is increased it has little effect on the
control loop time, however, more logic gates are
required for the FPGA device to implement the
control algorithm, consequently, the propagation
time of the chip is expected to increase.

By proper design it is possible for the FPGA


controller to obtain combined merits of the analog
and DSP type digital controller, makes it an ideal
candidature for a high performance FPZVS
converter.

6. REFERENCE
Fig.5 Switching patterns versus voltage of primary
side. [1] M. Marx and D. Schroder ‘Analysis of a Zero-
Voltage-Transition DC-DC Full-Bridge
To confirm the zero voltage transition achieved by Converter’, IEEE Transactions on Power
this design, the gating signals versus the steady Electronics, pp. 298-303, 1995.
state response of the primary voltage, VAB, are [2] W. Chen, F.C. Lee, M. M. Jovanovic and J. A.
given in Fig.5, results are compared with the ZVS Sabate, ‘A Comparative Study of a Class of
conditions. Full Bridge Zero-Voltage-Switched PWM
Converters’, IEEE Transactions on Power
Regarding the ZVS conditions, with the switching Electronics, pp. 893-899, 1995.
sequence as shown, the leg A (left one in Fig.1) is [3] M. M. Walters and W. M. Polivka ‘A High-
the A-P leg, this means that immediately before and Density Modular Power Processor for
after the turn-on of S1 or S3, the converter is in a Distributed Military Power Systems’, Proc,
passive state when it is freewheeling, resulting in APEC 1989, pp. 403-412, 1989.
VAB of zero. That ZVS conditions are [4] R. Redl, N.O. Sokal and L. Balogh, ‘A Novel
Soft-Switching Full-Bridge DC/DC Converter:
Prior to the turn-on of S1, VS1=0 and VAB = 0; Analysis, Design Considerations, and
Prior to the turn-on of S3, VS3=0 and VAB = 0; Experimental Results at 1.5 kW, 100 kHz’,
IEEE Transactions on Power Electronics,
The leg B is the P-A leg, immediately before and Vol.6, No.3, pp.408-418, 1991.
after the turn-on of S2 or S4, the converter is in a [5] L.H. Mweene, C. A.Wright and M.F. Schlecht,
active state and the power is transferred to the ‘A 1 kW 500kHz Front-End Converter for a
transformer secondary. Thus VAB is equal to the Distributed Power Supply System’, IEEE
input supply VI, gives the ZVS conditions as below Transactions on Power Electronics,
Vol.6.NO.3.pp.398-407, 1991.
Prior to the turn-on of S2, VS2=0 and VAB =Vi; [6] P. F. Kocybik and K. N. Bateson, ‘Digital
Prior to the turn-on of S4, VS4=0 and VAB = -Vi Control of a ZVS Full-Bridge DC-DC
Converter’, IEEE Transactions on Power
Although VDS is not shown in Fig.5, it can be Electronics, pp.687-693, 1995.
derived from VAB which satisfy above ZVS [7] B. Andreycak, ‘Phase Shifted, Zero Voltage
conditions as depicted in Fig.5. This means that Transition Design Considerations and the
VSi =0 for i= 1, 2, 3 & 4 is met at the instant of turn UC3875 PWM Controller’, Product &
on of each MOSFET, the ZVS operation is thus Applications Handbook 1995-96, Unitrode
achieved. Integrated Circuits Corporation.
[8] Louis Baker, ‘VHDL Programming with
5. CONCLUSION Advanced Topics’, John Wiley and Sons, Inc.,
1993.
The design example of the FPGA digital controller [9] Jayaram Bhasker, ‘A Guide to VHDL Syntax’,
and simulation results for both the controller and Prentice-Hall, Inc., 1995.
the converter are presented. The current mode [10] Simon S. Ang, ‘Power-Switching Converters’,
control is applied which is ready to be replaced by Marcel Dekker, Inc., 1995.
an advanced control algorithm during the software
programming. The control loop time is found
approximate to the A/D conversion time, this

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