A Miniature Q-band CMOS LNA with Triple-cascode Topology

Bo-Jr Huang, Huei Wang and Kun-You Lin

Dept. of Electrical Engineering and Graduate Institute of Communication Engineering

National Taiwan University, 1 Roosevelt Road, Sec. 4, 10617 Taipei, Taiwan, R. O. C.

Abstract — In this paper, a miniature Q-band low noise the cascode devices to minimize the noise figure and enhance
amplifier (LNA) is demonstrated using 0.13Įμm CMOS the stability of the LNA. Based on the triple-cascode structure
technology. The triple-cascode topology is utilized to achieve a with noise reduced technique, a single-stage CMOS LNA
high gain performance with a compact size. In addition, two
inductors are placed between the cascode devices to reduce the
achieves a small signal gain of 12.6 dB and NF of 4 dB at 38
noise and enhance the stability of the LNA. The LNA presents a GHz, with a miniature chip size of 0.42ġǘġ 0.6 mm2. The total
maximum small signal gain of 12.6 dB and a minimum noise power consumption is 24 mW. This is the first triple-cascode
figure of 4 dB at 38 GHz, with a power consumption of 24 mW. LNA in MMW regime reported to date.
The chip size is only 0.42ġ ǘ 0.6 mm2, including all the testing
pads. To the best of our knowledge, this is the first triple-
cascode LNA in millimeter-wave (MMW) regime reported to
date.

Index Terms — Low noise amplifier, cascode, CMOS, MMIC.

I. INTRODUCTION
In RF front-end of a receiver, the LNA contributes most of
the noise figures. Therefore, the design and optimization in
the noise figure, gain, and power consumption for a CMOS
LNA becomes the major concern in millimeter-wave
integrated circuits (MMICs). In the conventional designs, the
common-source configuration is usually used to implement a
CMOS LNA [1]-[2]. In order to make the best trade-off
between the maximum small signal gain and the minimum
noise figure, the inductive source degeneration [3] and the
transformer feedback [4] structures were reported. However,
a single-stage common-source LNA can not provide high Fig. 1. (a) Cascode device, (b) triple-cascode device.
gain, especially in MMW bands. Consequently, multiple
cascade stages for the LNA are required to achieve the gain II. CIRCUIT DESIGN
performance. This will also increase the power consumption,
chip size and noise figure. In recently reported papers, the The LNA is fabricated in TSMC commercial 0.13-μm
LNAs with the cascode device [5]-[9] become popular. The MS/RF purpose CMOS technology, that provides one-poly-
cascode structure is composed of a common-source and a eight-metal (1P8M), with ultra thick metal of 3.3-μm. Metal-
common-gate transistor. It has the advantages of high gain insulator-metal capacitors and polysilicon resistors are
and compact size. In [10], the triple-cascode topology was available. The fmax and fT of the CMOS process are 108 GHz
proposed to implement a high gain power amplifier at 2.4 and 91 GHz, respectively [9].
GHz. Nevertheless, as the operation frequency increases to In general, the cascode structure features a higher
MMW bands, the common-gate stage will contribute a maximum stable power gain (MSG) than the common-source
considerable noise, and thus results in high noise figure of a configuration. Also, the triple-cascode configuration presents
cascode or triple-cascode structure in MMW LNA design. In a higher MSG than the cascode cell. The schematics of the
[11], the parallel resonant inductor was used to reduce the cascode and the triple-cascode device are shown in Fig. 1.
noise of the cascode device, but a large inductor and bypass The triple-cascode cell consists of a common-source transistor,
capacitor are required. M1, and two common-gate transistors, M2, and M3. The
In this paper, another approach is proposed to reduce the combinations of the device size are chosen similar to the
noise of the triple-cascode configuration at MMW frequencies. method reported in [9]. The transistor M1 is selected to be 16
Two series small inductors are designed and placed between finger NMOS with total gate width of 40 μm. M2 and M3 are

978-1-4244-2804-5/09/$25.00 © 2009 IEEE 677 IMS 2009

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24 finger NMOS with total gate with of 60 μm and 32 finger
NMOS with total gate width of 80 μm, respectively.
Under class-A bias condition, the simulated MSG/MAG
and minimum noise figure (NFmin) of the cascode devices are
shown in Fig. 2. It is observed that the triple-cascode device
presents a MSG of 21.5 dB and a NFmin of 3.5 dB at 40 GHz.
The cascode device has a MSG of 15.3 dB and a NFmin of 2.8
dB. Despite the triple-cascode device shows better MSG than
the cascode device, it suffers higher NFmin than the cascode
device. In the mean while, the triple-cascode configuration is
more unstable due to its high gain.

40 10

Cascode 9
Triple-cascode
8
30
7
MSG/MAG (dB)

6
NFmin (dB)
20 5

4 Fig 3. The triple-cascode cell with noise reduced inductors.

3
10
2 50
L1=0.1nH, L2=0.1nH
1 L1=0.2nH, L2=0.15nH
40 L1=0.3nH, L2=0.25nH
0 0
0 20 40 60 80 100

Frequency (GHz)
MSG/MAG (dB)

30

Fig. 2. Simulated MSG/MAG and NFmin of the cascode and triple- 20

cacode device.
10
To reduce the noise contributed by M2 and M3, two
inductors, L1 and L2, are designed and placed between the 0
cascode devices, as shown in Fig. 3. At MMW bands, the 0 10 20 30 40 50 60 70 80
Frequency (GHz)
parasitic capacitances (Cp1~Cp4) of M2 and M3 will cause
excess noise at the output port. By adding the inductors to the
cascode cell, L1 and L2 incorporate with the parasitic (a)
capacitances to be a resonator, so that the parasitic
capacitances of the common-gate stages can be eliminated. 10
L1=0.1nH, L1=0.1nH
Figure 4 presents the MSG and NFmin versus the operation 9 L1=0.2nH, L1=0.15nH
L1=0.3nH, L2=0.25nH
frequency with various L1 and L2. It is observed that with L1 8
Without inductor
烌0.3 nH and L2烌0.25 nH the triple-cascode cell is stable 7

above 40 GHz. However, the triple-cascode cell still retains 6

NFmin(dB)

its MSG below 40 GHz. In the mean while, the NFmin is 5

reduced from 3.5 dB to 2.6 dB. With L1 and L2, the noise 4

figure is minimized and the triple-cascode configuration can 3

be applied to implement the Q-band LNA. 2

0
0 10 20 30 40 50 60 70 80
Frequency (GHz)

(b)
Fig. 4. (a) Simulated MSG/MAG, and (b) NFmin versus frequency of
the triple-cascode cell with various combinations of L1 and L2.

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 M3
VG3
VDD
L1

M2
VG2
L2

M1

VG1

Fig. 5. Circuit schematic of the proposed Q-band LNA.

Fig. 6. Chip photograph of the LNA with the area of 0.252 mm2.
Figure 5 shows the circuit schematic of the proposed Q-
band LNA with single-stage triple-cascode topology. Each 20
gate is biased through a 5-kΩ resistor. T-networks are utilized S21
S11
Small Signal Gain & Return Losses (dB)
to simplify and implement the input and output matching 15
S22
circuits. The input network is matched for the minimum 10
noise figure, and the output is conjugately matched for the
5
maximum small signal gain. All the matching networks are
formed with thin-film microstrip lines, so that they can be 0

easily meandered to achieve a compact layout [9]. The chip

-5
photograph is presented in Fig. 6 with a die size of 0.42ġ ǘġ 0.6
mm2, including all the testing pads. -10

-15

III. MEASUREMENT -20

0 10 20 30 40 50 60
The triple-cascode LNA was measured via on-wafer Frequency (GHz)
probing using Agilent HP8510 test set. Figure 7 plots the
measured small signal gain and return losses of the proposed Fig. 7. Measured small signal gain and return losses of the proposed
LNA. It is observed that the LNA has a measured peak gain LNA.
of 12.6 dB at 38 GHz, with the input return loss of 8 dB and
the output return loss of 11.8 dB. The 3-dB bandwidth is from 5.0
35 to 43 GHz. Over the 3-dB bandwidth, the input and output 4.8
return losses are better than 6 and 5 dB, respectively. The
4.6
measured reverse isolations are all better than 30 dB from 35
4.4
to 43 GHz. Figure 8 illustrates the measured NF. The LNA
has a NF of 3.8 to 4.5 dB from 35 to 43 GHz. At 38 GHz, the 4.2
NF (dB)

measured 1-dB compression point (P1dB) is shown in Fig. 9. 4.0

The LNA has an output P1dB of -2.2 dBm with a total power 3.8
consumption of 24 mW. 3.6
Table I summarizes the previously reported CMOS and
3.4
SOI Q-band LNAs, and compares with this work. The single-
3.2
stage triple-cascode LNA achieves a miniature size and high
gain performance with very low noise figure and power 3.0
34 35 36 37 38 39 40 41 42
consumption. Moreover, it is the first triple-cascode LNA in Frequency (GHz)
MMW regime reported to date.
Fig. 8 Measured NF of the proposed LNA.

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 TABLE I
COMPARISON TABLE OF PREVIOUSLY REPORTED Q-BAND LNAS AND THIS WORK
Process Topology Peak Gain (dB) NF (dB) PDC (mW) Size (mm2) Reference
0.18-μm 3-stage 7@40GHz N/A 300 2.04 [6]
CMOS Cascode
90-nm 2-stage 7.3@35GHz N/A 10.5 N/A [2]
CMOS CS
90-nm 1-stage 11.9@35GHz 3.6@35GHz 40.8 0.18 [7]
SOI Cascode
0.13-μm 3-stage 19@40GHz N/A 36 1.43 [8]
CMOS Cascode
0.13-μm 3-stage 20@43GHz 6.3@41GHz 36 0.525 [1]
CMOS CS
65-nm 2-stage 14.3@42GHz 6@50GHz 43.2 0.286 [12]
CMOS CS
0.13-μm 1-stage 12.6@38GHz 4@38GHz 24 0.252 This Work
CMOS Triple-cascode

through Chip Implementation Center (CIC) of Taiwan. This

12 work was supported in part by the National Science Council
10 of Taiwan, R.O.C. (NSC 96-2219-E-002-015, NSC96-2219-
8 Gain (dB)
E-002-020) and NTU Excellent Research Projects (95R0062-
6
4 AE00-01, 97R0062-03, 97R0533-1).
2
0
-2 REFERENCES
-4
-6
[1] Jeng-Han Tsai, et al., “A miniature Q-band low noise amplifier
-8 Output Power (dBm) using 0.13Įμm CMOS technology,” IEEE MWCL, vol. 16, no. 6,
-10
pp. 327-329, June 2006.
-12
[2] M.A. Masud, et al., “90 nm CMOS MMIC amplifier,” in IEEE
-14
RFIC Symp. Dig., June 2004, pp. 201-204.
-16
[3] Shih-Chieh Shin, et al., “A 3.9-dB NF low-noise amplifier
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-30 -25 -20 -15 -10 -5
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ACKNOWLEDGEMENT [12] M. Varonnen, et al., “Millimeter-wave integrated circuits in
65-nm CMOS,” IEEE JSSC, vol. 43, no. 9, pp. 1991-2002, Sep.
The chip was fabricated by Taiwan Semiconductor (TSMC) 2008.

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