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CH2 3 14 AGND
CH3 4 13 CLK
CH4 5 12 DOUT
CH5 6 11 DIN
CH6 7 10 CS/SHDN
CH7 8 9 DGND
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, V SS = 0V, VREF = 5V,
TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters Sym Min Typ Max Units Conditions
Conversion Rate
Conversion Time tCONV — — 12 clock
cycles
Analog Input Sample Time tSAMPLE 1.5 clock
cycles
Throughput Rate fSAMPLE — — 100 ksps VDD = VREF = 5V
— — 50 ksps VDD = VREF = 2.7V
DC Accuracy
Resolution 12 bits
Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3204/3208-B
— ±1.0 ±2 MCP3204/3208-C
Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes
over-temperature
Offset Error — ±1.25 ±3 LSB
Gain Error — ±1.25 ±5 LSB
Dynamic Performance
Total Harmonic Distortion — -82 — dB VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion — 72 — dB VIN = 0.1V to 4.9V@1 kHz
(SINAD)
Spurious Free Dynamic — 86 — dB VIN = 0.1V to 4.9V@1 kHz
Range
Reference Input
Voltage Range 0.25 — VDD V Note 2
Current Drain — 100 150 µA
— 0.001 3.0 µA CS = VDD = 5V
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
tCSH
CS
tSUCS
tHI tLO
CLK
tSU tHD
DIN MSB IN
tDO tR tF tDIS
tEN
DOUT Null Bit MSB OUT LSB
CLK 1 2 3 4
Voltage Waveforms for tDO
DOUT B11
CLK tEN
tDO
Voltage Waveforms for tDIS
DOUT
VIH
CS
DOUT 10%
Waveform 2†
* Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.
† Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.
1.0 2.0
0.8 Positive INL VDD = VREF = 2.7 V
1.5
0.6
1.0
0.4 Positive INL
INL (LSB)
0.5
INL (LSB)
0.2
0.0 0.0
-0.2 -0.5
Negative INL
-0.4 Negative INL -1.0
-0.6
-1.5
-0.8
-2.0
-1.0
0 10 20 30 40 50 60 70 80
0 25 50 75 100 125 150
Sample Rate (ksps) Sample Rate (ksps)
FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL)
vs. Sample Rate. vs. Sample Rate (VDD = 2.7V).
2.5
2.0
2.0
1.5
1.5 Positive INL
1.0
1.0 Positive INL
INL (LSB)
INL (LSB)
0.5 0.5
0.0 0.0
-0.5 -0.5
-1.0 Negative INL -1.0 Negative INL
-1.5 -1.5
-2.0
-2.0
0 1 2 3 4 5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF (V)
FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL)
vs. VREF. vs. VREF (VDD = 2.7V).
1.0 1.0
0.8 VDD = VREF = 2.7 V
0.8
FSAMPLE = 50 ksps
0.6 0.6
0.4 0.4
INL (LSB)
INL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL)
vs. Code (Representative Part). vs. Code (Representative Part, VDD = 2.7V).
1.0 1.0
VDD = VREF = 2.7 V
0.8 0.8
Positive INL FSAMPLE = 50 ksps
0.6 0.6
Positive INL
0.4 0.4
INL (LSB)
INL (LSB)
0.2 0.2
0.0 0.0
-0.4 -0.4
-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL)
vs. Temperature. vs. Temperature (VDD = 2.7V).
1.0 2.0
VDD = VREF = 2.7 V
0.8 1.5
0.6
1.0
0.4
DNL (LSB)
DNL (LSB)
0.5
0.2
Positive DNL Positive DNL
0.0 0.0
-0.2 -0.5
Negative DNL
-0.4
Negative DNL -1.0
-0.6
-0.8 -1.5
-1.0 -2.0
0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80
Sample Rate (ksps) Sample Rate (ksps)
3.0 3.0
VDD = VREF = 2.7 V
2.0 2.0 FSAMPLE = 50 ksps
Positive DNL
1.0 1.0
DNL (LSB)
Positive DNL
DNL (LSB)
0.0 0.0
-2.0 -2.0
-3.0 -3.0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF (V)
1.0 1.0
VDD = VREF = 2.7 V
0.8 0.8
FSAMPLE = 50 ksps
0.6 0.6
0.4 0.4
DNL (LSB)
DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code
1.0 1.0
0.8 0.8 VDD = VREF = 2.7 V
FSAMPLE = 50 ksps
0.6 0.6
0.4 Positive DNL 0.4 Positive DNL
DNL (LSB)
DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
Negative DNL Negative DNL
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
4 20
3 18
VDD = VREF = 2.7 V
FSAMPLE = 50 ksps 16
Offset Error (LSB)
2
Gain Error (LSB)
14 VDD = VREF = 5V
1 FSAMPLE = 100 ksps
12
0 10
-1 8 VDD = VREF = 2.7V
6 FSAMPLE = 50 ksps
-2 VDD = VREF = 5 V
FSAMPLE = 100 ksps 4
-3
2
-4 0
0 1 2 3 4 5 0 1 2 3 4 5
VREF (V) VREF (V)
FIGURE 2-15: Gain Error vs. VREF. FIGURE 2-18: Offset Error vs. VREF.
0.2 2.0
0.0 VDD = VREF = 2.7 V 1.8
FSAMPLE = 50 ksps VDD = VREF = 5 V
-0.2 1.6
-0.4 1.4
-0.6 1.2
-0.8 1.0
-1.0 0.8 VDD = VREF = 2.7 V
FSAMPLE = 50 ksps
-1.2 VDD = VREF = 5 V 0.6
FSAMPLE = 100 ksps
-1.4 0.4
-1.6 0.2
-1.8 0.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs.
Temperature.
100 100
90 VDD = VREF = 5 V VDD = VREF = 5 V
90
FSAMPLE = 100 ksps FSAMPLE = 100 ksps
80 80
70 70
SFDR (dB)
SNR (dB)
60 60
50 50 VDD = VREF = 2.7 V
FSAMPLE = 50 ksps
40 VDD = VREF = 2.7V 40
30 FSAMPLE = 50 ksps 30
20 20
10 10
0 0
1 10 100 1 10 100
Input Frequency (kHz) Input Frequency (kHz)
FIGURE 2-20: Signal to Noise (SNR) vs. FIGURE 2-23: Signal to Noise and
Input Frequency. Distortion (SINAD) vs. Input Frequency.
0
80
-10 VDD = VREF = 5 V
70 FSAMPLE = 100 ksps
-20
-30 60
VDD = VREF = 2.7V
SINAD (dB)
THD (dB)
FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal to Noise and
(THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level.
12.0
12.00
11.75 11.5
11.50
11.25 11.0
ENOB (rms)
ENOB (rms)
FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits
(ENOB) vs. VREF. (ENOB) vs. Input Frequency.
100 0
-30
60
50 V DD = VREF = 2.7 V -40
FSAMPLE = 50 ksps
40 -50
30
-60
20
-70
10
0 -80
1 10 100 1 10 100 1000 10000
Input Frequency (kHz) Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection
Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency.
0 0
-10 VDD = VREF = 5 V -10 VDD = VREF = 2.7 V
-20 FSAMPLE = 100 ksps -20 FSAMPLE = 50 ksps
-30 FINPUT = 9.985 kHz -30 FINPUT = 998.76 Hz
4096 points 4096 points
Amplitude (dB)
-40 -40
Amplitude (dB)
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000
Frequency (Hz) Frequency (Hz)
500 100
450 VREF = VDD V REF = VDD
90
All points at FCLK = 2 MHz, except All points at FCLK = 2 MHz except
400 80
at VREF = VDD = 2.5 V, FCLK = 1 MHz at V REF = VDD = 2.5 V, FCLK = 1 MHz
350 70
300
IDD (µA)
60
IREF (µA)
250 50
200 40
150 30
100 20
50 10
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IREF vs. VDD.
400 100
90 VDD = VREF = 5 V
350
80
300
VDD = VREF = 5 V 70
250
IREF (µA)
60
IDD (µA)
200 50
VDD = VREF = 2.7 V
40
150 VDD = VREF = 2.7 V
30
100
20
50 10
0 0
10 100 1000 10000 10 100 1000 10000
Clock Frequency (kHz) Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency.
400 100
VDD = VREF = 5 V VDD = VREF = 5 V
350 90
FCLK = 2 MHz FCLK = 2 MHz
80
300
70
250
IDD (µA)
IREF (µA)
60
200 50
VDD = VREF = 2.7 V 40
150
FCLK = 1 MHz VDD = VREF = 2.7 V
30
100 FCLK = 1 MHz
20
50
10
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature.
80 2.0
1.8
30 0.8
0.6
20
0.4
10 0.2
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100
VDD (V) Temperature (°C)
FIGURE 2-37: IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage
Current vs. Temperature.
100.00
VDD = VREF = CS = 5 V
10.00
IDDS (nA)
1.00
0.10
0.01
-50 -25 0 25 50 75 100
Temperature (°C)
VDD
Sampling
Switch
VT = 0.6V
RSS CHx SS RS = 1 kΩ
C SAMPLE
VA CPIN ILEAKAGE
VT = 0.6V = DAC capacitance
7 pF ±1 nA = 20 pF
VSS
Legend
VA = Signal Source Ileakage = Leakage Current At The Pin
Due To Various Junctions
Rss = Source Impedance SS = Sampling switch
CHx = Input Channel Pad Rs = Sampling switch resistor
Cpin = Input Pin Capacitance Csample = Sample/hold capacitance
Vt = Threshold Voltage
2.5
V DD = 5 V
Clock Frequency (MHz)
2.0
1.5
1.0
VDD = 2.7 V
0.5
0.0
100 1000 10000
tCYC tCYC
tCSH
CS
tSUCS
CLK
SGL/
DIN Start DIFF D2 D1 D0 Don’t Care Start SGL/
DIFF D2
tSAMPLE tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB
first data, followed by zeros indefinitely (see Figure 5-2 below).
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
tCYC
tCSH
CS
tSUCS
Power Down
CLK
Start
DIN D2 D1 D0 Don’t Care
SGL/
DIFF
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely.
** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a
high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
CS
MCU latches data from A/D
converter on rising edges of SCLK
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
HI-Z NULL
DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Start
MCU Transmitted Data Bit
(Aligned with falling 0 0 0 0 SGL/
SGL/ D2
0 1 DIFF D1 DO X X X X X X X X X
edge of clock) DIFF D2 D1 DO X X X X X
MCU Received Data
(Aligned with rising ? ?
? ?
? ?
? 0
0 B11 B10 B9 B8 B7 B6
B6 B5
B5 B4
B4 B3
B3 B2
B2 B1
B1 B0
B0
(Null) B11 B10 B9 B8 B7
? ? ? ? ? ? ?
edge of clock)
Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits
FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Data is clocked out of A/D
converter on falling edges
SGL/
DIN D2 D1 DO Don’t Care
Start DIFF
HI-Z NULL
DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Start
MCU Transmitted Data Bit
(Aligned with falling 0 0 0 0 0 1 SGL/
edge of clock) DIFF D2 D1 DO X X X X X X X X X X X X X X
Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits
FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
VDD
10 µF
4.096V
Reference
0.1 µF 1 µF
MCP1541
1 µF
IN+ VREF
MCP3204
C1 IN-
R1 MCP601
VIN +
R2
-
C2
R4
R3
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing
filter for the signal being converted by the MCP3204.
DGND AGND
0.1 µF
Device 3
XXXXXXXXXXXXXX MCP3204-B
XXXXXXXXXXXXXX I/P
YYWWNNN YYWWNNN
XXXXXXXXXXX MCP3204-B
XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN YYWWNNN
XXXXXXXX 3204-C
YYWW IYWW
NNN NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office.
XXXXXXXXXXXXXX MCP3208-B
XXXXXXXXXXXXXX I/P
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XXXXXXXXXXXXX MCP3208-B
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YYWWNNN IYWWNNN
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08/01/02