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PROPOGATION DELAY

EC6601 – VLSI DESIGN

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• In most design there will be a number of paths
that require attention to timing details called
critical path

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• In most design there will be a number of paths
that require attention to timing details called
critical path

1
1
0

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• In most design there will be a number of paths
that require attention to timing details called
critical path

1
2ns
1
0 2ns

1 2ns

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• The critical paths can be affected at four levels

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• The critical paths can be affected at four levels
• Architectural Level
- how many gate delays
- how fast addition occurs
- how fast memories are accessed
and
- how long the signals take to
propagate along a wire
S.Shanmuga Raju | AP-ECE| DR NGP IT |
DELAY ESTIMATION
• The critical paths can be affected at four levels
• Architectural Level
• Logic level
- types of function blocks
- number of stages of gates
- fan-in and fan-out of the gates

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• The critical paths can be affected at four levels
• Architectural Level
• Logic level
• Circuit level
- transistor sizes
- other styles of CMOS logic

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• The critical paths can be affected at four levels
• Architectural Level
• Logic level
• Circuit level
• Layout level
- Floorplanning

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION
• The critical paths can be affected at four levels
• Architectural Level
• Logic level
• Circuit level
• Layout level

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION
• Rise time tr
- time for a waveform to rise from 20% to
80% of its steady state value

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION
• Rise time tr

• Fall time tf
- time for a waveform to fall from 80% to 20%
of its steady state value

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION
• Rise time tr

• Fall time tf

• Edge Rate trf


trf = (tr + tf)/2

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION

• Propagation delay time tpd


- maximum time from the input
crossing 50% to the output crossing 50%

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION
• Propagation delay time tpd

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION

• Propagation delay time tpd

• Contamination delay time tcd


- minimum time from the input
crossing 50% to the output crossing 50%

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY - DEFINITION
• Rise time tr

• Fall time tf

• Edge Rate trf

• Propagation delay time tpd

• Contamination delay time tcd

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DELAY ESTIMATION

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
𝜌𝐿
• Resistance 𝑅 =
𝐴

• Area A = D x W

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
• For NMOS of width W = 1unit, the effective
resistance
Reff = 1R

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
• For PMOS of width W = 1unit, the effective
resistance
Reff = 2R

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
• What should be the width of PMOS and
NMOS to have resistance R for both transistors

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
• What should be the width of PMOS and
NMOS to have resistance R for both transistors

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE
• Find the transistor width of a 2-input NAND
gate to achieve effective rise and fall
resistance equal to that of a unit inverter.

S.Shanmuga Raju | AP-ECE| DR NGP IT |


EFFECTIVE RESISTANCE

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DIFFUSION CAPACITANCE

S.Shanmuga Raju | AP-ECE| DR NGP IT |


DIFFUSION CAPACITANCE

S.Shanmuga Raju | AP-ECE| DR NGP IT |