IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.

6, JUNE 2011 1075

A Distributed Filter Within a Switching Converter for

Application to 3-D Integrated Circuits
Jonathan Rosenfeld and Eby G. Friedman, Fellow, IEEE

Abstract—A design methodology for distributing a buck con-

verter filter for application to 3-D circuits is described. The 3-D
filter exploits transmission line properties, permitting the genera-
tion and distribution of power supplies to different planes. As com-
pared to a conventional LC filter, the proposed filter only requires
on-chip capacitors without the use of on-chip inductors. Addition-
ally, the physical structure of the filter simultaneously enables the
distribution of the current to the load while filtering the switching
signal at the input. A case study in a 0.18- m CMOS 3-D tech-
nology demonstrates the generation of a 1.2 V power supply deliv-
ering 700 mA peak current.
Index Terms—3-D integrated circuits, dc-dc buck converters,
distributed filters.

I. INTRODUCTION

N THE ERA of rapid technology scaling, the performance

I and reliability of integrated circuits (IC) have reached limits
that are difficult to surpass. As a result, novel design methodolo-
Fig. 1. 3-D circuit with multiple power supplies.

gies for high performance, high complexity ICs are required.
3-D nanoscale technology can provide the required characteris-
tics of future state-of-the-art integrated systems. With 3-D cir-
cuits [1], new design challenges arise. One primary requirement
of 3-D integrated systems is diverse, high quality, and reliable
power [2]. This fundamental issue of power generation and dis-
tribution in 3-D circuits is explored in this paper.
3-D integrated circuits are comprised of multiple planes with
many circuit domains. The different planes are typically ded-
icated to a specific function, forming a highly heterogeneous
system [1], [3], [4]. As an example, RF, analog, communi-
cations, and digital circuits are typically located on different
planes, requiring several power supply voltages, as illustrated
in Fig. 1. In this example, , , , and are
generated from the primary power supply . distributed filter produces the target transfer function, passing
Multiple circuit domains require several power supplies to
reliably operate and provide sufficient and stable current. To
provide circuit domains with the appropriate power supplies,
dc-dc converters are distributed across each plane [5] as it is
often impractical to provide external power supplies due to the
Manuscript received April 21, 2009; revised October 07, 2009. First pub-
lished April 26, 2010; current version published May 25, 2011. This work was
supported in part by the National Science Foundation under Contract CCF-
0541206, CCF-0811317, and CCF-0829915, grants from the New York State
Office of Science, Technology & Academic Research to the Center for Ad-
vanced Technology in Electronic Imaging Systems, and by grants from Intel
Corporation, Eastman Kodak Company, and Freescale Semiconductor Corpo-
ration.
J. Rosenfeld and E. G. Friedman are with the Department of Electrical and
Computer Engineering, University of Rochester, Rochester, NY 14627 USA
(e-mail: rosenfeld.jonathan@gmail.com).
Digital Object Identifier 10.1109/TVLSI.2010.2045601
1063-8210/$26.00 © 2010 IEEE
limited number of input pins. Moreover, planes located far from
the faces of the 3-D cube require a large number of expensive
3-D vias to distribute the power supply across the plane.
To alleviate these difficulties, dc-dc converters are distributed
on-chip, generating a specific voltage required by the different
circuit blocks within each plane of a 3-D system. A suitable
dc-dc converter for low power applications is a buck converter
[5], [6]. A buck converter generates an output supply voltage
smaller than the input supply voltage [5].
The filter portion of a buck converter to generate and
distribute power supplies in 3-D integrated circuits is the pri-
mary focus of this paper. The proposed filter is comprised of
on-chip interconnects and capacitors, eliminating the need for
an on-chip inductor [7]. For a specific dc voltage ripple, the
the dc component of the input signal while attenuating the high
frequency harmonics.
This paper is organized into five sections. Background on
the operation of a conventional buck converter is reviewed in
Section II. In Section III, a methodology for designing these cir-
cuits is described. To exemplify the proposed approach, a case
study is described in Section IV, while a performance analysis
of the distributed filter is presented in Section V. Some conclu-
sions are offered in Section VI.
II. BACKGROUND
A standard topology of a buck converter for high performance
microprocessors is depicted in Fig. 2(a) [5]. The power MOS-
FETs produce an ac signal at node A by a signal controlled by
a pulse width modulator (PWM) [8], [9], as shown in Fig. 2(b).
1076 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011
Fig. 2. Conventional dc-dc converter: (a) buck converter circuit [5] and (b)
signal at the output of the power MOSFETs (node A).
The ac signal at node A is filtered by a filter composed of a
second-order low pass band LC filter. Assuming the resonance
frequency is less than the switching frequency of the
power MOSFETs, the filter only passes the dc component of the
signal and a residue composed of the high frequency harmonics.
The dc component of the signal shown in Fig. 2(b) is
(1)
where , , and are the duty cycle, time period, and
input power supply, respectively, and and are the rise
and fall times, respectively, of the switching signal produced by
the PWM circuit. In the case of , (1) reduces to
(2)
Hence, the buck converter produces an output voltage at
node B equal to . compared to a lumped LC filter, consider the transfer function
The power transistors are typically large in physical size and
are therefore driven by tapered buffers [10]. These buffers are
controlled by the PWM circuit. The feedback PWM circuit
senses the output voltage supply at node B and modifies
the control signal to ensure that the appropriate duty cycle
is produced at node A. In this manner, the output voltage is
maintained at the desired value while compensating for vari-
ations in the load current and input voltage. The performance
and functionality of the different circuit domains under load
current and dc input voltage variations are dependent upon the
maximum voltage fluctuations generated by the buck converter,
which is therefore regulated to provide the target voltage [5].
The performance of a buck converter can be improved by in-
tegrating these converters on-chip. In this manner, the parasitic
losses associated with the interconnects among the noninte-
grated components of the dc-dc converter are significantly
decreased. Moreover, integrated converters benefit by advances
in on-chip technologies and high operating frequencies. Mono-
lithic fully integrated dc-dc converters can therefore achieve
higher efficiency as compared to nonintegrated converters
[11]–[14].
Integrating dc-dc converters on-chip in both 2-D and 3-D
technologies, however, imposes challenges as the on-chip inte-
gration of large inductive and capacitive elements is problem-
atic. A significant issue is the poor parasitic impedance charac-
teristics exhibited by the on-chip inductors [15], [16], which de-
grades the performance of the on-chip converter. To improve the
quality factor of a 2 nH inductor and reduce the ripple current
within the inductors, magnetic coupling between two on-chip
inductors has been used in a dc-dc converter [17]. Although
the size and magnitude of the on-chip inductors and capacitors
required to implement a buck converter are reduced with in-
creasing switching frequency, the on-chip passive devices com-
prising the filter are large and cannot be practically integrated in
the megahertz frequency regime [18]–[20].
A 3-D technology provides several advantages as compared
to a 2-D technology. When the on-chip capacitors used by a
distributed filter are implemented with active devices, less met-
allization resources are required to connect these capacitors to
different sections of the filter as compared to a 2-D technology.
Since in 3-D circuits each plane has a dedicated active device
layer, routing congestion is reduced due to the smaller distance
between the interconnect and the corresponding capacitor. Also,
in a 2-D technology, the input power supply to the power MOS-
FETs (which are located within the substrate) is connected by
the lowest metal layers, therefore, additional routing resources
are required.
In a 3-D technology, the plane closest to the input power
supply accommodates the power MOSFETs, saving metalliza-
tion resources. The capacitance and inductance of the through
silicon vias are exploited, reducing the required length of the
interconnects and the size of the capacitors. An inherent benefit
of utilizing the proposed filter in 3-D systems is that the genera-
tion and distribution of the power supply occur simultaneously,
while in a 2-D technology, the filter is only used to generate the
power supply.
To obtain insight into the operation of a distributed filter as
of two types of filters, as depicted in Fig. 3. A second-order low
pass LC filter is used in a typical conventional dc-dc converter.
When the effective output resistance of the power MOSFETs
as well as the effective series resistance of the inductor are in-
cluded, two poles at different frequencies are formed, resulting
in a roll-off slope of 20 dB/decade in the megahertz and 40
dB/decade in the gigahertz frequency range. The frequency be-
havior of a distributed filter in the megahertz frequency range
is therefore similar to a lumped LC filter, as can be observed in
Fig. 3. When and the interconnect resistance are included in
the analysis, a pole in the megahertz frequency is formed, re-
sulting in a roll-off slope of 20 dB/decade. Note that in this
ROSENFELD AND FRIEDMAN: DISTRIBUTED FILTER WITHIN A SWITCHING CONVERTER
Fig. 3. Transfer functions of LC and distributed filters.
Fig. 4. Distributed filter.
example, a sharp 100 dB/decade roll-off slope is formed in the
gigahertz frequency range, suppressing the high frequency har-
monics of the ac signal produced by the power MOSFETs. The
distributed nature of the proposed filter forms multiple poles at
approximately the same high frequency, resulting in a large neg-
ative slope.
III. DESIGN METHODOLOGY
A design methodology for a distributed buck converter is de-
scribed in this section. Design guidelines are provided based on
the expressions developed here. The physical structure of the
distributed filter as well as the current load characteristics are
described in Section III-A. In Section III-B, the transfer func-
tion of the filter is used to determine the condition that satisfies
a target power supply ripple while the efficiency and area of the
3-D filter are determined in Section III-C. Finally, design guide-
lines are described in Section III-D.
A. Physical Structure and Current Load Properties of a 3-D
Filter
The proposed distributed filter is depicted in Fig. 4. The filter
is driven by power MOSFETs [see Fig. 2(a)] which are modeled
as a voltage source followed by an effective resistance . are
1077
Fig. 5. Current load profile.
The voltage source is assumed to be periodic, as illustrated
in Fig. 2(b).
The filter is composed of transmission lines terminated with
lumped capacitances. The inter-plane structure is connected by
3-D vias. At the target plane , the load is represented by a pe-
riodic current load and a reference clock signal, as shown in
Fig. 5. Note that the current load characterizes the approximate
current profile of a specific circuit module on a plane. re-
mains at during clock low, providing dc current flow by the
power supply. As with a conventional buck converter, a feed-
back PWM circuit senses the output node of the filter and ad-
justs the duty cycle of the signal driving the power MOSFETs
[see Fig. 2(a)].
In 3-D circuits, the ability to deliver current is primarily lim-
ited by the 3-D vias. The maximum current that can be delivered
through a single 3-D via therefore determines the current mag-
nitude
(3)
where , , and are, respectively, the maximum
current density, cross-sectional area, and number of 3-D vias
on the same plane. Consequently, the maximum cross-sectional
area of the interconnects (see Fig. 4) distributing the current
within the different planes is
(4)
where is the maximum current density of the intercon-
nect.
In practical circuits, however, a significant amount of current
is sunk by the load. To satisfy this requirement, multiple struc-
tures , as depicted in Fig. 4, are connected in parallel, deliv-
ering amperes. In this case, the number of 3-D vias
within the filter on each plane is equal to the number of parallel
connected structures, . The effective resistance and in-
ductance per unit length of the interconnects and 3-D vias, as
well as the output resistance of the driver (see Fig. 4), are
times smaller. The capacitance per unit length of the intercon-
nects and 3-D vias, as well as the on-chip lumped capacitors,
times larger.
1078 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011

B. Transfer Function of a 3-D Filter
To characterize the impedance of the filter (between and
), the overall transfer function is determined based on the
ABCD matrices. Hence, the overall ABCD matrix of a filter
spanning planes is
(5)
where is the th harmonic of the signal. In the case of the
signal illustrated in Fig. 2(b) and assuming , the
fundamental harmonic (positive and negative) is
(12)
Equation (10) implies that the required amplitude of the transfer
function for a specific ripple voltage is

The right matrix in the right-hand side of (5) is

(13)

Once the current profile of a circuit is determined, the in-

terconnect length to , shown in Fig. 4, and the required
ripple voltage are chosen. Based on (7), the magnitude of
(6)
the transfer function at is plotted as a function of the ca-
pacitances to . The interconnect length and capacitance
where and are the characteristic impedance and propaga- are chosen to satisfy (13). Since these design expressions are
tion constant of the RLC interconnects, respectively, and complex and unsuitable for manual calculations, numerical
are the interconnect length and capacitance on the th plane, techniques are used.
respectively, and are the characteristic impedance and An important issue is the duty cycle of the signal driving the
propagation constant of the 3-D vias, respectively, and is the power MOSFETs (see Fig. 4) that produces the correct power
length of the 3-D via on the th plane. The transfer function of supply voltage. Note that in this case, the duty cycle determined
the filter is from (2) does not provide the proper dc voltage level. This be-
havior occurs since the signal at the input of a distributed filter
(7) is degraded by the resistance and the input impedance of the
filter , forming a voltage divider. To obtain the duty cycle
required for a specific dc voltage, consider the input impedance
where and are obtained from (5), and and are
of the filter at DC
the radian frequency of the clock and switching signals, respec-
tively.
Since a practical filter within a buck converter does not (14)
provide ideal low pass characteristics, the signal at node B,
shown in Fig. 2(a), carries a small amount of high frequency where , , , and are defined in (6), and is the dc
harmonics generated by the switching power MOSFETs. component of the current load
Hence, the voltage at node is
(15)
(8)
The dc component of the signal at the input of the filter (in-
where is the dc component of the output voltage described cluding in Fig. 4) is
by (1) and is the voltage ripple transferred by the non-
ideal characteristics of the filter. When only the fundamental
(16)
harmonic is passed, exhibits a sinusoidal behavior

(9)
To satisfy a target ripple voltage (peak-to-peak), the magni-
tude of the filter transfer function at the switching frequency
has to be below a specific value. To satisfy this objective, con-
sider the output signal in the frequency domain
the dc voltage transferred by the filter to the target plane. In (16),
is the duty cycle provided by the PWM feedback circuit
[see Fig. 2(a)]. Consequently, to achieve a specific dc voltage at
the output of the filter, the duty cycle in (2) is
(17)

(10) Observe from (17) that is always larger than the original
duty cycle obtained from (2), limiting the magnitude of the
The periodic input signal can be represented by a Fourier generated power supply. When the interconnects within the dis-
series tributed filter are resistive, approaches (no reflections
occur at the input). It is typically preferable to design the filter
(11) to ensure that is closer to to provide a large tuning
range for the PWM circuit.
ROSENFELD AND FRIEDMAN: DISTRIBUTED FILTER WITHIN A SWITCHING CONVERTER 1079

C. Efficiency and Area of a 3-D Filter

An important property of a buck converter is the power effi-
ciency. The efficiency of a distributed filter within a buck con-
verter is

(18)

where is the average power delivered to the load and

is the average power consumed by the filter. The power expres-
sions and are, respectively,

(19)

(20)

where is the root-mean-square value of the driving signal

with a duty cycle , and are, respectively Fig. 6. Required magnitude of the transfer function.

(21)
and a switching frequency 100 MHz. Consider the design
space of the filter, as shown in Fig. 7. The modified duty cycle
(22) , ratio between the duty cycle [see (2)] and ,
capacitance, and filter efficiency are depicted as a function of
The area occupied by a 3-D filter is the output dc voltage and series resistance (see Fig. 4). The
modified duty cycle is shown in Fig. 7(a). Observations
of Fig. 7(a) reveal that under the specified operating conditions,
this filter cannot convert 3.3 to 3 V since for all values of ,
(23) is greater than one. The feasible operation of the dis-
tributed filter is therefore limited to about 2.5 V.
where and are the area occupied by the on-chip ca-
To narrow the design space, recall that is always
pacitors and 3-D vias on the th plane, respectively.
greater than (see Section III-B). To permit a larger opera-
and are the width and spacing of the interconnects on the th
tional range of the feedback PWM circuit, should be
plane, respectively. As mentioned in Section III-A, and are,
chosen close to . A new design metric is therefore defined
respectively, the number of planes spanned by the filter and the
which is the ratio of to , as shown in Fig. 7(b).
number of parallel connected filter structures. The generation
This ratio should be as close to one as possible. As shown
and distribution of additional power supplies, as illustrated in
in Fig. 7(b), the ratio decreases as increases.
Fig. 1, requires the use of additional dc-dc converters and dis-
The lowest permissible ratio is chosen to be 0.5 to
tributed filters.
accommodate a tradeoff between the ratio and the
D. Design Guidelines filter efficiency.
As mentioned in the beginning of this subsection, less ca-
In order to provide a comprehensive perspective of the design
pacitance is required for lower conversion ratios, as shown in
space, several design parameters that affect the performance
Fig. 7(c). As expected, with a larger series resistance of the
of the distributed filter are investigated. To determine the re-
power MOSFETs , the required capacitance can be decreased
quired magnitude of the transfer function of the filter for dif-
to satisfy the target magnitude of the transfer function. Finally,
ferent output voltage ripples and dc voltages, consider Fig. 6.
the filter efficiency is shown in Fig. 7(d). The general
The output dc voltage ranges between 0.8 and 3 V (assuming
trend for all output DC voltages is that the filter efficiency in-
a 3.3 V input dc voltage), while the required voltage ripple
creases with higher , as evident from (18) and (20). From
ranges between 1% and 10%. As expected, the magnitude of
Figs. 7(b)–(d), the permissible range for is
the transfer function increases for higher voltage ripple, since a
larger amplitude of the dominant harmonic of the input signal
(24)
is permitted to pass. Furthermore, as the output dc voltage be-
comes larger, an increase in the transfer function is evident in
(10). Consequently, a lower capacitance and fewer resistive in- (25)
terconnects are required. Once the required output dc voltage is
chosen for a specific voltage ripple, permitting the target magni-
tude of the transfer function to be determined, the design space IV. CASE STUDY
of the distributed filter is specified. To demonstrate the design methodology described in
In this example, all of the interconnect lengths are 1 mm Section III, an example DC-DC converter based on the MIT
with a voltage ripple 5%, input dc voltage 3.3 V, Lincoln Lab (MITLL) 180 nm 3-D integration process [21],
1080 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011
Fig. 7. Design space of a distributed filter: (a) modified duty cycle as a function of R ; (b) duty cycle ratio as a function of R ; (c) capacitance as a function of
R ; (d) filter efficiency as a function of R .
[22] is described in this section. Since the ability to deliver
current is primarily limited by the 3-D via, characterization
of the maximum current that can flow through a single via is
described in Section IV-A. A distributed filter based on a 3-D
technology is described in Section IV-B and compared to an
implementation in a 2-D technology in Section IV-C. In order
to quantify the advantages of the proposed distributed filter as
compared to a conventional buck converter filter, a traditional
filter is described in Section IV-D for the same performance
requirements as a distributed filter. SPICE simulations are
performed based on the 3-D MITLL technology.
A. Current Load Characterization
The MITLL technology is a 0.18 m low power, fully de-
pleted silicon-on-insulator (FDSOI) CMOS process where three
independent wafers are physically bonded to form a 3-D inte-
grated structure. Each plane has three aluminum metallization
layers. In this technology, the maximum current density is [22]
3 mA
- (26)
m
Since the cross-sectional area of a 3-D via in this technology
is 1.5 1.5 m , the maximum current that can flow through a
single 3-D via, based on (3), is
7 mA (27)
In this case study, the current load waveform, depicted in Fig. 5,
has the following characteristics: 3 GHz, and and
are and , respectively.
B. Distributed 3-D Filter
To overcome the difficulty described in Subsection IV-D, a
distributed filter circuit has been developed that generates and
distributes the power supply to a target plane within a 3-D struc-
ture. This filter is described in this section. The resistance, in-
ductance, and capacitance per unit length of the interconnects
(Metal 3) and 3-D vias are extracted based on the predictive
technology model (PTM) [23]–[25], as listed in Table I. The
width of the interconnects is determined by the maximum cur-
rent density of the MITLL 3-D technology. Assuming that both
the interconnect and 3-D vias support the same current density
ROSENFELD AND FRIEDMAN: DISTRIBUTED FILTER WITHIN A SWITCHING CONVERTER
TABLE I
RLC INTERCONNECT (ALUMINUM) AND 3-D VIA IMPEDANCES
Fig. 8. Magnitude of the transfer function at ! for different line lengths and
capacitances.
of 3 mA m , the maximum cross-sectional area of the inter-
connect determined from (4) is 1.5 1.5 m . The thickness
of the interconnect for this technology is 630 nm, resulting in
an approximately 4 m wide line. Note that each 3-D via is
7.34 m long, connecting three planes, as illustrated in Fig. 4.
For the same performance requirements as a conventional
filter, the magnitude of the transfer function at for different
capacitances and interconnect lengths, assuming
and , is depicted in Fig. 8. An output
resistance of the power MOSFETs 7.36 is assumed in
this case study.
As the interconnect line length increases, less capacitance is
required, as evident in Fig. 8. To satisfy the required voltage
ripple, the target interconnect length in this example is 1 As mentioned in Section II, the distributed filter can also be
mm with a capacitance 42 pF. The dc voltage at the output
of the filter is shown in Fig. 9. The simulated ripple of the output
dc voltage is 52 mV (4.3% of the output dc voltage), satisfying
the design objective of a maximum 5% voltage ripple. In this
example, the required duty cycle of the signal driving the power
MOSFETs is , and the efficiency of the filter is
about 88%.
If additional current is required, the distributed filter can be
extended by connecting multiple structures in parallel. For ex-
ample, to enlarge this structure to produce 700 mA, 100 par-
allel structures are required. In this case, the effective resistance
and inductance per unit length, listed in Table I, and are
times smaller, while the capacitance per unit length is times
larger. The multiple parallel filters produce the same transfer
function magnitude, as shown in Fig. 8. The same interconnect
1081
Fig. 9. DC voltage at the output of a distributed filter.
Fig. 10. Distributed filter in a 2-D technology.
lengths and capacitances are therefore chosen, producing a 1.2
volt power supply with 700 mA maximum current, resulting in
a total of 4.2 nF/plane. The interconnect network and the capac-
itors per plane occupy, in this example, about 0.42 mm .
C. Distributed Filter in a 2-D Technology
implemented in a 2-D technology, as shown in Fig. 10. In a 2-D
technology, the filter spans all metal layers down to the device
layer where conventional vias are used to connect the different
metal layers.
To provide an effective comparison to the 3-D case, a 180
nm 2-D TSMC technology with six copper metal layers is used.
Additionally, the width of all of the metal interconnects and the
output resistance of the driver are assumed to be 4 m and
7.36 , respectively, as in the 3-D case. The RLC parameters for
this technology are listed in Table II.
Following the same design methodology and performance
requirements as used for the 3-D case, the magnitude of the
transfer function at for different capacitances and intercon-
nect lengths, assuming
and , is depicted in
1082 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011
TABLE II
RLC INTERCONNECT (COPPER) IMPEDANCES IN A 2-D TECHNOLOGY
Fig. 11. Magnitude of the transfer function at ! for different line lengths and
capacitances in a 2-D technology.
TABLE III
PERFORMANCE COMPARISON OF THE DISTRIBUTED FILTER IMPLEMENTED IN A
2-D AND 3-D TECHNOLOGY
Fig. 11. To ensure a proper comparison with the 3-D case, the
interconnect length in this example is also 1 mm, resulting
in a capacitance 2 nF (see Fig. 11). The total on-chip ca-
pacitance in the 2-D case is therefore 12 nF. The re-
quired duty cycle of the signal driving the power MOSFETs is
, and the efficiency of the filter is about 88%.
The area occupied by this filter is about 12.25 mm .
A comparison of the filter implemented in a 2-D and 3-D tech-
nology is provided in Table III. Note that the 3-D implementa-
tion exhibits better characteristics due to several reasons. The
on-chip capacitance density is ten times larger in a 3-D tech-
nology, translating into a larger area occupied by the filter in a
2-D technology. Additionally, in the 3-D technology, the capac-
itance is distributed among the three planes. Furthermore, the
capacitance required in the 2-D technology is 2.85 larger than
the capacitance in the 3-D case.
The requirement for on-chip capacitance in the 2-D tech-
nology increases due to the following rationale. The cutoff
frequency of the distributed low pass filter is proportional
to , where is the total resistance of the
filter interconnects and is the total on-chip capac-
itance connected to the interconnects on different planes,
(see Fig. 4). To maintain the same cutoff
frequency as in the 3-D case and since is lower in the 2-D
case, the requirement for increases (in this example, by
2.85). The resistance in the 2-D case is lower as compared
to the 3-D technology since in the 2-D technology, copper
interconnects are used while aluminum interconnects are used
in the 3-D technology.
Finally, the efficiency of the filter in both cases is approxi-
mately the same (88%). Summarizing, the distributed filter re-
quires significantly less total area when implemented within a
3-D technology as compared to a 2-D technology (in this ex-
ample, 30 times less, as inferred from Table III).
D. Conventional Filter
A conventional buck converter filter is composed of a second
order low pass LC filter, as shown in Fig. 2(a). Assuming the
inductor and capacitor exhibit ideal characteristics, the transfer
function of the LC filter is
(28)
where , , and are the effective output resistance of the
power MOSFETs and the inductor and capacitor of the conven-
tional filter, respectively.
In this example, a practical 2 nH on-chip inductor is used,
based on the characterization in [17]. This inductor has been
designed in a 130-nm CMOS technology, conducting 130 mA
maximum current, with 75 m line width and 600 m diam-
eter. In order to conduct 700 mA, five 2 nH inductors are con-
nected in parallel, resulting in 0.4 pH total inductance. The dc-dc
conversion is from 3.3 to 1.2 V ( ) at a switching
frequency 100 MHz. The effective output resistance of
the power MOSFETs in a 0.18- m CMOS technology deliv-
ering 700 mA is 7.36 . To achieve 5% (
peak-to-peak) ripple voltage, the magnitude of the transfer func-
tion at 100 MHz according to (13) is 0.016. To satisfy these re-
quirements, the corner frequency of an LC low pass filter, i.e.,
the resonant frequency, should be about one decade less than .
This condition results in 20 nF and five 0.4 pH in-
ductors. Note that for these performance requirements, signifi-
cant area is required. The inductors and capacitor occupy about
4 mm as compared to 0.42 mm per plane occupied by the dis-
tributed filter.
V. PERFORMANCE ANALYSIS
To obtain deeper insight into the performance characteristics
of the proposed filter, an analysis over a wide range of design
parameters is presented in this section. In all cases, the filter is
designed to satisfy less than 5% voltage ripple with an input
3.3 dc voltage. In the simulation of a 3-D filter, the parameters
and structure presented in the case study discussed in Section IV
are assumed.
To place these results in the context of a conventional filter,
the inductor and capacitor values as a function of switching fre-
quency for different current loads are illustrated in Fig. 12. As
ROSENFELD AND FRIEDMAN: DISTRIBUTED FILTER WITHIN A SWITCHING CONVERTER
Fig. 12. Conventional LC filter: (a) capacitance and (b) inductance.
expected, the magnitude of the lumped inductor and capacitor
decreases as the switching frequency increases. However, in the
megahertz frequency region, the magnitude of the capacitor is
between 100 pF and 100 nF, while the magnitude of the inductor
is between 60 nH and 10 H. In current technologies, these large
inductors cannot be implemented on-chip. When the switching
frequency is increased to gigahertz frequencies, the magnitude
of the on-chip inductor becomes realizable on-chip. Note that in
this case, the current load is assumed to only affect the output
resistance of the power MOSFETs. Therefore, at higher current
loads (above 100 mA), insignificant changes in the magnitude
of the capacitance and inductance can be observed in Fig. 12.
The efficiency, total capacitance, and area per plane of the
distributed filter as a function of switching frequency for dif-
ferent current loads are shown in Fig. 13. At a 1 MHz switching
frequency, the efficiency of the filter reaches 80%. At higher fre-
quencies, the efficiency is significantly greater, reaching 98% at
500 MHz, 1 GHz, and 3 GHz. Since only the filter efficiency is
considered, excluding the power MOSFETs, the efficiency at the
higher frequencies is dependent on the input impedance of the
distributed filter which does not change significantly at higher
frequencies. The input impedance remains approximately the
same at higher frequencies since the capacitors to of
the distributed filter contribute less to the input impedance. As
expected, the total capacitance and area occupied by the dis-
tributed filter decreases as the frequency increases. This be-
1083
Fig. 13. 3-D distributed filter: (a) efficiency, (b) total capacitance per plane,
and (c) total area per plane.
havior occurs since less capacitance and shorter interconnects
are required at higher frequencies to satisfy the target voltage
ripple.
As shown in Fig. 12(b), the magnitude of the required in-
ductor within an LC filter varies between 50 and 10 000 nH for
switching frequencies up to 1 GHz. The large range of induc-
tance is attributed to the wide range of switching frequencies,
i.e., 1 MHz to 1 GHz. At 3 GHz, the required inductor is less than
10 nH. This characteristic implies that at switching frequencies
used in current technologies, i.e., up to several megahertz [26],
a conventional LC filter cannot be implemented on-chip.
To evaluate the capability of providing a wide voltage con-
version range, as required in 3-D circuits, the proposed method-
ology is compared to three on-chip converters [17], [27], [28],
as shown in Fig. 14. The proposed converter in this example
1084 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011
Fig. 14. Comparison of power efficiency.
distributes 200 mA maximum current. As evident from Fig. 14,
the power efficiency of the proposed converter is greater than
the other converters. A primary reason for the superior power
efficiency is that the proposed converter eliminates the need for
an on-chip inductor and any associated losses.
VI. CONCLUSION
Integrating dc-dc converters on-chip can significantly en-
hance the performance and reliability of integrated circuits.
Conventional filters, however, are difficult to integrate due to
the large magnitude of the on-chip inductors and capacitors.
A distributed buck converter filter for application to three-di-
mensional circuits is proposed in this paper. By exploiting
the low pass bandwidth properties of transmission lines, si-
multaneously generating and distributing power supplies to
different planes is possible. An example converter based on the
MITLL 3-D CMOS technology is described, demonstrating a
dc-dc converter that can generate a 1.2 V power supply while
delivering 700 mA.
A performance analysis considering the filter efficiency,
total capacitance, and physical area is performed for a wide
range of switching frequencies and current loads. A conven-
tional on-chip LC filter in the megahertz frequency range
is not practical due to the large inductors. Alternatively, an
on-chip distributed filter can be implemented in the megahertz
frequency range, achieving high efficiency, suitable for 3-D
integration.
REFERENCES
[1] V. F. Pavlidis and E. G. Friedman, Three-Dimensional Integrated Cir-
cuit Design. San Mateo, CA: Morgan Kaufmann, 2009.
[2] J. Sun, D. Giuliano, S. Devarajan, J.-Q. Lu, T. P. Chow, and R. J. Gut-
mann, “Fully monolithic cellular buck converter design for 3-D power
delivery,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17,
no. 3, pp. 447–451, Mar. 2009.
[3] R. G. Gutmann, J. Q. Lu, Y. Kwon, J. F. McDonald, and T. S. Cale,
“Three-dimensional ICs: A technology platform for integrated systems
and opportunities for new polymeric adhesives,” in Proc. IEEE Int.
Conf. Polymers Adhesives Microelectron. Photon., Oct. 2001, pp.
173–180.
[4] C. S. Tan, R. J. Gutmann, and L. R. Reif, Wafer Level 3-D ICs Process
Technology. New York: Springer, 2008.
[5] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design.
New York: Wiley, 2006.
[6] R. W. Erickson and D. Maksimovic, Fundamentals of Power Elec-
tronics. Norwell, MA: Kluwer, 2001.
[7] J. Rosenfeld and E. G. Friedman, “On-chip DC-DC converters for
three-dimensional ICs,” in Proc. IEEE Int. Symp. Quality Electron.
Des., Mar. 2009, pp. 759–764.
[8] H. Kim, H.-J. Kim, and W.-S. Chung, “Pulsewidth modulation circuits
using CMOS OTAs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54,
no. 9, pp. 1869–1878, Sep. 2007.
[9] B. Sahu and G. A. Rincon, “An accurate, low-voltage, CMOS
switching power supply with adaptive on-time pulse-frequency modu-
lation (PFM) control,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.
54, no. 2, pp. 312–321, Feb. 2007.
[10] B. S. Cherkauer and E. G. Friedman, “A unified design methodology
for CMOS tapered buffers,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 3, no. 1, pp. 99–111, Mar. 1995.
[11] R. S. Kagan and M. Chi, “Improving power supply efficiency with
mosfet synchronous rectifiers,” in Proc. IEEE Int. Conf. Polymers Ad-
hesives Microelectron. Photon., Jul. 1982, pp. D4.1–D4.9.
[12] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Low-
voltage-swing monolithic DC-DC conversion,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 51, no. 5, pp. 241–248, May 2004.
[13] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Cascode
monolithic DC-DC converters for reliable operation at high input
voltages,” Analog Integr. Circuits Signal Process., vol. 42, no. 3, pp.
231–238, May 2005.
[14] V. Kursun, V. K. De, E. G. Friedman, and S. G. Narendra, “Mono-
lithic voltage conversion in low-voltage CMOS technologies,” Micro-
electron. J., vol. 36, no. 9, pp. 863–867, May 2005.
[15] A. M. Niknejad and R. G. Meyer, “Analysis design, and optimization
of spiral inductors and transformers for Si RF ICs,” IEEE J. Solid-State
Circuits, vol. 33, no. 10, pp. 1470–1481, Oct. 1998.
[16] W.-Z. Chen, W.-H. Chen, and K.-C. Hsu, “Three-dimensional fully
symmetric inductors, transformer, and Balun in CMOS technology,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 7, pp. 1413–1423,
Jul. 2007.
[17] J. Wibben and R. Harjani, “A high-efficiency DC-DC converter using
2 nH integrated inductors,” IEEE J. Solid-State Circuits, vol. 43, no. 4,
pp. 844–854, Apr. 2008.
[18] T. Karnik et al., “High-frequency DC-DC conversion: Fact or fiction,”
in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 245–248.
[19] T. Suetsugu and M. K. Kazimierczuk, “Integration of class DE inverter
for on-chip DC-DC power supplies,” in Proc. IEEE Int. Symp. Circuits
Syst., May 2006, pp. 3133–3136.
[20] P. Hazucha, G. Schrom, H. Jaehong, B. A. Bloechel, P. Hack, G. E.
Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar, “
A 233-MHz 80%–87% efficient four-phase DC-DC converter utilizing
air-core inductors on package,” IEEE J. Solid-State Circuits, vol. 40,
no. 4, pp. 838–845, Apr. 2005.
[21] MIT Lincoln Laboratories, Cambridge, “MITLL low-power FDSOI
CMOS process application notes,” 2006.
[22] MIT Lincoln Laboratories, Cambridge, “MITLL low-power FDSOI
CMOS process design guide,” 2006.
[23] Nanoscale Integration and Modeling Group, Arizona State Univ.,
Tempe, “Predictive technology model,” [Online]. Available:
http://www.eas.asu.edu/~ptm
[24] I. Savidis and E. G. Friedman, “Electrical characterization and mod-
eling of 3-D vias,” in Proc. IEEE Int. Symp. Circuits Syst., May 2008,
pp. 784–787.
[25] I. Savidis and E. G. Friedman, “Closed-form expressions of 3-D via re-
sistance, inductance, and capacitance,” IEEE Trans. Electron Devices,
vol. 56, no. 9, pp. 1873–1881, Sep. 2009.
[26] R. W. Erickson and D. Maksimovic, Fundamentals of Power Elec-
tronics. New York: Springer, 2004.
[27] G. Patounakis, Y. W. Li, and K. L. Shepard, “A fully integrated on-chip
DC-DC conversion and power management system,” IEEE J. Solid-
State Circuits, vol. 39, no. 3, pp. 443–452, Mar. 2004.
[28] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan,
and S. Borkar, “Area-efficient linear regulator with ultra-fast load
regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940,
Apr. 2005.
ROSENFELD AND FRIEDMAN: DISTRIBUTED FILTER WITHIN A SWITCHING CONVERTER
Jonathan Rosenfeld received the B.S. degree in
mechanical engineering from Technion—Israel
Institute of Technology, Haifa, Israel, in 1999, the
Bachelors of Technology degree (with honors) in
electronic engineering from Ort-Braude College,
Karmiel, Israel, in 2003, and the M.S. and Ph.D.
degrees in electrical and computer engineering from
the University of Rochester, Rochester, NY, in 2005
and 2009, respectfully.
He was an intern with Intrinsix Corporation, Fair-
port, NY, in 2005, where he designed Gm-C circuits
for 61-modulator ADC for FM tuner. In 2007, he was an intern with Eastman
Kodak Company, Rochester, NY, where he developed column-based multiple
ramp integrated ADC for CMOS image sensors. His research interests include
the areas of interconnect design, resonant clock and data distribution networks,
on-chip DC-DC converters, 3-D circuits, and the design of analog and mixed-
signal integrated circuits.
1085
Eby G. Friedman (F’00) received the B.S. degree
from Lafayette College, Easton, PA, in 1979, and the
M.S. and Ph.D. degrees from the University of Cal-
ifornia, Irvine, in 1981 and 1989, respectively, all in
electrical engineering.
From 1979 to 1991, he was with Hughes Aircraft
Company, rising to the position of manager of the
Signal Processing Design and Test Department, re-
sponsible for the design and test of high performance
digital and analog IC’s. He has been with the Depart-
ment of Electrical and Computer Engineering, Uni-
versity of Rochester, Rochester, NY, since 1991, where he is a Distinguished
Professor. He is also a Visiting Professor at the Technion-Israel Institute of
Technology, Haifa, Israel. His current research and teaching interests include
high performance synchronous digital and mixed-signal microelectronic design
and analysis with application to high speed portable processors and low power
wireless communications. He is the author of almost 400 papers and book chap-
ters, several patents, and the author or editor of 13 books in the fields of high
speed and low power CMOS design techniques, high speed interconnect, and the
theory and application of synchronous clock and power distribution networks.
Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems
and Computers, Chair of the IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS steering committee, and a Member of several
editorial boards and conference technical program committees. He previously
was the Editor-in-Chief of the IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS, a Member of the editorial board of the
PROCEEDINGS OF THE IEEE, a Member of the Circuits and Systems (CAS)
Society Board of Governors, Program and Technical chair of several IEEE
conferences. He was a recipient of the University of Rochester Graduate
Teaching Award, and the College of Engineering Teaching Excellence Award.
He is a Senior Fulbright Fellow.