Clock Gating and Associated Timing

Checks
Product Version Genus 17.1
November, 2017
Copyright Statement

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
 Clock Gating and Associated Timing Checks

Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Overview...................................................................................................................... 4
Defining Terminologies ................................................................................................ 6
Conditions for the Clock-gating Checks to be Inferred................................................. 7
Setup and Hold Checks ............................................................................................... 8
Case Studies ............................................................................................................... 9
Recommendations ..................................................................................................... 15
Support ...................................................................................................................... 17
Feedback ................................................................................................................... 17

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 3
 Clock Gating and Associated Timing Checks

Purpose
This application note explains the following:

1. What is clock gating?

2. What are clock-gating timing checks?

3. Recommendations

Audience
This document is intended for Design Engineers who are involved in the timing closure
of digital designs and want to understand clock-gating timing checks.

Overview
Clock nets toggle the most and drive large clock tree structures. Hence, switching in
clock nets can cause up to 50 percent or more of dynamic power dissipation.

The best way to reduce dynamic power dissipation is to turn the clock off when not
required. The technique of turning the clock off is called clock gating.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 4
 Clock Gating and Associated Timing Checks

The following figure shows a common example of a circuit for which the synthesis tool
would employ the clock-gating technique:

It has been observed that clock gates, when placed early in the clock tree structure, can
save a lot of power.

By default, Genus requires the register bus to be a minimum of 3-bit wide to employ
clock-gating structures on the clock network. It has been observed that clock gating on
a single-bit register is not area- and power-efficient.

The clock gate checks ensure that a glitch-free and unclipped clock passes through the
clock-gating structure. The clock gate checks consist of the clock gate setup checks and
clock gate hold checks. To understand these checks, you need to be familiar with
certain terms, which are explained in the next section.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 5
 Clock Gating and Associated Timing Checks

Defining Terminologies
1. Gating signal: This signal, when active, will turn the clock off.

2. Dominant or controlling state of the clock: This is the state or level of the clock
signal at which the output is controlled only by the clock signal, and is not
affected by the state of the gating signal. Hence, the clock dominates the gating
signal.

For AND, NAND clock-gating cells, the dominant state of the clock signal will be
state ‘0’. This is because the output of AND, NAND gates will not depend on the
gating signal when the clock is at state 0.

For OR, NOR gates, the controlling state of the clock will be state ‘1’.

Genus will be able to identify the dominant state from the gating cell the clock
signal drives. If the non-controlling state specified by
“set_clock_gating_check” differs from the functionality of the clock-gating
cell, Genus will flag a warning.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 6
 Clock Gating and Associated Timing Checks

Conditions for the Clock-gating Checks to be Inferred

Genus only does clock-gating setup checks. Genus will infer clock-gating setup checks
on the clock-gating cells that are either instantiated by Genus during synthesis or are
recognized by Genus as clock-gating cells.

1. Genus can be made to recognize user-defined custom cells using the

“lp_clock_gating_module” attribute.

2. Genus can be made to recognize the clock-gating cells that were either manually
inserted or inserted by a third-party tool using the “clock gating import”
command. This command will return the total number of CG instances imported.

Currently, the Genus-LP engine recognizes the following structures as clock-

gating instances:

A. Two-input AND or NAND gates that have a clock signal driving one of the
inputs. In this case, the other pin is assumed to be the enable pin.

Note: If the other pin is a part of the test network, the Genus-LP engine
will not recognize the gate as a clock-gating instance.

B. Integrated clock-gating cells

Currently, the Genus-LP engine does not recognize these structures as CG

instances, if they were defined in a separate module that is instantiated in the
netlist.

Genus will recognize a cell as a clock-gating cell with the “clock_gating

import” command if:

A. A clock pin or a primary output port exists in the transitive fanout of the
clock gate. The tool can do tracing through pad cells.

B. The gating signal is not a clock.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 7
 Clock Gating and Associated Timing Checks

Setup and Hold Checks

Setup Check: This check is performed with respect to the edge of the clock that
transforms the state of the clock signal from controlling state to non-controlling state.

Hold Check: This check is performed with respect to the edge of the clock that
transforms the state of the clock signal from non-controlling to controlling state.

The following figure shows the setup and hold check for ‘AND, NAND’ type gating cell.

If the data changes during the non-controlling state, it will lead to clipping of the clock as
shown in the following image:

Data

Gated CLK

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 8
 Clock Gating and Associated Timing Checks

Case Studies
Example 1
Consider the following definitions in the SDC:

create_clock -name CLK1 -period 4 -waveform {0 2} [get_ports CLK1]

create_clock -name CLK2 -period 4 -waveform {0 2} [get_ports CLK2]

Setup check: The output of flip flop ‘FF1’ registered at 0ns should reach pin ‘in1’ of
‘Gating cell’ prior to 4- ns.

Genus will optimize the path from flop FF1 to the gating cell such that this constraint is
met.

Hold check: The output of flip flop ‘FF1’ registered at 0ns should reach pin ‘in1’ of
‘Gating cell’ at or after 2+ ns. The PnR tool will add buffers in the clock path to meet this
requirement.

Hence, it is required that the gating signal should reach the gating cell between the time
frame of “2ns-4ns”.

In this example, if flip flop ‘FF1’ is a negative-edge-triggered flip flop, the hold check
requirement will be met as shown in the following example. However, meeting the setup
requirement will become stringent for Genus with such a design because the output of
the flip flop will now have only half the clock cycle to reach the gating signal.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 9
 Clock Gating and Associated Timing Checks

Example 2
Consider the following definitions in the SDC:

create_clock [get_ports clk1] -name clk1 -period 8 -waveform {0 4}

create_clock [get_ports clk2] -name clk2 -period 4 -waveform {0 2}

In this example, the “enable” is clocked by a slow clock with a time period of 8ns. The
destination flop is clocked by a faster clock with a time period of 4ns.

Setup check: The output of flip flop ‘FF1’ registered at 0ns should reach pin ‘in1’ of
‘Gating cell’ prior to 4ns. Genus will optimize the path from flop FF1 to the gating cell to
meet this constraint.

Hold check: The output of flip flop ‘FF1’ registered at 0ns should reach pin ‘in1’ of
‘Gating cell’ at or after 2+ ns. The PnR tool will add buffers in the clock path to meet this
requirement.

Hence, it is required that the gating signal should reach the gating cell between the time
frame of “2ns-4ns”.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 10
 Clock Gating and Associated Timing Checks

Timing report from Genus

Here, the timing report is shown in pico seconds:

The capture time is 4000 ps.

The arrival time is 320 ps.

Hence, the setup check passes with a positive slack of 3680 ps.

Timing report from the PnR tool

The same path will fail the hold check because the “enable” will reach pin A of the clock
gate before 2ns. The backend tool will insert buffers to push the arrival of the signal in
the 2ns-4ns window.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 11
 Clock Gating and Associated Timing Checks

Example 3
In this example, the “enable” is clocked by a faster clock with a time period of 4ns. The
destination flop is clocked by a slow clock with a time period of 8ns.

create_clock [get_ports clk1] -name clk1 -period 4 -waveform {0 2}

create_clock [get_ports clk2] -name clk2 -period 8 -waveform {0 4}

Setup check: In this case, Genus will choose the most restrictive time to perform the
setup check. The output of flip flop ‘FF1’ registered at 4ns should reach pin ‘in1’ of the
gating cell prior to 8ns. Genus will optimize the path from flop FF1 to the gating cell
such that this constraint is met.

Timing report from RC

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 12
 Clock Gating and Associated Timing Checks

Timing report of the PnR tool (Hold check)

In this case, the backend tool will choose the most restrictive time to perform the hold
check. The output of flip flop ‘FF1’ registered at 0ns should reach pin ‘A’ of gating cell
“g8” after 4+ ns.

Important: A paradoxical situation arises here, because as soon as the backend tool
adds buffers to meet the hold-time constraint, the setup time will get violated. The delay
added to meet the hold time should sensitize pin A of instance g8 at 4+ns, and the delay
to meet the setup is 4-ns.

The solution in this situation is a clock-gating cell with a D-glitching latch. The D-
glitching latch is clocked with the inversion of clock CLK2. This ensures that the latch
will be active only in the controlling state of clock CLK2. The tool must ensure that the
hold time for the D-glitching latch is met.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 13
 Clock Gating and Associated Timing Checks

The hold check passes with the D-glitching latch as the starting point of the timing path.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 14
 Clock Gating and Associated Timing Checks

Recommendations
Inferring clock-gating check on the select pin of a MUX
A clock-gating check is done with respect to the controlling level of the clock; for
example, at the rising clock edge for the AND gate.

Because the change in the clock input of the MUX does not always control the MUX
output, Genus does not create an automatic clock-gating check for the select pin. If you
need to have a clock-gating check done, you need to set a constraint using the SDC
set_clock_gating_check command:

set_clock_gating_check -high -setup 0.01 mux/sel

Disabling the clock-gating check inferred by Genus at a

combinational cell where clock and data signal are the inputs
Genus creates an external delay and breaks the timing path on the pin on which Genus
infers the clock-gating check. You can also use the following SDC commands to disable
the clock-gating check in Genus:

1. remove_clock_gating_check[-setup] [-rise] [-fall] [-high |

-low] [instance | pin]...

Refer to the reference manual to know about the various options of this
command. You can remove the clock-gating checks from the specified instances
or pins.

Note: To write out this constraint in the output SDC file, you must set the
following variable:

set write_remove_cgc 1

2. set_disable_clock_gating_check

Refer to the reference manual to know about the various options of this
command.

Note: This command is supported only on the mapped instances and the pins of
the mapped instances. This command is not supported on the clock pins of an
instance.

To write this constraint in the output SDC file, you must set the following variable:

set write_disable_and_rmdisable_cgc 1

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 15
 Clock Gating and Associated Timing Checks

3. Genus creates an external delay and breaks the timing path on the pin on which
Genus infers the clock-gating check.

To disable the timing check on a pin, you can direct the tool to disable the
breaking of the timing path. Here is an example:

set_attr break_timing_paths false [find / -pin ABC/EX_PIN]

4. To restore the clock-gating checks inferred on the specified pins or the enable
pins of the specified instances that were present before applying the
set_disable_clock_gating_check command, use the following command:

remove_disable_clock_gating_check [-setup] [-rise] [-fall]

[-high | -low] {pin | instance}...

Note: This command is supported only on the mapped instances and the pins of
the mapped instances. This command is not supported on the clock pins of an
instance.

To write this constraint in the output SDC file, you must set the following variable:

set write_disable_and_rmdisable_cgc 1

5. The priority of multiple set_clock_gating_check constraints on an object:

Consider a scenario in which, for a clock-gating cell, a non-zero setup

requirement is present in the library and different values of the clock-gating setup
check get applied on the same object from a different
set_clock_gating_check command.

The final set_clock_gating_check command for the ICG will be determined

through the following decreasing priority order:

1. set_clock_gating_check on the clock gate enable pin

2. set_clock_gating_check on the clock gate instance

3. Value from the Liberty library

4. set_clock_gating_check on the clock

5. Setup check on the design

6. Default setup check of 0ps for the design

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 16
 Clock Gating and Associated Timing Checks

Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.

Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.

Learn more at Cadence Support Portal - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 17