An Evaluation of Selected Solid-State Transformer

Topologies for Electric Distribution Systems

Roderick J. Garcia Montoya1, Adithya Mallela2, Juan Carlos Balda3
Department of Electrical Engineering
University of Arkansas
Fayetteville, AR, USA
1
rjgarcia@uark.edu, 2amallela@uark.edu, 3jbalda@uark.edu

Abstract— Multiple topologies of solid-state transformers
(SST) were proposed for locomotive traction systems, and
more recently, for electric power distribution systems
because of advantages such as reduced volume and weight,
and functionalities not always possible with traditional
fundamental-frequency transformers. The main goal of this
paper is to evaluate selected SST topologies based on dual-
active bridge (DAB) converters as well as a new SST
topology based on boost converters in order to establish
their suitability for emerging applications in electric power
distribution systems. The evaluation is based on the number
of power semiconductor devices, requirements imposed
upon the high-frequency (HF) transformers, system losses,
and a simplified cost comparison. The new boost-based SST
topology has the highest system efficiency among the
evaluated topologies, but requires twice the number of
power semiconductor devices when using the same high-
voltage device in all topologies.
Index Terms — Boost converter, dual-active bridge, high-
frequency transformer design, solid-state transformer, system losses.
I. INTRODUCTION
The fundamental-frequency transformer performs very
efficiently the function of stepping down or up from one
voltage level to another one in distribution systems; however,
volume and weight are relatively large, and disturbances on
one side are reflected to the other side. There are several
applications where having small volume and weight are
critical, and additional functions, such as continuous voltage
regulation (instead of step-wise regulation) or fault current
limiting under sub-cycle intervals, are required or desirable
turning the SST to be a better solution at the expense of lower
efficiencies, greater complexity, and greater cost [1]-[10].
When stepping down a voltage, the high-voltage (HV) inputs
of the SST modules are normally connected in series, and the
LV outputs in parallel [6]-[8]. In most cases, the HV input is a
single-phase ac source, and the low-voltage (LV) output could
have one and/or three phases.
Several topologies have been proposed to realize a SST
system for distribution systems with the most generic one
having three stages: a front-end rectifier, a dual-active bridge
(DAB) converter, and a back-end inverter [3], [4], [7]. The
DAB could be formed using full or half bridges [3]-[7], [11]-
[13]. The most common configurations have (i) full bridges on
both sides of the DAB [4]-[6], (ii) half bridges on both sides of
the DAB [7], and (iii) a half bridge on the DAB primary side
and a full bridge on the DAB secondary [8]. Six SST
topologies ranging from single stage to three stages were
compared in reference [13]; the authors concluded that the
topology classified as SST topology (i) above is the most
suitable for the SST implementation. However, no half-bridge
topology and the impact of each topology upon the HF
transformer design in terms of efficiency and volume were
considered.
With the main goal of identifying advantages and
disadvantages of SST topologies for emerging distribution
system applications such as dc building distribution, SST
topologies (i)-(iii) and a new boost-based topology (iv) [14]-
[15] are evaluated in terms of the number of semiconductor
devices, the requirements set upon the HF transformer, total
system losses, and a simple cost comparison.
This paper is organized as follows. The selected SST
topologies are described in section II which includes design
equations and equations to calculate the average and rms
current values for the boost-based SST topology. An optimized
method for designing HF transformers is presented in section
III. This method follows the procedure in [16] to calculate an
optimum flux density at which the losses are minimum, but it
has been extended to account for the required leakage
inductance of each topology for optimum power transfer, and
tradeoffs between efficiency and volume. The analysis of the
case study using simulation results and demonstration of the
boost-based SST topology feasibility via a scaled-down
prototype are presented in Section IV. In addition, the results
from the calculation of the power converter and transformer
losses are given in section V. Finally, a comparative cost
analysis is addressed in section VI and concluding remarks in
section VII.
II. DESCRIPTION OF THE SELECTED TOPOLOGIES
The four selected SST topologies are given in Figs. 1-4 with
the new boost-based SST topology, initially proposed for LED
power supplies and having unidirectional power flow, is
considered because of the potential for reducing the number of
semiconductor devices on the HV side. The theoretical
waveforms of the new boost-based SST topology (iv) are given
in Fig. 5. A case study rated 600 kVA per phase and stepping
down the voltage from 7.2 kVac to 400 Vdc is utilized for
comparison purposes.

978-1-4799-6735-3/15/$31.00 ©2015 IEEE 1022

 All topologies are operating at a 50% duty cycle since the power rating [12]. The main equations and operational modes
boost-based one must operate at this duty cycle to apply an ac for the topologies based on the DAB (Figs. 1-3) have been
voltage to the HF transformer with zero average [13]. Three of extensively described in the available literature [3]-[6]; thus, the
the selected SST topologies are based on DAB converters with boost-based SST topology
either half or full bridges. The major difference is the impact that
these topologies have upon the HF transformer and the selection Switches S1 and S2 (see Fig. 4) perform the same function as
of semiconductor devices. Two semiconductor devices are the switch in a boost dc-dc converter during the positive and
replaced by two capacitors in a half bridge with respect to a full negative cycles, respectively, of the fundamental-frequency ac
bridge; so, the voltage applied to the transformer is half the input input voltage. At a 50% duty cycle, the dc-bus voltage is twice
voltage for a half bridge on the primary side, and/or half the the peak of the source voltage Vin,pk, and the blocking capacitor
output voltage for a half bridge on the secondary side. Therefore, Cb voltage is half of the dc-bus voltage. Therefore, the voltage
the current through the primary or secondary winding and VT1 applied to the HF transformer is identical to the topologies
switching devices is twice the current in a full bridge for equal based on a DAB.

AC-DC AC-DC
AC-DC DC-DC
DC-DC DC-DC
3.7 kVdc IB1 IB2
3.7 kVdc IB1 IB2 3.7 kVdc IB1 IB2

+
+ +
+
+
+ + + +
Ip 400 Vdc
Ip 400 Vdc Ip 400 Vdc
- -
VT1 VT2 - - - - -
VT1 VT2
- VT1 VT2
-
± 10%

± 10%
7.2 kVac ± 10%
7.2 kVac

AC-DC

7.2 kVac
AC-DC AC-DC
Module 2 Module 2 Module 2

AC-DC AC-DC AC-DC

Module N Module N Module N

Fig. 1. SST topology (i) based on a DAB Fig. 2. SST topology (ii) based on a DAB with Fig. 3. SST topology (iii) based on a DAB with a
with full bridges half bridges half bridge on the primary and a full bridge on
the secondary

AC-DC
DC-DC
VT1 θ
Is1
D1 Ø
LB + + +
ILB S1 Cb
Ip VT2 θ
Is2 400 Vdc
- -
D2 VT1 VT2
S2 -
ILB
θ
7.2 kVac ± 10%

Ip
θ

AC-DC
Module 2
IS1
θ

IS2 θ

Mode 1 2 3 4 5 6
AC-DC Interval δ δ' Ø π π+Ø π+ß 2π
Conducting
Module M=2N switches DS1 S1 DS2 S2
and diodes
D1
Fig. 4. SST topology (iv) based on the boost Fig. 5. Theoretical waveforms of the boost-based SST
converter topology (iv)

1023
A. Design Equations for the Boost-Based SST Topology Mode 1: 0 < 𝜃 ≤ 𝛿
The equations determining the values of the blocking The conducting devices are D1 and Ds1 (antiparallel diode
capacitor Cb and the boost inductor LB are given by: of S1). The average and rms currents of DS1 are calculated from:
𝑓𝑠𝑤
1 ∅ 𝜋 𝑓 2(𝑟−1)𝜋+𝛿
𝐶𝑏 = [∫𝛿′ (𝐺𝜃)𝑑𝜃 + ∫∅ (𝐻(𝜃 − ∅) + 𝐼∅ )𝑑𝜃 + 𝐼 2 𝐷𝑠1,𝑟𝑚𝑠 = 𝑓𝑠 ∙ ∑𝑟=1
𝐿
(∫2(𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃) +
𝜔𝑠𝑤 ×∆𝑉 (8)
𝜋+𝛿 ′
(1) 2
∫𝜋 (−𝐺(𝜃 − 𝜋) + 𝐼𝜋 )𝑑𝜃 ] 𝑖𝑝 (𝜃)] 𝑑𝜃)
𝑉𝑖𝑛,𝑝𝑘 𝑇𝑠𝑤 𝑓𝑠𝑤
𝐿𝐵 = × , (2) 𝐿 𝑓 2(𝑟−1)𝜋+𝛿
𝐼𝑖𝑛,𝑝𝑘 2 𝐼𝐷𝑠1,𝑎𝑣𝑔 = 𝑓𝑠 ∙ ∑𝑟=1 (∫2(𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃) +
𝑉𝑇1 +𝑉𝑇2 ′ (9)
where ∆𝑉 = 0.1%𝑉𝑏 , 𝜔𝑠𝑤 = 2𝜋𝑓𝑠𝑤 , 𝐺 = , 𝑖𝑝 (𝜃)] 𝑑𝜃),
𝜔𝑠𝑤 𝐿𝑙𝑘
𝑉𝑇1 −𝑉𝑇2 ′
𝐻= , 𝑓𝑠𝑤 the switching frequency, Llk the transformer
𝜔𝑠𝑤 𝐿𝑙𝑘 where the transformer primary current 𝑖𝑝 is given by:
leakage inductance, VT1 the transformer applied primary 𝑖𝑝 (𝜃) = 𝐺𝜃 + 𝐼𝑜 , (10)
voltage, and VT2’ the transformer secondary voltage referred to with Io being the transformer primary current at 𝜃 = 0:
the primary side. The integral in (1) calculates the capacitor −𝑉𝑇1 𝑉 ′ 𝑇2
charge variation ∆Q from 𝛿 ′ to 𝜋 + 𝛿 ′ (Fig. 5). 𝐼𝑜 = [𝜋 + (2∅ − 𝜋)]. (11)
2𝜔𝑠𝑤 𝐿𝑙𝑘 𝑉𝑇1
The boost inductor current 𝑖𝐿𝐵 and its rms value 𝐼𝐿𝐵,𝑟𝑚𝑠 per Mode 2: 𝛿 < 𝜃 ≤ ∅
the procedure in [17] are derived as, The switch S1 is turned on at zero voltage switching (ZVS)
𝑉𝑖𝑛,𝑝𝑘 𝑠𝑖𝑛(𝜃) at 𝜃 = 𝛿. The boost inductor current flows through S1 together
𝑖𝐿𝐵 (𝜃) = .𝜃 (3) with the transformer primary current that is given by:
𝜔𝑠 𝐿𝐵
𝑖𝑝 (𝜃) = 𝐺(𝜃 − 𝛿) (12)
𝑓𝑠𝑤
2 (2𝑟−1)𝜋
𝑓𝐿 2
𝐼 𝐿𝐵,𝑟𝑚𝑠 = 𝑓𝑠 ∙ ∑𝑟=1 (∫2(𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃)] 𝑑𝜃 + Mode 3: ∅ < 𝜃 ≤ 𝜋
(4)
(2𝑟−1)𝜋+𝛽 The switch S1 is still conducting. From Fig. 5, the
∫(2r−1)𝜋 [𝑖′𝐿𝐵 (𝜃)]2 𝑑𝜃), transformer secondary voltage VT2 changes its polarity from
negative to positive at 𝜃 = ∅ following the switching signals.
where 𝜔𝑠 = 2𝜋𝑓𝑠 , fs is the fundamental or source frequency, Therefore, the transformer primary current is given by:
and 𝑖′𝐿𝐵 is the decreasing boost current during the second half
cycle. 𝑖𝑝 (𝜃) = 𝐻(𝜃 − ∅) + 𝐼∅ , (13)
B. Operational Modes for the Boost-Based SST Topology with 𝐼∅ being the transformer primary current at 𝜃 = ∅:
There are six modes of operation describing the boost-based 𝑉𝑇1 𝑉 ′ 𝑇2
SST topology as shown in Fig. 5. One important aspect is that 𝐼∅ = [2∅ + 𝜋 ( − 1)] (14)
2𝜔𝑠𝑤 𝐿𝑙𝑘 𝑉𝑇1
the currents through the switches S1 and S2 are equal to the sum Considering modes 2 and 3, the average and rms currents
of the transformer primary current 𝑖𝑝 and boost inductor through the switch S1 can be expressed as follows:
current 𝑖𝐿𝐵 : 𝑓𝑠𝑤
𝑓𝐿 2(𝑟−1)𝜋+∅
𝑖𝑠1 (𝜃) = 𝑖𝑝 (𝜃) + 𝑖𝐿𝐵 (𝜃). (5) 𝐼 2
= 𝑓𝑠 ∙ ∑𝑟=1 [(∫2(𝑟−1)𝜋+𝛿′ [𝑖𝐿𝐵 (𝜃) +
𝑆1 ,𝑟𝑚𝑠 (15)
(2𝑟−1)𝜋
References [14]-[15] proposed this topology for a power 𝑖𝑝 (𝜃)]2 ) 𝑑𝜃 + (∫2(𝑟−1)𝜋+∅[𝑖𝐿𝐵 (𝜃) + 𝑖𝑝 (𝜃)]2 ) 𝑑𝜃]
supply application and described the operation principle;
however, the average and rms current equations necessary to 𝑓𝑠𝑤
calculate the conduction and switching losses were not given. 𝐿 𝑓 2(𝑟−1)𝜋+∅
𝐼𝑆1 ,𝑎𝑣𝑔 = 𝑓𝑠 ∙ ∑𝑟=1 [(∫2(𝑟−1)𝜋+𝛿′[𝑖𝐿𝐵 (𝜃) + (16)
Based on the operating waveforms shown in Fig. 5, the average
(2𝑟−1)𝜋
and rms current equations in each operating mode can be 𝑖𝑝 (𝜃)]) 𝑑𝜃 + (∫2(𝑟−1)𝜋+∅[𝑖𝐿𝐵 (𝜃) + 𝑖𝑝 (𝜃)]) 𝑑𝜃]
obtained as follows:
The HV diode D1 is active during the whole positive cycle From mode 1 through mode 3 the energy from the source
of the fundamental frequency while HV diode D2 is active voltage is stored in the boost inductor. At the end of mode 3
during the negative cycle. The average and rms values for D1 (𝜃 = 𝜋) the switch S1 turns off.
(which also apply for D2) are given by [17]: Mode 4: 𝜋 < 𝜃 ≤ 𝜋 + ∅
The diode Ds2 conducts before switch S2 turns on for a certain
𝐼 2 𝐿𝐵,𝑟𝑚𝑠 interval in this operating mode. The average and rms currents
𝐼 2 𝐷1,𝑟𝑚𝑠 = (6)
2 can be calculated as:
𝑓𝑠𝑤 𝑓𝑠𝑤
𝑓𝑠 𝑓𝐿 (2𝑟−1)𝜋 𝑓 (2𝑟−1)𝜋+∅
𝐼𝐷1,𝑎𝑣𝑔 = ∑𝑟=1 (∫2(𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃)] 𝑑𝜃 + 𝐼 2 𝐷𝑠2,𝑟𝑚𝑠 = 𝑓𝑠 ∙ ∑𝑟=1
𝐿
(∫(2𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃) + (17)
2 (7)
(2𝑟−1)𝜋+𝛽 2
∫(2𝑟−1)𝜋 [𝑖′𝐿𝐵 (𝜃)] 𝑑𝜃) 𝑖𝑝 (𝜃)] 𝑑𝜃)

1024
 𝑓𝑠𝑤
𝑓
𝐿 (2𝑟−1)𝜋+∅ System and Topology Specifications
𝐼𝐷𝑠2,𝑎𝑣𝑔 = 𝑓𝑠 ∙ ∑𝑟=1 (∫(2𝑟−1)𝜋 [𝑖𝐿𝐵 (𝜃) + 1.
(18) 𝑆, 𝑉𝑝 , 𝑛 𝑉𝑠 , 𝑓, 𝑇𝑎 , ∆𝑇, 𝜂, 𝐷, 𝐿𝑙𝑘
𝑖𝑝 (𝜃)]𝑑𝜃)
Core Material Properties
𝑖𝑝 (𝜃) = −𝐺(𝜃 − 𝜋) + 𝐼𝜋 , (19) 2. 𝐵𝑠𝑎𝑡 , 𝐾𝑐 , 𝛼, 𝛽
where 𝐼𝜋 = −𝐼𝑜 for symmetry.
Optimal Flux Density
Mode 5: 𝜋 + ∅ < 𝜃 ≤ 𝜋 + 𝛽 3. 𝐵𝑜𝑝𝑡
Switch S2 turns on at ZVS in this operating mode where the
boost inductor releases its energy to the dc-link capacitor, and
the transformer primary current is given by: 4.
Core Dimensions
𝐴𝑝 , 𝐴𝑐 , 𝑊𝑎 , 𝑀𝐿𝑇 …
𝑖𝑝 (𝜃) = −𝐻[𝜃 − (𝜋 + ∅)] + 𝐼𝜋+∅ . (20)
For symmetry: 𝐼𝜋+∅ = −𝐼∅ . Winding Arrangement & Dimensions
5. 𝐽𝑜 , 𝑁𝑝 , 𝑁𝑠 , 𝐴𝑤𝑝 , 𝐴𝑤𝑠 , 𝑑𝑖
The boost inductor current reaches zero at the end of this
mode ( 𝜃 = 𝜋 + 𝛽 ) since operation is in discontinuous Not
Leakage Inductance Evaluation
conduction mode (DCM). However, the instant at which it 6. ′ desired
𝐿𝑙𝑘
reaches zero changes following the fundamental frequency
𝑓𝑠 and the switching frequency 𝑓𝑠𝑤 .
Not
Volume Calculation
Mode 6: 𝜋 + 𝛽 < 𝜃 ≤ 2𝜋 7. desired
𝑉𝑐 , 𝑉𝑤 , 𝑉𝑇
The total current flowing through S2 is obtained from modes
5 and 6 as follows:
𝜂′ < 𝜂 Core and Winding Losses
𝑓𝑠𝑤 8. 𝑃𝑐𝑜𝑟𝑒 , 𝑃𝑐𝑢 , 𝜂′
𝑓𝐿 (2𝑟−1)𝜋+𝛽
𝐼 2𝑆2 ,𝑟𝑚𝑠 = 𝑓𝑠 ∙ ∑𝑟=1 [(∫(2𝑟−1)𝜋+∅ [𝑖𝐿𝐵 (𝜃) + 𝜂′ ≥ 𝜂
(21)
(2𝑟)𝜋 Temperature Rise & Isolation Level
𝑖𝑝 (𝜃)]2 ) 𝑑𝜃 + (∫(2𝑟−1)𝜋+𝛽[𝑖𝐿𝐵 (𝜃) + 𝑖𝑝 (𝜃)]2 ) 𝑑𝜃] 9. ∆𝑇′, 𝑑𝑖 ′
𝑓𝑠𝑤 ∆𝑇′ > ∆𝑇
𝑓𝐿 (2𝑟−1)𝜋+𝛽 ∆𝑇′ ≤ ∆𝑇 𝑑𝑖 ′ ≥ 𝑑𝑖 𝑑𝑖 ′ < 𝑑𝑖
𝐼𝑆2 ,𝑎𝑣𝑔 = 𝑓𝑠 ∙ ∑𝑟=1 [(∫(2𝑟−1)𝜋+∅ [𝑖𝐿𝐵 (𝜃) +
(22) Optimum Design
(2𝑟)𝜋 10. Considering Leakage Inductance
𝑖𝑝 (𝜃)]) 𝑑𝜃 + (∫(2𝑟−1)𝜋+𝛽[𝑖𝐿𝐵 (𝜃) + 𝑖𝑝 (𝜃)]) 𝑑𝜃]

The switch S2 is turned off at 𝜃 = 2𝜋 starting the next
switching cycle.
III. TRANSFORMER DESIGN ANALYSIS
The comparison of the SST topologies in [13] did not
account for transformer design considerations that are
evaluated here. The transformer design flowchart shown in Fig.
6 is used to design the HF transformer for each topology; a
comparison of these designs should determine the impacts of
each topology upon the HF transformer. The optimized
transformer design procedure in [16] was extended to account
for the leakage inductance required for optimum power transfer
[4], [6], [18], [19]. The goal was to integrate this inductance
into the transformer leakage inductance to eliminate the need
for an external inductor and achieve a higher system power
density. The transformer design main steps in Fig. 6 are as the
following:
1. System and topology specifications: the main system
specifications are defined including the rated power S, primary
Vp and secondary Vs voltages, operating frequency f, ambient
temperature Ta, temperature rise ΔT, and expected transformer
efficiency η. In addition, the duty cycle D and the desired
leakage inductance Llk for optium power transfer are introduced
as part of the topology specifciations. In a DAB, the transferred
power Po can be related to the leakage inductance as follows
[4], [6]:
Fig. 6. Transformer design flowchart
∅
𝑉𝑇1 × 𝑉𝑇2 ′ × ∅(1 − )
𝑃𝑜 = 𝜋 . (23)
𝜔𝑠𝑤 𝐿𝑙𝑘
The same relationship is obtained for the boost-based SST
topology.
2. Core material properties: the core material selection is
influenced by the design tradeoff between cost, efficiency and
volume. Consideration for core material selection have been
presented in [9], [20], [21], [22]. Among the soft-magnetic
materials, amorphous, ferrite, nanocrystalline, and silicon steel
are prefered for medium- and high-frequency applications [9],
[20], [21]. Amorphous material has been chosen for the case
study since it offers better cost-efficiency tradeoffs when
compared to nanocrystalline and its high stauration flux density
that allows for a greater reduction in volume when compared to
ferrite [9], [20]. Once the core material is selected, the
saturation flux density Bsat, and the Steinmetz coefficients𝑘, 𝛼
and 𝛽 are obtained from the data provided by the manufacturer.
3. Optimum flux density: the expresion for an optimum flux
density Bopt is derived in [16] considering that minimum losses
are obtained when the copper and core losses are equal. Bopt is
calculated from [16]:

1025
 2 1
(ℎ𝑐 𝑘𝑎 ∆𝑇)3 𝐾𝑣 𝑓𝑘𝑓 𝑘𝑢 6
𝐵𝑜𝑝𝑡 = 1 7 ( ∑ 𝑉𝐴
) (24)
3
√4(𝜌𝑤 𝑘𝑤 𝑘𝑢 )12 (𝑘𝑐 𝐾𝑐 𝑓)12
where 𝑘𝑎 , 𝑘𝑐 , 𝑘𝑤 are coefficients related to the types of cores.
Their typical values are 𝑘𝑎 = 40, 𝑘𝑐 = 5.6, and 𝑘𝑤 = 10
[23], [24]. ∑ 𝑉𝐴 is the total transformer power rating, hc is the
coefficient of heat transfer, and ku is the window utilization
factor. A recommended value for ku is 40% [4], [16]. kf is the
stacking factor (0.95 for laminated cores). Kv is defined as the
waveform factor because it depends on the shape of the voltage
waveform applied to the windings. For instance, Kv = 4.44 for
sinusoidal waveform and Kv = 4 for a square waveform [23].
Even though Bsat = 1.56T for the selected material, Bopt is well
below this value (around 0.3T) to have a balance between
efficiency and volume.
4. Core dimension: For the optimim conditions in step 3,
the transformer core size is selected based on the area product
relationship Ap given by [16], [22]:
8
√2 ∑ 𝑉𝐴 7
𝐴𝑝 = (
𝐾𝑣 𝑓𝐵𝑜𝑝𝑡 𝑘𝑓 𝐾𝑡 √𝑘𝑢 ∆𝑇
) resulting temperature rise ΔT’ is evaluated in order to ensure
5. Winding arrangements and dimensions: Considering the
effects of the copper loss, core loss, and the thermal heat
transfer, an equation for the optimum value of current density
can be calculated by [16], [22]:
ℎ𝑐 𝑘𝑎 ∆𝑇 1 arrangement in step 5.
𝐽𝑜 = √𝜌 .√ .8
𝑤 𝑘𝑤 2𝑘𝑢 √𝐴𝑝
Here 𝜌𝑤 is the resistivity of the winding. In addition, the
required isolation level is taken into account by estimating a
minimum distance between conductors di per the procedure
given in [22]. Based on the current density the wire is selected
from manufacturer catalogs and the required number of turns
for the primary Np and secondary Ns is then obtained.
6. Leakage inductance evaluation: It is desired to
incorporate the leakage inductance required for optimum power
transfer through the transformer in the DAB- and boost-based
topologies. There are different methods for estimating the
leakage inductance which depends upon the transformer
geometry and winding arrangements. For example, the leakage
inductance for a shell-type core arrangement referred to the
primary is given by [4], [18]:
1 ℎ
𝐿𝑙𝑘 = 𝜇𝑜 𝑁𝑝 2 𝑀𝐿𝑇. ,
3 𝑤
where MLT is the mean length of a turn, w is the width of the
windings inside the core, h is the height of the window area.
The estimation of the leakage inductance is a critical design
step; therefore, the winding and core arrangements should be
carefully selected. Different winding and core arrangements are
discussed in [18] where the effect of orthogonal flux is also
analyzed.
7. Volume calculation: the volume of the core Vc and
windings Vw can be related to the area product by [24]:
𝑉𝑐 = 𝑘𝑐 𝐴𝑝 3/4
𝑉𝑤 = 𝑘𝑤 𝐴𝑝 3/4 (29)
If the application is characterized by space limitations and
the requirement is not fulfilled, a new design iteration can be
considered by selecting a different operating flux density in
step 3; however, the efficiency could be compromised.
8. Core and winding losses: the core losses are determined
using the Improved Generalized Steinmetz Equation (iGSE)
which can be applied when having non-sinusoidal excitations.
𝑇 𝛼
1 𝑑𝐵(𝑡)
𝑃𝑣 = ∫ 𝑘1 | | |Δ𝐵|𝛽−𝛼 𝑑𝑡 (30)
𝑇 0 𝑑𝑡
𝑘
𝑘1 = 2𝜋 , (31)
(2𝜋)𝛼−1 ∫0 |cos 𝜃|𝛼 |sin 𝜃|𝛽−𝛼 𝑑𝜃
where Pv is the core loss per unit volume.
9. Temperature rise and isolation level: At this point the
(25)
that the temperature rise given in the system specifications
(step 1) is not exceeded. In addition, the required isolation level
is evaluated by calculating the distance between conductors di’
per the procedure given in [22]. If the requirements are not
fulfilled, a new iteration is initiated considering two options:
changing the core dimensions in step 4, or the winding
(26)
Finally, an optimized design which also considers the
required leakage inductance depending on the topology can be
obtained. The specifications of the selected SST topologies for
the considered case study are given in Table I. The four selected
SST topologies yielded the four transformer designs in Table
II. The designs requiring lower leakage inductances resulted in
having lower efficiencies and larger volumes due to the higher
current capability that was required. The transformer for the
boost-based topology is rated at 100 kVA; therefore, a
comparison would not be applicable.
IV. ANALYSIS OF THE CASE STUDY
Table I provides the main specifications of the four SST
topologies for the considered case study. The design equations
for the boost-based SST topology derived in Section II were
used for designing the case study. Insulated gate bipolar
transistors (IGBTs) have been selected for both sides of the SST
(27)
topologies; in particular, the HV devices were 6.5-kV IGBTs to
minimize the number of modules; hence, the HF transformers
[3], [9]. For SST topologies (i) to (iii), the HV dc bus is Vin,pk
thus, each topology requires three SST modules with each one
having a HV dc bus of 3.7 kVdc and rated 200 kVA. The
simulation results for the boost-based SST topology are
presented in Fig. 7. The overall HV dc bus is twice Vin,pk;
therefore, six SST modules are required when the IGBTs are
subjected to the same dc-bus voltage of 3.7 kVdc. Then, each
transformer is rated 100 kVA. From the theoretical analysis in
Section II, the voltage applied to the transformer VT1 is half of
the dc-bus voltage which can be noticed in Fig. 7(a). A half
(28) bridge is considered for the secondary side; therefore, the
secondary voltage is identical to topology (ii) as shown in
1026
 TABLE I. MAIN SPECIFICATIONS OF THE SELECTED SST TOPOLOGIES
Transformer
Transformer Peak Current No. of Devices
Voltage (V) (A) Power Rating
SST No. of Per Module
Topology Modules (kVA) HV LV
HV LV HV LV
IGBT Diodes IGBT
i 3700 400 125 1000 3 200 24 0 12
ii 1850 200 250 2000 3 200 18 0 6
iii 1850 400 250 1000 3 200 18 0 12
iv 1850 200 125 1000 6 100 12 12 12

TABLE II. TRANSFORMER DESIGN COMPARISON

SST (a)
Topologies i ii iii iv
Llk (mH) 2.77 0.693 0.617 1.39
Volume (dm3) 36.5 43.6 41.5 25.6
Pfe (W) 412 467 473 83.72 (b)
Pcu (W) 382 398 383 147.19
𝛈′ (%) 99.60 99.57 99.57 99.77
Fig. 7(b). The secondary voltage is phase shifted with respect to
the primary voltage and leads to the transformer primary current (c)
waveform shown in Fig. 7(c) whose peak value is 125 A as
indicated in Table I. The boost current follows the source and
switching frequency, as can be seen from Figs. 7(d) and (e), and
reaches its peak value at 108 A.
A. Experimental Results (d)
The feasibility of the boost-based SST topology is validated
with a scaled-down prototype rated at 1 kW, and 300 Vac (424
Vpk) to 60 Vdc. The primary voltage was stepped down with a
transformer turns ratio of 14 to get 30 Vac on the transformer
secondary side, and then rectified with a half-bridge, as in Fig. (e)
4, to get 60 Vdc at the output. The switching frequency fsw is 20
kHz, the duty cycle is fixed at 50%, the boost inductor LB is 2.2
mH, the dc-link capacitor Cd is 1300 µF, and the blocking
capacitor Cb is 6.8 µF. The transformer leakage inductance Llk, Fig. 7. Simulation results of the case study for boost-based SST topology.
calculated for optimum power transfer as explained in section (a) Transformer primary voltage, (b) transformer secondary voltage, (c)
transformer primary current, (d) boost inductor current, and (e) zoomed
III, is 1.1 mH. The experimental waveforms of the scaled-down boost inductor current.
prototype are presented in Fig. 8. From Fig. 8(a), the voltage
applied to the transformer is the peak input voltage of 424 V The conduction and switching losses in the IGBTs and diodes
since the blocking capacitor is been charged to half of the dc- were calculated per the procedure in [24]. The conduction losses
link voltage. Fig, 7(b) shows that the transformer primary are given by:
current has the same behavior as the SST topologies based on
the DAB [3]-[6]. Only two switching cycles of the boost 𝑃𝑐,𝑠 = 𝑈𝑠𝑜 . 𝐼𝐼𝐺𝐵𝑇,𝑎𝑣𝑔 + 𝑅𝑠 . 𝐼𝐼𝐺𝐵𝑇,𝑟𝑚𝑠 2 (𝐼𝐺𝐵𝑇) (32)
inductor current can be seen in Fig. 7(c); however, the peak
value changed together with the source frequency (i.e., 60 Hz) 𝑃𝑐,𝑑 = 𝑈𝑑𝑜 . 𝐼𝑑,𝑎𝑣𝑔 + 𝑅𝑑 . 𝐼𝑑,𝑟𝑚𝑠 2 (𝑑𝑖𝑜𝑑𝑒), (33)
as shown in Fig. 7(d). Thus, the boost-based SST topology (iv)
can convert the voltage directly from ac to dc without using a where the parameters 𝑈𝑠𝑜 , 𝑅𝑠 , 𝑈𝑑𝑜 , and 𝑅𝑑 are obtained from
front-end rectifier stage as it is needed in the SST topologies (i), the data provided by the manufacturer. In addition, the switching
(ii), and (iii). losses are calculated from:

V. THEORETICAL SST SYSTEM LOSSES 𝑃𝑠𝑤 = (𝐸𝑜𝑛 + 𝐸𝑜𝑓𝑓 )𝑓𝑠𝑤 , (34)

The total SST system losses are divided into conduction where Eon and Eoff are the turn on and turn off losses,
losses Pc and switching losses (Psw) for the power converters, respectively. Zero-current switching takes place in the DAB
and copper losses Pcu and core losses Pfe for the HF transformers. through the different operating modes, and the capacitors in

1027
 VI. COMPARATIVE COST ANALYSIS
The selection of the devices is based on the specifications
(a) given in Table I. IGBTs rated at 6.5kV/250A are considered for
the front-end rectifier in the SST topologies (i), (ii), and (iii).
Topology (iv) does not have a front-end controlled rectifier
stage since it uses two HV diodes. The rated current of the
IGBTs for the HV and LV side of the DAB on topology (ii) is
twice the rated current of the IGBTs in topology (i). Thus,
6.5kV/250A IGBTs are considered for topology (i) and
(b) 6.5kV/500A IGBTs in topology (ii). Although the price of a
single IGBT with higher current rating is more expensive than
the IGBT with lower current rating (about 20% for the same
voltage rating), the cost of the full-bridge configuration may be
about 20% higher than a half-bridge configuration, as shown in
Fig. 9 [12], [26]. Moreover, the cost of the two extra transistors
(c) in the full bridge is around 60% higher than the cost of the
capacitors in the half bridge, thus topology (ii) is still less
expensive than topology (i). Topology (iii) has a full-bridge at
the secondary side, thus it is only 9% less expensive than
topology (i). The cost of topology (iv) is 16% less than the cost
of topology (i) when considering only IGBTs and diodes

Fig. 8. Experimental results of the scaled-down prototype for the boost- 100%
based SST topology. (a) Transformer primary voltage, b) transformer
primary current, (c) boost inductor current. 80%

60%
parallel with the switches enable ZVS during turn on and quasi
ZVS during turn off [4]-[6]. ZVS is also achieved in the boost- 40%
based topology [14]. These considerations where taken into
20%
account when calculating the switching losses. Rectifier stage
losses were calculated per the procedure in [25]. 0%
The average and rms current values for the IGBTs and i ii iii iv
diodes through the various operating modes were calculated Fig. 9. Cost comparison of selected SST topologies considering only
making use of the theoretical waveforms (see Fig. 5 as an IGBTs and diodes.
example). In section II, equations for average and rms currents
through S1, S2, Ds1, Ds2, D1, and D2 (see Figs. 4-5) for the boost-
100%
based SST topology were derived. For the three standard SST
topologies during steady-state conditions, the waveforms are 80%
repeated every cycle of the switching frequency (i.e., 3 kHz for
60%
the DAB and 1.8 kHz for the front-end bridge rectifier). Special
consideration was taken for the boost-based SST topology 40%
because the boost current varies with the applied (ac source)
20%
input voltage; thus, the cycle of the fundamental frequency (i.e.,
60 Hz) must be considered besides the cycle of the switching 0%
frequency (i.e., 3 kHz) [17]. The power losses per module for all i ii iii iv
four SST topologies are listed in Table III (rounded off to the
nearest integer). The rectifier stage has the highest losses since Fig. 10. Total cost comparison of selected SST topologies.
the devicesFig.
are7. considered
Experimental results
to beof operating
the boost-based SST topology.
under (a) Primary
hard switching.
voltage, (b) primary current, and (c) boost inductor current.

TABLE III. POWER LOSSES PER MODULE FOR THE SELECTED SST TOPOLOGIES

SST Psw Pc Rectifier Psw + Pc Transformer Total Losses SST System

Topologies (W) (W) (W) Losses (W) (kW) Efficiency

i 280 2372 10400 794 13.85 93.52%

ii 279 2373 10400 865 13.92 93.49%
iii 280 2373 10400 856 13.91 93.5%
iv 540 3278 - 231 4.05 96.1%

1028
(Fig. 9). However, considering the IGBTs, diodes, dc-link
capacitors, inductor, and transformers, the topology (iv) has the
highest cost among the selected SST topologies, as shown in
Fig. 10. Topology (ii) ended up being the cheapest topology, at
a cost 16% lower than topology (iv).
VII. CONCLUDING REMARKS
SST topologies (ii) and (iii) have 25% fewer devices on the
primary side when compared to SST topology (i), but the
devices operate at twice the current level on the primary side.
SST topology (ii) also has 50% fewer devices on the secondary
side at twice the rated current. The transformer designs for SST
topologies (ii) and (iii) have the lowest leakage inductance, but
their volumes and losses are higher than those for SST topology
(i) due to the need for larger copper area of the windings. The
transformer for the boost-based SST topology (iv) is half rated,
so a comparison of transformer losses would not be applicable.
The total losses per module for the standard SST topologies (i),
(ii), and (iii) are nearly similar, which means the SST system
efficiencies are also similar. The SST topology (iv) has
approximately one third of the losses per module; therefore, it
has the highest system efficiency; however, it requires twice the
number of modules because of the limited voltage rating of HV
IGBTs. This requirement has an impact on the total cost of the
system; therefore, the boost-based SST topology has the highest
cost among the selected SST topologies.
ACKNOWLEDGMENT
The authors are grateful for the financial support from the
National Science Foundation Industry/University Cooperative
Research Center on Grid-connected Advanced Power
Electronics Systems (GRAPES). Mr. Roderick Garcia is also
grateful for the financial support from the Fulbright-SENACYT
program.
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