8170 ServiceManual

SERVICE MANUAL FOR
8170
BY: Jacey Liu
TESTING
TESTING TECHNOLOGY
TECHNOLOGY DEPARTMENT
DEPARTMENT // TSSC
TSSC
Jan . 2002
8170 N/B MAINTENANCE
CONTENTS
1. Hardware Engineering Specification-------------------------------------------------------------------------------- 4
1.1 Introduction-------------------------------------------------------------------------------------------------------------------------------- 4
1.2 System Architecture---------------------------------------------------------------------------------------------------------------------- 5
1.3 Electrical Characteristic----------------------------------------------------------------------------------------------------------------- 22
1.4 APPENDIX--------------------------------------------------------------------------------------------------------------------------------- 32
1.5 BIOS Specification------------------------------------------------------------------------------------------------------------------------ 39
2. System Assembly & Disassembly ------------------------------------------------------------------------------------ 82

2.1 System View-------------------------------------------------------------------------------------------------------------------------------- 82
2.2 System Disassembly---------------------------------------------------------------------------------------------------------------------- 86
3. Definition & Location Connectors / Switches Setting ----------------------------------------------------------- 104
3.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 104

3.2 D/D Board----------------------------------------------------------------------------------------------------------------------------------- 107
3.3 Touch PAD Board------------------------------------------------------------------------------------------------------------------------- 108
4. Definition & Location Major Components------------------------------------------------------------------------- 109
4.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 109

4.2 D/D Board---------------------------------------------------------------------------------------------------------------------------------- 111
5. Pin Descriptions of Major Components ---------------------------------------------------------------------------- 112
5.1 Pentium 4(Willamette/Northwood) Micro-FCPGA 478 pin---------------------------------------------------------------------- 112

5.2 Intel 82845(Brookdale Memory Controller HUB)---------------------------------------------------------------------------------- 118
5.3 Intel 82801BA(I/O Controller HUB )------------------------------------------------------------------------------------------------- 125
5.4 PCI4410(PCMCIA/1394 LINK Controller )---------------------------------------------------------------------------------------- 130
1
CONTENTS
6. System Block Diagram ------------------------------------------------------------------------------------------------- 136
7. Maintenance Diagnostic ------------------------------------------------------------------------------------------------ 137

7.1 Introduction-------------------------------------------------------------------------------------------------------------------------------- 137
7.2 Error Codes-------------------------------------------------------------------------------------------------------------------------------- 138
7.3 Debug Card-------------------------------------------------------------------------------------------------------------------------------- 140
8. Trouble Shooting -------------------------------------------------------------------------------------------------------- 142

8.1 No Power------------------------------------------------------------------------------------------------------------------------------------ 143
8.2 Battery Can not Be Charged----------------------------------------------------------------------------------------------------------- 148
8.3 No Display---------------------------------------------------------------------------------------------------------------------------------- 151
8.4 VGA Controller Failure LCD No Display------------------------------------------------------------------------------------------- 153
8.5 VGA Controller Failure External Monitor No Display--------------------------------------------------------------------------- 155
8.6 Memory Test Error----------------------------------------------------------------------------------------------------------------------- 157
8.7 Keyboard(K/B) and Touch Pad(T/B) Test Error----------------------------------------------------------------------------------- 159
8.8 Hard Drive Test Error------------------------------------------------------------------------------------------------------------------- 161
8.9 CD-ROM Drive Test Error------------------------------------------------------------------------------------------------------------- 163
8.10 USB Port Test Error-------------------------------------------------------------------------------------------------------------------- 165
8.11 PIO Port Test Error--------------------------------------------------------------------------------------------------------------------- 167
8.12 PC-Card Failure------------------------------------------------------------------------------------------------------------------------- 169
8.13 IEEE1394 Failure----------------------------------------------------------------------------------------------------------------------- 171
8.14 Audio Failure---------------------------------------------------------------------------------------------------------------------------- 173
8.15 LAN Test Failure------------------------------------------------------------------------------------------------------------------------ 176
9. Spare Parts List ---------------------------------------------------------------------------------------------------------- 178
2
CONTENTS
10. System Explode View ------------------------------------------------------------------------------------------------- 189
11. Circuit Diagram -------------------------------------------------------------------------------------------------------- 190
12. Reference ---------------------------------------------------------------------------------------------------------------- 215
3
1.Hardware Engineering Specification

1.1 Introduction
1.1.1 General Description
This document describes the system hardware engineering specification for 8170 portable notebook computer system.
The 8170 notebook computer is a new mainstream high performance notebook in the MiTAC notebook family.
1.1.2 System Overview

CPU mPGA 478 -PIN Socket Support Intel Pentium (Willamette)/Northwood in mFC-PGA2 package
Video 1. Dual independent Displays(LCD/CRT, LCD/TV,CRT/TV)
2. Support Motion Compensation and iDCT
3. Support Simultaneous display
Momory Two 144Pin SO-DIMM ,withont and on-board Memory
PCMCIA 1. Support one slot of TypeII
2. Non Support Zoom video/Audio Function
IDE Support 2 IDE channel,Up to Ultra DMA 100
LCD Display Support Dual 85MHz LVDS interface.
Support up to QXGA(2048*1536) Resolution
Button 5 Easy Start Button(functions defined by user)& 1 Mail Receive Button
LAN Support to 10/100 Based T
Modem 56Kbps V.90 MDC Modem
Pointing Glide PAD with 2 Buttons and 1 scroll button
Keyboard Internal Key Matrix Keyboard
BIOS 512KB Flash EEPROM (Include System BIOS&VGA BIOS)
4
Audio 1. AC'97 Interface Codec. Sound Blaster Pro Compatible.

2. Built-In 21W speaker and 1 Mono-Microphone
I/O Port 1. Bi-Direction Parallel Port (EPP/ECP) 2. External VGA Port(D-SUB 15Pins)
3. 2 Standard USB 1.1 Port 4. SPIDF Jack
5. RJ-11 Port for Modem 6. Microphone In Jck
7. RJ-45 Port for LAN 8. VR for Audio Volume Control
9. DC Input Jack 10.Mini IEEE 1394 Port
11. S-Video Output Port(NTSC/PAL) 12. Battery Connector
Suspend Mode POS(S1), Suspend to RAM(S3), Suspend to Disk(S4)
Indicator HDD,FDD,CD-ROM,Num Lock,Caps Lock, Scroll Lock LEDs
1.2 System Architecture

1.2.1 Block Diagram(without Power System)
5
8170 System Block Diagram
6
1.2.2 Function Description
1.2.2.1 CPU
Socket Intel Pentium 4/ Northwood processors with 100MHz FSB.400MHz system bus.Capable of mFC-PGA2
package
Available at 1.50, 1.60, 1.70, 1.80, 1.90 and 2 GHz
Binary compatible with applications running on previous members of the Intel microprocessor line
Intel® NetBurst™ micro-architecture
System bus frequency at 400 MHz
Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency
Hyper Pipelined Technology
Advance Dynamic Execution
---Very deep out-of-order execution
---Enhanced branch prediction
Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops
8 KB Level 1 data cache
256 KB Advanced Transfer Cache (on-die,full speed Level 2 (L2) cache) with 8-way associatively and Error
Correcting Code (ECC)
144 new Streaming SIMD Extensions 2 (SSE2) instructions
Enhanced floating point and multimedia unit for enhanced video, audio,encryption, and 3D performance
Power Management capabilities
---System Management mode
---Multiple low-power states 7
Optimized for 32-bit applications running on advanced 32-bit operating systems
8-way cache associatively provides improved cache hit rate on load/store operations.
1.2.2.2 CORE LOGIC

Intel Brookdale 82845 Memory Control HUB
Intel® Pentium® 4 Processor (478 pin package) Support:
---Enhanced Mode Scaleable Bus Protocol
---2x Address, 4x Data
---System Bus interrupt delivery
---400 MHz system bus
---System Bus Dynamic Bus Inversion (DBI)
---32-bit system bus addressing
---12 deep In-Order Queue
---AGTL+ bus driver technology with integrated AGTL+ termination resistors
System Memory Support
---Directly supports one SDR SDRAM channel, 64 bits wide (72 bits with ECC)
---133 MHz SDR SDRAM devices
---64 Mb, 128 Mb, 256 Mb and 512 Mb technologies for x8 and x16 devices
---By using 64 Mb technology, the smallest memory capacity possible is 32 MB
---Configurable optional ECC operation (single bit Error Correction and multiple bit Error Detection)
---Page sizes of 2 KB, 4 KB, 8 KB and 16 KB (individually selected for every row)
---Thermal management
---Maximum of 3 Double-Sided DIMMs (6rows populated) with unbuffered PC133 (with or without ECC)
---3 GB Maximum using 512 Mb technology
---Supports up to 24 simultaneous open pages
---Maximum memory bandwidth of 1.067 GB/s with PC133 8
Hub Interface to Intel® 82801BA ICH2
---266 MB/s point-to-point hub interface to ICH2
---66 MHz base clock
---MSI interrupt messages, power management state change, SMI, SCI and SERR error indication
Accelerated Graphics Port (AGP) Interface
--- Supports a single AGP device (either a connector or on the motherboard)
---Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol
---Supports only 1.5 V AGP electrical characteristics
---32 deep AGP request queue
---Delayed transaction support for AGP-to-System Memory FRAME# semantic reads
System Interrupt Support
---System bus interrupt delivery mechanism
---Interrupts signaled as upstream memory writes from AGP/PCI
---Supports peer MSI between hub interface and AGP
---Provides redirection for IPI and upstream interrupts to the system bus
Power Management
---SMRAM space remapping to A0000h
---Supports extended SMRAM space above 256 MB, additional TSEG from Top of Memory
interface are not supported
---PC ’99 suspend to DRAM support
---ACPI, Revision 1.0b compliant power management
---APM, Revision 1.2 compliant power management
---NT Hardware Design Guide, Version 1.0 compliant
Package
---MCH: 593 pin FC-BGA (37.5 x 37.5 mm)
9
Intel 82801BA Internal Connect HUB
PCI Bus I/F

---Supports PCI at 33 MHz
---Supports PCI Rev 2.2 Specification
---133 MByte/sec maximum throughput
---Supports up to 6 master devices on PCI
---One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller)
Integrated LAN Controller
---WfM 2.0 Compliant
---Interface to discrete LAN Connect component
---10/100 Mbit/sec Ethernet support
---1 Mbit/sec HomePNA* support
Integrated IDE Controller
---Independent timing of up to 4 drives
---Ultra ATA/100/66/33, BMIDE and PIO modes
Read transfers up to 100MB/s, Writes to 89 MB/s
---Separate IDE connections for Primary and Secondary cables
---Implements Write Ping-Pong Buffer for faster write performance
USB
---2 UHCI Host Controllers with a total of 4 ports
---USB 1.1 compliant
---Supports wake-up from sleeping states S1–S4
---Supports legacy Keyboard/Mouse software
AC'97 Link for Audio and Telephony CODECs
---AC’97 2.1 compliant 10
---Independent bus master logic for 5 channels (PCM In/Out, Mic Input, Modem In/Out)
---Separate independent PCI functions for Audio and Modem
---Support for up to six channels of PCM audio output (full AC3 decode)
---Supports wake-up events
Interrupt Controller
---Support up to 8 PCI interrupt pins
---Supports PCI 2.2 Message-Based Interrupts
---Two cascaded 82C59
---Integrated I/O APIC capability
---15 interrupts supported in 8259 mode, 24 supported in I/O APIC mode
---Supports Serial Interrupt Protocol
---Supports Front-Side Bus interrupt delivery
1.8 V operation with 3.3 V I/O
---5V tolerant buffers on IDE, PCI, USB Over current and Legacy signals
GPIO
---TTL, Open-Drain, Inversion
Timers Based on 82C54
---System timer, Refresh request, Speaker tone output
Power Management Logic
---ACPI 1.0 compliant
---ACPI Power Management Timer
---PCI PME# support
---SMI# generation
---All registers readable/restorable for proper resume from 0V suspend states
---Support for APM-based legacy power management for non-ACPI implementations
11
External Glue Integration
---Integrated Pull-up, Pull-down and Series Termination resistors on IDE and processor interface
Enhanced Hub I/F buffers improve routing flexibility (Not available with all Memory Controller Hubs)
Firmware Hub (FWH) I/F supports BIOS memory size up to 8 MBs
Low Pin count (LPC) I/F
---Allows connection of legacy ISA and X-Bus devices such as Super I/O
---Supports two Master/DMA devices.
Enhanced DMA Controller
---Two cascaded 8237 DMA controllers
---PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs
---Supports LPC DMA
---Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels
Real-Time Clock
---256-byte battery-backed CMOS RAM
---Hardware implementation to indicate century rollover
System TCO Reduction Circuits
---Timers to generate SMI# and Reset upon detection of system hang
---Timers to detect improper processor reset
---Integrated processor frequency strap logic
SM Bus
---Host interface allows processor to communicate via SM Bus
---Slave interface allows an external Micro controller to access system resources
---Compatible with most 2-Wire components that are also I2C compatible
12
Supports ISA bus via external PCI-ISA Bridge
360-pin EBGA package
1.2.2.3 Memory
64MB PC133 SDRAM SO-DIMM Expandable to 1024MB(2 SODIMM slots).
Support 3.3V PC133 SDR SDRAM only.
Table 1.1 MEMORY EXPANSION CAPACITY

67.6mm ( 2.66”)
Slot1 Slot2 Total
64MB 0 64MB
64MB 32MB 96MB 54 pin or 54 pin or 54 pin or 54 pin or
31.75mm
64MB 64MB 128MB 50 pin
TSOP
50 pin
TSOP
50 pin
TSOP
50 pin
TSOP (1.25”)
SPD
64MB 128MB 192MB
64MB 256MB 320MB
64MB 512MB 576MB
128MB 128MB 256MB 1 143
59 61
128MB 256MB 384MB
128MB 512MB 640MB
256MB 256MB 512MB
256MB 512MB 768MB
512MB 512MB 1024MB Figure 1.1 SO-DIMM MODULE
13
1.2.2.4 I/O Ports
• CRT Port
@ Standard VGA compatible port
@ DDC1 and DDC2B compliant
Table 1.2 CRT CONNECTOR
PIN SIGNAL DESCRIPTION

1 RED Red analog video output
2 GREEN Green analog video output
3 BLUE Blue analog video output
4 Monitor Sense Monitor Sense
5 GND Ground 5 4 3 2 1
6 GND Ground
10 6
7 GND Ground
8 GND Ground 15 14 13 12 11
9 VCC +5VDC
10 GND Ground
11 Monitor Sense Monitor Sense
12 CRT DATA Data from DDC monitor
13 HSYNC Horizontal Sync Control
14 VSYNC Vertical Sync control
Figure 1.2 CRT CONNECTOR
15 CRT CLK Clock to DDC monitor
14
• Standard 4 Pins S-VIDEO Port for TV-Out
@ Support 1024*768 resolution
@ Support 848*480 resolution in 16:9 mode
@ Support PAL and NTSC system
Table 1.3 S-VIDEO CONNECTOR

1 GND -
2 GND -
3 LUMA O Pin 1
4 CRMA O
Figure1.3 S-VIDEO Port
• IEEE1394 Port
Table 1.4 IEEE1394 CONNECTOR

1 TPB- I/O
2 TPB+ I/O
3 TPA- I/O
4 TPA+ I/O
Figure1.4 IEEE1394 Port
• AUDIO Ports
@ Built in 1 mono microphone
15
@ SPDIF
@ Microphone In
• RJ11
@ Connection to Modem Daughter Board connector
Table 1.5 MODEM CONNECTOR

PIN SIGNAL NAME DIRECTION DESCRIPTION
1 NC - No Connect
2 LINE+ I/O Phone Line Positive
3 LINE- I/O Phone Line Negative
4 NC - No Connect
Figure 1.5 MODEM Port
• RJ45
@ Connection to on-board NIC controller
Table 1.6 LAN CONNECTOR

1 TX+ Out Transmit Data Ring
2 TX- Out Transmit Data Tip
3 RX+ IN Receive Data Ring
4 TERM 1 - Internal termination resistor
5 TEMR 2 - Internal termination resistor
6 RX IN Receive Data Tip
7 TERM 3 - Internal termination resistor
8 TERM 4 - Internal termination resistor Figure 1.6 LAN CONNECTOR
16
• USB Port
@ Two industry standard USB 1.1 ports
Table 1.7 USB Port2

1 VCC - USB Device Power (+5VDC)
2 DATA- I/O Balanced Data Negaitve
3 DATA+ I/O Balanced Data Posiitve
4 GND - Ground
Figure 1.7 USB Port
• Parallel Port
@ Configurable as logical ports LPT1,LPT2 or LPT3
@ EPP rev 1.7 & 1.9 compatible
@ ECP(IEEE 1284) compatible
@ Industry standard 25 Pins connector
Figure 1.8 PARALLEL PORT CONNECTOR
17
Table 1.8 PARALLEL Port
1 STROBE# O Data Strobe
2 PD0 I/O PP Data bit 0
10 -ACK I Printer Acknowledge
11 BUSY I Printer Busy
12 PE I Paper Out
13 SLCT I Print Select Acknowledge
14 -AUTOFDXT O Auto Line Feed
15 -ERROR I Printer Error
16 -INIT O Reset Printer
17 SLCTIN# I Select In
18 GND - Ground
19 GND - Ground
20 GND - Ground
21 GND - Ground
22 GND - Ground
23 GND - Ground
24 GND Ground
25 GND - Ground
Case GND - Ground
18
1.2.2.5 PC CARD SLOT
One Type II/I slot supporting the 1997 PC Card standard, and including full R2(16-bit) and 32-bit Card
bus Data transfer
TI PCI4410(PCMXCIA Controller)& TI TPS2211(Power Switch)
1.2.2.6 GRAPHICAL SUBBSYSTEM

ATI Mobility M6 graphical controller embedded 8M DDR SDRAM
1.2.2.7 DISPLAY
Internal LCD Display is 14.1” TFT ISP XGA color
External Video refresh rate of up to 100HZ support
---Vertical refresh frequencies to meet VESA requirements
---Simultaneous video in specified video modes-switchable with hot key
1.2.2.8 READ ONLY MEMORY(BIOS FLASH)

Fully compatible with industry standard software including windows 2000 & Windows XP
Fully support APM V1.2 and latest ACPI specification
4Mb Flash BIOS
Inside BIOS core
1.2.2.9 POWER MANAGEMENT FEATURES

Local standby mode(individual device such as HDD, graphics controller,LCD etc..)
19
CPU Idle mode(including ACPI modes C1 and C2)
Suspend mode(including S1 and S3 ACPI modes)
Fully APM V1.2 compliant
Fully ACPI V1.1 compliant
Hibernate for Windows 2000 and windows XP
Thermal management
Fully US EPA Energy start compliant
1.2.2.10 KEYBOARD CONTROLLER

Hitachi H8-3437S
1.2.2.11 SUPER I/O

Ns PC87393F LPC interface Ultra I/O
1.2.2.12 LEDS INDICATOR

CDROM & HDD & NUM & CAP & SCROLL & EMIAL
1.2.2.13 BUTTONS
EMAIL BIN & FIVE PIECE EASY START RTN
20
1.2.2.14 MODEM
Table 1.9 MODEM DAUGHTER BOARD CONNECTOR

PIN SIGNAL NAME PIN SIGNAL NAME
1 MONO_OUT 2 NC
3 GND 4 MODEM_SPK
5 NC 6 NC
7 NC 8 GND
9 NC 10 +5V
11 NC 12 NC
13 NC 14 NC
15 GND 16 Pull Up to +3V
17 +3V 18 +5V
19 GND 20 GND
21 +3V 22 ACSYNC
23 ACSDOUT 24 MSDIN
25 -ACRST 26 MSDIN
27 GND 28 GND
29 GND 30 ACBITCLK
21
1.3 Electrical Characteristic

1.3.1 Power On Sequence
Figure 1.9 Power on Sequence
22
1.3.2 Power On Suspend Sequence
Figure 1.10 Power on Suspend Sequence
1.3.3 Resume from Power Suspend Sequence
Figure 1.11 Resume from Power Suspend Sequence
23
1.3.4 Suspend to RAM Sequence
Figure 1.12 Suspend to RAM sequence
24
1.3.5 Resume from Suspend to RAM Sequence
Figure 1.13 Resume from Suspend to RAM Sequence
25
1.3.6 Suspend to Disk Sequence
Figure 1.14 Suspend to Disk Sequence
26
1.3.7 Resume from Suspend to Disk Sequence
Figure 1.15 Resume from Suspend to Disk Sequence
27
1.3.8 ICH2 GPI/O Pin Define

Pin Name Signal Name Power Type During Immediately After S1 S3 S4/S5 Description
PCIRST# PCIRST#
GPIO0 PULL-UP +3.3VS I PC/PCI DEVICE DRIVEN
GPIO1 PULL-UP +3.3VS I PC/PCI DEVICE DRIVEN
GPIO2 PULL-UP +3.3VS X X X X X X X
GPIO3 PULL-UP +3.3VS I HIGH-Z HIGH-Z HIGH-Z
GPIO4 PULL-UP +3.3VS I HIGH-Z HIGH-Z HIGH-Z
GPIO6 PULL-UP +3.3VS I MAIN I/O
GPIO7 PULL-UP +3.3VS I
GPIO8 -SCI +3.3VA I ACPIMODE-SCI
GPIO11 PULL-UP +3.3VA I HIGH-Z HIGH-Z DEFINED DEFINED DEFINED
GPIO12 -EXTSMI +3.3VA I DOS MODE -SMI
GPIO13 PULL-UP +3.3VA I
GPIO16 TP +3.3VS O HIGH-Z HI HI OFF OFF
GPIO17 PULL-UP +3.3VS O HIGH-Z HI HI OFF OFF
GPIO18 PULL-UP +3.3VS O HI DEFINED OFF OFF
GPIO19 -ENABKL_MASK +3.3VS O HI HI DEFINED OFF OFF MASK ENABLE
GPIO20 -CDROM_PWRON +3.3VS O HI HI DEFINED OFF OFF Control CDROM Power on
GPIO21 -HDD_PWRON +3.3VS O HI HI DEFINED OFF OFF Control HDD Power on
GPIO22 DRAMENA +3.3VS O HIGH-Z HIGH-Z DEFINED OFF OFF DRAM Data select
GPIO23 PULL-UP +3.3VS OD LOW LOW DEFINED OFF OFF
GPIO24 -1394WR +3.3VA O HIGH-Z HI DEFINED DEFINED DEFINED 1394EEPROM R/W
GPIO25 -PCIRST_MSK +3.3VA O HIGH-Z HI DEFINED DEFINED DEFINED MASK PCIRST
GPIO27 -GATE1394 +3.3VA O HIGH-Z HI DEFINED DEFINED DEFINED RST CARD BOARD
GPIO28 SPK_OFF +3.3VA O HIGH-Z HI DEFINED DEFINED DEFINED OFF SPEAKER
28
1.3.9 Power Consumption Of Suspend Mode

Suspend To RAM<TBD
Suspend To Disk/Soft-Off/Mechanical Off<TBD
1.3.10 Clock Harmonic List

Clock Harmonic
Unit: M
12.288 14.318 16 24 24.576 25 27 32.758 33 48 65 66 100 133
1 12.288 14.318 16 24 24.576 25 27 32.758 33 48 65 66 100 133
2 24.576 28.636 32 48 49.152 50 54 65.516 66 96 130 132 200 266
3 36.864 42.954 48 72 73.728 75 81 98.274 99 144 195 198 300 399
4 49.152 57.272 64 96 98.304 100 108 131.032 132 192 260 264 400 532
5 61.44 71.59 80 120 122.88 125 135 163.79 165 240 325 330 500 665
6 73.728 85.908 96 144 147.456 150 162 196.548 198 288 390 396 600 798
7 86.016 100.226 112 168 172.032 175 189 229.306 231 336 455 462 700 931
8 98.304 114.544 128 192 196.608 200 216 262.064 264 384 520 528 800 1064
9 110.592 128.862 144 216 221.184 225 243 294.822 297 432 585 594 900 1197
10 122.88 143.18 160 240 245.76 250 270 327.58 330 480 650 660 1000 1330
11 135.168 157.498 176 264 270.336 275 297 360.338 363 528 715 726 1100 1463
12 147.456 171.816 192 288 294.912 300 324 393.096 396 576 780 792 1200 1596
13 159.744 186.134 208 312 319.488 325 351 425.854 429 624 845 858 1300 1729
14 172.032 200.452 224 336 344.064 350 378 458.612 462 672 910 924 1400 1862
15 184.32 214.77 240 360 368.64 375 405 491.37 495 720 975 990 1500 1995
16 196.608 229.088 256 384 393.216 400 432 524.128 528 768 1040 1056 1600 2128
17 208.896 243.406 272 408 417.792 425 459 556.886 561 816 1105 1122 1700 2261
18 221.184 257.724 288 432 442.368 450 486 589.644 594 864 1170 1188 1800 2394
19 233.472 272.042 304 456 466.944 475 513 622.402 627 912 1235 1254 1900 2527
20 245.76 286.36 320 480 491.52 500 540 655.16 660 960 1300 1320 2000 2660
21 258.048 300.678 336 504 516.096 525 567 687.918 693 1008 1365 1386 2100 2793
22 270.336 314.996 352 528 540.672 550 594 720.676 726 1056 1430 1452 2200 2926
23 282.624 329.314 368 552 565.248 575 621 753.434 759 1104 1495 1518 2300 3059
24 294.912 343.632 384 576 589.824 600 648 786.192 792 1152 1560 1584 2400 3192
25 307.2 357.95 400 600 614.4 625 675 818.95 825 1200 1625 1650 2500 3325
29
26 319.488 372.268 416 624 638.976 650 702 851.708 858 1248 1690 1716 2600 3458
27 331.776 386.586 432 648 663.552 675 729 884.466 891 1296 1755 1782 2700 3591
28 344.064 400.904 448 672 688.128 700 756 917.224 924 1344 1820 1848 2800 3724
29 356.352 415.222 464 696 712.704 725 783 949.982 957 1392 1885 1914 2900 3857
30 368.64 429.54 480 720 737.28 750 810 982.74 990 1440 1950 1980 3000 3990
31 380.928 443.858 496 744 761.856 775 837 1015.5 1023 1488 2015 2046 3100 4123
32 393.216 458.176 512 768 786.432 800 864 1048.26 1056 1536 2080 2112 3200 4256
33 405.504 472.494 528 792 811.008 825 891 1081.01 1089 1584 2145 2178 3300 4389
34 417.792 486.812 544 816 835.584 850 918 1113.77 1122 1632 2210 2244 3400 4522
35 430.08 501.13 560 840 860.16 875 945 1146.53 1155 1680 2275 2310 3500 4655
36 442.368 515.448 576 864 884.736 900 972 1179.29 1188 1728 2340 2376 3600 4788
37 454.656 529.766 592 888 909.312 925 999 1212.05 1221 1776 2405 2442 3700 4921
38 466.944 544.084 608 912 933.888 950 1026 1244.8 1254 1824 2470 2508 3800 5054
39 479.232 558.402 624 936 958.464 975 1053 1277.56 1287 1872 2535 2574 3900 5187
40 491.52 572.72 640 960 983.04 1000 1080 1310.32 1320 1920 2600 2640 4000 5320
1.3.11 Audio Performance

8170 meet all the following items.
Table 1.10 Digital Playback (PC-D-A) for line Output

Test Items Mobile System
Full Scale Output Voltage >=0.7Vrms(3.3V audio)
Sample Frequency Accuracy <=0.1
Frequency Response(44.1ks/sec) 20Hz~15Hz
Frequency Response(48ks/sec) 20Hz~15Hz
Dynamic Range(SNR) >=70dBFSA
THD+N <=-55dBFS
Cross-talk >=50dB
30
Table 1.11 Analog Pass-Through(A-A) for line input to line Output
Frequency Response 20Hz~15kHz
THD+N <=-55dBFS
Cross-talk >=50dB
Table 1.12 Analog Pass-Through(A-A) for Microphone input to line Output

Frequency Response 100Hz~12kHz
THD+N <=-50dBFS
Table 1.13 Digital Recording(A-D-PC) for Microphone input

Full Scale Input Voltage >=100mVrms
Sample Frequency Accuracy <=0.1%
Frequency Response(22.05ks/sec) 100Hz~8.8kHz
THD+N <=-50dBFS
31
1.4 APPENDIX
APPENDIX A WILLAMETTE CPU CORE FEQUENCY SELECTION
Bus Ratio Core Freq LINT[1]#NMI A20M# IGNNE# LINT[0]#/INTR

1/8 800MHz H H H H
1/10 1.00GHz H H L H
1/11 1.10GHz H H L L
1/12 1.2GHz H L H H
1/13 1.3GHz H L H L
1/14 1.4GHz H L L H
1/15 1.5GHz H L L L
1/16 1.6GHz L H H H
1/17 1.7GHz L H H L
1/18 1.8GHz L H L H
1/19 1.9GHz L H L L
1/20 2.0GHz L L H H
1/21 2.1GHz L L H L
1/22 2.2GHz L L L H
1/23 2.3GHz H H H L
1/24 2.4GHz L L L L
32
APPENDIX B VOLTAGE INDENTIFICATION DEFFINITION
VID4 VID3 VID2 VID1 VID0 Vcc_max

1 1 1 1 1 VRM output off
1 1 1 1 0 1.100
1 1 1 0 1 1.125
1 1 1 0 0 1.150
1 1 0 1 1 1.175
1 1 0 1 0 1.200
1 1 0 0 1 1.225
1 1 0 0 0 1.250
1 0 1 1 1 1.275
1 0 1 1 0 1.300
1 0 1 0 1 1.325
1 0 1 0 0 1.350
1 0 0 1 1 1.375
1 0 0 1 0 1.400
1 0 0 0 1 1.425
1 0 0 0 0 1.450
0 1 1 1 1 1.475
0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
0 0 1 0 1 1.725
0 0 1 0 0 1.750
0 0 0 1 1 1.775
0 0 0 1 0 1.800
0 0 0 0 1 1.825
0 0 0 0 0 1.850
33
APPENDIX C FREQUENCY TABLE FOR BCLK[1:0]
BSEL1 BSEL0 Function

L L 100MHZ
L H RSV
H L RSV
H H RSV
LCD CABLE REQUIREMENT

Each differential pair need meet maximum in impedance 100Ω
DC impedance have to meet maximum impedance 5m Ω in each line
Unipac UB 141X01/Hyundai HT14X13/HannStar HSD141PX11 LCD Cable Pin Define
Signal name M/B Pin Number LCD module pin number

LCDVCC 1 1
LCDVCC 2 2
GND 3 3
GND 4 4
GND 5 7
GND 6 10
TX2CLK+ 7 NC
TXCLK+ 8 15
TX2CLK- 9 NC
TRCLK- 10 14
GND 11 13
GND 12 16
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TX2OUT0+ 13 NC
TX2OUT1+ 14 NC
TX2OUT0- 15 NC
TX2OUT1- 16 NC
GND 17 NC
GND 18 NC
TX2OUT2+ 19 NC
TXOUT0+ 20 6
TX2OUT2- 21 NC
TXOUT0- 22 5
GND 23 19
GND 24 20
TXOUT2+ 25 12
TXOUT1+ 26 9
TXOUT2- 27 11
TXOUT1- 28 8
GND 29 NC
GND 30 NC
LCD_ID0 31 NC
+3VS 32 NC
LCD_ID1 33 NC
+3VS 34 NC
LCD_ID2 35 NC
+3VS 36 NC
NC 37 NC
NC 38 NC
NC 39 NC
NC 40 NC
35
LCD Panel Type Link Pin

Unipac 14.1" TFT:UB 141X01 31&32 tied together
Hyundai 14.1" TFT: HT14X13 33&34 tied together
HannStar 14.1" TFT: HSD141PX11 31&32,33&34 tied together
COM N141P1 LCD Cable Pin Define
Signal name M/B pin Number LCD module pin number

LCDVCC 1 1
LCDVCC 2 2
GND 3 3
GND 4 4
GND 5 NC
GND 6 NC
TX2CLK+ 7 20
TXCLK+ 8 12
TX2CLK- 9 19
TXCLK- 10 11
GND 11 NC
GND 12 NC
TX2OUT0+ 13 14
TX2OUT1+ 14 16
TX2OUT0- 15 13
TX2OUT1- 16 15
GND 17 NC
GND 18 NC
TX2OUT2+ 19 18
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TXOUT+ 20 6
TX2OUT2- 21 17
TXOUT0- 22 5
GND 23 NC
GND 24 NC
TXOUT2+ 25 10
TXOUT1+ 26 8
TXOUT2- 27 9
TXOUT1- 28 7
GND 29 NC
GND 30 NC
LCD_ID0 31 NC
+3VS 32 NC
LCD_ID1 33 NC
+3VS 34 NC
LCD_ID2 35 NC
+3VS 36 NC
NC 37 NC
NC 38 NC
NC 39 NC
NC 40 NC
37
DISPLAY Link Pin

COM 14.1" SXGA+N141P1 35&36 tied together
LCD Panel ID Define Table
LCD Panel LCD_ID2 LCD_ID1 LCD_ID0

Uniqac 0 0 1
Hyundai 0 1 0
HannStar 0 1 1
CMO 1 0 0
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1.5 BIOS Specification

1.5.1 BIOS Feature
@ Inside BIOS for Intel 845 + ICH2 chipset
@ 256KB flash ROM
@ ACPI 1.0b Compliant (S1, S3, S4, S4BIOS)
@ Support APM 1.2 (POS, STR, STD)
@ SMBIOS 2.3.1
@ Support external 1.44MB USB Floppy
@ Support DVD-ROM and CD-ROM
@ Support Multi-boot function
@ Plug & Play for Devices
@ Support FIR
@ Silence Boot with Logo customized
@ Wake-up from USB
@ Fast boot bypass RAM/Floppy/CDROM testing
@ BIOS Lock function
Add the BIOS lock string at shadow memory address F000:E0C2
39
1.5.2 Component&Drives
Please refer to the chapter of Power Management for state definitions. For PCI and PnP terms, please refer to
respective specifications
1.5.2.1 CPU
@ Intel Pentium 4 Processors Willamette//Northwood, Support upto 1.7GHz, 400 Mhz FSB
@ Pentium 4 with 256K L2 Cache
@ 64Kbyte on-chip L1 Cache
@ CPU’s Power transition (Please refer to the chapter of Power Management for state definitions)
When in G0/Full-On, CPU can be in C0/C1/C2.
When in G1(STR)/G2(STD)/G3(Mechanical Off) State, CPU power is removed.
1.5.2.2 Memory System

@ Two SODIMM for SDRAM extension from 64MB to 512MB Pentium 4 with 256K L2 Cache
@ 400MHz Host Bus, 33MHz PCI Bus, 133MHz Memory Clock
@ Dynamically row power-down
@ Support Auto-refresh and Self-refresh command
@ Auto-detect CAS latency Programming
@ Memory Auto-sizing
@ 1/2/4 Bank SDRAM support, up to 4 page could open at any time
40
1.5.2.3 PCI Devices
@ USB
---4 USB port are built in SB chipset (only 2 are supported in this model)
---Wake up from USB device is supported on POS/STR
@ VGA
---LCD panel could be turn on/off via function hotkey, or Lid switch if users define “Blank LCD” on cover
closed in SCU.
---When in G0/Full-On/Idle, VGA stays in D0 state, Panel stays on. However, if no VGA activities detected
for a specific period defined in SCU, VGA will go to D1 state, and Panel will be turned off.
---When in G2/G3/STD/Soft-Off/Mechanical Off State, VGA and Panel are power off.
---When in G1/Standby, VGA stays in D2 state, Panel stays off, Hsync/Vsync is cut.
---When in G1/STR, VGA stays in D3 state, Panel stays off, Hsync/Vsync is cut, especially, Note: VRAM
is shared on system DRAM, so no special circuit is provided for VRAM refresh when G1/STR.
@ AUDIO
---When in G0/Full-On/Idle, Audio stays in D0 state
---When in G2/G3/STD/Soft-Off/Mechanical Off State, Audio is power off.
@ MODEM
---Ring wake-up supported in G1/Standby/Suspend states.
---When in G0/Full-On/Idle, Modem stays in D0 state
---When in G2/G3/STD/Soft-Off/Mechanical Off State, Modem is power off.
@ PMCIA(TI4410)
---PME# supported
41
---When in G0/Full-On/Idle, PCMCIA stays in D0 state if PC card is inserted, and stays in D2 state once PC
card is removed.
---When in G2/G3/STD/Soft-Off/Mechanical Off State, PCMCIA is power off.
---When in G1/Standby, PCMCIA stays in D1 state.
---When in G1/Suspend, PCMCIA stays in D3 state.
@ IEE1394(TI4410)
--- PME# supported
@ LAN(RTL8139CL)
---PME# supported
PCI Devices IDSEL

PCI Device IDESL Register Setting Bus/ Device/ Function
Intel 845 00 / 00 / 00
P2P (NB) 00 / 01 / 00
P2P (SB) AD14 00 / 30 / 00
LPC Bridge AD15 00 / 31 / 00
IDE AD15 00 / 31 / 01
USB #1 AD15 00 / 31 / 02
SMB AD15 00 / 31 / 03
USB #2 AD15 00 / 31 / 04
AC’97 AD15 00 / 31 / 05
MC’97 AD15 00 / 31 / 06
VGA 01 / 00 / 00
LAN AD18 02 / 02 / 00
PCMCIA AD19 02/ 03 / 00
IEEE 1394 AD19 02/ 03 / 01
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PCI IRQ Routing
CI Device PIRQ A PIRQ B PIRQ C PIRQ D PIRQ H PFA Bus/ Device/
Function
Intel 845 0x0000 00 / 00 / 00
P2P (NB) 0x0008 00 / 01 / 00
P2P (SB) 0x00F0 00 / 30 / 00
LPC Bridge 0x00F8 00 / 31 / 00
IDE 0x00F9 00 / 31 / 01
USB #1 INT D# 0x00FA 00 / 31 / 02
SMB 0x00FB 00 / 31 / 03
USB #2 INT C# 0x00FC 00 / 31 / 04
AC’97 INT B# 0x00FD 00 / 31 / 05
MC’97 INT B# 0x00FE 00 / 31 / 06
VGA INT A# 0x0100 01 / 00 / 00
LAN INT A# 0x0210 02 / 02 / 00
PCMCIA INT A# 0x0218 02/ 03 / 00
IEEE 1394 INT B# 0x0219 02/ 03 / 01
1.5.2.4 PCI Device

@ Plug & Play Interface
---Plug and Play BIOS Spec. Rev. 1.0A Compliant
---No ESCD supported
@ RTC
---User could setup current date and time in SCU. RTC must be Y2K compliant
---User could also setup a RTC wake-up event at any time of a month.
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@ DMA
---ECP/FIR also use DMA but they are programmable
@ PIC
---IRQ0 is used by the system timer
---IRQ1 is used by KBC (Key Board Controller)
---IRQ2 is used by slave PIC
---IRQ3 is used by IR
---IRQ5 is used by Audio
---IRQ7 is used by LPT port
---IRQ8 is used by RTC (Real Time Clock)
---IRQ9 is shared by SCI
---IRQ10 is used by LAN
---IRQ10 is used by PCMCIA
---IRQ10 is used by IEEE 1394
---IRQ10 is also shared by VGA
---IRQ12 is used by mouse
---IRQ13 is used internally by CPU to recognize FPU interrupts
---IRQ14 is used by IDE channel 1
---IRQ15 is used by IDE channel 2
---Preserve two IRQs (4, 6, 11) for other devices to use.
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@ Super I/O
---SIO chip could enter a full power down mode once system enter Suspend states
---Printer Port
Print port will enter power down mode when G1/G2/G3/STD/Suspend/Standby state.
---IR Port
IR port will enter power down mode and IR module’s power will be cut off when G1/G2/G3/STD/
Suspend/Standby state.
@ KBC
---H8 will automatically control its power state. Please refer to KBC’s specification
1.5.2.5 IDE Devices
@ Hard Disk
---HD will enter standby mode whenever no access request is made.
---HD will enter standby mode when the system entering Standby state.
---HD will enter sleep mode when the system entering Suspend state.
@ CDROM
---CD drive will enter standby mode whenever no access request is made.
---CD drive enter standby mode when the system entering Standby state.
---CD drive enter sleep mode when the system entering Suspend state
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1.5.2.6 AC’97 Device
@ AC’97 Interface
@ Audio Codec
---Enter the most power saving state during Suspend.
@ Modem Codec
---Enter the most power saving state during Suspend
1.5.2.7 SMB
(1) South Bridge SMB BUS
@ SMBUS Device
SMB Device Read Addr Write Addr
SDRAM 0 0xA1 0xA0
SDRAM 1 0xA1 0xA0
CLK_GEN 0xD3 0xD2
@ SDRAM
---Use SMB link to read configuration data from SDRAM
---Turn off clock if no SO-DIMM insert automatically when POST
@ Clock Generator
---Spread spectrum is enabled during POST
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(2) H8 SMB BUS
@ Battery Pack
---This is polling by KBC (H8)
@ Thermal Sensor
---Sensed by H8
@ Charger
---Directly controlled by H8, please refer to KBC specification
1.5.2.8 Mechanics
@ Button
---1 Power Button, 5 Easy Start Buttons, 1 E-Mail Received Button.
@ LID Switch
---See 1.6.7
@ LEDs
---All LEDs are controller via H8, Please refer to H8 Specification
@ FAN
---Controlled by H8
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1.5.3 BIOS Setup
1.5.3.1 Introduction
SCU allows you to configure the BIOS settings. Those settings are vital for your notebook to identify the
types of installed devices as well as to utilize special features. Typical menu items include Date and Time,
the types of disk drives, and IDE settings. Special features include Power Saving and Password settings
The settings information is stored in the CMOS (Complementary Metal Oxide Semiconductor) RAM,
which is powered by a RTC backup battery.
You may need to run SCU when
* You see an error message on the screen requesting you to run SCU
* You want to restore the factory default settings
* You want to modify some specific settings
1.5.3.2 Starting SCU

SCU is built into the system board. To run SCU, press [F2] during system startup. The main SCU screen
appears as shown in Figure 1.15.
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Insyde Software SCU Aug 23, 2001 2:34:12 pm

Startup Memory Disks Components Power Exit
Devices System
Primary Master = 0 MB CPU = Pentium 4
Primary Slave = 0 MB CPU Speed = 0 MHz
Secondary Master= 0 MB
Secondary Slave = 0 MB
Serial Port 2 = COM2, 2F8, IRQ3
Parallel Port = LPT1, 378, IRQ 7 Memory
Base = 640 KB
Extended = 64512 KB
Shadow = 176 KB
Reserved = 208 KB
Total RAM = 65536 KB
Cache (Ext) = 256 KB
Press <Alt> Key to activate menus, and cursor keys to navigate. Mouse left
button, spacebar, and <Enter> keys accept menu item. Mouse right button and
<Esc> key cancel current action.
Figure 1.16 Main SCU Screen
The SCU screen can be divided into three areas:
@ On the top line of the screen is the menu bar, which lists the titles of the available menus Each menu title
contains a pull-down menu, which displays items for settings
@ The middle section of the screen displays current settings of the system. If you open a pull-down menu
and select an item that provides multiple options, a submenu will pop up and let you make further
selections.
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@ The bottom window provides alternative information. Normally it gives the keyboard/mouse instructions
for moving around and making selections. When a menu item is highlighted, the window will provide
more detailed description of the item.
1.5.3.3 Moving Around and Making Selections
You must go through two or three levels to complete the setting for an item. In most cases, there are three
levels: menu title, pull-down menu, and submenu.
To move around and make selections, you can use both the touch pad/mouse and keyboard
@ Using the Touch pad/Mouse

You are advised to use the touch pad or mouse. It is more straightforward than using the keyboard.
For most items, simply move the pointer with the touch pad/mouse and left-click on the intended item.
To cancel your selection, click the right button. For some items, you will need to select with the arrow
keys.
@ Using the keyboard

Keyboard information can be found at the bottom of the screen. You can also use the shortcut key, which
is highlighted in a different color on the screen.
Described below is the general procedure to complete a setting by use of the keyboard:
® Select a menu title with the left/right arrow key and press [Enter] to pull down the menu. You can
directly pull down a menu You can directly pull down a menu by pressing [Alt] and the shortcut key.
® From the pull-down menu, select an item with the up/down arrow key and press [Enter] to access the
submenu or change the setting, The submenu displays further options that you can select.
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® For most menu items, pressing the [Tab] key will jump from one item to another, thus allowing you to
go through the items quickly. To confirm the changes you make, press [Enter] or select the OK button.
To cancel the changes, press [Esc] or select the Cancel button.
1.5.3.4 Startup Menu
The Startup pull-down menu, as shown below, contains some basic configuration and password settings of
the system
Startup
Date and Time >
Splash Boot Logo
√ Fast Boot
Boot Device >
Set Admin password >
Set User password >
SCU Color Scheme >
@ Data and time

The “Date and Time” item sets the system date and time. When this item is selected, the submenu will
display as shown below:
Date and Time
Day 23 Hour 16
Month 8 Minute 56
Year 2001 Second 53
OK Cancel
OK Cancel
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@ Splash Boot Logo
The “Splach boot Logo” item to enable or disable the big boot logo on screen when system is booting.
When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline
(_) indicates Disabled. The default setting is Disabled
@ Fast Boot
The “Fast Boot” item, when enabled, speeds up the booting procedure by bypassing the memory test.
(_) indicates Disabled. The default setting is Enabled.
@ Boot Device
The “Boot Device” item sets the sequence of booting device. When this item is selected, the submenu
will display as shown below.
Boot Device
1st Boot Device 2nd Boot Device 3rd Boot Device
( ) Hard Disk C (.) Hard Disk C ( ) Hard Disk C

( ) CD-ROM Drive ( ) CD-ROM Drive (.) CD-ROM Drive
(.) Diskette A ( ) Diskette A ( ) Diskette A
OK Cancel
OK Cancel
The default setting is Diskette A, Hard Disk C, then CD-ROM Drive
NOTE: If you set all booting options to the same device (say, Hard Disk C),. then the notebook will try to
boot from that device only
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@ Set Admin Password
This item lets you set up administrator-level password. When this item is selected, the submenu will
display as shown below:
Set Admin password
Enter old ADMIN Password: ..........
Enter new ADMIN Password: ..........
Verify new ADMIN Password: ..........

Verify password when...
[X] Boot System

[ ] Enter SCU
OK Cancel
OK Cancel
You can directly enter the new password if no password has previously existed. If a password has been
previously set up, you have to enter the correct old password before setting up a new one. In either case,
you have to enter the new password twice to complete the setting.
NOTE:
1. If you want to clear a previous password, you can enter the old password and leave the following fields
blank
2. The administrator password is required for booting and entering SCU, so the “Verify password when
…” setting can not be changed
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@ Set User Password
This item lets you set up user-level password. When this item is selected, the submenu will display as
shown below:
Set User password
Enter old User Password: ..........
Enter new User Password: ..........
Verify new User Password: ..........

Verify password when...
[X] Boot System

[ ] Enter SCU
OK Cancel
OK Cancel
The procedure to set up the user password is the same as “Set Admin Password”.
NOTE:
1. You can not set up the user password unless the administrator password has been set up.
2. If both the administrator and user passwords are set up, only one password is required to boot the
system
3. To modify the SCU settings, you have to enter the administrator password. The user password only
allows you to browse the settings.
4. If the “Resume System” item is checked, the password is required only when the system is restored
from “Suspend-to-disk” status.
54
@ SCU Color Scheme
The “Splach boot Logo” item select color set for your viewing. When this item is selected, the submenu
will display as shown below:
SCU Color Scheme
Select Color:
(.) Color
( ) Alternate Color
( ) Black and White
( ) Reverse Black and
OK Cancel
OK Cancel
The default setting is “Color”.
1.5.3.5 Memory Menu

Memory
Cache Systems >
@ Cache System
Cache Systems
L1 Cache L2 Cache
( ) Disabled ( ) Disabled
(.) Write Back (.) Write Back
OK Cancel
OK Cancel
The default settings of the “L1 Cache” and “L2 Cache” are “Write Back”. 55
1.5.3.6 Disk Menu
Disks
√ Internal HDC
√ IDE Setting >
Virus Alert >
@ Internal HDC
The “Internal HDC” item sets if an internal hard drive is present.
(_) indicates Disabled
The default setting is Enabled
@ IDE Setting
The “IDE Settings” item sets the type of the hard disk drive in your system. When this item is selected,
the submenu will display as show below:
IDE Settings
HDD Timing I/O 32 bit transfer

( ) Standard ( ) Disabled
( ) Fast PIO (.) Enabled
( ) Multiword DMA
( ) Ultra DMA-33 HDD Block transfer
(.) ATA-66/100
( ) Disabled
(.) Enabled
OK Cancel
OK Cancel
56
The “HDD Timing” item sets the data transmit mode of the hard drive. The default setting is Ultra DMA-33
The “I/O 32 bit transfer” item, if enabled, allows you to have better data transfer rate. This effect is more
noticeable under DOS system. The default setting is Enabled
The “HDD Block transfer” item, if enabled, allows you to use hard disk with large capacity. The default
setting is Enabled
@ Virus Alert
The “Virus Alert” item, when enabled, gives warning messages if the hard disk boot sector (partition
table) has been changed
(_) indicates disabled
The default setting is Disabled.
1.5.3.7 Components
Components
COM Ports >
LPT Port
√ PS/2 Mouse Port
Legacy Usb >
√ Keyboard Numlock
Keyboard Repeat >
@ COM Ports
The “COM Ports” item sets the settings of COM Port A and B. When this item is selected, the submenu
57
COM Ports
COM B I/O Settings Mode Setting For COM B

( ) Disabled ( ) IrDA (HPSIR)
( ) COM1, 3F8, IRQ4 ( ) ASK IR
(.) COM2, 2F8, IRQ3 (.) FAST IR
( ) COM3, 3E8, IRQ4
( ) COM4, 2E8, IRQ3 DMA Setting For Fast IR
(.) DMA 0
( ) DMA 1
( ) DMA 3
OK Canel
OK Canel
COM B is assigned to IR function. You can further select the IR mode in “Mode Setting for COM B”
item and DMA channel in“DMA Setting For Fast IR” when you select “Fast IR” in the mode setting.
@ LPT Ports
The “LPT Port” item sets the settings of LPT port. When this item is selected, the submenu will display
as shown below:
58
LPT Port
Port Address Port Definition

( ) None ( ) Standard AT (Centronics)
(.) LPT1, 378, IRQ7 ( ) Bidirectional (PS-2)
( ) LPT2, 278, IRQ5 ( ) Enhanced Parallel (EPP)
( ) LPT3, 3BC, IRQ7 (.) Extended Capabilities (ECP)
DMA Setting For ECP Mode

(.) DMA 0
( ) DMA 1
( ) DMA 3
EPP Type : EPP 1.7
OK Cancel
OK Cancel
Your system supports EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port) standards
which turn the standard parallel port into a high speed bi-directional peripheral port. If you select ECP
item, you can further choose which DMA channel to use.
@ PS/2 Ports
The “PS/2 Mouse Port” item enables or disables the PS/2 mouse port
(_) indicates Disabled. The default setting is enabled.
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@ Legacy USB
The “Legacy USB” item sets the settings of legacy USB port which enables or disables the USB keyboard,
USB mouse, USB floppy and USB CD-ROM in DOS and SCU. When this item is selected, the submenu
Legacy USB
[X] Enable USB Port
[X] Enable USB FDD

[ ] Enable USB CDROM
OK Cancel
OK Cancel
The “Enable USB Port” item enables or disables USB keyboard and USB mouse. The default setting is
enabled
The “Enable USB FDD” item enables or disables USB FDD. The default setting is enabled.
The “Enable USB FDD” item enables or disables boot from USB CDROM. The default setting is disabled
@ Keyboard Numlock
Keyboard Numlock” item sets if the numeric keypad will function
(_) indicates Disabled. The default setting is Enabled.
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Note: If you disable this option, you can only activate the numeric keypad by holding down the [Fn] key
first, even when the Num Lock indicator is on. However, an externally-connected keyboard is not
affected by this feature.
@ Keyboard Repeat
The “Keyboard Repeat” item sets the repeat rate and delay time of key strokes. When this item is
selected, the submenu will display as shown below:
Keyboard Repeat
Key Repeat Rate Key Delay
( ) 2 cps ( ) 1/4 sec

( ) 6 cps (.) 1/2 sec
(.) 10 cps ( ) 3/4 sec
( ) 15 cps ( ) 1 sec
( ) 20 cps
( ) 30 cps
OK Cancel
OK Cancel
The “Key Repeat Rate” sets the repeat rate when you hold down a key, while the “Key Delay” item sets
the delaying time between key repeats
61
1.5.3.8 Power Menu
The Power pull-down menu, as shown below, contains the Power Management settings which help save
power
Power
√ Enable Power Saving
Low Power Saving
Medium Power Saving
High Power Saving
√ Customize >
Suspend Controls >
Resume Timer >
@ Enable Power Saving

The “Enable Power Saving” item is the master control for the Power Management features. If this item
is disabled, all Power menu items except “Suspend Controls” will be automatically disabled.
(_) indicates Disabled. The default setting is enabled
@ Low Power Saving / Medium Power Saving / High Power Saving / Customize
four items are mutually-exclusive options. You can select one of them. A check mark (√) indicates
Enabled; an underline (_) indicates is enabled an underline (_) indicates Disabled
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Descriptions of the four options are:
Options Descriptions
Max Performance Select this option for the pre-defined settings which allow maximum
performance but shortest battery life.
Balanced Power Saving Select this option for the pre-defined settings which allow moderate
performance and moderate battery life.
Max Power Saving Select this option for the pre-defined settings which allow longest
battery life but minimum performance.
Customize Select this option for setting up your own preferences. When this
option is selected, the submenu will display as shown below that
allows you to set up Power Saving features. (See the next subsection
for information.)
Note: Under Windows98/Windows Me/Windows2000, have built-in ACPI configurations which will
override these settings When the “Customize” item is selected, the submenu will display as
shown below:
Customize
Video Timeout: Always On

Disk Timeout: Always On
Global Timeout: Always On
Monitor Video Activity: Disabled
OK Cancel
OK Cancel
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Video Timeout :
The “Video Timeout” item sets the time-out period for the monitor to power down if it is not in use
during the set period. The monitor will power up again when any key is pressed.
The available options are 30 Sec, 2 Min, 5 Min, 10 Min, 15 Min, 30 Min and Always On.
Disk Timeout:
The “Disk Timeout” item sets the time-out period for the hard disk to power down if it is not in use during
the set period. The hard disk will power up again when next accessed.
The available options are 30 Sec, 1 Min, 1.5 Min, 2 Min, and Always On.
Global Timeout:
The “Global Timeout” item sets the time-out period for initiating Standby mode. Whenever the system.
begins idling, the Power Saving starts the time-out for the Standby mode. If the system has been idled for
the specified time-out period, system will enter Standby mode.
If Standby mode is in effect, several system subsystems go into standby or off mode so that system power
will be reduced. The system will wake up from Standby mode when system activity is detected.
The available options are 1 Min, 2 Min, 4 Min, 6 Min, 8 Min, 12 Min, 16 Min, and Always On.
Monitor Video Activity

The “Monitor Video Activity” item sets if the video activity will be monitored. If enabled, any activity on
the screen (such as showing a movie title) will prevent the monitor from powering down.
The available options are Enabled and Disabled.
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@ Suspend Controls
The “Suspend Controls” item lets you micromanage several suspend features. When this item is selected,
the submenu will display as shown below:
Suspend Controls
Power Button Function: Power On/Off
Lid Switch Function: Blank LCD
Suspend type
( ) Suspend To Disk
(.) Suspend To Ram
Suspend Timeout: Never

Suspend-to-disk: Never
OK Cancel
OK Cancel
Power Button Function :

This item sets the function of the power button. The available options are Power On/Off and Suspend/
Resume.
Note: When this item is set to “Suspend/Resume”, you can turn off the power by pressing the button for 4
seconds.
Lid Switch Function :

This item sets the sequential event when the top cover is closed while power is on. The available options
are Blank LCD, Suspend and CRT/TV Display.
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Suspend Type:
This item sets the suspend mode the system will enter. The available options are Suspend To Disk,
Suspend To RAM.
When Suspend-to-RAM mode is initiated, several subsystems will enter standby or power-off mode
to conserve power. The system will wake up from Suspend-to-RAM mode when a key is pressed. “
Resume Timer”, if enabled, can also wake up the system from Suspend-to-RAM mode.
When Suspend-to-Disk mode is initiated, the system preserves all the running application programs as a
file in a “suspend-to-disk partition” on the hard disk and then turns off automatically.
Suspend Timeout :
The “Suspend Timeout” item sets the time-out period for initiating suspend mode. This item works in
conjunction with previous "Global Timeout" item. When the system enters standby mode, the Power
Saving starts the time-out for the Suspend mode. If the system has been in standby mode for the specified
time-out period, system will enter Suspend mode.
The Suspend mode is determined by the “Suspend Type” item in the “Suspend Controls” submenu. It
can be Suspend-to-RAM, Suspend-to-Disk.
The available options are 1 Min, 5 Min, 10 Min, 20 Min, 20 Min, 30 Min, and Never.
Suspend-to-disk:
The “Suspend-to-disk” item sets the time-out period for initiating suspend-to-disk mode. This item works
in conjunction with previous "Suspend Timeout" item. When the system enters suspend-to-ram mode, the
Power Saving starts the time-out for the Suspend-to-disk mode. If the system has been in suspend-to-ram
mode for the specified time-out period, system will enter suspend-to-disk mode.
The available options are 1 Min, 5 Min, 10 Min, 20 Min, 30 Min, and Never.
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@ Resume Timer
The Resume Timer” item sets the date and time the system will resume from suspend mode. When this
item is selected, the submenu will display as shown below :
Resume Timer
Alarm Resume : Disable

Resume Month 8
Resume Day 8
Resume Hour 12
Resume Minute 0
OK Cancel
OK Cancel
The default setting is Disabled
1.5.3.9 Exit Menu

The Exit pull-down menu, as shown below, displays ways of exiting SCU. After finished with your
settings, you must save and exit SCU so that the settings can take effect
Exit
Save and Exit >
Exit (No Save) >
Default Settings >
Restore Settings >
Version Info >
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Descriptions of the Exit choices are:
Choices Descriptions
Save and Reboot Save changes and reboot the system.
Exit (No Save) Exit without saving the changes you have made.
Default Settings Load factory default values for all the items.
Restore Settings Restore previous values for all the items.
Version Info Show BIOS version information
1.5.4 Function Hotkeys
Fn + F5 Toggle display output. The display switch sequence, please refer to chapter 6
Fn + F6 Brightness Down (16 levels)
Fn + F7 Brightness Up (16 levels)
Fn + F10 Enable/Disable battery warning beep
Fn + F11 Panel on/off
Fn + F12 Suspend to RAM or disk
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1.5.5 Display Out
When you boot the system with CRT, display output is LCD&CRT mode.
When boot with CRT, the display switch sequence by hotkey FnF5 is as following:
LCD&CRT->LCD->CRT
When boot with CRT and TV, the display switch sequence by hotkey FnF5 is as following:
LCD&CRT->TV&CRT->TV->LCD->CRT
1.5.6 LID
@ In Non-ACPI Operating System:
LID switch function is dependent on the setting in BIOS setup menu.
“Blank LCD” - LCD will be blank when LID is closed.
Before LID is closed LID is closed LID is opened

LCD is active LCD is blank LCD is active
LCD is blank LCD is blank LCD is blank
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“Suspend” -system will enter suspend mode when LID is closed.

System is On System enters Suspend System still in Suspend
System in Suspend System still in Suspend System still in Suspend
“CRT/TV Display” -display will be switched to CRT/TV when LID is closed.

When the LID is closed, the LCD will be inactive and external display device will be active.
When the LID is opened, the display devices status (active/inactive) will be restored to the
state before the LID is closed.
Some special conditions are list below.

LCD (active) LCD (inactive) LCD (active)
CRT (present, inactive) CRT (active) CRT (inactive)
TV(present, inactive) TV(inactive) TV(inactive)
LCD (inactive) LCD (inactive) LCD (active)
CRT/TV is present CRT/TV is plugged out CRT/TV is not present
@ In ACPI Operating System:

The LID switch function is dependent on the setting of the Power Management in the operating system.
70
1.5.7 VGA Resolution of Windows 98/Me Driver

(Need Modifying via VGA Driver)
LCD(LCD&CRT)
Resolution Color
640*480 256, 16bit, 32bit
800*600 256, 16bit, 32bit
1024*768 256, 16bit, 32bit
CRT(TV)
Resolution Color
640*480 256, 16bit, 32bit
800*600 256, 16bit, 32bit
1024*768 256, 16bit, 32bit
1280*1024 256, 16bit
1600*1200 256, 16bit
TV(TV+CRT)
Resolution Color
640*480 256, 16bit, 32bit
800*600 256, 16bit, 32bit
71
1.5.8 LED Indicators

System has nine status LED indicators to display system activity which include below LCD panel unit and
above keyboard:
1.5.8.1 Three LED indicators below LCD panel unit:

From left to right that indicate AC POWER, BATTERY POWER and BATTERY STATUS
® AC POWER: This LED lights green when the notebook is being powered by AC, and flash (on 1
second, off 1 second ) when Suspend to DRAM is active using AC power. The LED is off when the
notebook is off or powered by batteries, or when Suspend to Disk.
® BATTERY POWER:This LED lights green when the notebook is being powered by batteries, and
flashes (on 1 second, off 1 second ) when Suspend to DRAM is active using battery power. The LED
is off when the notebook is off or powered by AC, or when Suspend to Disk.
® BATTERY STATUS:During normal operation, this LED stays off as long as the battery is charged.
When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps
per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged, or
orange (amber) if the battery is being charged.
1.5.8.2 Five LED indicators in front of palm rest:

From left to right that indicates CD-ROM/MO, HARD DISK DRIVE, , NUM LOCK, CAPS LOCK and
SCROLL LOCK.
72
1.5.8.3 Mail/Blue-Tooth LED indicators in front of palm rest:
The left side green LED flashing means new mail coming. Otherwise the LED is always OFF. The right
side red LED ON means Blue-Tooth module turn ON.
1.5.9 Power Management
1.5.9.1 Features
® APM 1.2/1.1/1.0 compliant
® Battery warning beep
® Battery low suspend to RAM/disk
® Cover switch close to panel off, standby, or suspend
® Hot-key suspend
® Hot-key panel on/off
® Auto clock throttling to prevent overheating
® ACPI 1.0 compliant
® User programmable standby/suspend timers and sustained events when OS doesn’t support APM/ACPI
1.5.9.2 Device power state

Note: Each device power states are described in the chapter titled Components & Drives. Please refer to
those paragraphs. BIOS will not automatically manage devices’ power states if ACPI engaged or APM
engaged but disabled.
73
1.5.9.3 System power state
Definitions when ACPI engaged
Global States:
G0 – Global system is working
G1 – Global system is sleeping
G3 – Global system is mechanical-off
Suspend States:
S1 – CPU stop, no system context lost
S2 – CPU stop, no system context lost except CPU & cache’s context is lost
S3 – CPU stop, the whole system context lost except system memory content is maintained
S4 – CPU stop, all system context saved to nonvolatile media before lost.
S5 – Soft Off
CPU States:
C0 – CPU is working
C1 – CPU is in Auto Halt Mode
C2 – CPU is in Quick Start Mode, the system will maintain the cache coherency
C3 – CPU is in Deep Sleep Mode, the system must disable any event which could make the cache
lost coherency. This model is not support C3 mode.
74
1.5.9.4 Definitions when APM engaged
System States:
Full On -Full running state, the system is in optimized performance
Idle -Clock throttling state, CPU is running between C0 & C2 states
Standby -Same as S1/S2 above
Suspend -Same as S3 above (Including save-to-ram and power-on-suspend)
Save to Disk -Same as S4 above
Note: When Save to Disk partition is not made on disk, BIOS will choose Save to RAM instead of Save to Disk
Enter Condition:
Idle -Entered when CPU Idle Function is called
Standby -Entered when SetPowerState(Standby) Function is called
Suspend -Entered when SetPowerState(Suspend) is called, and user select STR in SCU
Save to Disk -Entered when SetPowerState(Suspend) is called, and user select STD in SCU
Resume Event :
Idle -Resume when CPU Busy Function is called
Standby -Resume only when keyboard device have activities, when ring come in on internal
modem or PCMCIA card. The reason for not selecting track-pad as resume event is that,
it’s too sensitive sometimes
Suspend -Entered when SetPowerState(Suspend) is called, and user select STR in SCU
Save to Disk -Entered when SetPowerState(Suspend) is called, and user select STD in SCU
75
Event Notifications:
Standby -When all the devices have no system activities for a specific time period, BIOS will
inform a standby event once OS calls GetPMEvent Function.
Suspend -When all the devices have no system activities for a specific time period, BIOS will
inform a suspend event once OS calls GetPMEvent Function.
Activities -System activities is defined in SCU one by one. SCU also includes two columns for the
time periods for Standby and Suspend. In addition, Keyboard activity is always one of
the system activities. Whenever any system activities detected, timers for Standby and
Suspend are reloaded into the value specified. By the way, RTC could also
programmable to wake up the system from Standby and Suspend states.
Exception -Note, when APM is disabled, BIOS should disable all timers and not to automatically
power manage devices. Furthermore, the APM BIOS will neither response to CPU Idle
Function, nor recognize the time periods set for Standby and Suspend in SCU.
1.5.9.5 Definitions when no APM or ACPI engaged
System States:
Full On -Full running state, the system is in optimized performance
Idle -No Idle mode support in this situation .
Standby -Same as S1/S2 above
Suspend -Same as S3 above (Including save-to-ram and power-on-suspend)
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Save to Disk -Same as S4 above
Note: When Save to Disk partition isn’t made on disk, BIOS will choose Save to RAM instead of Save to Disk
Resume Event:
Standby -Resume when keyboard/trackpad/PS2 devices have activities, when ring come in on
internal modem or PCMCIA card, or when COM has activities if user select to resume
from COM port
Suspend -Same as resume events for Standby state
Save to Disk -Resume when User push power button
Enter conditions:
-The timers for Standby and Suspend mode when APM engaged are also applied to this
situation that no APM or ACPI engaged.
Special Events:
-Cover switch, or called lid could trigger an event to LCD panel off, Standby(S1/S2), or
Suspend(S3/S4). The exact state triggered is selected in SCU
-Power button is also a resume event for all power saving mode except the Idle state
-When battery capacity is low under 10% while AC is not plug-in, system will begin to
alert via PC speaker. User could also press Fn+F10 to disable/enable the warning beep.
Once the battery capacity is critically under 3%, system BIOS will try to force the whole
system into the STD state.
77
1.5.9.6 Save to disk partition utility
0VMAKFIL.EXE S support partition only

Usage: 0VMAKEFILE.EXE -P<partition size>
< Partition size>= total of system RAM size + total of video RAM size
1.5.9.7 ACPI
@ Custom Software SMI Command for ACPI(Modifying if Need)
(1) 0x81 : Notify BIOS that the system is going to enter S3

(2) 0x82 : Notify BIOS that the system wake up from S3
(3) 0x83 : Get AC Status
(4) 0x84 : Get Battery General Status (_STA)
(5) 0x85 : Get Battery Information (_BIF)
(6) 0x86 : Get Battery Present Status (_BST)
(7) 0x87 : Get Battery Trip Point (_BTP)
78
@ CMOS mapping for ACPI battery control method to use (Modifying if Need)
Index Description Comment

0x40 AC Status Bit0: 0 – AC present
1 – AC not present
0x41 Battery Info 1 Bit0:
Bit1: 0 – NiMH
1 – LiON
0x42 Battery Info 2 Bit0: 0 – Battery not present
1 – Battery present
Bit1:
Bit2: 0 – no force charge
1 – force charge
Bit3:
0x43 Battery Info 3 Bit0: 0 – no trickle charge
1 – trickle charge
0x44~0x45 Last Full Charge Capacity
0x46~0x47 Remaining Capacity
0x48~0x49 Design Capacity
0x4A~0x4B Design Voltage
0x4C SOC1
0x4D Current Voltage
0x4E Battery Trip Point
1.5.10 Post Massage

Reference to 7.2
79
1.5.11 GPIO settings
1.5.11.1 South Bridge
@ GPIO Signal
I/O Address GPIO Register I/O Address Map
GPIO # Multi. Func./Note Type Signal Name / Description Signal Select Register
0 REQ[A]# I
1 REQ[B]#/REQ[5]# I
2 Not Implement N/A
3 PIRQ[F]# I
4 PIRQ[G]# I
5 Not Implement N/A
6 I
7 I
8 I SCI#
9 Not Implement N/A
10 Not Implement N/A
11 SMBALERT# I
12 I EXTSMI#
13 I
16 GNT[A]# O
17 GNT[B]#/GNT[5]# O
18 O
19 O ENABKL_MSK#
20 O CDROM_PWRON#
21 O HDD_PWRON#
80
22 O DRAMENA
23 O
24 I/O 1394WR# GPIOBASE+04 bit24 = 0
25 I/O PCIRST_MSK# GPIOBASE+04 bit25 = 0
27 I/O GATE1394# GPIOBASE+04 bit27 = 0
28 I/O SPK_OFF GPIOBASE+04 bit28 = 0
81
2. System Assembly & Disassembly

2.1 System View

2.1.1 Front View
Stereo Speaker Set
Device Indicators
Mini IEEE1394 Connector
Audio Input Connector

Line Out Phone Jack
Volume Control
Top Cover Latch
2.1.2 Left-Side View

Kensington Lock
Ventilation Openings
RJ-45 Connector
PC Card Slot

Hard Disk Drive
82
2.1.3 Right-Side View

Battery Pack
CD-ROM/DVD-ROM Drive

2.1.4 Rear View
Power Connector
S-Video Output Connector
USB Ports
Parallel Port
D/D Fan
RJ-11 Connector
VGA Port
Ventilation Openings

83
2.1.5 Top-Open View

LCD Screen
Microphone

Keyboard
Touch pad
Power Button

Easy Start Buttons
Battery Charge Indicator
Battery Power Indicator
AC Power Indicator

84
2.2 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.2.1 Battery Pack

2.2.2 Keyboard
Modular Components 2.2.3 CPU
2.2.4 HDD Module
2.2.5 CD/DVD-ROM Drive
2.2.6 SO-DIMM
NOTEBOOK
2.2.7 LCD Assembly
LCD Assembly Components 2.2.8 LCD Panel
2.2.9 Inverter Board
2.2.10 System Board
Base Unit Components
2.2.11 Touch pad
2.2.12 Modem Card
85
2.2.1 Battery Pack

Disassembly
1. Carefully put the notebook upside down.
2. Slide the release lever to the “unlock” ( ) position (), then slide and hold the release lever outwards and
pull the battery pack out of the compartment (). (Figure 2-1)
Figure 2-1 Remove the battery pack
Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.
2. Slide the release lever to the “lock” ( ) position.
86
2.2.2 Keyboard
Disassembly
1. Insert a small rod, such as a straightened paper clip, into the eject hole near the power
connector of the notebook. (Figure 2-2)
Figure 2-2 Insert a rod easy to remove Figure 2-3 Remove LED Panel
LED Panel
2. Open the top cover. Push the rod firmly and slide the LED panel to the left (). Then lift the LED panel up from
the left side () (Figure 2-3)
87
3. Remove three screws fastening keyboard on the base unit cover. (Figure 2-4)
4. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-5)
Figure 2-4 Remove three Screws Figure 2-5 Remove keyboard
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Replace the LED panel.
88
2.2.3 CPU
Disassembly
1. Remove the LED panel and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly.)
2. Remove five screws locking the heatsink cover. (Figure 2-6)
Figure 2-6 Remove the cover Figure 2-7 Remove the heatsink
3. Remove three screws locking the heatsink. (Figure 2-7)
89
4. Disconnect the fan’s power cord from the system board, then lift up the heatsink. (Figure 2-8)
Figure 2-8 Remove the fan’s power cord Figure 2-9 Remove the CPU
5. push the lever to the right. Then lift up the lever to the vertical position. Finally, remove the existing CPU.
Reassembly
1. Carefully, Align the arrowhead corner of the CPU with the beveled corner of the socket, then insert the CPU
pins into the holes. Place the lever back to the horizontal position and push the lever to the left .
2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with
three screws.
3. Replace the keyboard .Then replace LED panel.
90
2.2.4 HDD Module

Disassembly
2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-10)
Figure 2-10 Remove HDD Module Figure 2-11 Disassemble the hard disk
3. Remove six screws to separate the hard disk drive from the metal shield. (Figure 2-11)
Reassembly
1. To install the hard disk drive, place it in the bracket and secure with six screws.
2. Slide the HDD module into the compartment and secure with one screw.
91
2.2.5 CD/DVD-ROM Drive
Disassembly
1. Remove the LED panel and keyboard. (See section 2.2.2 Disassembly.)
2. Remove two screws locking the CD/DVD-ROM drive. (Figure 2-12)
Figure 2-12 Push out the CD/DVD -ROM drive
3. Use the screwdriver to push the metal pad to the right and the CD/DVD-ROM drive will pop out. Hold the
CD/DVD-ROM drive and slide it outwards carefully. (Figure 2-12)
Reassembly
1. Push the CD/DVD-ROM drive into the compartment.
2. Secure the CD/DVD-ROM drive with two screws.
3. Replace the keyboard and LED panel.
92
2.2.6 SO-DIMM
Disassembly
2. Remove four screws to access the SO-DIMM socket.
3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-13,14)
Figure 2-13 Remove the SO-DIMM Cover Figure 2-14 Remove the SO-DIMM
Reassembly
1. To install the SO-DIMM, match the SO-DIMM's notched part with the socket's projected part
and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the
retaining clips lock the SO-DIMM into position.
2. Replace three screws to lock the SO-DIMM socket cover.
93
2.2.7 LCD Assembly
Disassembly
1. Open the top cover. Remove the LED panel, keyboard, and heat sink . (See section 2.2.2 and 2.2.Disassembly.)
2. Pull out the antenna from the CPU compartment.
3. Remove the two hinge covers. (Figure 2-15)
Figure 2-15 Remove the LCD hinge covers Figure 2-16 Remove cables and Screws
to separate LCD
4. Disconnect the LCD cable from the system board, and remove four screws of the hinges. Now you can
separate the LCD assembly from the base unit. (Figure 2-16)
94
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws on the hinges.
2. Reconnect the antenna to the connector on the Mini PCI socket.
3. Reconnect the LCD cable to the system board.
4. Replace the heatsink, keyboard and LED panel.two hinge covers.
5. Replace two hinge covers.
95
2.2.8 LCD Panel

Disassembly
1. Remove the LCD assembly. (See section 2.2.7 Disassembly.)
2. Remove the four rubber pads and four screws on the corners of the panel. (Figure 2-17)
Figure 2-17 Remove LCD frame Figure 2-18 Remove LCD panel
3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out.
Repeat the process until the frame is completely separated from the housing.
4. Remove the two screws on two sides and two screws on the lower part of of the LCD panel, and disconnect the
cable from the inverter board. (Figure 2-18)
Reassembly
1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board.
2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads.
3. Replace the LCD assembly. (See section 2.2.7 Reassembly.) 96
2.2.9 Inverter Board
Disassembly
1. Remove the LCD assembly. (see section 2.2.7 Disassembly. ).
2. Detach the LCD Panel. (See section 2.2.8 Disassembly. )
3. To remove the inverter board on the bottom of the LCD assembly, disconnect the cable and
remove one screw. (Figure 2-19)
Figure 2-19 Remove the Inverter Board
Reassembly
1. Fit the inverter board back into place and secure with one screw.
2. Reconnect the cable.
3. Replace the LCD frame. (See section 2.2.8 Reassembly.)
4. Replace the LCD assembly. (See section 2.2.7 Reassembly.)
97
2.2.10 System Board
Disassembly
1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
(See sections2.2.1; 2.2.2; 2.2.3; 2.2.4; 2.2.5; 2.2.7 Disassembly.)
2. Remove fourteen screws on the bottom of the notebook. (Figure 2-20)
Figure 2-20 Remove the bottom Figure 2-21 Remove the speaker assembly
3. Remove the speaker assembly from the notebook. (Figure 2-21)
98
4. Remove five screws on the rear side of the notebook, and remove three screws locking on the base unit cover.
(Figure 2-22)
Figure 2-22 Remove the base unit cover Figure 2-23 Lift up the base unit cover
5. Lift up the base unit cover and disconnect the touch pad cord. (Figure 2-23)
99
6. Remove two screws fastening the button board on base unit. and then disconnect two cables from the
system board. (Figure 2-23)
Figure 2-23 Remove the screws Figure 2-24 Remove the base unit cover
7. Remove five screws from the system board,and lift up the base unit to access the system board. (Figure 2-24)
Reassembly
1. Replace five screws fastening the base unit
2. Reconnect two cables to the system board.
3. Replace the button board with two screws.
4. Reconnect the touch pad cable and replace the base unit cover.
5. Replace three screws fastening the base unit cover.
6. Replace five screws on the rear side of the notebook.
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7. Replace the speaker assembly.
8. Replace fourteen screws on the bottom of the notebook.
9. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
101
2.2.11 Touch PAD

Disassembly
1. Remove the base unit cover. (See steps 1-6 in section 2.2.11 Disassembly.)
2. Remove the six screws to lift up the touch pad holder and touch pad panel. (Figure 2-25)
Figure 2-25 Remove the touch pad
Reassembly
1. Replace the touch pad holder and touch pad panel, and secure with six screws.
2. Assemble the notebook. (See section 2.2.11 Reassembly.)
102
2.2.12 Modem Card

Disassembly
1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive, and LCD assembly.
(See sections2.2.1; 2.2.2; 2.2.3; 2.2.4; 2.2.5; 2.2.7 Disassembly.)
2. Disassemble the notebook to access the system board. (See section 2.2.10 Disassembly.)
3. Remove the two screws fastening the modem card,and then disconnect the cable from system board. (Figure 2-26)
Figure 2-26 Remove the Modem card
Reassembly
1. Reconnect the cable to the modem card and secure the modem card with two screws.
2. Assemble the notebook. (See section 2.2.10 Reassembly.)
103
3. Definition & Location Connectors / Switches Setting

3.1 Main Board ( Side A)
J1:External VGA Connector

J10
J6 J3 J20 J2:LCD Connector
J28
J3:D/D Board connector
J5 VR1
J4 J11
SW6
J4: Modem Daughter Board to RJ11Connector
J15
J19
J13 J5:Easy Start Button Connector
J22
U1 J12 J16
J21
J6:External USB(PIO,IR,TV OUT)Connector
J1 J14
J2
J18 J7:CPU FAN Connector
J7
J8:Card Bus Socket
J8
J9:RJ45
J10:Secondary EIDE Connector
J9 J11:Modem Daughter Board

J509
J12:Internal Keyboard Connector

J13:RJ11
104

3.1 Main Board ( Side A)
J14:Primary EIDE Connector

J10
J6 J3 J20 J15:Touch PAD Connector
J28
J16:Internal Microphone
J5 VR1
J4 J11 J18:Internal Speaker Connector(L channel)
SW6
J15
J19
J13 J19:Line Out Phone Jack
J22
U1 J12 J16
J21
J20:Internal Speaker Connector(R channel)
J1 J14
J18 J21:Mini IEEE1394 Connector
J2
J7
J22:External Micro Phone Jack
J8 J28:Battery Connector
VR1:Volume regulator
J9
SW6:Switch Cover
J509
105

3.1 Main Board ( Side B )
PU508
U508
J502:D/D FAN connector
J503:DIMM1
U509 J502
U507 J505:DIMM2
U504
U516
J505
U505
J503
106

3.2 D/D Board
J4 J1:Parallel port connector

J1
IR
PJ2 J5 J2:USB2 connector
J2 J3 J6
J3:USB0 connector
PJ1
J4:TV Out connector
PU1
J5:Power Jack connector
J6:Inverter Board connector
PJ1:D/D Board connector
PJ2: External USB(PIO,IR,TV
OUT)Connector
USB0
USB0
Power
Power Jack
Jack connector
connector
connector
connector
J3 J2
J5 J4 J1
TV
TV Out
Out Parallel
Parallel port
port D/D Board Rear Side View
connector
connector connector
connector
107

3.3 Touch PAD Board
U1 SW1:SCRL UP
SW2:RIGHT
J1
SW3:LEFT
Connect to
MB J15 SW4:SCRL DOWN
J500 J501:Touch PAD connector(to MB)

SW1
SW3 SW2
J501
SW4
108
4. Definition & Location Major Components

4.1 Main Board ( Side A )
U1:P4(Willamette/Northwood)Micro CPU
U3:82845 (Memory controller HUB)
U18 U4:RTL8139CL(LANPHY)
U13 U7:PCI4410(PCMCIA/1394 controller)
U3
U12 U11:74AHC373_V
U1 U11
U12:Flash Rom
U13:SN74CBTD3384(Level Shift)
U17 U17:82801BA(I/O controller)
U18: Audio amplifier
U7 U4
J509
109

4.1 Main Board ( Side B )
U504:TPS2211
U507:ICS950805(Clock generator)
PU508 U508:Micro Controller(H8 F3437)
U508 U509:PC87393(Supper I/O)
U516:ATI VGA controller
U507
U509 J502 PU508:LTC1709EG-9(CPU_CORE regulator)
U504
U516
110

4.2 D/D Board
J4
U501:PAC128401Q
J1 IR
J5
PJ2 U502:PAC128401Q
J2 J3
PU1:MAX1632(3V.5V.12V regulator)
PJ1
PU1 PU501:AO4400
PU502:SI4832DY
D/D Board (Side A) PU503:SI4800DY
PU504:AO4400
PU505:SI4832Dy
PU506:SI4800Y
U502 U501
PQ502:SI4835DY
PQ503:SI4835DY
PQ502
PU502
PQ503 PU505 PU501
PU503
PU506 PU504
D/D Board (Side B)

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5. Pin Descriptions of Major Components

5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin
Name Type Description Name Type Description
A[35:3]# Input/ A[35:3]# (Address) define a 2 36 -byte physical memory address AP[1:0]# Input/ AP[1:0]# (Address Parity) are driven by the request initiator along
Output space. In sub-phase 1 of the address phase, these pins transmit the Output with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A
address of a transaction. In sub-phase 2, these pins transmit correct parity signal is high if an even number of covered signals
transaction type information. These signals are low and low if an odd number of covered signals are low. This
must connect the appropriate pins of all agents on the Pentium 4 allows parity to be high when all the covered signals are high.
processor in the 478-pin package system bus. A[35:3]# are AP[1:0]# should connect the appropriate pins of all Pentium 4
protected by parity signals AP[1:0]#. A[35:3]# are source processor in the 478-pin package system bus agents. The following
synchronous signals and are latched into the receiving buffers by table defines
ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the
processor samples a subset of the A[35:3]# pins to determine Request Signals subphase 1 subphase 2
power-on configuration. A[35:24]# AP0# AP1#
A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks A[23:3]# AP1# AP0#
physical address bit 20 (A20#) before looking up a line in any
REQ[4:0]# AP1# AP0#
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the system bus
wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only frequency. All processor system bus agents must receive these
supported in real mode. signals to drive their outputs and latch their inputs.
A20M# is an asynchronous signal. However, to ensure recognition All external timing parameters are specified with respect to the
of this signal following an Input/Output write instruction, it must be rising edge of BCLK0 crossing V CROSS .
valid along with the TRDY# assertion of the corresponding BINIT# Input/ BINIT# (Bus Initialization) may be observed and driven by all
Input/Output Write bus transaction. Output processor system bus agents and if used, must connect the
ADS# Input/ ADS# (Address Strobe) is asserted to indicate the validity of the appropriate pins of all such agents. If the BINIT# driver is enabled
Output transaction address on the A[35:3]# and REQ[4:0]# pins. All bus during power-on configuration, BINIT# is asserted
agents observe the ADS# activation to begin parity checking, to signal any bus condition that prevents reliable future operation.
protocol checking, address decode, internal snoop, or deferred reply If BINIT# observation is enabled during power-on configuration,
ID match operations associated with the new transaction. and BINIT# is sampled asserted, symmetric agents reset their bus
ADSTB[1:0]# Input/ Address strobes are used to latch A[35:3]# and REQ[4:0]# on their LOCK# activity and bus request arbitration state machines. The bus
Output rising and falling edges. Strobes are associated with signals as agents do not reset their IOQ and transaction tracking state
shown below. machines upon observation of BINIT# activation. Once the BINIT#
assertion has been observed, the bus agents will re-arbitrate for the
system bus and attempt completion of their bus queue and IOQ
Signals Associated Strobe entries.
REQ[4:0]#, A[16:3]# ADSTB0# If BINIT# observation is disabled during power-on configuration, a
A[35:17]# ADSTB1# central agent may handle an assertion of BINIT# as appropriate to
the error handling architecture of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus
Input/
BNR# agent who is unable to accept new bus transactions. During a bus
Output
stall, the current bus owner cannot issue any new transactions.
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BPM[5:0]# Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance D[63:0]# Input/ D[63:0]# (Data) are the data signals. These signals provide a 64-bit
Output monitor signals. They are outputs from the processor which indicate Output data path between the processor system bus agents, and must
the status of breakpoints and programmable counters used for connect the appropriate pins on all such agents. The data driver
monitoring processor performance. BPM[5:0]# should connect the asserts DRDY# to indicate a valid data transfer.
appropriate pins of all Pentium 4 processor in the 478-pin package D[63:0]# are quad-pumped signals and will thus be driven four
system bus agents. times in a common clock period. D[63:0]# are latched off the falling
BPM4# provides PRDY# (Probe Ready) functionality for the TAP edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
port. PRDY# is a processor output used by debug tools to determine data signals correspond to a pair of one DSTBP# and one DSTBN#.
processor debug readiness. The following table shows the grouping of data signals to data
BPM5# provides PREQ# (Probe Request) functionality for the TAP strobes and DBI#.
port. PREQ# is used by debug tools to request debug operation of Quad-Pumped Signal Groups
the processor. Please refer to the Intel® Pentium® 4 Processor in
the 478-pin Package and Intel® 850 Chipset Platform Design DSTBN#/
Data Group DBI#
Guide for more detailed information. DSTBP#
These signals do not have on-die termination. the Intel® D[15:0]# 0 0
Pentium® 4 Processor in the 478-pin Package and Intel® 850 D[31:16]# 1 1
Chipset Platform Design Guide for termination requirements. D[47:32]# 2 2
BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of D[63:48]# 3 3
the processor system bus. It must connect the appropriate pins of all
processor system bus agents. Observing BPRI# active (as asserted Furthermore, the DBI# pins determine the polarity of the data
by the priority agent) causes all other agents to stop issuing new signals. Each group of 16 data signals corresponds to one DBI#
requests, unless such requests are part of an ongoing locked signal. When the DBI# signal is active, the corresponding data
operation. The priority agent keeps BPRI# asserted until all of its group is inverted and therefore sampled active high.
requests are completed, then releases the bus by deasserting BPRI#. DBI[3:0]# Input/ DBI[3:0]# are source synchronous and indicate the polarity of the
BR0# Input/ BR0# drives the BREQ0# signal in the system and is used by the Output D[63:0]# signals. The DBI[3:0]# signals are activated when the data
Output processor to request the bus. During power-on configuration this pin on the data bus is inverted. The bus agent will invert the data bus
is sampled to determine the agent ID = 0. signals if more than half the bits, within the covered group, would
This signal does not have on-die termination and must be change level in the next cycle.
terminated. DBI[3:0] Assignment To Data Bus
BSEL[1:0] Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to
select the processor input clock frequency. The required frequency Bus Signal Data Bus Signals
is determined by the processor, chipset and clock synthesizer. All
agents must operate at the same frequency. The Pentium 4 DBI3# D[63:48]#
processor in the 478-pin package operates currently at a 400 MHz DBI2# D[47:32]#
system bus frequency (100 MHz BCLK[1:0] frequency). For more DBI1# D[31:16]#
information about these pins, including termination DBI0# D[15:0]#
recommendations.
COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision DBR# Output DBR# is used only in processor systems where no debug port is
resistors. Refer to the Intel® Pentium® 4 Processor in the 478-pin implemented on the system board. DBR# is used by a debug port
Package and Intel® 850 Chipset Platform Design Guide for details interposer so that an in-target probe can drive system reset. If a
on implementation. debug port is implemented in the system, DBR# is a no connect in
the system. DBR# is not a processor signal.
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DBSY# Input/ DBSY# (Data Bus Busy) is asserted by the agent responsible for HIT# Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey
Output driving data on the processor system bus to indicate that the data HITM# Output transaction snoop operation results. Any system bus agent may
bus is in use. The data bus isreleased after DBSY# is deasserted. assert both HIT# and HITM# together to indicate that it requires
This signal must connect the appropriate pins on all processor Input/ a snoop stall, which can be continued by reasserting
system bus agents. Output HIT# and HITM# together.
DEFER# Input DEFER# is asserted by an agent to indicate that a transaction IERR# Output IERR# (Internal Error) is asserted by a processor as the result of
cannot be guaranteed in-order completion. Assertion of an internal error. Assertion of IERR# is usually accompanied by
DEFER# is normally the responsibility of the addressed a SHUTDOWN transaction on the processor system bus. This
memory or Input/Output agent. This signal must connect the transaction may optionally be converted to an external error
appropriate pins of all processor system bus agents. signal (e.g., NMI) by system core logic. The processor will keep
DP[3:0]# Input/ DP[3:0]# (Data parity) provide parity protection for the IERR# asserted until the assertion of RESET#, BINIT#, or
Output D[63:0]# signals. They are driven by the agent responsible for INIT#.
driving D[63:0]#, and must connect the appropriate pins of all This signals does not have on-die termination.
Pentium 4 processor in the 478-pin package system bus gents. IGNNE# Input IGNNE# (Ignore Numeric Error) is asserted to force the
DSTBN[3:0]# Input/ Data strobe used to latch in D[63:0]#. processor to ignore a numeric error and continue to execute
Output noncontrol floating-point instructions. If IGNNE# is deasserted,
Signals Associated Strobe the processor generates an exception on a noncontrol
D[15:0]#, DBI0# DSTBN0# floating-point instruction if a previous floating-point instruction
D[31:16]#, DBI1# DSTBN1# caused an error.IGNNE# has no effect when the NE bit in
control register 0 (CR0) is set. IGNNE# is an asynchronous
D[47:32]#, DBI2# DSTBN2#
signal. However, to ensure recognition of this signal following
D[63:48]#, DBI3# DSTBN3#
an Input/Output write instruction, it must be valid along with the
DSTBP[3:0]# Input/ Data strobe used to latch in D[63:0]#. TRDY# assertion of the corresponding Input/Output Write bus
Output transaction.
Signals Associated Strobe INIT# Input INIT# (Initialization), when asserted, resets integer registers
D[15:0]#, DBI0# DSTBP0# inside the processor without affecting its internal caches or
D[31:16]#, DBI1# DSTBP1#
floating-point registers. The processor then begins execution at
the power-on Reset vector configured during power-on
D[47:32]#, DBI2# DSTBP2# configuration. The processor continues to handle snoop requests
D[63:48]#, DBI3# DSTBP3# during INIT# assertion. INIT# is an asynchronous signal and
FERR# Output FERR# (Floating-point Error) is asserted when the processor must connect the appropriate pins of all processor system bus
detects an unmasked floating-point error. FERR# is similar to agents. If INIT# is sampled active on the active to inactive
the ERROR# signal on the Intel 387 coprocessor, and is transition of RESET#, then the processor executes its Built-in
included for compatibility with systems using MSDOS*-type Self-Test (BIST).
floating-point error reporting. ITPCLKOUT[1:0] Output The ITPCLKOUT[1:0] pins do not provide any output for the
GTLREF Input GTLREF determines the signal reference level for AGTL+ input Pentium® 4 processor in the 478-pin package. Refer to
pins. GTLREF should be set at 2/3 V CC. GTLREF is used by the ITP_CLK[1:0] Input ITP_CLK[1:0] are copies of BCLK that are used only in
AGTL+ receivers to determine if a signal is a logical 0 or processor systems where no debug port is implemented on the
logical 1. Refer to the Intel® Pentium® 4 Processor in the system board. ITP_CLK[1:0] are used as BCLK[1:0] references
478-pin Package and Intel® 850 Chipset Platform Design for a debug port implemented on an interposer. If a debug port
Guide for more information. is implemented in the system, ITP_CLK[1:0] are no connects in
the system. These are not processor signals.
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LINT[1:0] Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor
pins of all APIC Bus agents. When the APIC is disabled, the requires this signal to be a clean indication that the clocks and
LINT0 signal becomes INTR, a maskable interrupt request power supplies are stable and within their specifications.
signal, and LINT1 becomes NMI, a nonmaskable interrupt. ‘Clean’ implies that the signal will remain low (capable of
INTR and NMI are backward compatible with the signals of sinking leakage current), without glitches, from the time that the
those names on the Pentium processor. Both signals are power supplies are turned on until they come within
specification. The signal must then transition monotonically to a
asynchronous.
high illustrates the relationship of PWRGOOD to the RESET#
Both of these signals must be software configured via BIOS
signal. PWRGOOD can be driven inactive at any time, but
programming of the APIC register space to be used either as
clocks and power must again be stable before a subsequent
NMI/INTR or LINT[1:0]. Because the APIC is enabled by rising edge of PWRGOOD. It must also meet the minimum
default after Reset, operation of these pins as LINT[1:0] is the pulse width and be followed by a 1 to 10 ms RESET# pulse.
default configuration. The PWRGOOD signal must be supplied to the processor; it is
LOCK# Input/ LOCK# indicates to the system that a transaction must occur used to protect internal circuits against voltage sequencing
Output atomically. This signal must connect the appropriate pins of all issues. It should be driven high
processor system bus agents. For a locked sequence of throughout boundary scan operation.
transactions, LOCK# is asserted from the beginning of the RESET# Input Asserting the RESET# signal resets the processor to a known
first transaction to the end of the last transaction. state and invalidates its internal caches without writing back any
When the priority agent asserts BPRI# to arbitrate for ownership of their contents. For a power-on Reset, RESET# must stay
of the processor system bus, it will wait until it observes active for at least one millisecond after VCC and BCLK have
LOCK# deasserted. This enables symmetric agents to retain reached their proper specifications. On observing active
ownership of the processor system bus throughout the bus RESET#, all system bus agents will deassert their outputs within
locked operation and ensure the atomicity of lock. two clocks. RESET# must not be kept asserted for more than 10
MCERR# Input/ MCERR# (Machine Check Error) is asserted to indicate an ms while PWRGOOD is asserted.
Output unrecoverable error without a bus protocol violation. It may be A number of bus signals are sampled at the active-to-inactive
driven by all processor system bus agents. transition of RESET# for power-on configuration.
MCERR# assertion conditions are configurable at a system This signal does not have on-die termination and must be
level. Assertion options are defined by the following options: terminated on the system board.
Enabled or disabled. RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent
Asserted, if configured, for internal errors along with IERR#. (the agent responsible for completion of the current transaction),
Asserted, if configured, by the request initiator of a bus and must connect the appropriate pins of all processor system
transaction after it observes an error. bus agents.
Asserted by any bus agent when it observes an error in a bus RSP# Input RSP# (Response Parity) is driven by the response agent (the
agent responsible for completion of the current transaction)
transaction.
during assertion of RS[2:0]#, the signals for which RSP#
For more details regarding machine check architecture, please
provides parity protection. It must connect to the appropriate
refer to the IA-32 Software Developer’s Manual, Volume 3:
pins of all processor system bus agents.
System Programming Guide. A correct parity signal is high if an even number of covered
PROCHOT# Output PROCHOT# will go active when the processor temperature signals are low and low if an odd number of covered signals are
monitoring sensor detects that the processor has reached its low. While RS[2:0]# = 000, RSP# is also high, since this
maximum safe operating temperature. indicates it is not being driven by any agent guaranteeing
This indicates that the processor Thermal Control Circuit has correct parity.
been activated, if enabled.
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REQ[4:0]# Input/ REQ[4:0]# (Request Command) must connect the appropriate TDI Input TDI (Test Data In) transfers serial test data into the processor.
Output pins of all processor system bus agents. They are asserted by the TDI provides the serial input needed for JTAG specification
current bus owner to define the currently active transaction type. support.
These signals are source synchronous to ADSTB0#. Refer to the TDO Output TDO (Test Data Out) transfers serial test data out of the
AP[1:0]# signal description for a details on parity checking of processor. TDO provides the serial output needed for JTAG
these signals. specification support.
SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the TESTHI[12:8] Input TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC
processor. System board designers may use this pin to determine TESTHI[5:0] power source through a resistor for proper processor operation.
if the processor is present.
SLP# Input SLP# (Sleep), when asserted in Stop-Grant state, causes the THERMDA Other Thermal Diode Anode.
processor to enter the Sleep state. During Sleep state, the THERMDC Other Thermal Diode Cathode.
processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still operating. THERMTRIP# Output Assertion of THERMTRIP# (Thermal Trip) indicates the
Processors in this state will not recognize snoops or interrupts. processor junction temperature has reached a level beyond
The processor will recognize only assertion of the RESET# which permanent silicon damage may occur. Measurement of
signal, deassertion of SLP#, and removal of the BCLK input the temperature is accomplished through an internal thermal
while in Sleep state. If SLP# is deasserted, the processor exits sensor which is configured to trip at approximately 135°C.Upon
Sleep state and returns to Stop-Grant state, restarting its internal assertion of THERMTRIP#, the processor will shut off its
clock signals to the bus and processor core units. If the BCLK internal clocks (thus halting program execution) in an attempt to
input is stopped while in the Sleep state the processor will exit reduce the processor junction temperature. To protect the
the Sleep state and transition to the Deep Sleep state. processor, its core voltage (VCC) must be removed following
the assertion of THERMTRIP#. Once activated,
SMI# Input SMI# (System Management Interrupt) is asserted
THERMTRIP# remains latched until RESET# is asserted.
asynchronously by system logic. On accepting a System
While the assertion of the RESET# signal will de-assert
Management Interrupt, the processor saves the current state and
THERMTRIP# , if the processor’s junction
enter System Management Mode (SMM). An SMI
temperature remains at or above the trip level, THERMTRIP#
Acknowledge transaction is issued, and the processor begins
will again be asserted after RESET# is de-asserted.
program execution from the SMM handler.
TMS Input TMS (Test Mode Select) is a JTAG specification support signal
If SMI# is asserted during the deassertion of RESET# the
used by debug tools.
processor will tristate its outputs.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that
STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to
it is ready to receive a write or implicit writeback data transfer.
enter a low power Stop-Grant state. The processor issues a
TRDY# must connect the appropriate pins of all system bus
Stop-Grant Acknowledge transaction, and stops providing
agents.
internal clock signals to all processor core units except the
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
system bus and APIC units. The processor continues to snoop
TRST# must be driven low during power on Reset. This can be
bus transactions and service interrupts while in Stop-Grant state.
done with a 680 . pull-down resistor.
When STPCLK# is deasserted, the processor restarts its internal
VCCA Input VCCA provides isolated power for the internal processor core
clock to all units and resumes execution. The assertion of
PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
STPCLK# has no effect on the bus clock; STPCLK# is an
Package and Intel® 850 Chipset Platform Design Guide for
asynchronous input.
complete implementation details.
TCK Input TCK (Test Clock) provides the clock input for the processor
Test Bus (also knownas the Test Access Port).
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Name Type Description
VCCIOPLL Input VCCIOPLL provides isolated power for internal processor system
bus PLLs. Follow he guidelines for VCCA, and refer to the Intel®
Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for complete implementation
details.
VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor
core power(VCC). It can be used to sense or measure power near
the silicon with little noise.
VCCVID Input There is no imput voltage requirement for VCCVID for designs
intended tosupport only the Pentium 4 processor in the 478-pin
package. Refer to the Intel® Pentium® 4 Processor in the
478-pin Package and Intel® 850 Chipset Platform Design
Guide for more information.
VID[4:0] Output VID[4:0] (Voltage ID) pins can be used to support automatic
selection of power supply voltages (Vcc). These pins are not
signals, but are either an open circuit or a short circuit to VSS
on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are
needed to cleanly support processor voltage specification
variations. See 1.4 for definitions of these pins. The power
supply must supply the voltage that is requested by these pins,
or disable itself.
VSSA Input VSSA is the isolated ground for internal PLLs.
VSSSENSE Output VSSSENSE is an isolated low impedance connection to processor
core VSS. It can be used to sense or measure ground near the
silicon with little noise
TMS Input TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that
it is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of all system bus
agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset. This can be
done with a 680 . pull-down resistor.
VCCA Input VCCA provides isolated power for the internal processor core
PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide for
complete implementation details.
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5.2 Intel 82845(Brookdale Memory Controller HUB)

System Bus singnals
ADS# I/O Address Strobe: The system bus owner asserts ADS# to indicate the HA[31:3]# I/O Host Address Bus: HA[31:3]# connect to the system address bus.
AGTL+ first of two cycles of a request phase. AGTL+ During processor cycles, HA[31:3]# are inputs. The MCH drives
BNR# I/O Block Next Request: BNR# is used to block the current request bus HA[31:3]# during snoop cycles on behalf of the hub interface and
AGTL+ owner from issuing a new request. This signal dynamically controls AGP/Secondary PCI initiators. HA[31:3]# are transferred at 2x rate.
the system bus pipeline depth. Note that the address is inverted on the system bus.
BPRI# O Bus Priority Request: The MCH is the only Priority Agent on the HADSTB[1:0]# I/O Host Address Strobe: The source synchronous strobes used to
AGTL+ system bus. It asserts this signal to obtain the ownership of the AGTL+ transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
address bus. This signal has priority over symmetric bus requests and Strobe Address Bits
will cause the current symmetric owner to stop issuing new HADSTB0# HA[16:3]#, HREQ[4:0]#
transactions unless the HLOCK# signal was asserted. HADSTB1# HA[31:17]#
BR0# I/O Bus Request 0#: The MCH pulls the processor bus BR0# signal low HD[63:0]# I/O Host Data: These signals are connected to the system data bus.
AGTL+ during CPURST#. The signal is sampled by the processor on the AGTL+ HD[63:0]# are transferred at a 4x rate. Note that the data signals are
active - to-inactive transition of CPURST#. The minimum setup time inverted on the system bus.
for this signal is 4 BCLKs. The minimum hold time is 2 BCLKs and HDSTBP[3:0]# I/O Differential Host Data Strobes: The differential source synchronous
the maximum hold time is 20 BCLKs. BR0# should be three-stated HDSTBN[3:0]# AGTL+ strobes used to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer
after the hold time requirement has been satisfied. rate.
CPURST# O Processor Reset: The CPURST# pin is an output from the MCH. The Strobe Data Bits
AGTL+ MCH asserts CPURST# while RSTIN# (PCIRST# from the ICH2) is HDSTBP3#, HDSTBN3# HD[63:48]#, DBI3#
asserted and for approximately 1 ms after RSTIN# is deasserted. The HDSTBP2#, HDSTBN2# HD[47:32]#, DBI2#
CPURST# allows the processor to begin execution in a known state. HDSTBP1#, HDSTBN1# HD[31:16]#, DBI1#
DBSY# I/O Data Bus Busy: DBSY# is used by the data bus owner to hold the HDSTBP0#, HDSTBN0# HD[15:0]#, DBI0#
AGTL+ data bus for transfers requiring more than one cycle. HIT# I/O Hit: This signal indicates that a caching agent holds an unmodified
DEFER# O Defer Response: This signal, when asserted, indicates that the MCH AGTL+ version of the requested line. HIT# is also driven in conjunction with
AGTL+ will terminate the transaction currently being snooped with either a HITM# by the target to extend the snoop window.
deferred response or with a retry response. HITM# I/O Hit Modified: This signal indicates that a caching agent holds a
DBI[3:0]# I/O Dynamic Bus Inversion: DBI[3:0]# are driven along with the AGTL+ modified version of the requested line and that this agent assumes
AGTL+ HD[63:0]# signals. DBI[3:0]# Indicate if the associated data signals responsibility for providing the line. HITM# is also driven in
are inverted. DBI[3:0]# are asserted such that the number of data bits conjunction with HIT# to extend the snoop window.
driven electrically low (low voltage) within the corresponding 16-bit HLOCK# I/O Host Lock: All system bus cycles sampled with the assertion of
group never exceeds 8. AGTL+ HLOCK# and ADS#, until the negation of HLOCK# must be atomic
DBI[x]# Data Bits (i.e., no hub interface or AGP snoopable access to system memory are
DBI3# HD[63:48]# allowed when HLOCK# is asserted by the processor).
DBI2# HD[47:32]#
DBI1# HD[31:16]#
DBI0# HD[15:0]#
DRDY# I/O Data Ready. Asserted for each cycle that data is transferred.
AGTL+
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System Bus singnals
HREQ[4:0]# I/O Host Request Command: These signals define the attributes of the SCKE[5:0] O Clock Enable: These pins are used to signal a self-refresh or
AGTL+ request. In Enhanced Mode HREQ[4:0]# are transferred at 2x rate. AGTL+ Powerdown command to a SDRAM array when entering system
HREQ[4:0]# are asserted by the requesting agent during both halves suspend. SCKE is also used to dynamically powerdown inactive
of Request Phase. In the first half the signals define the transaction SDRAM rows. There is one SCKE per SDRAM row. These signals
type to level of detail that is sufficient to begin a snoop request. In the can be toggled on every rising SCLK edge.
second half the signals carry additional information to define the RDCLKO O Clock Output: RDCLKO is used to emulate source-synch clocking
complete transaction type. AGTL+ for reads. This signal connects to RDCLKIN.
The transactions supported by the MCH host bridge are defined in the SMA[12:0] O Multiplexed Memory Address: These signals are used to provide
Section 5.1. AGTL+ the multiplexed row and column address to SDRAM.
HTRDY# I/O Host Target Ready: HTRDY# indicates that the target of the RDCLKIN I Clock Input: RDCLKIN is used to emulate source-synch clocking
AGTL+ processor transaction is able to enter the data transfer phase. AGTL+ for reads. This signal connects to RDCLKO.
RS[2:0]# O Response Status: RS[2:0]# indicates the type of response according
AGTL+ to the following the table:
RS[2:0] Response Type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Failure (not driven by MCH)
101 No data response
110 Implicit Write back
111 Normal data response
SCS[11:0]# O Chip Select: These signals select the particular SDRAM components
AGTL+ during the active state.
Note: There are two SCS# signals per SDRAM row. These signals
can be toggled on every rising system memory clock edge.
SMA[12:0] O Multiplexed Memory Address: These signals are used to provide
AGTL+ the multiplexed row and column address to SDRAM.
SBS[1:0] O Memory Bank Select: SBS[1:0] define the banks that are selected
AGTL+ within each SDRAM row. The SMA and SBS signals combine to
address every possible location in a SDRAM device.
SRAS# O SDRAM Row Address Strobe: SRAS# is Used with SCAS# and
AGTL+ SWE# (along with SCS#) to define the DRAM commands.
SCAS# O SDRAM Column Address Strobe: SCAS# is used with SRAS#
AGTL+ andSWE# (along with SCS#) to define the SDRAM commands.
SWE# O Write Enable: SWE# is used with SCAS# and SRAS# (along with
AGTL+ SCS#) to define the SDRAM commands.
SDQ[63:0] I/O Data Lines: These signals are used to interface to the SDRAM data
AGTL+ bus.
SCB[7:0] I/O Check Bit Data Lines: These signals are used to interface to the
AGTL+ SDRAM ECC signals.
119

Hub Interface Signals AGP Flow Control Signals
HI_[10:0] I/O Hub Interface Signals: Signals used for the hub interface. RBF# I Read Buffer Full: RBF# indicates if the master is ready to accept
CMOS AGP previously requested low priority read data. When RBF# is asserted,
HI_STB I/O Hub Interface Strobe: One of two differential strobe signals used to the MCH is not allowed to initiate the return low priority read data.
CMOS transmit or receive packet data over the hub interface. That is, the MCH can finish returning the data for the request
HI_STB# I/O Hub Interface Strobe Compliment: One of two differential strobe currently being serviced. RBF# is only sampled at the beginning of a
CMOS signals used to transmit or receive packet data over the hub interface. cycle. If the AGP master is always ready to accept return read data,
then it is not required to implement this signal.
During FRAME# Operation: Not Used.
WBF# I Write-Buffer Full: Indicates if the master is ready to accept fast
AGP write data from the MCH. When WBF# is asserted, the MCH is not
AGP Addressing Signals allowed drive fast write data to the AGP master. WBF# is only
Name Type Description sampled at the beginning of a cycle. If the AGP master is always
PIPE# I Pipelined Read: This signal is asserted by the AGP master to ready to accept fast write data, then it is not required to implement
AGP indicate a full-width address is to be enqueued on by the target using this signal.
the AD bus. One address is placed in the AGP request queue on each During FRAME# Operation: Not Used.
rising clock edge while PIPE# is asserted. When PIPE# is deasserted,
no new requests are queued across the AD bus.
During SBA Operation: Not Used.
During FRAME# Operation: Not Used. AGP Status Signals
PIPE# is a sustained three-state signal from masters (graphics Name Type Description
controller), and is an MCH input.
Note: Initial AGP designs may not use PIPE# (i.e., PCI only 66 ST[2:0] O Status: ST[2:0] provides information from the arbiter to an AGP
MHz). Therefore, an 8 k. pull-up resistor connected to this pin is AGP Master on what it may do. ST[2:0] only have meaning to the master
required on the motherboard. when its G_GNT# is asserted. When G_GNT# is deasserted, these
SBA[7:0] I Sideband Address: These signals are used by the AGP master signals have no meaning and must be ignored. Refer to the AGP
AGP (graphics controller) to place addresses into the AGP request queue. Interface Specification, Revision 2.0 for further explanation of the
The SBA bus and AD bus operate independently. That is, a ST[2:0] values and their meanings.
transaction can proceed on the SBA bus and the AD bus During FRAME# Operation: These signals are not used during
simultaneously. FRAME#-based operation, except that a ¡¥111¡¦ indicates that the
During PIPE# Operation: Not Used. master may begin a FRAME# transaction.
During FRAME# Operation: Not Used.
Note: When sideband addressing is disabled, these signals are
isolated (no external/internal pull-up resistors are required).
NOTE: The above table contains two mechanisms to queue requests by the AGP master. Note that
the master can only use one mechanism. The master may not switch methods without a full
reset of the system. When PIPE# is used to queue addresses the master is not allowed to
queue addresses using the SBA bus. For example, during configuration time, if the master
indicates that it can use either mechanism, the configuration software will indicate which
mechanism the master will use. Once this choice has been made, the master will continue to
use the mechanism selected until the master is reset (and reprogrammed) to use the other
mode. This change of modes is not a dynamic mechanism but rather a static decision when
the device is first being configured after reset.
120

AGP Strobes Signals
AD_STB0 I/O Address/Data Bus Strobe-0: This signal provides timing for 2x and G_TRDY# I/O Target Ready: This signal indicates the AGP compliant target is
(s/t/s) 4x data on AD[15:0] and the C/BE[1:0]# signals. The agent that is (s/t/s) ready to provide read data for the entire transaction (when the transfer
AGP providing the data drives this signal. AGP size is less than or equal to 32 bytes) or is ready to transfer the initial
AD_STB0# I/O Address/Data Bus Strobe-0 Compliment: Differential strobe pair or subsequent block (32 bytes) of data when the transfer size is
(s/t/s) that provides timing information for the AD[15:0] and C/BE[1:0]# greater than 32 bytes. The target is allowed to insert wait states after
AGP signals. The agent that is providing the data drives this signal. each block (32 bytes) is transferred on write transactions.
G_STOP# I/O STOP: G_STOP Is an input when the MCH acts as a FRAME#-based
AD_STB1 I/O Address/Data Bus Strobe-1: This signal provides timing for 2x- and (s/t/s) AGP initiator and an output when the MCH acts as a FRAME#-based
(s/t/s) 4x-clocked data on AD[31:16] and C/BE[3:2]# signals. The agent that AGP AGP target. G_STOP# is used for disconnect, retry, and abort
AGP is providing the data drives this signal. sequences on the AGP interface.
AD_STB1# I/O Address/Data Bus Strobe-1 Compliment: The differential G_DEVSEL# I/O Device Select: This signal indicates that a FRAME#-based AGP
(s/t/s) compliment to the AD_STB1 signal. It is used to provide timing for (s/t/s) target device has decoded its address as the target of the current
AGP 4x-clocked data. AGP access. The MCH asserts G_DEVSEL# based on the DRAM address
SB_STB I Sideband Strobe: This signal provides timing for 2x- and 4x- range being accessed by a PCI initiator. As an input it indicates
AGP clocked data on the SBA[7:0] bus. It is driven by the AGP master whether any device on the bus has been selected.
after the system has been configured for 2x- or 4x- clocked sideband G_REQ# I Request: Indicates that a FRAME# or PIPE#-based AGP master is
address delivery. AGP requesting use of the AGP interface. This signal is an input into the
SB_STB# I Sideband Strobe Compliment: SB_STB# is the differential MCH.
AGP compliment to the SB_STB signal. It is used to provide timing for G_GNT# O Grant: During SBA, PIPE# and FRAME# operation, G_GNT#,
4x-clocked data. AGP along with the information on the ST[2:0] signals (status bus),
indicates how the AGP interface will be used next.
G_AD[31:0] I/O Address/Data Bus: These signals are used to transfer both address
AGP and data on the AGP interface.
AGP/PCISignals G_C/BE[3:0]# I/O Command/Byte Enable:
For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate AGP During FRAME# Operation: During the address phase of a
similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals transaction, G_C/BE[3:0]# define the bus command. During the data
are defined below. phase, G_C/BE[3:0]# are used as byte enables. The byte enables
Name Type Description determine which byte lanes carry meaningful data.
During PIPE# Operation: When an address is enqueued using
G_FRAME# I/O FRAME: During FRAME# Operations, G_FRAME# is an output
PIPE#, the G_C/BE# signals carry command information. The
(s/t/s) when the MCH acts as an initiator on the AGP Interface.
command encoding used during PIPE#-based AGP is DIFFERENT
AGP
than the command encoding used during FRAME#-based AGP cycles
G_IRDY# I/O Initiator Ready#: This signal indicates the AGP compliant master is (or standard PCI cycles on a PCI bus).
(s/t/s) ready to provide all write data for the current transaction. Once
AGP G_IRDY# is asserted for a write operation, the master is not allowed
to insert wait states. The master is never allowed to insert a wait state
during the initial data transfer (32 bytes) of a write transaction.
However, it may insert wait states after each 32-byte block is
transferred.
121

AGP/PCISignals Voltage Reference and Power Signals
G_PAR I/O Parity: HVREF Ref Host Reference Voltage: Reference voltage input for the data,
AGP During FRAME# Operations: This signal is driven by the MCH address, and common clock signals of the host AGTL+ interface.
when it acts as a FRAME#-based AGP initiator during address and SDREF Ref SDRAM Reference Voltage: Reference voltage input for DQ, DQS,
data phases for a write cycle, and during the address phase for a read RDCLKIN (SDR).
cycle. PAR is driven by the MCH when it acts as a FRAME#-based HI_REF Ref Hub Interface Reference: Reference voltage input for the hub
AGP target during each data phase of a FRAME#-based AGP interface.
memory read cycle. Even parity is generated across AD[31:0] and AGPREF Ref AGP Reference: Reference voltage input for the AGP interface.
G_C/BE[3:0]#.
HLRCOMP I/O Compensation for Hub Interface: This signal is used to calibrate
During SBA and PIPE# Operation: This signal is not used during
CMOS the hub interface I/O buffers. It is connected to a 40.2 . pull-up
SBA and PIPE# operation.
resistor with 1% tolerance and is pulled up to VCC1_8.
GRCOMP I/O Compensation for AGP: This signal is used to calibrate buffers. It is
CMOS connected to a 40.2 . pull-down resistor with a 1% tolerance.
HRCOMP[1:0] I/O Compensation for Host: These signals are used to calibrate the host
CMOS AGTL+ I/O buffers. Each signal is connected to a 24.9 . pull-down
Clocks, Reset, and Miscellaneous Signals resistor with a 1% tolerance.
Name Type Description HSWNG[1:0] I Host Reference Voltage: Reference voltage input for the
BCLK I Differential Host Clock In: These pins receive a differential host CMOS compensation logic.
BCLK# CMOS clock from the external clock synthesizer. This clock is used by all of SMRCOMP I/O System Memory RCOMP:
the MCH logic that is in the host clock domain. CMOS
66IN I 66 MHz Clock In: This pin receives a 66 MHz clock from the clock VCC1_5 1.5 V Power Input: These pins are connected to a 1.5 V power
CMOS synthesizer. This clock is used by AGP/PCI and hub interface clock source.
domains. VCC1_8 1.8 V Power Input Pins: These pins are connected to a 1.8 V power
Note: That this clock input is 3.3 V tolerant. source.
SCK[11:0] O System Memory Clocks (SDR): These signals deliver a VCCSM SDRAM Power Input Pins: These pins are connected to a 3.3 V
CMOS synchronized clock to the DIMMs. There are two per row. power source for SDR.
RSTIN# I Reset In: When asserted, this signal asynchronously resets the MCH VCCA[1:0] PLL Power Input Pins: These pins provide power for the PLL.
CMOS logic. RSTIN# is connected to the PCIRST# output of the ICH2. All VTT AGTL+ Bus Termination Voltage Inputs: These pins provide the
AGP/PCI output and bi-directional signals will also three-state AGTL+ bus termination.
compliant to PCI Rev 2.0 and 2.1 specifications. VSS Ground: The VSS pins are the ground pins for the MCH.
Note: This input needs to be 3.3 V tolerant.
TESTIN# I Test Input: This pin is used for manufacturing and board level test VSSA[1:0] PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL
CMOS purposes. on the MCH.
Note: This signal has an internal pull-up resistor.
122
5.3 Intel 82801BA(I/O Controller HUB )

Hub Interface Signals Firmware Hub Interface Signals
HL[11:0] I/O Hub Interface Signals FWH[3:0] / I/O Firmware Hub Signals: These signals are muxed with LPC address
HL_STB I/O Hub Interface Strobe: One of two differential strobe signals used to LAD[3:0] signals.
transmit and receive data through the hub interface. FWH[4] / I/O Firmware Hub Signals: This signal is muxed with LPC LFRAME#
HL_STB# I/O Hub Interface Strobe Complement: Second of the two differential LFRAME# signal.
strobe signals.
HLCOMP I/O Hub Interface Compensation: Used for hub interface buffer
compensation.
PCI Interface Signals
AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
LAN Connect Interface Signals address (32 bits). During subsequent clocks, AD[31:0] contain data.
Name Type Description The ICH2 drives all 0s on AD[31:0] during the address phase of all
LAN_CLK I LAN Interface Clock: This signal is driven by the LAN Connect PCI Special Cycles.
component. The frequency range is 0.8 MHz to 50 MHz. C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable
LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to signals are multiplexed on the same PCI pins. During the address
transfer data and control information to the integrated LAN phase of a transaction,C/BE[3:0]# define the bus command. During
Controller. These signals have integrated weak pull-up resistors. the data phase, C/BE[3:0]# define the
LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals to Byte Enables.
transfer data and control information to the LAN Connect component. C/BE[3:0]# Command Type
LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync 0000 Interrupt Acknowledge
signals are multiplexed onto this pin. 0001 Special Cycle
0010 I/O Read
0011 I/O Write
0110 Memory Read
0111 Memory Write
1010 Configuration Read
EEPROM Interface Signals 1011 Configuration Write
Name Type Description 1100 Memory Read Multiple
EE_SHCLK O EEPROM Shift Clock: EE_SHCLK is the serial shift clock output to 1110 Memory Read Line
the EEPROM. 1111 Memory Write and Invalidate
EE_DIN I EEPROM Data In: EE_DIN transfers data from the EEPROM to the All command encodings not shown are reserved. The ICH2 does not
ICH2. This signal has an integrated pull-up resistor. decode reserved values, and therefore will not respond if a PCI master
EE_DOUT O EEPROM Data Out: EE_DOUT transfers data from the ICH2 to the generates a cycle using one of the reserved values.
EEPROM. DEVSEL# I/O Device Select: The ICH2 asserts DEVSEL# to claim a PCI
EE_CS O EEPROM Chip Select: EE_CS is a chip-select signal to the transaction. As an output, the ICH2 asserts DEVSEL# when a PCI
EEPROM. master peripheral attempts an access to an internal ICH2 address or an
address destined for the hub interface (main memory or AGP). As an
input, DEVSEL# indicates the response to an ICH2- initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH2 until
driven by a target device.
123

PCI Interface Signals
FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the PAR I/O Calculated/Checked Parity: PAR uses "even" parity calculated on
beginning and duration of a PCI transaction. While the initiator 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the
asserts FRAME#, data transfers continue. When the initiator negates ICH2 counts the number of 1s within the 36 bits plus PAR and the
FRAME#, the transaction is in the final data phase. FRAME# is an sum is always even. The ICH2 always calculates PAR on 36 bits,
input to the ICH2 when the ICH2 is the target, and FRAME# is an regardless of the valid byte enables. The ICH2 generates PAR for
output from the ICH2 when the ICH2 is the Initiator. FRAME# address and data phases and only guarantees PAR to be valid one PCI
remains tri-stated by the ICH2 until driven by an Initiator. clock after the corresponding address or data phase. The ICH2 drives
IRDY# I/O Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, and tri-states PAR identically to the AD[31:0] lines except that the
to complete the current data phase of the transaction. It is used in ICH2 delays PAR by exactly one PCI clock. PAR is an output during
conjunction with TRDY#. A data phase is completed on any clock the address phase (delayed one clock) for all ICH2 initiated
both IRDY# and TRDY# are sampled asserted. During a write, transactions. PAR is an output during the data phase (delayed one
IRDY# indicates the ICH2 has valid data present on AD[31:0]. clock) when the ICH2 is the Initiator of a PCI write transaction, and
During a read, it indicates the ICH2 is prepared to latch data. IRDY# when it is the target of a read transaction. ICH2 checks parity when it
is an input to the ICH2 when the ICH2 is the Target and an output is the target of a PCI write transaction. If a parity error is detected, the
from the ICH2 when the ICH2 is an Initiator. IRDY# remains ICH2 sets the appropriate internal status bits, and has the option to
tri-stated by the ICH2 until driven by an Initiator. generate an NMI# or SMI#.
TRDY# I/O Target Ready: TRDY# indicates the ICH2's ability as a Target to PERR# I/O Parity Error: An external PCI device drives PERR# when it receives
complete the current data phase of the transaction. TRDY# is used in data that has a parity error. The ICH2 drives PERR# when it detects a
conjunction with IRDY#. A data phase is completed when both parity error. The ICH can either generate an NMI# or SMI# upon
TRDY# and IRDY# are sampled asserted. During a read, TRDY# detecting a parity error (either detected internally or reported via the
indicates that the ICH2, as a Target, has placed valid data on PERR# signal).
AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is GNT[0:4]# O PCI Grants: The ICH2 supports up to 6 masters on the PCI bus.
prepared to latch data. TRDY# is an input to the ICH2 when the ICH2 GNT[5]# / GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the
is the Initiator and an output from the ICH2 when the ICH2 is a GNT[B]# / other, but not both). If not needed PCI or PC/PCI, GNT[5]# can
Target. TRDY# is tri-stated from the leading edge of PCIRST#. GPIO[17]# instead be used as a GPIO.
TRDY# remains tri-stated by the ICH2 until driven by a target. Pull-up resistors are not required on these signals. If pullups are used,
STOP# I/O Stop: STOP# indicates that the ICH2, as a Target, is requesting the they should be tied to the Vcc3_3 power rail.
Initiator to stop the current transaction. STOP# causes the ICH2, as an GNT[B]#/GNT[5]#/GPIO[17] has an internal pullup.
Initiatior, to stop the current transaction. STOP# is an output when the PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
ICH2 is a target and an input when the ICH2 is an Initiator. STOP# is transactions on the PCI Bus. .
tri-stated from the leading edge of PCIRST#. STOP# remains Note:For 82801BAM ICH2-M, this clock does not stop based on the
tri-stated until driven by the ICH2. STP_PCI# signal. The PCI Clock only stops based on SLP_S1# or
REQ[0:4]# I PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. SLP_S3#.
REQ[5]# / REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the PCIRST# O PCI Reset: ICH2 asserts PCIRST# to reset devices that reside on the
REQ[B]# / other, but not both). If not used for PCI or PC/PCI, PCI bus. The ICH2 asserts PCIRST# during power-up and when S/W
GPIO[1] REQ[5]#/REQ[B]# can instead be used as GPIO[1]. initiates a hard reset sequence through the RC (CF9h) register. The
Note: REQ[0]# is programmable to have improved arbitration latency ICH2 drives PCIRST# inactive a minimum of 1 ms after PWROK is
for supporting PCI-based 1394 controllers. driven active. The ICH2 drives PCIRST# active a minimum of 1 ms
when initiated through the RC register.
SERR# I System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH2 has the ability to generate an NMI, SMI#, or interrupt.
124

PCI Interface Signals IDE Interface Signals(continued)
PME# I PCI Power Management Event: PCI peripherals drive PME# to PDA[2:0], O Primary and Secondary IDE Device Address: These output signals
wake the system from low-power states S1–S5. PME# assertion can SDA[2:0] are connected to the corresponding signals on the primary or
also be enabled to generate SCI from the S0 state. In some cases the secondary IDE connectors. They are used to indicate which byte in
ICH2 may drive PME# active due to an internal wake event. The either the ATA command block or control block is being addressed.
ICH2 will not drive PME# high, but it will be pulled up to VccSus3_3 PDD[15:0], I/O Primary and Secondary IDE Device Data: These signals directly
by an internal pull-up resistor. SDD[15:0] drive the corresponding signals on the primary or secondary IDE
CLKRUN# I/O PCI Clock Run: For the ICH2-M, CLKRUN# is used to support PCI connector. There is a weak internal pull-down resistor on PDD[7] and
(ICH2-M only) Clock Run protocol. This signal connects to PCI devices that need to SDD[7].
request clock re-start or prevention of clock stopping. PDDREQ, I Primary and Secondary IDE Device DMA Request: These input
REQ[A]# / I PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA SDDREQ signals are directly driven from the DRQ signals on the primary or
GPIO[0] Requests for the purpose of running ISA-compatible DMA cycles secondary IDE connector. It is asserted by the IDE device to request a
REQ[B]# / over the PCI bus. This is used by devices such as PCI-based Super data transfer, and used in conjunction with the PCI bus master IDE
REQ[5]# / I/O or audio codecs that need to perform legacy 8237 DMA but have function. They are not associated with
GPIO[1] no ISA bus. any AT-compatible DMA channel. There is a weak internal
When not used for PC/PCI requests, these signals can be used as pull-down resistor on these signals.
General Purpose Inputs. Instead, REQ[B]# can be used as the 6th PCI PDDACK#, O Primary and Secondary IDE Device DMA Acknowledge: These
bus request. SDDACK# signals directly drive the DAK# signals on the primary and secondary
GNT[A]# / O PC/PCI DMA Acknowledges [A:B]: This grant serializes an IDE connectors. Each signal is asserted by the ICH2 to indicate to the
GPIO[16] ISA-like DACK# for the purpose of running DMA/ISA master cycles IDE DMA slave devices that a given data transfer cycle (assertion of
GNT[B]# / over the PCI bus. This is used by devices such as PCI-based Super/IO DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used
GNT[5]# / or audio codecs which need to perform legacy 8237 DMA but have in conjunction with the PCI bus master IDE function and are not
GPIO[17] no ISA bus. associated with any AT-compatible DMA channel.
When not used for PC/PCI, these signals can be used as General PDIOR# O Primary and Secondary Disk I/O Read (PIO and Non-Ultra
Purpose Outputs. GNTB# can also be used as the 6th PCI bus master SDIOR# DMA): This is the command to the IDE device that it may drive data
grant output. These signal have internal pull-up resistors. on the PDD or SDD lines. Data is latched by the ICH2 on the
deassertion edge of PDIOR# or SDIOR#. The IDE device is selected
either by the ATA register file chip selects (PDCS1# or SDCS1#,
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
IDE Interface Signals acknowledge (PDDAK# or SDDAK#).
Name Type Description Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing to
PDCS1#, O Primary and Secondary IDE Device Chip Selects for 100 Range: disk, ICH2 drives valid data on rising and falling edges of PDWSTB
SDCS1# These signals are for the ATA command register block. This output or SDWSTB.
signal is connected to the corresponding signal on the primary or Primary and Secondary Disk DMA Ready (Ultra DMA Reads
secondary IDE connector. from Disk): This is the DMA ready for reads from disk. When
PDCS3#, O Primary and Secondary IDE Device Chip Select for 300 Range: reading from disk, ICH2 deasserts PRDMARDY# orSRDMARDY#
SDCS3# These signals are for the ATA control register block. This output to pause burst data transfers.
signal is connected to the corresponding signal on the primary or
secondary IDE connector.
125

IDE Interface Signals(continued) Interrupt Signals
PDIOW# O Primary and Secondary Disk I/O Write (PIO and Non-Ultra SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt
SDIOW# DMA): This is the command to the IDE device that it may latch data protocol.
from the PDD or SDD lines. Data is latched by the IDE device on the PIRQ[D:A]# I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
deassertion edge of PDIOW# or SDIOW#. The IDE device is selected can be routed to interrupts 3:7, 9:12, 14, or 15 as described in the
either by the ATA register file chip selects (PDCS1# or SDCS1#, Interrupt Steering section. Each PIRQx# line has a separate Route
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA Control Register.
acknowledge (PDDAK# or SDDAK#). In APIC mode, these signals are connected to the internal I/O APIC in
Primary and Secondary Disk Stop (Ultra DMA): ICH2 asserts this the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to
signal to terminate a burst. IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the
PIORDY I Primary and Secondary I/O Channel Ready (PIO): This signal ISA interrupts.
SIORDY keeps the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or PIRQ[H]#, I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
SDIOW# on writes) longer than the minimum width. It adds wait PIRQ[G:F]# can be routed to interrupts 3:7, 9:12, 14 or 15 as described in the
states to PIO transfers. GPIO[4:3], Interrupt Steering section. Each PIRQx# line has a separate Route
Primary and Secondary Disk Read Strobe (Ultra DMA Reads PIRQ[E]# Control Register.
from Disk): When reading from disk, ICH2 latches data on rising and In APIC mode, these signals are connected to the internal I/O APIC in
falling edges of this signal from the disk. the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the
Disk): When writing to disk, this is deasserted by the disk to pause ISA interrupts. If not needed for interrupts, PIRQ[G:F] can be used as
burst data transfers GPIO.
IRQ[14:15] I Interrupt Request 14:15: These interrupt inputs are connected to the
IDE drives. IRQ14 is used by the drives connected to the primary
controller and IRQ15 is used by the drives connected to the secondary
controller.
USB Interface Signals APICCLK I APIC Clock: The APIC clock runs at 33.333 MHz.
APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to send
USBP0P, I/O Universal Serial Bus Port 1:0 Differential: These differential pairs and receive data over the APIC bus. As inputs, the data is valid on the
USBP0N, are used to transmit Data/Address/Command signals for ports 0 and 1 rising edge of APICCLK.As outputs, new data is driven from the
USBP1P, (USB Controller 1). rising edge of the APICCLK.
USBP1N
USBP2P, I/O Universal Serial Bus Port 3:2 Differential: These differential pairs
USBP2N, are used to transmit Data/Address/Command signals for ports 2 and 3
USBP3P, USB Controller 2).
USBP3N
OC[3:0]# I Overcurrent Indicators: These signals set corresponding bits in the
LPC Interface Signals
USB controllers to indicate that an overcurrent condition has Name Type Description
occurred. LAD[3:0] / I/O LPC Multiplexed Command, Address, Data: Internal pull-ups are
FWH[3:0] provided.
LFRAME# / O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
FWH[4] abort.
LDRQ[1:0]# O LPC Serial DMA/Master Request Inputs: These signals are used to
request DMA or bus master access. Typically, they are connected to
external Super I/O device. An internal pull-up resistor is provided on
these signals.
126

Power Management Interface Signals
THRM# I Thermal Alarm: THRM# is an active low signal generated by C3_STAT# / O C3_STAT#: This ICH2-M signal is typically configured as
external hardware to start the hardware clock throttling mode. This GPIO[21] C3_STAT#. It is used for indicating to an AGP device that a C3 state
signal can also generate an SMI# or an SCI. ICH2-M only) transition is beginning or ending. If C3_STAT# functionality is not
SLP_S1# O S1 Sleep Control: Clock synthesizer or power plane control. This required, this signal can be used as a GPO.
(ICH2-M only) signal connects to clock synthesizer’s PWRDWN# signal. An SUSCLK O Suspend Clock: This signal is an output of the RTC generator circuit
optional use is to shut off power to non-critical systems when in the and is used by other chips for the refresh clock.
S1 (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to VRMPWRGD I VRM Power Good (ICH2 and ICH2-M): VRMPWRGD should be
Disk), or S5 (Soft Off) states. (ICH2) connected to be the processor’s VRM Power Good.
SLP_S3# O S3 Sleep Control: Power plane control. This signal is used to shut off VRMPWRGD/
power to all non-critical systems when in S3 (Suspend To RAM), S4 VGATE
(Suspend to Disk) or S5 (Soft Off) states. (ICH2-M)
SLP_S5# O S5 Sleep Control: Power plane control. This signal is used to shut VGATE / I VRM Power Good Gate (ICH2-M): VGATE is used for Intel®
power off to all non-critical systems when in the S4 (Suspend To VRMPWRGD SpeedStepTM technology support. It is an output from the
Disk) or S5 (Soft Off) states. (ICH2-M only) processor’s voltage regulator to indicate that the voltage is stable.
PWROK I Power OK: When asserted, PWROK is an indication to the ICH2 This signal can go inactive during a Intel® SpeedStepTM transition.
that core power and PCICLK have been stable for at least 1 ms. In non-Intel® SpeedStepTM technology systems this
PWROK can be driven asynchronously. When PWROK is negated, signal should be connected to the processor VRM Power Good.
the ICH2 asserts PCIRST#. AGPBUSY# I AGP Bus Busy: This signal supports the C3 state. It provides an
RSM_PWROK I Resume Well Power OK: When asserted, this signal is an indication (ICH2-M only) indication that the AGP device is busy. When this signal is asserted,
(ICH2 0nly) to the ICH2 that the resume well power (VccSus3_3, VccSus1_8) has the BM_STS bit will be set. If this functionality is not needed, this
been stable for at least10 ms. signal may be configured as a GPI.
LAN_PWROK I LAN Power OK: When asserted, this signal is an indication to the STP_PCI# O Stop PCI Clock: This signal is an output to the external clock
(ICH2-M only) ICH2-M that the LAN Controller power (VccLAN3_3, VccLAN1_8) (ICH2-M only) generator to turn off the PCI clock. It is used to support PCI
has been stable for at least 10 ms. CLKRUN# protocol. If this functionality is not needed, this signal
PWRBTN# I Power Button: The Power Button will cause SMI# or SCI to indicate can be configured as a GPO.
a system request to go to a sleep state. If the system is already in a STP_CPU# O Stop CPU Clock: Output to the external clock generator to turn off
sleep state, this signal will cause a wake event. If PWRBTN# is (ICH2-M only) the processor clock. It is used to support the C3 state. If this
pressed for more than 4 seconds, this will cause an unconditional functionality is not needed, this signal can be configured as a GPO.
transition (power button override) to the S5 state with only the BATLOW# I Battery Low: Input from battery to indicate that there is insufficient
PWRBTN# available as a wake event. Override will occur even if the (ICH2-M only) power to boot the system. Assertion prevents wake from S1–S5 state.
system is in the S1-S4 states. This signal has an internal pull-up This signal can also be enabled to cause an SMI# when asserted. In
resistor. desktop configurations this signal should be pulled high to VccSUS.
RI# I Ring Indicate: From the modem interface. This signal can be enabled CPUPERF# OD CPU Performance: This signal is used for Intel® SpeedStepTM
as a wake event; this is preserved across power failures. (ICH2-M only) technology support. It selects which power state to put the processo
RSMRST# I Resume Well Reset: RSMRST# is used for resetting the resume in. If this functionality is not needed, this signal can be configured as
power plane logic. a GPO. This is an open-drain output signal and requires an external
SUS_STAT# / O Suspend Status: This signal is asserted by the ICH2 to indicate that pull-up to the processor I/O voltage.
LPCPD# the system will be entering a low power state soon. This can be SSMUXSEL O SpeedStep Mux Select: This signal is used for Intel SpeedStepTM
monitored by devices with memory that need to switch from normal (ICH2-M only) technology support. It selects the voltage level for the processor. If
refresh to suspend refresh mode. It can also be used by other this functionality is not needed, this signal can be configured as a
peripherals as an indication that they should isolate their outputs that GPO.
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
127

Processor Interface Signals
A20M# O Mask A20: A20M# goes active based on setting the appropriate bit in SMI# O System Management Interrupt: SMI# is an active low output
the Port 92h register, or based on the A20GATE signal. synchronous to PCICLK. It is asserted by the ICH2 in response to one
Speed Strap: During the reset sequence, ICH2 drives A20M# high if of many enabled hardware or software events.
the corresponding bit is set in the FREQ_STRP register. STPCLK# O Stop Clock Request: STPCLK# is an active low output synchronous
CPUSLP# O Processor Sleep: This signal puts the processor into a state that saves to PCICLK. It is asserted by the ICH2 in response to one of many
substantial power compared to Stop-Grant state. However, during that hardware or software events. When the processor samples STPCLK#
time, no snoops occur. The ICH2 can optionally assert the CPUSLP# asserted, it responds by stopping its internal clock.
signal when going to the S1 state. RCIN# I Keyboard Controller Reset Processor: The keyboard controller can
FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor generate INIT# to the processor. This saves the external OR gate with
error signal on the processor. FERR# is only used if the ICH2 the ICH2’s other sources of INIT#. When the ICH2 detects the
coprocessor error reporting function is enabled in the General Control assertion of this signal, INIT# isgenerated for 16 PCI clocks..
Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is Note:
asserted, the ICH2 generates an internal IRQ13 to its interrupt 82801BA ICH2: The 82801BA ignores RCIN# assertion during
controller unit. It is also used to gate the IGNNE# signal to ensure transitions to the S3, S4 and S5 states. 82801BAM ICH2-M: The
that IGNNE# is not asserted to the processor unless FERR# is active. 82801BAM ignores RCIN# assertion during transitions
FERR# requires an external weak pull-up to ensure a high level when to the S1, S3, S4 and S5 states.
the coprocessor error function is disabled. A20GATE I A20 Gate: This signal is from the keyboard controller. It acts as an
IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error alternative method to force the A20M# signal active. A20GATE
pin on the processor. IGNNE# is only used if the ICH2 coprocessor saves the external OR gate needed with various other PCIsets.
error reporting function is enabled in the General Control Register CPUPWRGD OD CPU Power Good (82801BAM ICH2-M): This signal should be
(Device 31:Function 0, Offset D0, bit 13). If FERR# is active, connected to the processor’s PWRGOOD input. For Intel®
indicating a coprocessor error, a write to the Coprocessor Error SpeedStep™ technology support, this signal is kept high during a
Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains Intel® SpeedStep™ technology state transition to prevent loss of
asserted until FERR# is negated. If FERR# is not asserted when the processor context. This is an open-drain output signal (external
Coprocessor Error Register is written, the IGNNE# signal is not pull-up resistor required) that represents a logical AND of the
asserted. ICH2-M’s PWROK and VGATE / VRMPWRGD signals.
Speed Strap: During the reset sequence, ICH2 drives IGNNE# high
if the corresponding bit is set in the FREQ_STRP register.
INIT# O Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to
reset the processor. ICH2 can be configured to support processor
BIST. In that case, INIT# will be active when PCIRST# is active. SM Bus Interface Signals
INTR O Processor Interrupt: INTR is asserted by the ICH2 to signal the Name Type Description
processor that an interrupt request is pending and needs to be SMBDATA I/OD SMBus Data: External pull-up is required.
serviced. It is an asynchronous output and normally driven low.
SMBCLK I/OD SMBus Clock: External pull-up is required.
Speed Strap: During the reset sequence, ICH2 drives INTR high if
the corresponding bit is set in the FREQ_STRP register. SMBALERT#/ I SMBus Alert: This signal is used to wake the system or generate an
NMI O Non-Maskable Interrupt: NMI is used to force a non-maskable GPIO[11] SMI#. If not used for SMBALERT#, it can be used as a GPI.
interrupt to the processor. The ICH2 can generate an NMI when
either SERR# or IOCHK# is asserted. The processor detects an NMI
when it detects a rising edge on NMI. NMI is reset by setting the
corresponding NMI source enable/disable bit in the NMI Status and
Control Register.
Speed Strap: During the reset sequence, ICH2 drives NMI high if the
corresponding bit is set in the FREQ_STRP register.
128

System Management Interface Signals Miscellaneous Signals
INTRUDER# I Intruder Detect: This signal can be set to disable system if box SPKR O Speaker: The SPKR signal is the output of counter 2 and is internally
detected open. This signal’s status is readable, so it can be used like a "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This
GPI if the Intruder Detection is not needed. signal drives an external speaker driver device, which in turn drives
SMLINK[1:0] I/OD System Management Link: These signals are an SMBus link to an the system speaker. Upon PCIRST#, its output state is 1.
optional external system management ASIC or LAN controller. Note:
SPKR is sampled at the rising edge of PWROK as a functional strap.
External pull-ups are required.
RTCRST# I RTC Reset: When asserted, this signal resets register bits in the RTC
Note:
well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3
that SMLINK[0] corresponds to an SMBus Clock signal and
register). Note:
SMLINK[1] corresponds to an SMBus Data signal. Clearing CMOS in an ICH2-based platform can be done by using a
jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
Real Time Clock Interface TP0 I Test Point (82801BA ICH2): This signal must have an external
Name Type Description (ICH2 0nly) pull-up to VccSus3_3.
FS0 I Functional Strap: This signal is reserved for future use. There is an
RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 KHz crystal.
internal pullup resistor on this signal.
If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.
RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 KHz crystal.
If no external crystal is used, then RTCX2 should be left floating.
AC’97 Link Signals
AC_RST# O AC97 Reset: Master H/W reset to external Codec(s)
Other Clocks AC_SYNC O AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s)
AC_BIT_CLK I AC97 Bit Clock: 12.288 MHz serial data clock generated by the
CLK14 I Oscillator Clock: CLK14 is used for 8254 timers and runs at external Codec(s). See Note.
14.31818 MHz. AC_SDOUT O AC97 Serial Data Out: Serial TDM data output to the Codec(s)
82801BA ICH2: This clock is permitted to stop during S3 (or lower) Note:
states. AC_SDOUT is sampled at the rising edge of PWROK as a functional
82801BAM ICH2-M: This clock is permitted to stop during S1 (or strap..
lower) states. AC_SDIN[1:0] I AC97 Serial Data In 0: Serial TDM data inputs from the Codecs.
CLK48 I 48 MHz Clock: CLK48 is used to for the USB controller and runs at See Note.
48 MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
CLK66 I 66 MHz Clock: CLK66 is used to for the hub interface and runs at 66
MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
129
5.4 PCI4410(PCMCIA/1394 LINK Controller )

Power-Supply Terminals PCI Address and Data Terminals
GND Device ground terminals AD[0:31[ I/O PCI address/data bus. These signals make up the multiplexed PCI
VCC Power-supply terminal for core logic (3.3 V) address and data bus on the primary interface. During the address
phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit
VCCB Clamp voltage for PC Card interface. Matches card signaling address or other destination information. During the data phase,
environment, 5 V or 3.3 V. AD31–AD0 contain data.
VCCI Clamp voltage for miscellaneous I/O signals (MFUNC, GRST#, and C/BE[0:3]# I/O PCI bus commands and byte enables. These signals are multiplexed
SUSPEND#) on the same PCI terminals. During the address phase of a primary bus
VCCL Clamp voltage for 1394 link function PCI cycle, C/BE3#–C/BE0# define the bus command. During the data
VCCP Clamp voltage for PCI interface, ZV interface, SPKROUT, INTA#, phase, this 4-bit bus is used as byte enables. The byte enables
INTB# LED_SKT,VCCD0#, VCCD1#, VPPD0, VPPD1 determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0# applies to byte 0 (AD7–AD0), C/BE1#
applies to byte 1 (AD15–AD8), C/BE2# applies to byte 2
PC Card Power-Switch Terminals (AD23–AD16), and C/BE3# applies to byte 3 (AD31–AD24).
Name Type Description PAR I/O PCI bus parity. In all PCI bus read and write cycles, the PCI4410A
VCCD0# O Logic controls to the TPS2211 PC Card power-switch interface to device calculates even parity across the AD31–AD0 and
VCCD1# control AVCC C/BE3#–C/BE0# buses. As an initiator during PCI cycles, the
VPPD0 O Logic controls to the TPS2211 PC Card power-switch interface to PCI4410A device outputs this parity indicator with a one-PCLK
VPPD1 control AVPP delay. As a target during PCI cycles, the calculated parity is compared
to the initiator’s parity indicator. A compare error results in the
assertion of a parity error (PERR#).
PCI System Terminals
GRST# I Global reset. When global reset is asserted, GRST# causes the PCI Interface Control Terminals
PCI4410A device to place all output buffers in a high-impedance Name Type Description
state and reset all internal registers. When GRST# is asserted, the DECSEL# I/O PCI device select. The PCI4410A device asserts DEVSEL# to claim a
device is completely in its default state. For systems that require PCI cycle as the target device. As a PCI initiator on the bus, the
wake-up from D3, GRST# normally is asserted only during initial PCI4410A device monitors DEVSEL# until a target responds. If no
boot. PRST# should be asserted following initial boot so that PME target responds before timeout occurs, the PCI4410A device
context is retained when transitioning from D3 to D0. For systems terminates the cycle with an initiator abort.
that do not require wake-up from D3, GRST# should be tied to PRST. FRAME# I/O PCI cycle frame. FRAME# is driven by the initiator of a bus cycle.
When the SUSPEND mode is enabled, the device is protected from FRAME# is asserted to indicate that a bus transaction is beginning,
GRST#, and the internal registers are preserved. All outputs are and data transfers continue while this signal is asserted. When
placed in a high-impedance state, but the contents of the registers are FRAME# is deasserted, the PCI bus transaction is in the final data
preserved. phase.
PCLK I PCI bus clock. PCLK provides timing for all transactions on the PCI GNT# I PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the
bus. All PCI signals are sampled at the rising edge of PCLK. PCI4410A device access to the PCI bus after the current data
PRST# I PCI bus reset. When the PCI bus reset is asserted, PRST# causes the transaction has completed. GNT# may or may not follow a PCI bus
PCI4410A device to place all output buffers in a high-impedance request, depending on the PCI bus parking algorithm.
state and reset internal registers. When PRST is asserted, the device is IDSEL# I Initialization device select. IDSEL# selects the PCI4410A device
completely nonfunctional. After PRST# is deserted, the PCI4410A during configuration space accesses. IDSEL# can be connected to one
device is in a default state. When SUSPEND# and PRST# are of the upper 24 PCI address lines on the PCI bus.
asserted, the device is protected from PRST# clearing the internal
registers.All outputs are placed in a high-impedance state, but the
contents of the registers are preserved.
130

PCI Interface Control Terminals
IRDY# I/O PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to MFUNC1 I/O Multifunction terminal 1. MFUNC1 can be configured as GPI1,
complete the current data phase of the transaction. A data phase is GPO1, socket activity LED output, ZV switching outputs, CardBus
completed on a rising edge of PCLK, when both IRDY# and TRDY# audio PWM, GPE#, or a parallel IRQ. See Section 4.32,
are asserted. Until IRDY# and TRDY# are both sampled asserted, Multifunction Routing Register, for configuration details.
wait states are inserted. Serial data (SDA). When VCCD0# and VCCD1# are high after a PCI
PERR# I/O PCI parity error indicator. PERR# is driven by a PCI device to reset, the MFUNC1 terminal provides the SDA signaling for the serial
indicate that calculated parity does not match PAR when PERR# is bus interface. The two-terminal serial interface loads the subsystem
enabled through bit 6 (PERR_EN) of the command register (PCI identification and other register defaults from an EEPROM after a
offset 04h, see Section 4.4). PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for
REQ# O PCI bus request. REQ# is asserted by the PCI4410A device to request details on other serial bus applications.
access to the PCI bus as an initiator. MFUNC2 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI
SERR# O PCI system error. SERR# is an output that is pulsed from the DMA request, GPI2, GPO2, ZV switching outputs, CardBus audio
PCI4410A device when enabled through bit 8 (SERR_EN) of the PWM, GPE#, RI_OUT#, or a parallel IRQ. See Section 4.32,
command register (PCI offset 04h, see Section 4.4) indicating a Multifunction Routing Register, for configuration details.
system error has occurred. The PCI4410A device need not be the MFUNC3 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel
target of the PCI cycle to assert this signal. When SERR# is enabled IRQ or the serialized interrupt signal IRQSER. See Section 4.32,
in the command register, this signal also pulses, indicating that an Multifunction Routing Register, for configuration details.
address parity error has occurred on a CardBus interface. MFUNC4 I/O Multifunction terminal 4. MFUNC4 can be configured as PCI
STOP# I/O PCI cycle stop signal. STOP# is driven by a PCI target to request the LOCK#, GPI3, GPO3, socket activity LED output, ZV switching
initiator to stop the current PCI bus transaction. STOP# is used for outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ.
target disconnects and is commonly asserted by target devices that do See Section 4.32, Multifunction Routing Register, for configuration
not support burst data transfers. details. Serial clock (SCL). When VCCD0# and VCCD1# are high
TRDY# I/O PCI target ready. TRDY# indicates the primary bus target’s ability to after a PCI reset, the MFUNC4 terminal provides the SCL signaling
complete the current data phase of the transaction. A data phase is for the serial bus interface. The two-terminal serial interface loads the
completed on a rising edge of PCLK, when both IRDY# and TRDY# subsystem identification and other register defaults from an EEPROM
are asserted. Until both IRDY# and TRDY# are asserted, wait states after a PCI reset. See Section 3.6.1, Serial Bus Interface
are inserted. Implementation, for details on other serial bus applications.
MFUNC5 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI
DMA grant, GPI4, GPO4, socket activity LED output, ZV switching
Multifunction and Miscellaneous Terminals outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section
Name Type Description 4.32, Multifunction Routing Register, for configuration details.
INTA# O Parallel PCI interrupt. INTA# MFUNC6 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI
INTB# O Parallel PCI interrupt. INTB# CLKRUN# or a parallel IRQ. See Section 4.32, Multifunction
LED_SKT O PC Card socket activity LED indicator. LED_SKT provides an output Routing Register, for configuration details.
indicating PC Card socket activity. RI_OUT#/PME# O Ring indicate out and power-management event output. Terminal
MFUNC0 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI provides an output for ring-indicate or PME# signals.
interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV SPKROUT O Speaker output. SPKROUT is the output to the host system that can
switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. carry SPKR# or CAUDIO through the PCI4410A device from the PC
See Section 4.32, Multifunction Routing Register, for configuration Card interface. SPKROUT is driven as the exclusive-OR combination
details. of card SPKR#//CAUDIO inputs.
SUSPEND# I Suspend. SUSPEND# protects the internal registers from clearing
when the GRST or PRST signal is asserted. See Section 3.8.4,
Suspend Mode, for details.
131

16-Bit PC Card Address and Data Terminals
ADDR[0:25] O PC Card address. 16-bit PC Card address lines. ADDR25 is the most CE1# O Card enable 1 and card enable 2. CE1# and CE2# enable even- and
significant bit CE2# odd-numbered address bytes. CE1#enables even-numbered address
DATA[0:15] I/O PC Card data. 16-bit PC Card data lines. DATA15 is the most bytes, and CE2# enables odd-numbered address bytes.
significant bit. INPACK# I Input acknowledge. INPACK# is asserted by the PC Card when it
can respond to an I/O read cycle at the current address.DMA request.
INPACK# can be used as the DMA request signal during DMA
16-Bit PC Card Interface Control Terminals operations from a 16-bit PC Card that supports DMA. If it is used as a
Name Type Description strobe, the PC Card asserts this signal to indicate a request for a DMA
BVD1 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC operation.
(STSCHG#/RI#) Cards that include batteries. BVD1 is used with BVD2 as an IORD# O I/O read. IORD# is asserted by the PCI4410A device to enable 16-bit
indication of the condition of the batteries on a memory PC Card. I/O PC Card data output during host I/O read cycles. DMA write.
Both BVD1 and BVD2 are high when the battery is good. When IORD# is used as the DMA write strobe during DMA operations from
BVD2 is low and BVD1 is high, the battery is weak a 16-bit PC Card that supports DMA. The PCI4410A device asserts
and should be replaced. When BVD1 is low, the battery is no longer IORD# during DMA transfers from the PC Card to host memory.
serviceable and the data in the memory PC Card is lost. See Section IOWR# O I/O write. IOWR# is driven low by the PCI4410A device to strobe
5.6, ExCA Card Status-Change-Interrupt Configuration Register, for write data into 16-bit I/O PC Cards during host I/O write cycles.
enable bits. See Section 5.5, ExCA Card Status-Change Register, and DMA read. IOWR# is used as the DMA write strobe during DMA
Section 5.2,ExCA Interface Status Register, for the status bits for this operations from a 16-bit PC Card that supports DMA. The PCI4410A
signal. Status change. STSCHG# is used to alert the system to a device asserts IOWR during transfers from host memory to the PC
change in the READY, write protect, or battery voltage dead Card.
condition of a 16-bit I/O PC Card. Ring indicate. R# is used by 16-bit OE# O Output enable. OE# is driven low by the PCI4410A device to enable
modem cards to indicate a ring detection. 16-bit memory PC Card data output during host memory read cycles.
DMA terminal count. OE# is used as terminal count (TC) during
BVD2 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC DMA operations to a 16-bit PC Card that supports DMA. The
(SPKR#) Cards that include batteries. BVD2is used with BVD1 as an PCI4410A device asserts OE# to indicate TC for a DMA write
indication of the condition of the batteries on a memory PC Card. operation.
Both BVD1and BVD2 are high when the battery is good. When READ I Ready. The ready function is provided by READY when the 16-bit
BVD2 is low and BVD1 is high, the battery is weak and should be IREQ# PC Card and the host socket are configured for the memory-only
replaced. When BVD1 is low, the battery is no longer serviceable and interface. READY is driven low by the 16-bit memory PC Cards to
the data in the memory PC Card is lost. See Section 5.6, ExCA Card indicatethat the memory card circuits are busy processing a previous
Status-Change-Interrupt Configuration Register, for enable bits. See write command. READY is driven high when the 16-bit memory PC
Section 5.5, ExCA Card Status-Change Register, and Section 5.2, Card is ready to accept a new data-transfer command. Interrupt
ExCA Interface Status Register, for the status bits for this signal. request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the
Speaker. SPKR# is an optional binary audio signal available only host that a device on the 16-bit I /O PC Card requires service by the
when the card and socket have been configured for the 16-bit I/O host software. IREQ# is high (deasserted) when no interrupt is
interface. The audio signals from cards A and B are combined by the requested.
PCI4410A device and are output on SPKROUT.DMA request. BVD2
can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.
CD1# I Card detect 1 and Card detect 2. CD1# and CD2# are connected
CD2# internally to ground on the PC Card. When a PC Card is inserted into
a socket, CD1# and CD2# are pulled low. For signal status, see
Section 5.2, ExCA Interface Status Register.
132

16-Bit PC Card Interface Control Terminals CardBus PC Card Interface System Terminals
REG# O Attribute memory select. REG# remains high for all common CCLK O CardBus clock. CCLK provides synchronous timing for all
memory accesses. When REG# is asserted, access is limited to transactions on the CardBus interface. All signals except CRST#,
attribute memory (OE# or WE# active) and to the I/O space (IORD# CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#,
or IOWR# active). Attribute memory is a separately accessed section CVS2, and CVS1 are sampled on the rising edge of CCLK, and all
of card memory and generally is used to record card capacity and timing parameters are defined with the rising edge of this signal.
other configuration and attribute information. DMA acknowledge. CCLK operates at the PCI bus clock frequency, but it can be stopped
REG is used as a DMA acknowledge (DACK#) during DMA in the low state or slowed down for power savings.
operations to a 16-bit PC Card that supports DMA. The PCI4410A CCLKRUN# I/O CardBus clock run. CCLKRUN# is used by a CardBus PC Card to
device asserts REG# to indicate a DMA operation. REG# is used in request an increase in the CCLK frequency, and by the PCI4410A
conjunction with the DMA read (IOWR#) or DMA write (IORD#) device to indicate that the CCLK frequency is going to be decreased.
strobes to transfer data. CRST# O CardBus reset. CRST# brings CardBus PC Card-specific registers,
RESET O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. sequencers, and signals to a known state. When CRST# is asserted,
WAIT# I Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the all CardBus PC Card signals are placed in a high-impedance state,
completion of the memory or I/O cycle in progress. and the PCI4410A device drives these signals to a valid logic level.
WE# O Write enable. WE# is used to strobe memory write data into 16-bit Assertion can be asynchronous to CCLK, but deassertion must be
memory PC Cards. WE# also is used for memory PC Cards that synchronous to CCLK.
employ programmable memory technologies. DMA terminal count.
WE# is used as TC during DMA operations to a 16-bit PC Card that
supports DMA. The PCI4410A device asserts WE to indicate TC for CardBus PC Card Address and Data Terminals
a DMA read operation. Name Type Description
WP I Write protect. WP applies to 16-bit memory PC Cards. WP reflects CAD[0:31] I/O CardBus address and data. These signals make up the multiplexed
IOIS16# the status of the write-protect switch on 16-bit memory PC Cards. For CardBus address and data bus on the CardBus interface. During the
16-bit I/O PC cards, WP is used for the 16-bit port (IOIS16#) address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit
function. I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. address. During the data phase of a CardBus cycle, CAD31–CAD0
IOIS16# is asserted by the 16-bit PC Card when the address on the contain data. CAD31 is the most significant bit.
bus corresponds to an address to which the 16-bit PC Card responds,
CC/BE[0:3]# I/O CardBus bus commands and byte enables. CC/BE3#–CC/BE0# are
and the I/O port that is addressed is capable of 16-bit accesses.
multiplexed on the same CardBus terminals. During the address phase
DMA request. WP can be used as the DMA request signal during
of a CardBus cycle, CC/BE3#–CC/BE0# define the bus command.
DMA operations to a 16-bit PC Card that supports DMA. If used, the
During the data phase, this 4-bit bus is used as byte enables. The byte
PC Card asserts WP to indicate a request for a DMA operation.
enables determine which byte paths of the full 32-bit data bus carry
VS1# I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in meaningful data. CC/BE0# applies to byte 0 (CAD7–CAD0),
VS2# conjunction with each other, determine the operating voltage of the CC/BE1# applies to byte 1 (CAD15–CAD8), CC/BE2# applies to
PC Card. byte 2 (CAD23–CAD16), and CC/BE3# applies to byte 3
(CAD31–CAD24).
CPAR I/O CardBus parity. In all CardBus read and write cycles, the PCI4410A
device calculates even parity across the CAD and CC/BE buses. As
an initiator during CardBus cycles, the PCI4410A device outputs
CPAR with a one-CCLK delay. As a target during CardBus cycles,
the calculated parity is compared to the initiator’s parity indicator; a
compare error results in a parity-error assertion.
133

CardBus PC Card Interface Control Terminals
CAUDIO I CardBus audio. CAUDIO is a digital input signal from a PC Card to CSTOP# I/O CardBus stop. CSTOP# is driven by a CardBus target to request the
the system speaker. The PCI4410A device supports the binary audio initiator to stop the current CardBus transaction. CSTOP# is used for
mode and outputs a binary signal from the card to SPKROUT. target disconnects, and is commonly asserted by target devices
CBLOCK# I/O CardBus lock. CBLOCK# is used to gain exclusive access to a do not support burst data transfers.
target. CSTSCHG# I CardBus status change. CSTSCHG alerts the system to a change in
CCD1# I CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are the card’s status, and is used a wake-up mechanism.
CCD2# used in conjunction with CVS1 and CVS2 to identify card insertion CTRDY# I/O CardBus target ready. CTRDY# indicates the CardBus target’s
and interrogate cards to determine the operating voltage and card ability to complete the current data phase of the transaction. A data
type. phase is completed on a rising edge of CCLK, when both CIRDY and
CDEVSEL# I/O CardBus device select. The PCI4410A device asserts CDEVSEL# to CTRDY# are asserted; until this time, wait states are inserted.
claim a CardBus cycle as the target device. As a CardBus initiator on CVS1 CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and
the bus, the PCI4410A device monitors CDEVSEL# until a target CVS2 CVS2 are used in conjunction with CCD1# and CCD2# to identify
responds. If no target responds before timeout occurs, the PCI4410A card insertion and interrogate cards to determine the operating voltage
device terminates the cycle with an initiator abort. and card type.
CFRAME# I/O CardBus cycle frame. CFRAME# is driven by the initiator of a
CardBus bus cycle. CFRAME# is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal IEEE 1394 PHY/Link Interface Terminals
is asserted. When CFRAME# is deasserted, the CardBus bus Name Type Description
transaction is in the final data phase. PHY_CTL1 I/O PHY-link interface control. These bidirectional signals control
CGNT# O CardBus bus grant. CGNT# is driven by the PCI4410A device to PHY_CTL0 passage of information between the PHY and link. The link can drive
grant a CardBus PC Card access the CardBus bus after the current these terminals only after the PHY has granted permission, following
data transaction has been completed. a link request (LREQ).
CINT# I CardBus interrupt. CINT# is asserted low by a CardBus PC Card to PHY_DATA[0:7] I/O PHY-link interface data. These bidirectional signals pass data
request interrupt servicing from the host. between the PHY and link. These terminals are driven by the link on
CIRDY# I/O CardBus initiator ready. CIRDY indicates the CardBus initiator’s transmissions and are driven by the PHY on receptions. Only
ability to complete the current data DATA1–DATA0 are valid for 100-Mbit speed. DATA4–DATA0 are
phase of the transaction. A data phase is completed on a rising edge valid for 200-Mbit speed and DATA7–DATA0 are valid for 400-Mbit
speed.
of CCLK when both CIRDY and
PHY_CLK I System clock. This input provides a 49.152-MHz clock signal for
CTRDY are asserted. Until both CIRDY and CTRDY are sampled data synchronization.
asserted, wait states are inserted. PHY_REQ O Link request. This signal is driven by the link to initiate a request for
CPERR# I/O CardBus parity error. CPERR# reports parity errors during CardBus the PHY to perform some
transactions, except during special cycles. It is driven low by a target service.
two clocks following that data when a parity error is detected. LINKON I 1394 link on. This input from the PHY indicates that the link should
CREQ# I CardBus request. CREQ# indicates to the arbiter that the CardBus turn on.
PC Card desires use of the CardBus bus as an initiator. LPS O Link power status. LPS indicates that link is powered and fully
CSERR# I CardBus system error. CSERR# reports address parity errors and functional.
other system errors that could lead to catastrophic results. CSERR# is
driven by the card synchronous to CCLK, but deasserted by a weak
pull up, and may take several CCLK periods. The PCI4410A device
can report CSERR# to the system by assertion of SERR# on the PCI
interface.
134

Zoomed-Video Interface Terminals
ZV_HREF O Horizontal sync to the zoomed-video port
ZV_VSYHC O Vertical sync to the zoomed-video port
ZV_Y[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format
ZV_UV[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format
ZV_SCLK O Audio SCLK PCM
ZV_MCLK O Audio MCLK PCM
ZV_PCLK IO Pixel clock to the zoomed-video port
ZV_LRCLK O Audio LRCLK PCM
ZV-SDATA O Audio SDATA PCM
135
6. System Block Diagram

U1 VID[0:4]
Pentium 4
mFC-PGA2 478 Pin
J2
LCD Panel
PU508
400M CPU_CORE LTC1709
J1 U516 AGP4X 66M
Monitor
ATI VGA U3
133M J503 SO-DIMM1
J5 D/D 82845 MCH
TV OUT Board 593 PIN
mBGA J505 SO-DIMM2
U14
J14 1394
HDD TSB41AB1
IDE1 X3
32.768KHZ
J10 CD-ROM
IDE2 U7 J21
U8 PCI BUS 33M U7 Mini
U8
82801BA
82801BA ICH2
ICH2 1394
PCI4410
PCI4410
USB 360
360 PIN
PIN mBGA
mBGA
J2,J3 D/D U4
U4
USB Port Board
LANPHY U15
U15
LANPHY AUDIO J8
RTL8139CL AUDIO CODEC
CODEC
RTL8139CL Card BUS
LPC BUS Socket
U509
U509
D/D
Board Supper
Supper I/O
I/O
PC87393 ISA BUS J15
PC87393 U508 Touch Pad
U508 J12
H8/3437
H8/3437 Internal
U18
U18 J19
U12
U12 Amplifier Line Out
J1
Flash
Keyboard Amplifier
PIO Port FlashROM
ROM
136
7. Maintenance Diagnostic
7.1 Introduction
Every time the computer is turned on ,the system BIOS runs a series of internal checks on the
hardware. This power-on self test (post) allows the computer to detect problems as early as the
power-on stage. Error messages of post can alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If
the error occurs before the display, then the screen cannot display the error message. Error codes
or system beeps are used to identify a post error that occurs when the screen is not available.
The value for the diagnostic post (378H) is written at the beginning of the test. Therefore , if the
test fail, the user can determine where the problem occurs by reading the last value written to
post 378H by the PIO debug board plug at PIO port.
137
7.2 Error codes :

Following is a list of error codes in sequent display on the PIO debug board.
Code POST Routine Description Code POST Routine Description

10h Some type of lone reset 20h Test keyboard
11h Turn off FAST A20 for POST 21h Test keyboard controller
12h Signal power on reset 22h Check if CMOS RAM valid
13h Initialize the chipset 23h Test battery fail & CMOS X-SUM
14h Search for ISA Bus VGA adapter 24h Test the DMA controller
15h Reset counter / Timer 1 25h Initialize 8237A controller
16h User register config through CMOS 26h Initialize int vectors
17h Sizememory 27h RAM quick sizing
18h Dispatch to RAM test 28h Protected mode entered safely
19h Check sum the ROM 29h RAM test completed
1Ah Reset PIC’s 2Ah Protected mode exit successful
1Bh Initialize video adapter(s) 2Bh Setup shadow
1Ch Initialize video (6845Regs) 2Ch Going to initialize video
1Dh Initialize color adapter 2Dh Search for monochrome adapter
1Eh Initialize monochrome adapter 2Eh Search for color adapter
1Fh Test 8237A page registers 2Fh Signon messages displayed
138
7.2 Error codes :

Following is a list of error codes in sequent display on the PIO debug board.
Code POST Routine Description Code POST Routine Description

30h Special init of keyboard ctlr 40h Configure the COMM and LPT ports
31h Test if keyboard Present 41h Initialize the floppies
32h Test keyboard Interrupt 42h Initialize the hard disk
33h Test keyboard command byte 43h Initialize option ROMs
34h Test, blank and count all RAM 44h OEM’s init of power management
35h Protected mode entered safely(2) 45h Update NUMLOCK status
36h RAM test complete 46h Test for coprocessor installed
37h Protected mode exit successful 47h OEM functions before boot
38h Update output port 48h Dispatch to operate system boot
39h Setup cache controller 49h Jump into bootstrap code
3Ah Test if 18.2Hz periodic working
3Bh Test for RTC ticking
3Ch Initialize the hardware vectors
3Dh Search and init the mouse
3Eh Update NUMLOCK status
3Fh Special init of COMM and LPT ports
139
7.3 Debug Card

7.3.1 Diagnostic Tools :
The 378 Port Debug Card, a kind of tool, is designed mainly for Notebook . It can be used to test the
process of BIOS POST system. It composed of eight . LED and one PIO CONNECTOR as the below
figure shows
P/N:411904800001
DESCRIPTION :PWA;PWA-378PORT DEBUG BD
Note:Order it from MIC/TSSC
140
7.3 Debug Card

7.3.2 CIRCUIT:
25 14
PIO
13 1
CONNECTOR
LED
PIN DEFINITION OF PIO PORT

PIN 1 STB STROBE SIGNAL PIN 14 AFD AUTO LINE FEED
PIN 2-9 D0 - D7 PARALLEL PORT DATA BUS D0 TO D7 PIN15 ERR ERROR AT PRINTER
PIN10 ACK ACKNOWLEDGE HANDSHANK PIN16 INIT INITIATE OUTPUT
PIN11 BUSY BUSY SIGNAL PIN17 SLIN PRINTER SELECT
PIN12 PE PAPER END SIGNAL
PIN18-25
PIN13 SLCT PRINTER SELECTED GROUND
141
8.Trouble Shooting
8.1 No Power 8.9 CD-ROM Drive Test Error
8.2 Battery Can not Be Charged 8.10 USB Port Test Error
8.3 No Display 8.11 PIO Port Test Error
8.4 VGA Controller Failure LCD No Display 8.12 PC-Card Failure
8.5 VGA Controller Failure External Monitor 8.13 IEEE1394 Failure

No Display
8.6 Memory Test Error 8.14 Audio Failure
8.7 Keyboard(K/B) and Touch Pad(T/B) Test Error 8.15 LAN Test Error
8.8 Hard Drive Test Error
142
8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
PF501 PQ512
PL502
+5VAS P20
P2 PL503 P2 P21 P11
PD2 JS7 PU7 PL8 P20 D509 PU12 L6,L7
Power In ALWAYS +5VA VCC_RTC P13 +1.8VS VDD_DAC1.8
J5 PD501
P17 P11
L520 Q514 L507
H8_VDD5 P19 +3VS_SPD VDD_PLL1.8
PQ502
P11
PQ503 PR513 PL500 PL501PU1, L516 P8 L4
PR514 PD4-PD6 P2 PU2,PU500-PU508
P21
+3VCLKPCI VDD_PNLLL1.8
DVMAIN CPU_CORE P11
L518 P8 L514
Charge +3VCLKANA VDD_MEMPLL1.8
Board P8
L517
PU505 +3VCLKCPU
P1 P2
PU506 PU501
JL3 +3V +3VS L519 P8
+3VCLK66
JL2 U511
PU1 P1 PQ2 P2 P17 JL1
PL3 JS502 P15 VCC3_IR Mother
+12V +12VS AVDDAD L20
ADNP ADNP_1 ADNP_2 1394AVDD Board
P2 P2 P2
PU502 P16 P16
P1 PU504 P2 JS10 L12 L10
PU503 +3V_LAN AVDD_LAN
PU10
+5V +5VS
PU11 U504 P10
PU511,PU5 PU13 P21 R33
PU6,PL7, +1.5VS AGP_VREF
PU512,PU9
DBATT
PU8 P11 P11
PD4-PD6 P22 U505 L506
5V_AMP VDDR_MEM2.5 VDD_DAC2.5
VPPA VCCA P17
P15 L11 P11
P15
PU514
VDD_MCLK2.5
+3V_ICH +1.8V_ICH
P20 P21
143
8.1 No Power (1)

Power on Sequence
144
8.1 No Power (2)

2
PD2 3
1
PQ503 2
PJ1 J3 P22
SI4835DY PD3 ALWAYS 8
3
8
3 7 1
2 6
1 5 ADINP 10,12
S
D
G
PR4
JL2 DVMIAN 1
470K
PL502
120Z/100M
PR514 .1 JL3 MB
PQ502
SI4835DY
PF501 PL503 8
J5 6.5A/32VDC
120Z/100M 3 7 PR513 .1 PD6
2 6
1 5
S
D
PC505 PC510 PC509 PD501 G PD5
PC19 PR10 PC17
1U 0.1U 0.1U RLZ24D 100U 10K PJ2
POWER IN 0.1U J6 P22
PD4 ADINP_1 1 1
PR5
470k ADINP_2 2 2
+5VA
P20
PR16 D
470K PQ1 PR9 47K
2N7002 G LEARNING 3 3
PQ2 3 S
1
PR6 MB
100K
2
PC26
PL8 0.1U +5V
ALWAYS JS7 PU7 G
8 6
IN 5VTAP P19
2
SENSE OUT
1 S D Step1 : Connect Adaptor to ( D/D BD ) J5 & O/P “ALWAYS”.
12 LEARNING
7
SW_+5VA
3
FB ERR-
4 PD7 PQ1 Step2 : “ALWAYS” --> PU7 Generate +5VA. U508
SHUTDN GND PC24 S1231DS
From H8 10U Step3 : H8 O/P “LEARNING” for Charger Circuitry. H8
F3437 19 SW +5VA
Step4 : For MOSFET “PQ502&PQ503” G=0,D<-->S.
Mother Board Step5 : O/P “ADINP”& “DVMAIN”.
145
8.1 No Power (3)

PU11
SI4835DY P20 +5VA +5VAS
8
7 3
6 2
5 1 S D
PQ512
S
PR573 G
G
100K PD503 -ADEN(From H8)
J28 PL9 120Z
3 +3V
P20 1
PL10 120Z PF2 PU10 PQ511
SI4835DY
8 +5VA---->+5VAS 1
PL11 120Z PF1 7 3 DVMAIN
1,2 DBATT 6 2
5 1
S
D
G PR554
PC32 PC30 1M +5VAS
0.01U 0.1U
DVMAIN
Battery Connector
PR559 +5VA PR567 PR572 PR564
100K P19 47 100K 100K 475K
+12VS PU13 P21
8 PR563 U508 3 8 3
3 AO4400 PQ508 D +
+3V 7
+1.5VS 100K 1 BATT_DEAD 1
6 2 2N7002 H8 - 2
5 1 4
G -ADEN 30 F3437 2
D S S Q510 PU513A
PR23 4.7K G LMV393M
PR22 DTC144TKA
PQ510 PR566
4.7K PC44
PC42 SCK431 100K
10U P22 3
470P
PQ3 ADINP 1 PQ509
PC43 SCK431LCSK-5 PC45
PR561 DTC144WK
10P PR24 0.1U
4.7K 169K 2
Battery OVP
+3V---->+1.5VS
P21 +3VS ----> +1.8VS P21
+3V_ICH ----> +1.8V_ICH +3VS PU12 +1.8VS
+5V P20 AMS1085
+5V---->+3V_ICH +3V_ICH +1.8V-ICH 3
+3V_ICH PU514 VIN VOUT 2
PR616 1 VIN OUT 5
0 PU8 3 EN GND/ADJ PR19
2 3 2 4 PC558 1 1.2K PC9
VIN VOUT GND BYP PC37 PC10
4.7U 100U
1 PC559 AME8801 4.7U 0.1U
GND PC27 PC22 PC560
PC29 1U MEEV
4.7U 4.7U D8 0.1U 0.01U
RLZ3.6B PR20
560
146
8.1 No Power
Battery can not Charge
Check the following parts for cold solder or one of the following
Is the parts on the D/D Board may be defective, use an oscilloscope
notebook connected No
Connect to check the following signal or replace the parts one at a time and
to power (AC adaptor)? AC adaptor. test after each replacement.8
Yes Parts Signal
1. Make sure that the battery is good. J5 PL502 PL503 PD[501:503] ALWAYS ADINP
2. Make sure that the battery is installed properly. Board-level PQ1 PR5 PR9 PR514 DVMAIN ADINP_1
3. Check the D/D board is connected to M/B properly. Troubleshooting PR513 JL2 JL3 PD[2:6]
ADINP_2 LEARNING
PJ1 PJ2 J6 U508
Power Yes
Correct it.
OK?
No Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
Try another known good D/D Board. to check the following signal or replace the parts one at a time and
Board-level
test after each replacement.
Troubleshooting
Parts Signal
Yes PU7 PQ2 PL8 PQ1 +5VA SW_+5VA
Power Replace the
J28 PL[9:11] PF1 PF2 DBATT ADINP
OK? faulty D/D Board PU10 PU11 PR554 PR559
-ADEN BATT_DEAD
PQ[508:510] U508 Q510
No PU513 PR567 PR572 DVMAIN
Replace
PR564 PR566
Motherboard
147
8.2 Battery Can not Be Change

When the battery is installed but the battery status indicate LED display abnormal.
J3
10,12 ADINP
+5VAS
PR532 PR534 100K
D/D Board 10 PR569
PD5 PD4 1M
connector PR541 100K PR557 33
PR572
8 IN 5VTAP 6 100K
2
SENSE OUT 1 PC535 LI_OVP 8 5
PR570 12.1K
7 4.7U PC551 PL5 PL6 7 +
F/B
GNT 4 - 6
3 DBATT
SHUTDN 15 16 2 1U
4
VCTL CELLS LD0 PD502
PC536 PU510 PU513B PQ510
13 REFIN 2 LMV393M
0.1U LP295 P22 25 3 5 6 7
8 100K
J6 BST D PC20 PC18
1
PR548 10 10U 100U
2 ADINP_2 26 G
CSSN 24 4 PU5
DHI
PC542 S
PR552 10
1 ADINP_1 27 CSSP 1 2 3 PR13 8 8
0.1U PL7 3 3
0.035 7 7 DBATT
PR546 LX 23 6
5
2 2 6
5
1 1
10K 22 D
S
S D
E DL0V
PQ505 PC23 G G
8
PU511 5 6 7
B
BT3906 D 100U PU512 PU9
MAX1772 PD6 PR551 PC28
C PU6 G
1 21 4 1M 10U
PR547 DCIN DL0 PR14 PR15
33K S 1M 1M
1 2 3
D PC553 PGND 20
LI_OVP PQ506 1U
G 2N7002 PR556
19
S CSIP 1M
CSIN 18
PR553 BATT 17
47K ICTL IINP
PC539 D
PR537 14 28 PC538
PQ507
CHARGING 47K 0.1U 0.1U
69 G 2N7002
PR539 1K S
44
P19
PR555 DBATT
PR615 0 12.1K
40 PL9 120Z
+5VA BAT_V
PL14
PR536 3 PR565 PR562 PF2 PL10 120Z
U508 10K D510 100K 301K +5VAS
PL15
J28
H8 PR18 PF1 PL11 120Z
1,2
F3437 2 1 4.99K P20
39 BAT_VOLT
BAT_T 3
2 7
BAT_C 4
38 BAT_TEMP 1 8
BAT_D 5
99 BAT_CLK 3 6
23 BAT_DATA 4 5 PR17 Battery Connector
20K
RP518 33*4
148
8.2 Battery Can not Be Change

When the battery is installed but the battery status indicate LED display abnormal.
Battery can not Charge
Board-level
Troubleshooting
Is the
notebook connected No
Connect
to power (AC adaptor)? AC adaptor.
Yes Replace parts on the mother-board may be defective, use an oscilloscope
Motherboard to check the following signal or replace the parts one at a time and
test after each replacement.2
Parts Signal
1. Make sure that the battery is good. J3 J6 PU510 ADINP
2. Make sure that the battery is installed properly. PR548 PR552 ADINP_1
PQ505 PQ506
PR546 U508 ADINP_2
PU511 PR557 LI_OVP
PR534 PR541 CHANGING
PD502 PC542 DBTT
Yes PU5 PU6 BAT_T
Battery charge Correct it. PD[4:6] PL[5:7]
PL[9:11] PF[1:2] BAT_C
OK?
PQ507 J28 BAT_D
No PR556 PU513
PQ510 PR570
PR569 PU512
PU9
149
8.3 No Display
System Clock Check
+3VS J503
FS2 FS1 FS0 CPUCLK 61
P8
0 0 1 100MHz
R45 74
0 1 1 52 R592 33 HCLK_CPU
1K 133MHz
U1 142
FS0 54
From Pentium 4
R594 33 -HCLK_CPU SMBDATA0 141
CPU 51
FS1 55
H_BSEL
FS2 40
SDRAMCLK0
J505
R44 R608 33 HCLK_MCH 61
45
1K SDRAMCLK1
R50 -HCLK_MCH
U3 74
41 R612 33 Brookdale-
1K SDRAMCLK4
MCH82845 142
R621 33 66M_MCH66IN
21 SDRAMCLK5
141
R168
21 SMBCLK
+3VS 100K
L517
+5V Q7
120Z/100M 21 SMBDATA
+3VCLKCPU 46,50 FDV302
R51 10K
DS
SMBCLK
C626 C625 U507 39 R624 33 USBCLK_ICH P9 G
0.1U 2.2U U17 3 D
R596 33 14M_ICH
ICS950805 56 ICH2
82801BA
DRAMENA 1 Q6 SMBDATA
DTC144TKA
13 R616 33 PCICLK_ICH
SMBDATA 2
+3VS
L516 R620 33 66M_ICH Q8
D
22
120Z/100M FDV302 G
+3VCLKPCI 8,14 SMBDATA1
S
R609 33 PCICLK_LPC 8 R169
C619 C622 12 U509
0.1U 100K
2.2U R595 33 SIO_14.318MHZ 20 PC87383
R626 33 66M_AGP
23
+3VS
L518
120Z/100M R610 33 PCICLK_LAN
+3VCLKNA 1,26,37 11
C645 C649 10 R607 33 PCICLK_CARD

0.1U 2.2U
3
X502
14.318M
+3VS 3 U7
L519 2 U4 U516
2 PCI4410
120Z/100M RTL8139CL MOBILITY
19,32 4 HK
+3VCLK66 -M6
C618 C617
5P 5P
C641 C646
0.1U 2.2U
150
8.3 No Display
System Reset Check
+5VA
P4
H8_VDD5
L520 P7
U1 -CPURST U3
Pentium 4 MCH
+5VA U10
MAX809
P19 4 9 59 36 37 82845
H_PWRGD
3 2 -H8_RESET P19
VCC RESET# 1 -PCIRST
U13
GND
Level Shift
1 H8_PWROK 5 4 PWROK
21 P13
P10
SN74CBTD3384
+5VA U17 -PCIRST -PCIRST U516
U508 +5V
2 Q513 +3V_ICH
ICH2 VGA
3 D505 -H8_ICH2BIN DTC144TKA -PWRBTN M6
1 BAV99 18 82801BA R158
J5 Micro +5V 4.7K
P19 Controller
Tr>10ms
R100 -PCIRST_MSK
-POWERBTN
5
-PWRSW
23 H8/F3437 10K
-RSMRST
+3V
R617 1K Q15
C634 C181 DTC144TKA
.01U 1U
U16
5
P13
1
-HDD_RST -CDROM_RST A VCC U4
2 4 115
Y
Easy Start 3
B
-PCIRST_N
GNT
Button LANPHY
R56 33 R55 NC7S08 +3V
-BRSTDRV1 33 U8
A 1
2 -BRSTDRV2
5
H8_PWRON VCC
14 1 9 -PCIRST Y
J14 J10 5
R627 1M 3 NC7S08 4
P14 P14 P18
P15
Primary Secondary U509
X503 16MHZ U7
EIDE EIDE
8170 Connector Connector -CBRST
Power PC87393
C630 C633 PCI14410GHK
68P 68P Module
151
8.3 No Display
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor No
or LCD module Replace monitor
OK? or LCD.
Board-level
Yes Troubleshooting
Make sure that CPU module,

DIMM memory are installed
Properly.
If 378 Port Yes

Display Yes According error
OK? Correct it. Replace Have error code Cord to repair
Motherboard
No No
1.Try another known good CPU
module, DIMM module And BIOS.
2.Remove all of I/O device (FDD, Check system clock and reset
HDD, CD-ROM…….) from circuit.
motherboard except LCD or monitor.
1. Replace faulty part.

Display Yes 2. Connect the I/O device to the
To be continued
OK? M/B one at a time to find out
Clock and reset checking
which part is causing the problem.
No
152
8.4 VGA Controller Failure LCD No Display

There is no display or picture abnormal on LCD or monitor.
+3VS
F502 L505 J2
8 Q500 SMDC110 120Z/100M
7 3 NDS9410
6 2 LCDVCC 1,2 P12
TXCLK+, - TXOUT [0:2]+ ,- 5 1
TX2CLK+, - TX2OUT [0:2]+, - D
S
TXCLK+ -
G
C507 +12V
C506
C512 C503 C1 TX2CLK+ -
0.1U R515 10U 0.1U 1000P
470K 0.1U
2 Close to LCD TXOUT [0:2]+ - LCD

Connector
TX2OUT [0:2]+ -
R1
P10 31
Q502 LCD_ID0
ENPVDD DTC144WK 1 3 DISPLAY LCD_ID2 LCD_ID1 LCD_ID0
33
LCD_ID1
UNIQAC 0 0 1 35
U516 +3VS LCD_ID2
LCD_ID0 HYUNDAI 0 1 0 4 3 2 1
VGA-M6 LCD_ID1 HANNSTAR 0 1 1
RP520
47K*4
R22 5 6 7 8
LCD_ID2 CMO 1 0 0
10K
MOBILITY
M6
3 3
+5VAS
-ENABKL 2 2
J6 PJ2 L507
7 ENPBLT1
L510 J6
Q3 7 1
DTC144WK 1 1 Q12
DTC144WK BKL_VMAIN L509
2
P13 P1
3
L508
U17 8 8 BLADJ 4
-ENABKL_MSK
ICH2 5
Inverter
82801BA FA501 6
15 15 -AC_POWER 1 8 7
13 13 -BATT_LED 2 7 8
45 BLADJ 11 11 -BATT_G 3 6 9
P19
9 9 -BATT_R 4 5 10
U508 U514 Inverter Board
90 LED_DATA 1 10 -AC_POWER 11
Micro A QE
2 B 11 -BATT_LED GND1
Controller QF
91 LED_CLK 12 -BATT_G C513 C512
8 GND2
H8/F3437 CLK QG 0.1U 0.1U
1 -H8_RESET 9 13 -BATT_R
CLR QH
D/D Board
153
8.4 VGA Controller Failure LCD No Display

There is no display or picture abnormal on LCD or monitor.
VGA Controller Failure
Board-level
Troubleshooting
1.Confirm monitor is good and check the cable
are connected properly.
2. Try another known good LCD
One of the following parts on the mother-board may be

Replace defective, use an oscilloscope to check the following signal or
Yes Motherboard replace the parts one at a time and test after each replacement.
Display Replace faulty
OK? LCD
Parts: Signals:
U516 U17 -AC_POWER
No
Q3 Q12 -BATT_LED
R22 Q502 -BATT_R
Q500 R515 -BATT_G
Remove all the I/O device & cable from
C506 C507 -ENABLE_MSK
motherboard except extended LCD. -ENABKL
F502 L505
J2 D500 EVPVDD
J1 J6 TXCLK[+:-]
PJ2 FA501 TX2CLK[+:-]
L[508:510] TXOUT[0:2][+:-]
Connect the I/O device & cable TX2OUT[0:2][+:-]
Yes to the M/B one at a time to find U514
Display LCDVCC
L507 C513
OK? out which part is causing the BLADJ
C512
problem. BKL_VMAIN
No
154
8.5 VGA Controller Failure Monitor No Display

There is no display or picture abnormal on monitor.
F501 D500
+3VS +5VS SMDC110 D1FS4
+5VS
DDC2B
R544 R543
J1
4.7K 4.7K P12 16
P10 RED L500 120Z/100M
External VGA Connector

1
9
GREEN L501 120Z/100M 2
10
BLUE L502 120Z/100M 3
U516 G
FA500 11
4
VGA-M6 SDA S D 4 5 12
5
Q502
2N7002 3 6 13
6
MOBILITY 2 7 14
HSYNC 7
1 8
M6 15
8
VSYNC
G 17
SCL S D MONITOR
3
2
4
1
3
3
2
4
1
4
3
1
2
Q501 JL1
2N7002
CP3 RP501 CP501 GND_CRT15
22P*4 75*4 22P*4 CP500
22P*4 JL2
6
7
5
8
6
6
7
5
8
5
6
8
7
155
8.5 VGA Controller Failure Monitor No Display

There is no display or picture abnormal on monitor.
VGA Controller Failure
1.Confirm monitor is good and check the cable

are connected properly. Board-level
2. Try another known good monitor Troubleshooting
Replace
Yes Motherboard
Display Replace faulty
OK? monitor.
One of the following parts on the mother-board may be

No
defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
Remove all the I/O device & cable from
motherboard except extended monitor. Parts: Signals:
U516 R544 RED

R543 Q501 GREEN
Q501 CP3 BLUE
Connect the I/O device & cable RP501 CP501 SDA
Display Yes to the M/B one at a time to find FA500 L500 HSYNC
out which part is causing the L501 L502 VSYNC
OK?
CP500 F501 SCL
problem.
D500 J1
No
156
8.6 Memory Test Error

Either one or two extend SO-DIMM RAM Module is failure or system hangs up.
J505 SO-DIMM
+3V
P9
P7 CK[2:3] CKE[2:3]
RP7,RP9
MA [0:14] MAA [0:12]
SMBDATA1
0*8
MD [0:63] MDD [0:63]
+5V
SDRAMCLK1 SDRAMCLK1
SMBCLK
SDRAMCLK2 SDRAMCLK2 R51
10K
-MDQMA [0:7]
Q6 R1 P13
DRAMENA
DTC144TKA U17
-MCS[4:5]
U3 -CS[0:1] -MSWEA
-CS[4:5] -MSCASA ICH2
-SWEA RP3 -MSRASA
MCH G G 82801BA
-SCASA 0*8 -MCS[0:1]
82845 -SRASA -MSWEA J503 SO-DIMM S D D S SMBDATA1
-MSCASA
Q8
RP14 -MSRASA R169
2N7002
0*8 P9 Q7 100K
FDV302P
-MDQMA [0:7]
SMBDATA0 SMBDATA
SDRAMCLK4 SDRAMCLK4
R168
SDRAMCLK5 SDRAMCLK5 100K
MDD [0:63]
SMBCLK SMBCLK
MAA [0:12]
CK[0:1] CKE[0:1]
+3V
157
8.6 Memory Test Error

Either one or two extend SO-DIMM RAM Module is failure or system hangs up.
Memory Test Error
1.If your system installed with expansion Board-level

SO-DIMM module then check them for Troubleshooting
proper installation.
2.Make sure that your SO-DIMM sockets
are OK.
3.Then try another known good SO-DIMM
modules.
One of the following components or signals on the motherboard may
be defective ,Use an oscilloscope to check the signals or replace the
parts one at A time and test after each replacement.
Yes Replace the faulty Replace
Test
SDRAM module. Motherboard
OK? Parts: Signals:
U3 RP7 MD [0:63] -MSRASA
No
RP9 RP3 MDD [0:63] CK[0:3]
RP14 J505 MA[0:14] CKE[0:3]
J503 U17 MAA[0:14] SDRAMCLK1
If your system host bus clock running at
Q7 Q8
100MHZ then make sure that SO-DIMM -DQMA[0:7] SDRAMCLK2
Q15 R51
module meet require of PC 100. -MDQMA[0:7] SDRAMCLK4
-CS[0:3] SDRAMCLK5
-MCS[0:3] SMBCLK
-SWEA SMBDATA
-MSWEA SMBDATA0
Yes Replace the faulty -SCASA SMBDATA1
Test
SDRAM module. -MSCASA DRAMENA
Ok?
-SRASA
No
158
8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.
+5VA H8_VDD5
L520
P19 9,59,4
120Z/100M
P13
37
IRQ1
53
36
IRQ12
U17 54
J12
-IOR P19
96
KO[0:15]
ICH2
82801BA
-IOW
97
U508
XD[0:7]
KI[0:7]
ICH-A20GATE Micro
Internal Keyboard Connector
Controller
+5V
H8/F3437 J15
L13 120Z/100M 1
+5VA L16 P19
T_CLK 120Z/100M 3
10
R78 R66 L15
Touch-pad
U13 10K 10K T_DATA 120Z/100M 2 Oonnctor
57
P18 4
U509 -ROMCS 8 9 -H8_KBCS C149 C139 C135
Level Shift
72 95
2
47P 47P 0.1U
7 6 -H8_A20GATE
17
Supper I/O R627 1M
-H8_MCCS
PC87393 73 -MCCS
14 15
98 3
X503
74CBTD3384
16MHz
C633 C630
68P 68P
159
8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
Board-level
Troubleshooting
Is K/B or
T/P cable connected to No
Correct it.
notebook
properly?
Replace One of the following parts or signals on the motherboard

Yes Motherboard may be defective, use an oscilloscope to check the signals or
replace the parts one at a time and test after each replacement.
Try another known good Keyboard

or Touch-pad.(Internal or external) Parts Signals
U17 U509 IRQ1 KO[0:15]
U13 R78 IRQ12 KI[0:7]
U508 L520 -IOR T_CLK
Replace the faulty J12 L13 -IOW T_DATA
Test Yes
Keyboard or L15 L16
Ok? XD[0:7] XTAL
Touch-Pad X503 R627
-H8_KBCS EXTAL
C633 C630
-H8_A20GATE
No C149 C139
C135 J15 -H8_MCCS
160

Either an error message is shown, or the driver motor continues spinning, while reading data is from or
writing data is to hard drive.
+5VS
D S
+3VS Q13
+12VS C201
G
DTC144WK 0.1U
P13 +5VS
R137 1M
R138 C182 J21
10K 4.7U
R156
470
-HDDACTP
P14
-HDD_PWRON 39
Q14
D12
DTC144WK
PG1102W
+5VS
41,42
D513
EC10QS04
R84 R91
4.7K 10K
-HDDRST -HDD_RST
1
-PDACK -PDACK
U17 PDA1 PDA1
29
33
PDA0 PDA0
35
PIORDY PIORDY
ICH2 PDREQ PDREQ
27
21
-PDIOW -PDIOW
82801BA -PDIOR -PDIOR
23
25
IRQ14 INTRQ
31
-PCS1 -PCS1
37
-PCS3 -PCS3
38
PDA2 PDA2
36
PDD [0:15] DD [0:15]
R71 28
5.6K R49
Primary EIDE Connector
470 For Hard Disk
161

Either an error message is shown, or the driver motor continues spinning, while reading data is from or
writing data is to hard drive.
Hard Driver
Test Error
1. Check if BIOS setup is OK?.

2. Try another working drive and cable. Board-level
Troubleshooting
Yes
Re-boot
OK? Replace the faulty parts.
One of the following parts or signals on the motherboard may be
defective, use an oscilloscope to check the signals or replace the parts
No Replace
one at a time and test after each replacement.
Motherboard
PARTS: SIGNALS:
Check the system driver for proper
installation.
U17 R138 -HDDRST -PDACK
Q13 Q14 PDA1 PDA0
R137 C201 PIORDY PDERQ
C182 R84 -PDIOW -PDIOR
R91 R71 IRQ14 -PCS1
Yes R156 J21
Re - Test -PCS3 PDA
End
OK? PDD[0:15]
-HDD_PWRON
No
162
8.9 CD-ROM Drive Test Error

An error message is shown when reading data from CD-ROM drive.
+5VS
D S
+3VS Q503
+12VS C593
DTC144WK 0.1U
P13 R577 1M
G +5VS
R580 C587
10K 4.7U J10
R682
470
-CDACTP
P14
-CDROM_PWRON 37
Q504
D11
DTC144WK
PG1102W
+5VS
38-42
D508
EC10QS04
R37 R36
4.7K 10K
-CDROM_RST -CDROM_RST
5
-SDACK -SDACK
U17 SDA1 SDA1
28
31
SDA0 SDA0
33
SIORDY SIORDY
ICH2 SDREQ SDREQ
27
22
-SDIOW -SDIOW
82801BA -SDIOR -SDIOR
25
24
IRQ15 IRQ15
29 Secondary EIDE Connector
-SCS1 -SCS1
35 For CD-ROM
-SCS3 -SCS3
36
SDA2 SDA2
34
SDD [0:15] SDD [0:15]
R582
5.6K
163
8.9 CD-ROM Drive Test Error

An error message is shown when reading data from CD-ROM drive.
CD-ROM Driver
Test Error
Board-level
Troubleshooting
1. Try another known good compact disk.
2. Check install for correctly.

Test Yes
OK? Replace the faulty parts.
PARTS: SIGNALS:
No Replace
Motherboard U17 R580 -CDROM_RST
R577 Q503 CDROM_PWRON
Check the CD-ROM driver for proper Q504 C593 -SDACK
installation. C587 R36 SDA1
R37 R582 SDA0
R682 D12 SIORDY
J10 SDERQ
-SDIOW
Yes -SDIOR
Re - Test IRQ15
End
OK? -SCS1
-SCS3
No SDA2
SDD[0:15]
164
8.10 USB Port Test Error

An error occurs when a USB I/O device is installed.
U2
3 2 USB0VCC5
+5V VIN0 VCCOUT1
4 VIN1 USB2VCC5
VCCOUT0 1
RT9701-CBL
J6 PJ2 R4
P13 -USBOC1 46 46 -USBOC1

33k L1
D/D Board
120Z/100M
C1 R3 C501
1000P 47k 0.1U
J2
1 P3
USBP2_2- 16 16 USBP2_2- 2
4 3 3
L2
200Z/100M
1 2
4
USBP2_2+ 14 14 USBP2_2+
GND
U17
R502 R503
15K 15K
USB0VCC5
GND_USB
ICH2 R5
33K
L4
-USBOC0
82801BA 48 48 -USBOC0
120Z/100M
C4 R6
1000P 47K
C502 J6
0.1U
1 P3
USBP0_0- 30 30 USBP0_0- 2
4 3 3
L3
600Z/100M
1 2
4
USBP0_0+ 28 28 USBP0_0+
GND
R504 R505
15K 15K
Mother Board
165
8.10 USB Port Test Error

An error occurs when a USB I/O device is installed.
USB Test Error
Board-level
Troubleshooting
Check if the USB device is installed
properly. (Including charge board.)
Check the following parts for cold solder or one of the following parts
Test Yes
Correct it on the mother-board may be defective, use an oscilloscope to check the
OK? Replace following signal or replace the parts one at a time and test after each
Motherboard replacement.
No
Parts: Signals:
Replace another known good charge
board or good USB device. U17 J6 VCC5
PJ2 U2 USBVCC5
R4 R3
-USBOC1
C1 C502
USBP2_2-
R[502:505]
Re-test Yes L[1:4] R5 USBP2_2+
OK? Correct it
R6 C4 -USBOC0
J2 J6 USBP0_0-
No
USBP0_0+
166
8.11 PIO Port Test Error

When a print command is issued, printer prints nothing or garbage.
+5VS
U501 P3
PAC128401Q D501
BAS32L
P22 J6 PJ2 P2 12 13
J1
-P_STB RP1 8 1 -PP_STB 11 14 STB# 1
Mother Board 25
-P_AFD 7 2 -PP_AFD 10 15 AFD# 14
P3
23
P_LPD0 6 3 P_LPD0 9 16 LPD0 2
43
RP500 -P_ERR 5 4 -PP_ERR 8 17 ERR# 15
P18 21
P_LPD [0:3] 0*4
DP_LPD [0:3] P_LPD1 RP2 8 PP_LPD1
1 7 18 LPD1 3
41
-P_INIT 7 2 -PP_INIT 6 19 INIT# 16
RP502 19
P_LPD [4:7] 0*4 P_LPD2 6 3 PP_LPD2 5 20 LPD2 4

DP_LPD [4:7] 39
-P_SLIN 5 4 -PP_SLIN 4 21 SLIN# 17
17
U509 P_SLCT, -P_STB RP503

DP_SLCT, -DP_STB 37
P_LPD3 R1 0 PP_LPD3 3 22 LPD3 5
2 23
-P_AFD, -P_ERR 0*4 -DP_AFD, -DP_ERR 1 24 18-27
Supper I/O
D/D Board
-P_INIT, -P_SLIN RP504 -DP_INIT, -DP_SLIN U502 P3
PC87393 -P_ACK, P_BUSY 0*4 -DP_ACK, DP_BUSY PAC128401Q GND_IO2
RP3 12 13
120OHM/100MHZ
R500 P_LPD4 8 1 PP_LPD4 LPD4 6
35 11 14
0
P_PE DP_PE LPD5
P_LPD5 7 2 PP_LPD5 10 15 7
33
P_LPD6 6 3 PP_LPD6 9 16 LPD6 8
31
P_LPD7 5 4 PP_LPD7 8 17 LPD7 9
CP502 C504 29
100P*4 22P -P_ACK 8 1 -PP_ACK 7 18 ACK# 10
36
P_BUSY 7 2 PP_BUSY 6 19 BUSY 11
34
P_PE 6 3 PP_PE 5 20 PE 12
32
CP503 CP504 CP505
100P*4 100P*4 100P*4 P_SLCT 5 4 PP_SLCT 4 21 SLCT 13
27
RP4 3 22
X X
120OHM/100MHZ 2 23
1 24
Parallel Port
Connector
GND_IO2 GND_IO2
167
8.11 PIO Port Test Error

When a print command is issued, printer prints nothing or garbage.
PIO Test Error
Board-level
Troubleshooting
1. Check if PIO device is installed
properly. (J1)
2. Check CMOS LPT port setting properly.
Replace
Test Yes Motherboard
Correct it PARTS: SIGNALS:
OK?
U509 RP500 P_SLCT, SLIN#
No R500 C504 -P_STB LPD3
-P_AFD, LPD2
J6 PJ2
-P_ERR LPD4
RP1 RP2
Try another known good Yes Replace the P_LPD [0:7] LPD5
R1 RP3 -P_INIT,
PIO device. faulty parts. LPD6
RP4 U501 -P_SLIN LPD7
U502 J1 -P_ACK, ACK#
No RP[502:504] P_BUSY BUSY
CP[503:505] P_PE PE
AFD# SLCT
Yes LPD0
Re - Test ERR#
OK? End
LPD1
INIT#
No
168
8.12 PC-Card Socket Failure

An error occurs when a PC card device is installed.
+3V
VCCA
R46
0
J8
P15
U507 P8 10
R607 33 PCICLK_CARD CAD [0:31] CAD [0:31]
ICS950805 -CCBE [0:3] -CCBE [0:3]
CCLK -CRST -CAUDIO CCLK -CRST -CAUDIO

PCI BUS -CBLOCK -CCLKRUN -CBLOCK -CCLKRUN
P13 -CCD[ 1:2] -CCD[ 1:2]
A21 / IDSEL
-CBE [0:3] -CIRDY -CPERR -CSERR -CIRDY -CPERR -CSERR

-CSTOP -CTRDY -CINT -CSTOP -CTRDY -CINT
-CREQ -CGNT -CDEVSEL -CREQ -CGNT -CDEVSEL
U17 -IRQ0
U7
-GNT0
R2_D2 R2_D14 R2_A16 CPARC R2_D2 R2_D14 R2_A16 CPARC
-CARD_RI VS[1:2] CSTCHG VS[1:2] CSTCHG
ICH2 SERIRQ PCI4410GHK
82801BA -INTA
-INTC P15 +3V

9
+12V
3,4 +5V
3.3VA,B
-VCCEN1 2
-PCIRST VCCD1 5,6
VCCA VPPA
5VA,B
+3V_ICH -VCCEN0 1
VCCD0
U504
11-13
AVCCC,B,A
VPPEN0 15 VDDP0 10
R158 +3V
TPS2211 AVPP
4.7K VPPEN1 14
VDDP1
-CBRST Card Bus

U16 C609 C600 C601 C599
-PCIRST_RST 5 +3V Socket
1 4 0.1u 0.1u 0.1u 0.1u
A VCC
2 4 -PCIRST_N 1
B Y A Y C612 C603 C594 C82
3 -GATE1394 2
GNT B
5 0.1u 0.1u 0.1u 0.1u
Q15 3 GNT
U8
NC7S08
169
8.12 PC-Card Socket Failure

An error occurs when a PC card device is installed.
PC Card and
Test Error
1. Check if the PC CARD device

is installed properly. Board-level
2. Confirm PC card driver is installed ok. Troubleshooting
Test Yes Replace

OK? Correct it Motherboard Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
No to check the following signal or replace the parts one at a time and
Try another known good Parts: Signals

PC card device.
R607 U507 PCI BUS SIGNAL
U17 U8 CCLK -CRST
U7 U9 -CAUDIO -CBLOCK
C82 J8 -CCLKRUN -CCD[ 1:2]
Yes C594 C599
Re-test Change the faulty R2_D2 R2_D14
C600 C602 R2_A16 CPARC
OK? part then end. C603 C609 VS[1:2] CSTCHG
-VCCEN1 -VCCEN0
No VPPEN0 VPPEN1
170
8.13 IEEE1394 Failure

An error occurs when a PC card device or 1394 device is installed.
+3V
VCCA
R46
0
+3V +5V
P15
U507 P8 10
R607 33 PCICLK_CARD
Q5 R43
DTC144WK 47K
ICS950805 VCCEN1 8 P15
VCC
VCCEN0 C99
0.1U
Q4 R42 R53 R52 U9
P13 PCI BUS
DTC144WK 47K 4.7K 4.7K
7 WC-
Write Protect
A21 / IDSEL
when high P13
-CBE [0:3]
-1394WR
NM24C02N
5
SDA
6
U17 -IRQ0
SCLK
U7
-GNT0
-CARD_RI +3V 1394AVDD
ICH2 SERIRQ PCI4410GHK
L20
-PCLKRUN
30,31,42
82801BA -INTA PHY_D [0:7]
J21
P15 35 TPB- 1 2 1
-INTC PHY_CTL[0:1] P15
34 TPB+ 2
PHY_LREQ 4 3
1 L23
R73 10
U14 36 TPA- PLP32166
3
-PCIRST PHY_CLK 2 TSB41AB1 4
37 TPA+
PHY_LKON R80 10
+3V_ICH
19
1 2 GND1
R103 R115
R158 +3V
PHY_LPS 15 56 56 GND2
4.7K 4 3
60 TPBIAS 38 L24
X504 PLP32166
U16 -CBRST R105 R106 C200
FILTER1
FILTER0
-PCIRST_MSK 5 24.576MHZ 1U
1
A VCC 4 +3V 56 56
4 -PCIRST_N 1 1 2 59
2 Y A Y
Q15 B
3 GNT -GATE1394 2 5
B
3 GNT C134 C152 54 55 R124 C199
NC7S32
10P 10P C161 4.99K 270P
U8 0.1U
NC7S08
171
8.13 IEEE1394 Failure

An error occurs when a PC card device or 1394 device is installed.
IEEE1394 Test Error
1. Check if the 1394 device is installed Board-level

properly. Troubleshooting
2. Confirm 1394 driver is installed ok.
Replace
Motherboard
Test Yes
Correct it parts on the mother-board may be defective, use an oscilloscope
OK? to check the following signal or replace the parts one at a time and
No
Parts: Signals
Try another known good
1394 device. U507 U17 U7 PCI BUS SIGNAL PHY_CLK
U8 U14 X504 PCICLK_CARD PHY_LKON
C134 C152 Q5 -CBE[0:3] -IRQ0 PHY_LPS
Q4 R43 R42 -GNT0 -CARD_RI TPA+
R53 R52 U9 SERIRQ -INTA TPA-
Re-test Yes C99 L23 L24 -INTC CBRST TPB+
Change the faulty
OK? J21 R105 R103 VCCEN0 VCCEN1 TPB-
part then end.
R115 R106 R124 PHY_D[0:7] PHY_XI
No C199 C200 R607 PHY_CTL[0:1] PHY_XO
PHY_LREQ
172
8.14 Audio Failure

No sound from speaker after audio driver is installed.
+3VS AVDDAD +12VS

L14 C672 U511
120Z/100M 0.1U L540 7805
AUDIO IN 1 O I
3
GND
C702 C684 2 C674
0.1U 10U
L522 0.1U
P13 1 9 25 38
11
-ACRST P17
AGND
ACSDOUT 5
23 C196 2.2U R121 6.8K
LINE/IN/L J16 P17
ACSDIN R645 22 8
U17 LINE/IN/R
24 C183 2.2U R109 6.8K
1
Internal
Micro Phone
10 2
ACSYNC Jack
21 MIC1 C194 1U AGND
MIC1 AVDDAD
ICH2 R669 47K
ACBITCLK R648 22 6 R670 47K
L535
82801BA 120Z/100M
SPK_OFF To U18 C686 10U/10V P17 J22
Next Page +5VS
U15 U513 X
5
4
MC33078D MIC_3 3
SBSPKR ALC201 R671 4.7K
8 VCC+ 1IN+ 3
MIC_2 2
1
C675 C701 L525
C667 48 SPDIFOUT
7 2OUT 2IN+ 5
0.1U U510 0.068U/25V 120Z/100M
0.1U 6 1
NC7S32
2IN- 1OUT External
R151 4 VCC- 2IN+ 2 Micro Phone
1 5
R148
A VCC 36 AOUT_R 100K
LINE/OUT/R 68K Jack
P15 C669 C670 CAGND
0.1U 0.1U C209
35 AOUT_L
U7 62
-CARDSPK 2
B Y 4
12
PC_BEEP
LINE/OUT/L 10U/10V
To next
3 R646 R149
GND Page
470K R647 100K
PCI4410 R649
20K
47K
J10
2 C193 1U R134 6.8K
XTL/IN CD/R
20 CDROM_RIGHT 2 P14
R88 1M C191 1U R132 6.8K
3 XTL/OUT 18 CDROM_LEFT 1
CD/L
X2 24.576M C192 1U R133 0

19 CDROM_COMM 3
CD/GND
C148 C167 R142 R140 R141

6.8k 6.8k 0
CD-ROM
10P 10P
Audio Jack
173
8.14 Audio Failure

C710 2.2U R678 10K R667 15K C210 220U
AUDIO OUT
C694 680P
21 P17
RLINE IN
20
RHP IN R OUT+
22 SPKROUT+ 1 J20 Internal
R666 10K 15 SPKROUT- 2 R Speaker
R OUT- Connector
3 SPKLOUT+ 1 L
C709 2.2U R677 10K C693 470P L OUT+ P17
10 SPKLOUT- 2 J18
L OUT-
+3V_ICH Signal HI LOW

SPK_OFF Shut Down Norm al
VR1
5
C717 4.7U 10K L524 120Z/100M

AOUT_R SPK_OFF LINE_OUT_5 L536
4 7
11
MUTE IN 2
PLP3216S
1
6
C718 4.7U From U17
Q16 C204 220U LINE_OUT_2 L523 120Z/100M
DTC144TKA R166 9 4
1 3 MUTE OUT 3
10K
AOUT_L 8 SHUTDOWN
+5VS L537
C689 R143 R122 C688
2
From U15 L538

front page
100P 1K 1K 100P
120Z/100M J19
L529 120Z/100M 5
L47 C206
18
U18 4
120Z/100M R548 22 0.1U RVDD 2
7
5V_AMP LVDD 3
-DECT_HP/OPT 1 Line Out
C166 C168 Amplifier +3VS Q514
+3VS_SPD
L531 120Z/100M 7
Phone Jack
100U 0.1U DTA144WK 8 P17
5V_AMP 9
TPA0202 R685
10K
C708 2.2u R676 10k R665 15k Q515 R673
DTA144TKA 4.7K
5V_AMP R659
4.7K
C692 680P -DEVICE_DECT
4 R102
14 47K
LLINE IN SE/BTL#
5 16
HP/LINE# SPDIFOUT
R664 10K LHP IN R113 From U15 2 1
100K front page
Q10 3 4
C707 2.2u R675 10k C691 470P DTA144TKA L527 L532
120Z/100M PLP3216S
174
8.14 Audio Failure

Audio Drive Failure
Board-level
Troubleshooting
1. Check if speaker cables are connected
properly.
2. Make sure all the drivers are installed
properly.
Check the following parts for cold solder or one of the following parts on the
motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
Replace
Test Yes Motherboard 1.If no sound cause 2. If no sound cause 3. If no sound cause
OK? Correct it. of line out, check of MIC, check of CD-ROM, check
the following the following the following
No parts & signals: parts & signals: parts & signals:
Parts: Signals: Parts: Signals: Parts: Signals:

1.Try another known good speaker,
U15 X2 AOUT_R CDROM_RIGHT
CD-ROM. U510 U507
J16 J22 U15 MIC J10
2. Exchange another known good AOUT_L L535 L525 MIC_2 R[132:134] CDROM_LEFT
U17 U511
charger board. SPKROUT+ C701 R148 R[140:142]
VR1 U18 MIC_3 CDROM_COMM
SPKROUT- R149 R669 C[191:193]
C[707:710]
SPKLOUT+ U513 C194
R[664:667]
SPKLOUT- R151 C209
C[691:694]
R670 C686
L47 Q514 LINE_OUT_5
Re-test Yes Q515 Q10 LINE_OUT_2
Correct it. L[537:539] SPK_OFF
OK?
L523 L524 SPDIFOUT
L528 L531
No J[18:20]
175
8.15 LAN Test Error

An error occurs when a LAN device is installed.
L12 +3V_LAN AVDD_LAN AVDD_LAN

+3V
120Z/100M
L10 L9 L511
R541 C567
+3V_ICH 77,90,96 51 22P
P16 J9
R158 R542 C572
L508 10 PJTX+
P13 4.7K
92 TXD+
51 22P
PLP3216A
TX+ 8
1 2
7
TD+ P17 9 PJTX-
U16 TX- 7
-PCIRST_MSK 5 91 TXD- 8
1 VCC TD-
A R31 0 4 3 16 PJRX+
-PCIRST_N RX+ 6
U17 Q15
2
B Y 4 115
6
3
GNT AVDD_LAN R15 0 15 PJRX-
RX- 3
NC7S32
-PCIRST C40
ICH2 0.1U U2
-CBE[0:3]
82801BA R12 75 R530 75
L513 11 PJ4
TXC 5
86 RXIN- PLP3216A 1
1 2 RD+ 4
AD[0:31],-PCI_REQ1,-PCI_GNT1
-PCI_IRDY,-PCI_TRDY,-FRAME
U4 87 RXIN+ 4 3 2
RD-
RXC
R17 75 R531 75
14 PJ7
3 2
R549 R555 RDC
-DEVSEL,-STOP,-PCI_INTD 1
51 51
C566
C39
LANPHY 0.1U 1000P RJ45
H0011
P19 48 RTL8139CL XFMR_H0009
U508 Q512 C577
3 DTC144WK 0.1U
H8 LAN_WAKE 83
2
F3437 3V_LAN
1 50 1 CS
EECS 8
VCC
49 2 SK
MA2 U5 C69
R610 33 R32 0 48 3 0.1u
P8 11
PCICLK_LAN 116
MA0 DI
93C468 5
U507 47 4 GND
MA1 DO
ICS950805 L8
79
PLP3216A
XTALIN
X501
25MHZ
78 1 3
XTALOUT L_AGND
2
P15 -PCLKRUN 75
C585 C584
U7 4
10P 10P
PC14410GHK
176
8.15 LAN Test Error

An error occurs when a LAN device is installed.
LAN Test Error
1.Check if the driver is installed properly. Board-level

2.Check if the notebook connect with the Troubleshooting
LAN properly.
Replace Check the following parts for cold solder or one of the following
Test Yes parts on the mother-board may be defective, use an oscilloscope
Correct it. Motherboard
OK? to check the following signal or replace the parts one at a time and
No
Parts: Signals
U17 U508 U507 TXD+
-PCIRST_N
Check if BIOS setup is ok. R158 U16 Q512
-CBE[0:3] TXD-
R610 R32 R31
LAN_WAKE PJTX+
U4 L[8:10] R542
PCICLK_LAN PJTX-
R541 R549 R555
PCLKRUN PJRX+
L508 L513 C567
PJRX-
C572 C577 C540 XTALIN
PJ4
Re-test Yes U5 C69 X501 XTLOUT PJ7
OK? Correct it. C584 C585 R12 RXIN-
R17 R530 R31 RXIN+
No J9
177
9. Spare Parts List -- recommend (1)

Category Part Number Description Remark Category Part Number Description Remark
CPU 324180786162 BFM-IPC;IC,CPU,WILLA 526267120029(1/15 Delete, PWA;PWA- 411671200004 PWA;PWA-8170,D/D BD,SMT
The CPU not use in the part 8170,D/D
346671200011 INSULATOR;CD-ROM,M-B,8170
BD,T/U
SDRAM MODULE323767120001 BFM-IPC;DRAM MODULE, 526267120029 346671200036 INSULATOR,MDC,8170
COVER ASSY 340671200007 COVER ASSY; SPEAKER,8170 LCD ASSY 413000020305 BFM-IPC;LCD,UB141X01 526267120014,17,29
340671200007 COVER ASSY;KB,8170 413000020281 LCD;14X13-102,TFT,14 526267120037

PCB;PWA-8170 442164900010 TOUCH PAD MODULE;TM41PD-350 421671200002 WIRE ASSY;UNIPAC,14. 526267120014,17,29
TOUCHPAD BD 421671200001 WIRE ASSY;HYUNDAI,14 526267120037
422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU
HOUSING KIT 421671200007 WIRE ASSY;INVERTER,8170
340671200002 COVER ASSY;8170
340669900001 TILT UNIT;R,7170
340671200006 COVER ASSY;RAM,8170 1/17 ECR:7939102700 delete
340669900002 TILT UNIT;L,7170
340671200025 COVER ASSY;RAM-1,8170 1/17 ECR:7939102700 add
340671200016 HOUSING ASSY;HANNSTER,14.1",LCD,
343671200003 PLATE;KEYBOARD,8170
340671200017 HOUSING ASSY;UNIPAC, 526267120014,17,29
344669900003 COVER;HINGE,7170
340671200015 HOUSING ASSY;HYUNDAI 526267120037
421669900007 WIRE ASSY;TOUCHPAD,7170
341669900004 BRACKET;LCD,14.1",HYUNDAI,L,7170
340671200008 BRACKET ASSY;T-P,8170
345669900004 RUBBER;LCD,DOWN,7170
340671200019 SPERKER ASSY;L,8170
345671200001 RUBBER;LCD,UP,8170
340671200012 SPEAKER ASSY;R,8170
346664900010 FILM;LCD PROTEC,.14.2",235*300,5
421671200031 MICROPHONE ASSY;8170
340671200018 COVER ASSY;LCD,8170
421671200008 WIRE ASSY;MDC,8170 341669900003 BRACKET;LCD,14.1,HYU
340671200020 FAN ASSY;8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS 1/22 add option(7939102656)
PWA;PWA- 411671200001 PWA;PWA-8170,MOTHER BD 412671300001 PCB ASSY;D/A BD,SUMIDA,STINGRAY 1/22 add option(7939102656)
8170,MOTHER PWA;PWA-
412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ 411671200007 PWA;PWA-8170,ESB BD
BD,T/U
340671200003 HOUSING ASSY;8170 AC ADPT ASSY 442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817
BATT ASSY 442671200001 BATT ASSY;11.1V/6AH,LI-,PANASONI 242670800113 BFM-WORLD MARK;WINXP,7521N
178
9. Spare Parts List -- recommend (2)

Category Part Number Description Remark
HDD ASSY;30G 344669900010 CASE;HDD,7170
523467120012 BFM-IPC;HDD DRIVE,30 526267120029

KBD 531066990001 KBD;86,US,K000918E1,7170
531020237308 KBD;87,FR,K000918F1, 526267120014
531020237307 KBD;87,GR,K000918F1, 526267120017,29
AK;01-EN 332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC
332810000034 PWR CORD;250V/2.5A,2 526267120017
332810000043 PWR CORD;250V/3A,2P, 526267120037
421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C
BEZEL 340669900046 BEZEL ASSY;DVD ROM,QUANTA,7170
ASSY;DVD
343669900006 BRACKET;CD-ROM,7170
ROM,QUANTA,
523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN
179
9. Spare Parts List -- All (1)

Part Number Description Location(s) Part Number Description Location(s)
441999900204 AC ADPT ASSY OPTION;8170 272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C688,C689,PC528
442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817 272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C503,C504,C505,C506
541667120001 AK;01-EN,BOX,8170 272431105901 CAP;100U ,10V ,20%,7343,SMT PC1,PC3,PC8
541667120032 AK;EN,8170,UTILITY ONLY 272431107509 CAP;100U,2V,20%,7343,SDK-CAP C12,C28,PC572,PC573,PC57
441999900056 BATT ASSY OPTION;LI,9-CELL,8170 272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C101,C107,C108,C117,C134,
442671200001 BATT ASSY;11.1V/6AH,LI-,PANASONI 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C10,C11,C13,C14,C15,C17,C
298000000002 BATTERY HOLDER;FOR CR2032,BH-800 BT1 272023106701 CAP;10U ,25V ,+80-20%,1210,Y5U, PC20,PC28,PC541,PC544
338530010018 BATTERY; LI,3V/220MAH,CR-2032 BT1 272075120301 CAP;12P ,CR,50V ,5% ,0603,NPO,S C211,C212
340669900046 BEZEL ASSY;DVD ROM,QUANTA,7170 272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S C556,C559
242670800113 BFM-WORLD MARK;WINXP,7521N 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C122,C142,C160,C163,C164,
221669940001 BOX;AK,7170 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 PC2
340671200008 BRACKET ASSY;T-P,8170 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, C171,C522,C545,C681,PC518
343669900006 BRACKET;CD-ROM,7170 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC505
341669900005 BRACKET;LCD,14.1",HANNSTAR,R,717 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C183,C196,C622,C625,C646,
341669900004 BRACKET;LCD,14.1",HYUNDAI,L,7170 272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C638,C65,C81
421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C 272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C531
421671000001 CABLE ASSY;USB FDD 272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT C523,C524,C546,C547,C704
272075103702 CAP;.01U ,50V,+80-20%,0603,SMT C562,C576,C60,PC32,PC500, 272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S C187,C197,C203,C205,C504,
272072473402 CAP;.047U,16V ,10%,0603,X7R,SMT C651 272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S C16,C49,C514,C552,C59,C61
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C103,C104,C105,C109,C110, 272043226501 CAP;22U ,25V ,+-20%,1812,Y5U,SMT PC505,PC506,PC507,PC513,
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C501,C502,C507,C512,C513, 272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C199,C46,C93
272003683401 CAP;0.068U,CR,25V,10%,0805,X7R C701 272431337506 CAP;330U,4V,20%,7343,SMT PC7
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C1,C132,C141,C173,C174,C5 272432336506 CAP;33U,16V,+-20%,7343,POSCAP,SM C30,C31
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C1,C4,PC18,PC517,PC518 272421336501 CAP;33U,TT,8V,20%,3528,SMT C570,C571
272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C500,C502,C566 272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C125,C131,C153,C208,C35,C
180

272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C182,C54,C587 291000142404 CON;FPC/FFC,24P,1MM,H8.2,ST,ACES J12
272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y PC501,PC511,PC514 291000150804 CON;FPC/FFC,8P,1MM,R/A,2CONTAC,E J500
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C611,C691,C692,C693,C694, 331040020004 CON;HDR,FM,10P*2,2.54MM,R/A,H8,4 J3
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC20 331030044013 CON;HDR,FM,22*2,2MM,ST,C16805
272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,S C136,C139,C143,C149,C680, 331040050011 CON;HDR,FM,25P*2,1.27MM,R/A,HSG J6
272075509801 CAP;5P ,CR,50V,+ -.5PF,0603,NP C617,C618 291000011024 CON;HDR,FM,5P*2,1.27MM,ST,H4.5,S J501
272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C630,C633 331040020005 CON;HDR,MA,10P*2,2.54MM,R/A,H8.4 PJ1
221668950010 CARD BOARD,BTM,PALLET,M722 291000011209 CON;HDR,MA,12P*1,1.25,ST,SMT J6
221669950008 CARD BOARD;FRAME,PALLET,7170 291000024409 CON;HDR,MA,22P*2,2MM,R/A,SMT,ALL J14
221669950006 CARD BOARD;TOP,PALLET,7170 331040050009 CON;HDR,MA,25P*2,1.27MM,R/A,HSG PJ2
221671220002 CARTON;NON-BRAND,MSL,8170 331040050010 CON;HDR,MA,50P,0.8MM,R/A,H1.1 J10
431671200001 CASE KIT;8170 291000011027 CON;HDR,MA,5P*2,1.27MM,ST,H17.5, J5
344669900010 CASE;HDD,7170 291000020303 CON;HDR,SHROUD,MA,3P,1.25MM,R/A, J502
451669900051 CD ROM ME KIT;24X,7170 291000256823 CON;IC CARD PART;68P,0.635,H5,SM J8
273000500052 CHOKE COIL;0.7UH,1.6mOHM,25%,20A PL1,PL2 331000004018 CON;IEEE1394,MA,4P,.8MM,R/A,LINK J21
273000500053 CHOKE COIL;10UH,21.6mOHM,5.4A PL7 331870004017 CON;MINI DIN,4P,R/A,W/GROND,C108 J4
273000500053 CHOKE COIL;10UH,21.6mOHM,5.4A PL1 331810006044 CON;PHONE JACK,6P2C,H11.5,RJ11,T J13
273000111004 CHOKE COIL;160OHM/100MHZ,25%,321 L23,L24,L508,L513,L532,L53 291000810806 CON;PHONE JACK,8P8C,SMD,RJ45 J9
273000111004 CHOKE COIL;160OHM/100MHZ,25%,321 L2,L3 331840010005 CON;POF MINI JACK,10P,W/SPDIF,2F J19
273000500015 CHOKE COIL;50UH(REF),D.4*2,5.5T, L1 331910003039 CON;POWER JACK,3P,D=2.0,SINGATRO J5
331000007009 CON;BAT,7P,2.5MM,CENLINK J28 331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J22
331720015006 CON;D,FM,15P,2.29,R/A,3ROW J1 331000004025 CON;USB,MA,R/A,4P*1,2MM,85116-40 J2,J3
331720025005 CON;D,FM,25P,2.775,R/A J1 291000410201 CON;WFR,MA,2P,1.25,ST,SMT/MB J16,J18,J20,J4
291000153006 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST, J11 291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J7
291000144004 CON;FPC/FFC,20P*2,1.0MM,H=4.6,ST J2 291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J501
181

291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J15 288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 D500
345669600065 CONDUCTIVE TAPE;MB,SDRAM,RACE 288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 PD1
340671200007 COVER ASSY; SPEAKER,8170 288103103001 DIODE;EC31QS03L,30V,3A,SMT PD1,PD2,PD4,PD5,PD6
340671200002 COVER ASSY;8170 288103103001 DIODE;EC31QS03L,30V,3A,SMT PD4,PD5,PD6
340671200001 COVER ASSY;ID1,8170 288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D5,D7
340671200009 COVER ASSY;KB,8170 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD501
340671200018 COVER ASSY;LCD,8170 288100036001 DIODE;RLZ3.6B,ZENER,3.45V,5%,SMT D8
340671200006 COVER ASSY;RAM,8170 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM PD7
344671000001 COVER;FOR 7170;USB FDD 344670500042 DUMMY CARD;PCMCIA,TETRA
344669900003 COVER;HINGE,7170 523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN
272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP500,CP501,CP502,CP503, 523467120011 DVD ROM ASSY;8X,SDR-081,QUANTA,8
291006214438 DIMM SOCKET;144P,.8MM,H4,SX6E,HR J505 272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C166
291006214439 DIMM SOCKET;144P,.8MM,H4,SX6ER,H J503 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC18,PC23,PC46,PC47
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 PD503 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC11,PC19,PC4,PC5,PC9
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D501 272601227501 EC;220U ,10V,M,6.3*7.7,-15+105', C204,C210
288100054001 DIODE;BAT54,30V,200mA,SOT-23 D10,D16 312278206152 EC;820U ,4V,+-20%,10X10.5,FPCAP PC3,PC5,PC6,PC7
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D509,D510 227669900005 END CAP; HEATSINK, AK BOX,7170
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 PD2,PD3 227671200001 END CAP;8170
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1,D3,D4,D6 227669900004 END CAP;BATTERY,7170
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D501,D502,D503,D504,D505 227669900002 END CAP;FDD,FRAME,7170
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D502,D503 227669900003 END CAP;FDD,T/B,7170
288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD500,PD502 481671200002 F/W ASSY;KBD CTRL,8170 U508
288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD502 481671200001 F/W ASSY;SYS/VGA BIOS,8170 U12
288101003001 DIODE;EC10QS03L,30V,1A,SMT D508,D513 340671200020 FAN ASSY;8170
288101003001 DIODE;EC10QS03L,30V,1A,SMT PD503,PD504 523411442052 FD DRIVE;1.44M,3.5",D353FU,MITSU
182

523499993004 FDD DRIVER OPTION;EXT. FDD,7170 283466570001 IC;EEPROM,9346,64*16 BITS,SO8,SM U5
523467100002 FDD KIT;D353FUE,FOR 7170,USB,MSL 283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U9
273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN FA501 283450083002 IC;FLASH,512K*8-70,PLCC32,ST39SF
273000610014 FERRITE ARRAY;60OHM/100MHZ,3216, FA500 284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P,
273000610014 FERRITE ARRAY;60OHM/100MHZ,3216, RP1,RP2,RP3,RP4 284582801027 IC;ICH2,82801BA,BGA421 U17
273000130019 FERRITE CHIP;120OHM/100MHZ,1608, L500,L501,L502,L520,PL8 284595080001 IC;ICS950805,200MHZ,TSSOP56 U507
273000130019 FERRITE CHIP;120OHM/100MHZ,1608, L508,L510 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU513
273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L505,PL10,PL11,PL14,PL15, 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S PU7
273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L1,L4,L507,L509,PL2,PL3,PL 286329510001 IC;LP2951CM-3.3,VOLTAGE REGULATO PU510
273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L10,L11,L12,L13,L14,L15,L1 286317099001 IC;LTC1709-9,PWM,QSOP,36P PU508
273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L502,L503,L504,L505 286301632002 IC;MAX1632CAI,PWM CTRL,SSOP,28P PU1
273000130038 FERRITE CHIP;600OHM/100MHZ,1608, L523,L524,L525,L527,L528,L 286301772001 IC;MAX1772,PWM,QSOP,28P PU511
273000150022 FERRITE CHIP;60OHM/100MHZ,2012,S L17,L18,L19 286133078001 IC;MC33078D,LOW NOISE OP AMP.,SO U513
273000150022 FERRITE CHIP;60OHM/100MHZ,2012,S L501 286305248002 IC;MIC 5248-1.2BM5,LV12,LDO REG, U501
422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU 284500006003 IC;MOBILTY RADEON M6-D,BGA484 U516
346664900010 FILM;LCD PROTEC,.14.2",235*300,5 281300732001 IC;NC7S32,SINGLE OR GATE,SC70-5 U16,U510
341671200009 FINGER;EMI GROUND SMD FINGER,H=2 E1,E2,E3,E4,E5,E500,E502,E 281307085001 IC;NC7SZ08P5,2-INPUT & GATE,SC70 U8
341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501,E509,E510,E513 286307805010 IC;NJM78L05UA,VOL REGULATOR,SOT, U511
341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501 286302040002 IC;P2040B,LCD PANEL EMI,S0,8P U503
342600001203 FINGER;EMI GROUNDING SMD FINGER, E514,E515 284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSO U501,U502
288003600001 FIR;HSDL3600#007,FRONT VIEW,10P, U1 284587393002 IC;PC87393F,TQFP,100P U509
295000010044 FUSE;1.1A/6V,POLY SWITCH,1210,SM F500,F501,F502 284504410005 IC;PCI4410A,CARDBUS/OHCI,uBGA,20 U7
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1,PF2 286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U2
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF501 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ3,PQ510,Q505
346671200026 GASKET;1394,M/B,8170 286300055001 IC;TC55,3.3V,250mA,REG.,SOT89 PU8
183

286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U18 242669900005 LABEL;LCD SIDE,7170
286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U504 242600000195 LABEL;SOFTWARE,INSYDE BIOS-M
284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U14 441671200004 LCD ASSY;HANNSTAR,SXGA+,14.1",81
273000114002 INDUCTER;4.7UH,10%,1206,SMT L509,L512 451671200004 LCD ME KIT;HANNSTAR,SXGA+,14.1",
273000990023 INDUCTOR;10UH,CDRH125B,SMT PT1 413000020290 LCD;HSD141PK11-A,TFT,14.1",SXGA+
273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT D11,D12,D13,D14,D15
346671200036 INSULATOR,MDC,8170 344671000003 LENS;HOUSING,USB FDD
346671200011 INSULATOR;CD-ROM,M-B,8170 526267120001 LTXNX;8170/4BCI/30C/1US1/18D3A/X
346668300024 INSULATOR;DIMM P/N MB TOP,HOPE 561567120001 MANUAL KIT;EN,8170,N-B
346669900004 INSULATOR;INVERTER,7170 561567120013 MANUAL;USER'S,EN,8170,N-B
346671200007 INSULATOR;PCMCIA,8170 421671200031 MICROPHONE ASSY;8170
346671200008 INSULATOR;RTC,8170 416267120004 NB PF;HANNSTAR,SXGA+,14.1",8170
531099990101 KBD OPTION;86,US,7170 375102030010 NUT-HEX;M2,2,NIW
531066990001 KBD;86,US,K000918E1,7170 375120262008 NUT-HEX;M2.6,NCG
451671200052 LABEL KIT;N-B,8170 461671200002 PACKING KIT;N-B,8170
242600000145 LABEL;10*10,BLANK,COMMON 227669900006 PAD;LCD/KB,ANIT-STATIC,7170
242600000145 LABEL;10*10,BLANK,COMMON 221669950004 PARTITION;A,PALLET,7170
242662300009 LABEL;25*10MM,3020F 221669950001 PARTITION;AK BOX,7170
242600000378 LABEL;27*7MM,HI-TEMP 260'C 221669950005 PARTITION;B,PALLET,7170
242671200004 LABEL;AGENCY-GLOBAL,MSL,8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS
242600000157 LABEL;BAR CODE,125*65,COMMON 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/
242669900012 LABEL;BAR CODE,32x11MM,7170 316671200003 PCB;PWA-8170 TOUCHPAD BD R01
242600000433 LABEL;BLANK,11*5MM,COMMON 316671200002 PCB;PWA-8170/DD BD R01
242669900009 LABEL;BLANK,60*80MM,7170 316671200005 PCB;PWA-8170/ESB BD R01
242664800013 LABEL;CAUTION,INVERT BD,PITCHING 316671200001 PCB;PWA-8170/M BD R01
184

286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U18 242669900005 LABEL;LCD SIDE,7170
286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U504 242600000195 LABEL;SOFTWARE,INSYDE BIOS-M
284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U14 441671200004 LCD ASSY;HANNSTAR,SXGA+,14.1",81
273000114002 INDUCTER;4.7UH,10%,1206,SMT L509,L512 451671200004 LCD ME KIT;HANNSTAR,SXGA+,14.1",
273000990023 INDUCTOR;10UH,CDRH125B,SMT PT1 413000020290 LCD;HSD141PK11-A,TFT,14.1",SXGA+
273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT D11,D12,D13,D14,D15
346671200036 INSULATOR,MDC,8170 344671000003 LENS;HOUSING,USB FDD
346671200011 INSULATOR;CD-ROM,M-B,8170 526267120001 LTXNX;8170/4BCI/30C/1US1/18D3A/X
346668300024 INSULATOR;DIMM P/N MB TOP,HOPE 561567120001 MANUAL KIT;EN,8170,N-B
346669900004 INSULATOR;INVERTER,7170 561567120013 MANUAL;USER'S,EN,8170,N-B
346671200007 INSULATOR;PCMCIA,8170 421671200031 MICROPHONE ASSY;8170
346671200008 INSULATOR;RTC,8170 416267120004 NB PF;HANNSTAR,SXGA+,14.1",8170
531099990101 KBD OPTION;86,US,7170 375102030010 NUT-HEX;M2,2,NIW
531066990001 KBD;86,US,K000918E1,7170 375120262008 NUT-HEX;M2.6,NCG
451671200052 LABEL KIT;N-B,8170 461671200002 PACKING KIT;N-B,8170
242600000145 LABEL;10*10,BLANK,COMMON 227669900006 PAD;LCD/KB,ANIT-STATIC,7170
242600000145 LABEL;10*10,BLANK,COMMON 221669950004 PARTITION;A,PALLET,7170
242662300009 LABEL;25*10MM,3020F 221669950001 PARTITION;AK BOX,7170
242600000378 LABEL;27*7MM,HI-TEMP 260'C 221669950005 PARTITION;B,PALLET,7170
242671200004 LABEL;AGENCY-GLOBAL,MSL,8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS
242600000157 LABEL;BAR CODE,125*65,COMMON 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/
242669900012 LABEL;BAR CODE,32x11MM,7170 316671200003 PCB;PWA-8170 TOUCHPAD BD R01
242600000433 LABEL;BLANK,11*5MM,COMMON 316671200002 PCB;PWA-8170/DD BD R01
242669900009 LABEL;BLANK,60*80MM,7170 316671200005 PCB;PWA-8170/ESB BD R01
242664800013 LABEL;CAUTION,INVERT BD,PITCHING 316671200001 PCB;PWA-8170/M BD R01
185

271071270301 RES;27 ,1/16W,5% ,0603,SMT R502 271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R582,R71
271071301011 RES;301 ,1/16W,1% ,0603,SMT R5,R537 271071511812 RES;51.1,1/16W,1% 0603,SMT R507,R508,R510,R512,R513,
271071301311 RES;301K ,1/16W,1% ,0603,SMT PR562 271071560301 RES;56 ,1/16W,5% ,0603,SMT R103,R105,R106,R115
271071330302 RES;33 ,1/16W,5% ,0603,SMT PR557,R55,R56,R585,R586,R 271071561101 RES;560 ,1/16W,1% ,0603,SMT PR20
271071334301 RES;330K ,1/16W,5% ,0603,SMT R689 271071634111 RES;6.34K,1/16W,1% ,0603,SMT R104
271071333101 RES;33K ,1/16W,1% ,0603,SMT PR547 271071682301 RES;6.8K ,1/16W,5% ,0603,SMT PR519,R151,R24,R27,R550,R
271071333301 RES;33K ,1/16W,5% ,0603,SMT R4,R5 271071620102 RES;62,1/16W,1% 0603,SMT R2,R3,R506,R517
271071374211 RES;37.4K,1/16W,1% ,0603,SMT PR15 271071681101 RES;680 ,1/16W,1% ,0603,SMT R522
271071390302 RES;39 ,1/16W,5% ,0603,SMT R521 271071683301 RES;68K ,1/16W,5% ,0603,SMT R148
271071472101 RES;4.7K ,1/16W,1% ,0603,SMT PR23,PR24,PR572,R158,R19 271071750302 RES;75 ,1/16W,5% ,0603,SMT R12,R17,R514,R530,R531
271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR18,R124,R587 271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R107,R108,R117,R118,R154,
271071402811 RES;40.2 ,1/16W,1% ,0603,SMT R16,R8,R82 271071841101 RES;845 ,1/16W,1% ,0603,SMT R533
271071402311 RES;402K ,1/16W,1% ,0603,SMT PR568 271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP521
271071432211 RES;43.2K,1/16W,1% ,0603,SMT PR571 271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP508
271071470301 RES;47 ,1/16W,5% ,0603,SMT R581 271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP510
271071471302 RES;470 ,1/16W,5% ,0603,SMT R156,R157,R682,R683,R684, 271621102302 RP;1K*8 ,10P,1/32W,5% ,1206,SMT RP2,RP505
271071474301 RES;470K ,1/16W,5% ,0603,SMT PR16,R1,R501,R642,R646 271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP518
271071474301 RES;470K ,1/16W,5% ,0603,SMT PR4,PR5,PR506 271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP511
271071475011 RES;475 ,1/16W,1% ,0603,SMT R619 271611473301 RP;47K*4 ,8P ,1/16W,5% ,0612,SMT RP520
271071475311 RES;475K ,1/16W,1% ,0603,SMT PR564 271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP512,RP515
271071473301 RES;47K ,1/16W,5% ,0603,SMT PR553,R102,R42,R43,R579,R 271611682301 RP;6.8K*4,8P ,1/16W,5% ,0612,SMT RP1,RP506,RP507,RP509
271071473301 RES;47K ,1/16W,5% ,0603,SMT PR9,R3,R6 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP501
271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R520,R527,R528,R529,R535, 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP501
271071499211 RES;49.9K,1/16W,1% ,0603,SMT PR516,PR542 271621822302 RP;8.2K*8,10P,1/32W,5% ,1206,SMT RP15,RP16,RP17,RP18
271071499011 RES;499 ,1/16W,1% ,0603,SMT R14 345671000001 RUBBER FOOT;HOUSING,USB FDD
186

345669900004 RUBBER;LCD,DOWN,7170 370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
345671200001 RUBBER;LCD,UP,8170 370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL
565167120001 S/W;CD ROM,SYSTEM,8170 340671200012 SPEAKER ASSY;R,8170
565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO 340671200019 SPERKER ASSY;L,8170
340671200013 SCREW ASSY;CPU,8170 377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW
340671200014 SCREW ASSY;IC,82845,8170 341668300008 STANDOFF;MDC MODEM,NLK,HOPE
371102011502 SCREW;M2L15,FLT(+),NIW/NLK 297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW1,SW2,SW3,SW4,SW5,SW6
323760000002 SDRAM MODULE;256M,8M*16,PC133,SP 297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW1,SW2,SW3,SW4
340671200005 SHIELDING ASSY;TOP,8170 297030105003 SW;TOGGLE,SPST,5V/1mA,MPU-101-80 SW6
561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 346671200002 THERMAL PAD;HEATSINK,CPU,8170
370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK 310111103012 THERMISTOR;10K,1%,RA,0603,1P R4
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 340669900002 TILT UNIT;L,7170
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 340669900001 TILT UNIT;R,7170
370102630601 SPC-SCREW;M2.6L6,HDt0.5,NIWNLK 442164900010 TOUCH PAD MODULE;TM41PD-350
370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ500,PQ501,PQ506,PQ507
370102010205 SPC-SCREW;M2L2(t0.3),N/W/WLK 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ1,PQ3
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK, 288203400001 TRANS;AO3400,N-MOSFET,SOT-23 Q13,Q503
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK, 288203401001 TRANS;AO3401,P-MOSFET,SOT-23 PQ1,PQ512,Q1,Q509
370102010309 SPC-SCREW;M2L3.0,NIW/NLK,HD07 288204400001 TRANS;AO4400,N-MOSFET,SO-8 PU13,Q500,U505
370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 288204400001 TRANS;AO4400,N-MOSFET,SO-8 PU501,PU504
370102010405 SPC-SCREW;M2L4,NIW,K-HD(+),NYLOK 288200144002 TRANS;DTA144WK,PNP,SMT Q514
370102010405 SPC-SCREW;M2L4,NIW,K-HD(+),NYLOK 288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 PQ511,Q10,Q15,Q2,Q506,Q5
370102010608 SPC-SCREW;M2L6,KD,HDψ 3 ,NIB/NL 288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ2,PQ509,Q12,Q14,Q3,Q4,
370102010606 SPC-SCREW;M2L6,K-HD(t0.2),NIB/NL 288200302001 TRANS;FDV302P,P-CHANNEL,SOT23 Q7
370102010605 SPC-SCREW;M2L6,NIW,HDT=0.4,779 288203906018 TRANS;MMBT3906L,PNP,Tr35NS,TO236 PQ505
187

Part Number Description Location(s)
288202303001 TRANS;SI2303DS,P-MOSFET,SOT-23 PQ2
288104362001 TRANS;SI4362DY,N-HOSFET,S08 PU1,PU2,PU501,PU502,PU5
288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU5
288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU503,PU506
288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU6
288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU502,PU505
288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PU10,PU11,PU512,PU9
288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ502,PQ503
288204892001 TRANS;SI4892DY,N-MOSFET,SO8 PU500,PU503,PU506,PU507
273001050065 TRANSFORMER;10/100 BASE,LF-H72P, U2
373101710301 T-SCREW;I,M1.7,L3,K-HD,D3.0,NIB
373002010002 T-SCREW;S.M2 L4, PAN(+),NIW
373002010003 T-SCREW;S.M2 L5, PAN(+),NIW
270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-0 S500
271911103906 VR;10K,20%,0.05W,RN101GAC10KPGJ- VR1
421671200004 WIRE ASSY;HANNSTAR,14.1",SXGA,LC
421671200007 WIRE ASSY;INVERTER,8170
421671200008 WIRE ASSY;MDC,8170
421669900007 WIRE ASSY;TOUCHPAD,7170
274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X502
274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X503
274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X1,X2
274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X501
274012700401 XTAL;27MHZ,20PPM,16PF,7*5,4P,SMT X500
274013276114 XTAL;32.768KHZ,10PPM,12.5PF X3
188
A B
MODEL : 8170 Revision 02

Contexts
Title Page History of Schematics
Cover Sheet 1 Revision 0A (EVT)
1.ADD 1UF FOR ADM1021A Temperature Monitor.
System Block Diagram 2 2.DEL EMAIL BTN SW5 AND D16 LED INCICATOR.
3.+1.8VA CHANGE (+1.8V_ICH) FOR ICH2.
Power Block Diagram 3 4.+3VA CHANGE (+3V_ICH) FOR ICH2.
5.-PCIRST CONTROL HDD & CD_ROM RESET,CHANGE VON GPIO PIN EACH RESET FOR S3 WEAKUP.
P4-CPU (1/2) 4 6.ADD TWO 10K PULL_UP RESISTOR FOR H8 THERMAL SENSE ,TWO FAN FREEBACK SCHEMATIC.
7.ADD U515 & CHANGE J5 FOR 8170 QK/B AND 8175 LED/B COMMON.
P4-CPU (2/2) 5 8.ADD -LID PIN ON J6 FOR 8175 COVER SWITCH.
9.MODIFY TOUCH_PAD +5VS CHANGE +5VS.
BROOKDALE-MCH845(1/2) 6 10.MODIFY LANPHY +3VS CHANGE +3V.
2
11.MODIFY ICH2 +5VA CHANGE +5V. 2
BROOKDALE-MCH845(2/2) 7 12.MODIFY RTC CIRCUITRY +3VA CHANGE +5VA VON 330K & 1M DIVIDER.
Clock Generator,Screw holes 8 Revision 0B (DVT)

1.ADD DIODE FOR S.B +5VS DRAIN.
SO-DIMM Memory X 2 9 2.ADD C717 &C718 (4.7U) for boot time "popo"tone.
3.ADD R162 modify 2M BIOS pull +5VS.
VGA-M6(1/2) 10 4.Change SDRAM Q8 for IO_DATA ram module.
5.ADD 1U CAP for inverter RED too light.
VGA-M6(2/2) 11 6.IEEE1394 modify 1394_GND of digital GND for ESD issue.
7.MDC modify to digital GND.
LCD & CRT Interface 12 8.Modify FAN feedback +5V change +5VS and FAN control pin modify +5VS change +5V.
9.Second fan modify connect Vertical to Horizontally.
ICH2 13
HDD, CDROM Connector & PULL-UP RESISTER 14 Revision 01 (PVT)
1.CHANGE CAP 0.068U OF 0603 TO 0805.
PCMCIA/1394 Controller(PCI4410) & Socket 15 2.LAN OF MA8(PIN61) PULL HI +3V.
3.R163,R164,R696,R697,L535 CHANGE OF DFS FOR COST DOWN.
LANPHY,MDC 16 4.AMP(MUTE IN) ADD PULL HI +5VS.
5.LCD CONNECT PROVISION 5P CAP.
Audio Codec & Amplifier 17
TOUCH PAD,BIOS,SUPER-IO 18 POWER STATES IDSEL BUS MASTER
STATE IDSEL CHIP REQ/GNT CHIP
Micro Controller(H8) 19 VOTAGE FULL ON STR STD MEC-OFF REMARK AD18 -REQ0/-GNT0 PCMCIA
SIGNAL
AD11 -REQ1/-GNT1 LAN
Battery Connector &3V,5V-RESUME POWER 20 -SUSB - HIGH LOW LOW LOW AD18 LAN -REQ2/-GNT2
AD19 PCMCIA -REQ3/-GNT3 NU
CPU Vcore,1.8V,1.5V 21 -SUSC - HIGH HIGH LOW LOW -REQ4/-GNT4 NU
ADP +19V O O O O
DC-DC CONNECTOR,CHARGER 22 PCIINT
BATTERY +12V O O O O PCIINT CHIP
RTC_VCC +3.3V O O O O INTA PCMCIA/ATI VGA
INTC PCMCIA/1394
CPU_CORE +1.75V O X X X INTH USB2
+1.8VS +1.8V O X X X INTD USB1/LAN
+1.8V_ICH +1.8V O O X X
1 COMP
VDDR_MEM2.5 +2.5V O X X X 2 GND
3 IN-1
+3VS +3.3V O X X X
1
DRAW DESIGN CHECK ISSUED +3V +3.3V O O X X
4
5
GND
POWER
1
6 IN-2
+3V_ICH +3.3V O O X X
7 GND
+5VS +5V O X X X 8 SOLDER
+5V +5V O O X X
+5VA +5V O O 0 0
+12VS +12V O X X X
+12V +12V O O X X
Title
Cover Sheet
Size Document Rev

C 411671200001 02
Number
Date: Friday, December 28, 2001 Sheet 1 of 22
A B
A B
8170 System Block Diagram Pentium 4

Willamette/Northwood
C.P.U.
ADM 1021
Micro-FCPGA 478 pin
Thermal Recorder
IC CARD TPS2211
-HA3..31]
-HD[0..63]
Power Switch
Control
Socket
SSOP 16
A[0..25]
D[0..15]
Control
DDC
2
VSYNC 2
HSYNC 144 Pin SO-DIMM Socket*2

CRT R ATI
1394
G M6 Brookdale
PHY
PCI 4410 B
VGA AGP BUS 4X MD[0..63]
TSB41AB1 PCMCIA/1394 LINK S Y MCH

MA[0..14]
TI PQFP64 CONTROLLER C
Vedio
SO-DIMM
BGA 484 BGA 593 DRAM Control
uBGA 209 TFT LCD LVDS DATA
MINI 14.1"/15.1"
AD[0..31]
1394
Control
PCI BUS 13 HUB LINK

AD[0..31]
Control
USB0
HUB[0..11]
3
Control
Control
AD[0..31]
Controller 0
3 USB1
Controller 1 External
RJ45 RTL8139CL Microphone
LQFP 128
Internal
Intel 82801BA Microphone
PD[0..15] 16
(HDD)
Primary EIDE
ICH2 Internal
Control Speaker
AC Link 5
BGA 421 Realtek ALC201 TPA 0202
Secondary EIDE
SD[0..15] 16 Audio Codec Amplifier SPDIF

PQFP 48 JACK Clock
(CDROM/DVD)
Control Generator
5 M.D.C. RJ-11 ICS950805
LPC
(30 pin) JACK

Control
1
IR Module Cover Switch
1
HP-3600 NS87393 H8-3437 1
ISA BUS Keyboard Controller

Super I/O Internal Keyboard
PRINTER PQFP 100
TQFP 100PIN
PORT
External Keyboard
Power Button
Flash ROM Touch PAD
512KB
FAN1 For CPU
PLCC 32 16MHz FAN2 For D/D
Title
System Block Diagram
Size Document Rev

411671200001 02
Number
A B
5 4 3 2 1
POWER DIAGRAM OF THE 8170 +3V +12VS +1.5VS
Shut Down 1.8VS

MUST BE MEET ICH2
SUSB# MOSFET (FOR VGA) POWER ON SEQUENCE
D
VDDR_MEM2.5 D
PWR_ON
Shut Down
MOSFET
DC/DC BOARD +3VS * OPTION(NO LINK)
+1.5VS MCH ?
Shut Down Shut Down CPU_CORE

ATI_M6
CPU(FOR 1.7G) 49.3A
20mA
Protecter MOSFET +1.8V *ATI_M6 1200mA

ADAPTOR Self Diode 3.3V DC to DC Convertor +5VS +1.8VS MCH 350mA
Dischange ICH2
ATI_M6
350mA
1200mA
+5V +1.8VA ICH2 5mA
VDDR_MEM2.5 ATI_M6 470mA
Shut Down Shut Down +3V MCH ?

learning SODIMM
M6
2A
330mA
5V DC to DC Convertor MOSFET ICH2

RTL8139CL
410mA
330mA
+12V +12VS IEEE1394
PCI4410
PCMCIA CARD
69mA
79mA
500mA
C P Channel D/VMAIN Shut Down Shut Down +3VS *MCH
ICH2
CLOCK
?
410mA
280mA
C
MOSFET 12V DC to DC Convertor MOSFET M6

SIO
20mA
50mA
Battery Discharge SI4835DY
LCD 800mA
Pack CPU_CORE_EN +3VA ICH2 15mA
CPU_CORE +5V MODEM

PCMCIA CARD
?
500mA
Vcc Core DC to DC Convertor +5VS IDE

CD-ROM
ALC200
900mA
1500mA
40mA
USBX2 1000mA
LTC1709-9 AUDIO AMP 1000mA
+5VA H8 40mA
Diode
+5VA
Charge
Always Regulator
LP2951
B B
High +5V
Low Rsense +3V_ICH
Choke
Side Regulator
TC55RP3302
EMB
MUST BE MEET ICH2
POWER ON SEQUENCE
+1.8V_ICH
Regulator
CC AME8801
PWM CHARGE
Charge IC CC Charge
SWITCH
A MAX1772 SI4925DY A
CV
Title
Power Block Diagram
Size Document Rev

411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
-HD[0..63]
(6) -HD[0..63]
-HA[3..31]
(6) -HA[3..31] U1A U1B
-HA3 K2 G1 -H_ADS -HD31 H25 M23 -HD32
-HA4 A#3 ADS# -H_ADS (6) -HD30 D#31 D#32 -HD33
K4 AC1 K23 N22
-HA5 A#4 AP#0 -HD29 D#30 D#33 -HD34
L6 V5 J24 P21
-HA6 A#5 AP#1 -HD28 D#29 D#34 -HD35
K1 AA3 L22 M24
-HA7 A#6 BINIT# -H_BNR -HD27 D#28 D#35 -HD36
L3 G2 -H_BNR (6) M21 N23
-HA8 A#7 BNR# -HD26 D#27 D#36 -HD37
M6 H24 M26
-HA9 A#8 -HD25 D#26 D#37 -HD38
L2 L25 G26 N26
-HA10 A#9 DP#3 -HD24 D#25 D#38 -HD39
M3 K26 L21 N25
-HA11 A#10 DP#2 -HD23 D#24 D#39 -HD40
D M4 K25 D26 R21 D
-HA12 A#11 DP#1 -HD22 D#23 D#40 -HD41
N1 J26 F26 P24
-HA13 A#12 DP#0 -HD21 D#22 D#41 -HD42
M1 E25 R25
-HA14 A#13 TESTHI8 -HD20 D#21 D#42 -HD43
N2 U6 F24 R24
-HA15 A#14 TESTHI8 TESTHI9 -HD19 D#20 D#43 -HD44
N4 W4 F23 T26
-HA16 A#15 TESTHI9 TESTHI10 -HD18 D#19 D#44 -HD45
N5 Y3 G23 T25
-HA17 A#16 TESTHI10 -H_BR0 -HD17 D#18 D#45 -HD46
T1 H6 -H_BR0 (6) E24 T22
-HA18 A#17 BR#0 -HD16 D#17 D#46 -HD47
R2 H22 T23
-HA19 A#18 -H_BPRI CPU_CORE -HD15 D#16 D#47 -HD48
P3 D2 -H_BPRI (6) D25 U26
-HA20 A#19 BPRI# -HD14 D#15 D#48 -HD49
P4 J21 U24
-HA21 A#20 -H_DBSY -HD13 D#14 D#49 -HD50
R3 H5 -H_DBSY (6) D23 U23
-HA22 A#21 DBSY# -H_DEFER -HD12 D#13 D#50 -HD51
T2 E2 -H_DEFER (6) C26 V25
A#22 DEFER# D#12 D#51
1
-HA23 U1 H2 -H_DRDY -HD11 H21 U21 -HD52
-HA24 A#23 DRDY# -H_DRDY (6) -HD10 D#11 D#52 -HD53
P6 F3 -H_HIT R509 R3 R2 G22 V22
-HA25 A#24 HIT# -H_HIT (6) -HD9 D#10 D#53 -HD54
U3 E3 -H_HITM 300/NA 62 62 B25 V24
-HA26 A#25 HITM# -H_HITM (6) -HD8 D#9 D#54 -HD55
T4 R506 62 1% 0603 0603 0603 0603 C24 W26
-HA27 A#26 1% -HD7 D#8 D#55 -HD56
V2 AC3 1 2 CPU_CORE C23 Y26
-HA28 A#27 IERR# -THRMTRIP -HD6 D#7 D#56 -HD57
2
R6 B24 W25
-HA29 A#28 -H_INIT -H_PROCHOT -HD5 D#6 D#57 -HD58
W1 W5 -H_INIT (13) D22 Y23
-HA30 A#29 INIT# -H_INIT -HD4 D#5 D#58 -HD59
T5 C21 Y24
-HA31 A#30 -H_LOCK -HD3 D#4 D#59 -HD60
U4 G4 -H_LOCK (6) A25 Y21
-H_ADSTB1 A#31 LOCK# -HD2 D#3 D#60 -HD61
(6) -H_ADSTB1 R5
ADSTB#1 DESIGN GUIDE PAGE 236 A23
D#2 D#61
AA25
-H_ADSTB0 L5 V6 -HD1 B22 AA22 -HD62
(6) -H_ADSTB0 -H_REQ4 H3
ADSTB#0 MCERR# DESCRIPTION(NO extra pull-up -HD0 B21
D#1 D#62
AA24 -HD63
-H_REQ3 REQ#4 D#0 D#63
J3
REQ#3 RESET#
AB25 -CPURST
-CPURST (6) resistors required)
-H_REQ2 J4 F4 -H_RS2 -DBI[0..3] -DSTBP[0..3]
REQ#2 RS#2 (6) -DBI[0..3] -DSTBP[0..3] (6)
-H_REQ1 K5 G5 -H_RS1 -DBI0 E21
-H_REQ0 REQ#1 RS#1 -DBI1 DBI#0
J1 F1 -H_RS0 G25 F21 -DSTBP0
REQ#0 RS#0 -DBI2 DBI#1 DSTBP#0
AB1 AB2 -H_RS[0..2]
-H_RS[0..2] (6) P26 J23 -DSTBP1
A#35 RSP# -DBI3 DBI#2 DSTBP#1
(6) -H_REQ[0..4] -H_REQ[0..4] Y1 J6 -H_TRDY
-H_TRDY (6) V21 P23 -DSTBP2
A#34 TRDY# DBI#3 DSTBP#2
W2 W23 -DSTBP3
A#33 -DSTBN0 E22 DSTBP#3
V3
A#32 -DSTBN1 K22 DSTBN#0
-DSTBN2 R22 DSTBN#1
WMT478/NWD_14 -DSTBN3 W22 DSTBN#2
DSTBN#3
(6) -DSTBN[0..3] -DSTBN[0..3] WMT478/NWD_14
C C
PRECISION FSB COMPENSATION RESISTORS

R7
H_COMP0 -H_A20M U1C
1 2 TP547 1
51.1 0603 1 -H_IGNNE HCLK_CPU AF22 AD6 H_BSEL0
TP40 (8) HCLK_CPU BCLK0 BSEL0 H_BSEL0 (8)
1% 1 H_INTR -HCLK_CPU AF23 AD5 1 TP2
TP42 (8) -HCLK_CPU BCLK1 BSEL1
1 2 H_COMP1 1 H_NMI TP6 1 AC26 A6 TESTHI11
TP41 ITP_CLK0 TESTHI11
51.1 0603 CPU_CORE TP8 1 AD26 L24 H_COMP0
1% R507 ITP_CLK1 COMP0 H_COMP1
P1
-H_A20M COMP1
(13) -H_A20M C6
-H_FERR A20M# -H_BMP5
B6 AB4
(13) -H_FERR -H_IGNNE FERR# BPM#5 -H_BMP4
PLACE THESE INSIDE SOCKET CAVITY B2
IGNNE# BPM#4
AA5
1
(13) -H_IGNNE -H_BMP3
Y6
R521 R514 R503 R516 R513 R508 R519 R515 R512 H_INTR BPM#3 -H_BMP2
D1 AC4
39 75 150 51 51 51 51 51 51 (13) H_INTR H_NMI LINT0 BPM#2 -H_BMP1
REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1% 0603 0603 0603 (13) H_NMI
E5
LINT1 BPM#1
AB5
-H_BMP0
0603 0603 0603 0603 0603 0603 -H_SMI B5 AC6
(13) -H_SMI -H_STPCLK SMI# BPM#0
Y4
-H_BMP5 (13) -H_STPCLK STPCLK# TESTHI0
2
AD24
-H_BMP4 PVID4 TESTHI0 TP5
AE1 AE25 1
-H_BMP3 PVID3 VID4 DBR# TESTHI12
AE2 AD25
-H_BMP2 PVID2 VID3 TESTHI12
AE3
CPU_CORE -H_BMP1 PVID1 VID2 H_GTLREF2_3
AE4 AA6
-H_BMP0 PVID0 VID1 GTLREF3
AE5 F6
PVID[0..4] VID0 GTLREF2
AA21
ITP_TDI (21) PVID[0..4] GTLREF1 CPU_GTLREF
F20
ITP_TDO GTLREF0
RP2 AF2
TESTHI4 ITP_TMS CPU_CORE VCC TESTHI5
1 10 1 AF3 AC23
TESTHI5 TESTHI0 TP1 RSVD TESTHI5 TESTHI4
2 9 (5) VCCPVID AF4 AC24
TESTHI6 TESTHI1 ITP_TCK PLL_VCCA VCCVID TESTHI4 TESTHI3
3 8 AD20 AC20
TESTHI7 TESTHI2 -ITP_RESET VCCA TESTHI3 TESTHI2
4 7 1 A5 AC21
TESTHI3 TP4 VCCIO_PLL VCCSENSE TESTHI2 TESTHI7
5 6 AE23 AB22
PLL_VSSA VCCIOPLL TESTHI7 TESTHI6
AD22 AA20
VSSA TESTHI6
1
1
1K*8 1206 1 A4 AF26 1 TP7
R502 R522 TP3 VSSSENSE SKTOCC#
27 680 AE21 AA2 TESTHI1
0603 0603 RSVD TESTHI1 H_PWRGD
RP505 A22 AB23 H_PWRGD (13)
TESTHI11 RSVD PWRGOOD -H_PROCHOT
1 10 A7 C3
TESTHI12 TESTHI8 CPU_THERMDA RSVD PROCHOT# -SLP
PLACE CLOSE TO CPU SOCKET
2
2 9 B3 AB26 -SLP (13)

B TESTHI9 CPU_THERMDC THRMDA SLP# B
3 8 C4
TESTHI10 -THRMTRIP THRMDC
4 7 A2
THRMTRIP# ITP_TCK
5 6 D4
TCK ITP_TDI
AD3 C1
RSVD TDI ITP_TDO
1K*8 1206 AF25 D5
RSVD TDO ITP_TMS
AD2 F7
RSVD TMS -ITP_RESET
AF24 E6
RSVD TRST#
WMT478/NWD_14
Close to CPU socket

+5VS
One 220PF for each GTL REF Pin
CPU_CORE
4" MAX. CPU_CORE
1
CPU_CORE PLACE AT CPU END C536
R520 0.1U
1
1 2 H_GTLREF2_3 0603
49.9 0603 U502 50V
2
1
1% L2 L3 1 2
TEST VDD
1
R511 C522 C523 C524 4.7UH 4.7UH R517 16
THERMAL RECORDER
TEST1
1
100 1U 220P 220P 2012 2012 R6 R510 R5 10
0603 0805 0603 0603 51 51 301 CPU_THERMDA ADD0 R526
3 6
D+ ADD1 Layout Note:
2
1% 5% 5% 5% 0603 0603 0603 62 10K

2
4
D-
1
R518 0603 0603
2
1%
C531 ALERT
11 W=12mil
2
2200P 7
0/NA 7343 C30 0603 GND1
2
8 12
0603 PLL_VCCA -H_FERR CPU_THERMDC GND2 SDATA H8_THRM_DATA (19)
+
2
2 1
20%
1
5 14
CPU_CORE 16V 33U H_PWRGD NC1 SCLK H8_THRM_CLK (19)
PLACE AT CPU END 9
NC2
R527
CPU_GTLREF -H_BR0 W/S=12/12 mils 13
NC3 STBY
15
1 2
49.9 0603 PLL_VSSA
(キキキキキキ ADM1021 QSOP16B
1
1
1% -CPURST
as short as
1
1
R525 C545 C547 C546 R523 R524 C715
100
0603
1U
0805
220P
0603
220P
0603 7343 C31
possible 0_DFS
0603
0_DFS
0603
1U
0603
A A
5% 5% 5% VCCIO_PLL
+
1%
2
2
2 1
20%
2
2
16V 33U CPU SIGNAL TERMINATION
GTL Reference CKT PLL SUPPLY FILTER

Title
P4-CPU(1/2)
Size Document Rev

Custom 411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
D D
CPU_CORE
CPU_CORE
1
C15 C26 C14 C24
10U 10U 10U 10U
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
1206 1206 1206 1206
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
AF5
AF7
AF9
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
E12
E14
E16
E18
E20
F11
F13
F15
F17
F19
10V 10V 10V 10V
C8
D7
D9
U1D
A8
B7
B9
E8
2
F9
N6 AE7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS VSS
N3 AE24
VSS VSS
1
N24 AE22 C550 C529 C528 C13 C29 C521
VSS VSS CPU_CORE
N21 AE19 10U 10U 10U 10U 10U 10U
VSS VSS 1206 1206 1206 1206 1206 1206
P5 AD14
VSS VSS 10V 10V 10V 10V 10V 10V
2
P2 AD12
VSS VSS
P25 AD10
VSS VSS
1
P22 AD8 C12 C28
VSS VSS
1
R26
VSS VSS
AD4 C8 C514 C16 C552 + 150U + 150U
1
R4 AD1 C518 C517 C18 C20 C23 C19 22U 22U 22U 22U 7343 7343
VSS VSS 1210 1210 1210 1210 10V 10V
R1 AD23 10U 10U 10U 10U 10U 10U
VSS VSS 1206 1206 1206 1206 1206 1206 10V 10V 10V 10V
2
R23 AD21
VSS VSS 10V 10V 10V 10V 10V 10V CPU_CORE
2
T6 AE17
VSS VSS
T3 AE15
VSS VSS
T24 AE13
VSS VSS
T21 AE11
VSS VSS
1
U5 AE9 C21 C27 C25 C17 C543 C11
C VSS VSS C
U2 AE26 10U 10U 10U 10U 10U 10U
VSS VSS
1
U25 AB20 1206 1206 1206 1206 1206 1206 C534 C544 C538 C22 C540 C539 C532 C549 C533 C548
VSS VSS 10V 10V 10V 10V 10V 10V
2
U22 AC17 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
VSS VSS 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
V26 AC15
VSS VSS 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V
2
G21 AC13
VSS VSS
H26 AC11
VSS VSS
1
H4 AC9 C9 C7 C551 C542 C541 C537
VSS VSS
H1 AC7 10U 10U 10U 10U 10U 10U
VSS VSS 1206 1206 1206 1206 1206 1206
H23 AC5
VSS VSS 10V 10V 10V 10V 10V 10V
2
J5 AC2
VSS VSS
J2 AC25
VSS VSS
J25 AC22
VSS VSS
J22 AC19
VSS VSS
1
K6 AD18 C535 C530 C526 C525 C513 C10
VSS VSS
K3 AD16 10U 10U 10U 10U 10U 10U
VSS VSS 1206 1206 1206 1206 1206 1206
K24 AA4
VSS VSS 10V 10V 10V 10V 10V 10V
2
K21 AA1
VSS VSS
L26 AA23
VSS VSS
L4 AA19
VSS VSS
L1 AB18
VSS VSS
L23 AB16
VSS VSS
M5 AB14
VSS VSS
M2 AB12
VSS VSS
AB10
VSS
M25 AB8
VSS VSS
M22 AB6
VSS VSS
E11 AB3
VSS VSS
E9 AB24
VSS VSS
E26 AB21
VSS VSS
E7 V4
VSS VSS
E4 V1
VSS VSS
E1 V23
VSS VSS
E23 W6
VSS VSS
E19 W3
VSS VSS
F18 W24
VSS VSS
F16 W21
VSS VSS
F14 Y5
VSS VSS
F12 Y2
VSS VSS
F10 Y25
VSS VSS
F8 Y22
VSS VSS
F5 AA17
B VSS VSS B
F2 AA15
VSS VSS +5VS +5VS
F25 AA11
VSS VSS
F22 AA9
VSS VSS
G6 AA26
VSS VSS
1
G3 AA7
VSS VSS R504 R505
G24
VSS 10 10K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0603 0603
AA13
AF18
AF16
AF14
AF12
AF10
AF20
C25
C22
C19
D18
D16
D14
D12
D10
D24
D21
D20
C17
C15
C13
C11
AF8
AF6
AF1
E17
E15
E13
A24
A21
A19
B18
B16
B12
B10
B26
B23
B20
A17
A15
A13
A11
A26
B14
2
C5
C2
D8
D6
D3
C9
C7
A3
B8
B4
A9
WMT478/NWD_14 U501
1 4 CPU_CORE_EN
IN PG CPU_CORE_EN (21)
3
EN VCCPVID
2 5 VCCPVID (4)
GND OUT
1
C515
1
0.1U MIC5248
0603 C516
16V SOT25 1U
0603
2
10%
2
A A
Title
P4-CPU(2/2)
Size Document Rev

Custom 411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
-HA[3..31] -HD[0..63] U3D

(4) -HA[3..31] U3C -HD[0..63] (4)
W8 A15
-HA3 -HD0 VSS_0 VSS_71
D T4 AA2 W26 A11 D
-HA4 HA3# HD0# -HD1 VSS_1 VSS_72
T5 AB5 Y6 A7
T3 AA5 Y22 A3
U3 AB3 V8 F24
R3 AB4 V6 F20
P7 AC5 AC26 F16
R2 AA3 AC23 F12
P4 AA6 AC21 F8
R6 AE3 AC20 E29
P5 AB7 AC18 E26
-HA13 HA12# HD9# -HD10 VSS_10 VSS_81
P3 AD7 AC4 E4
-HA14 HA13# HD10# -HD11 VSS_11 VSS_82
N2 AC7 AC1 E1
-HA15 HA14# HD11# -HD12 VSS_12 VSS_83
N7 AC6 AB22 D21
-HA16 HA15# HD12# -HD13 VSS_13 VSS_84
N3 AC3 AB19 D17
-HA17 HA16# HD13# -HD14 VSS_14 VSS_85
K4 AC8 AB16 D13
-HA18 HA17# HD14# -HD15 VSS_15 VSS_86
M4 AE2 AB15 D9
-HA19 HA18# HD15# -HD16 VSS_16 VSS_87
M3 AG5 AB14 D5
-HA20 HA19# HD16# -HD17 VSS_17 VSS_88
L3 AG2 AB13 A27
-HA21 HA20# HD17# -HD18 VSS_18 VSS_89
L5 AE8 AG20 A23
-HA22 HA21# HD18# -HD19 VSS_19 VSS_90
K3 AF6 AG18 A19
-HA23 HA22# HD19# -HD20 VSS_20 VSS_91
J2 AH2 AG1 K27
-HA24 HA23# HD20# -HD21 VSS_21 VSS_92
M5 AF3 AF25 K7
-HA25 HA24# HD21# -HD22 VSS_22 VSS_93
J3 AG3 AF21 J29
-HA26 HA25# HD22# -HD23 VSS_23 VSS_94
L2 AE5 AF19 J26
-HA27 HA26# HD23# -HD24 VSS_24 VSS_95
H4 AH7 AF17 J22
-HA28 HA27# HD24# -HD25 VSS_25 VSS_96
N5 AH3 AF15 J6
-HA29 HA28# HD25# -HD26 VSS_26 VSS_97
G2 AF4 AF13 J4
-HA30 HA29# HD26# -HD27 VSS_27 VSS_98
M6 AG8 AF11 J1
-HA31 HA30# HD27# -HD28 VSS_28 VSS_99
L7 AG7 AF9 K5
HA31# HD28# -HD29 VSS_29 VSS_100
AG6 AF7 H21
-H_REQ[0..4] HD29# -HD30 VSS_30 VSS_101
(4) -H_REQ[0..4] AF8 AF5 H19
-H_REQ0 HD30# -HD31 VSS_31 VSS_102
U6 AH5 AJ27 H17
-H_REQ1 HREQ0# HD31# -HD32 VSS_32 VSS_103
T7 AC11 AJ17 H15
R7 AC12 AJ15 H13
U5 AE9 AJ13 H11
U2 AC9 AJ11 H9
-H_ADSTB0 HREQ4# HD35# -HD36 VSS_36 VSS_107
(4) -H_ADSTB0 R5 AE10 AJ9 G26
-H_ADSTB1 HADSTB0# HD36# -HD37 VSS_37 VSS_108
(4) -H_ADSTB1 N6 AD9 AJ7 P8
HADSTB1# HD37# -HD38 VSS_38 VSS_109
AG9 AJ5 P6
HD38# -HD39 VSS_39 VSS_110
AC10 AJ3 N29
-HCLK_MCH HD39# -HD40 VSS_40 VSS_111
(8) -HCLK_MCH K8 AE12 AH23 N22
HCLK_MCH BCLK# HD40# -HD41 VSS_41 VSS_112
(8) HCLK_MCH J8 AF10 AH21 N17
C HYRCOMP BCLK HD41# -HD42 VSS_42 VSS_113 C
AC13 AG11 AH19 N15
HYSWING HRCOMP1 HD42# -HD43 VSS_43 VSS_114
AD13 AG10 AG22 N13
HXRCOMP HSWNG1 HD43# -HD44 VSS_44 VSS_115
AC2 AH11 AD6 N8
HRCOMP0 HD44# -HD45 VSS_45 VSS_116
AA7 AG12 AD8 N4
-DSTBP[0..3] HSWNG0 HD45# -HD46 VSS_46 VSS_117
(4) -DSTBP[0..3] AE13 AD10 N1
HD46# VSS_47 VSS_118
2
-DSTBP0 AF12 -HD47 AD12 M23

-DSTBP1 R532 R9 -DSTBP0 HD47# -HD48 VSS_48 VSS_119
AD3 AG13 AD14 L26
-DSTBP2 24.9 24.9 -DSTBN0 HDSTBP0# HD48# -HD49 VSS_49 VSS_120
AD4 AH13 AD16 L24
-DSTBP3 0603 0603 -DBI0 HDSTBN0# HD49# -HD50 VSS_50 VSS_121
AD5 AC14 AD19 L22
-DSTBN[0..3] 1% 1% -DSTBP1 DBI0# HD50# -HD51 VSS_51 VSS_122
(4) -DSTBN[0..3] AE7 AF14 AD22 L8
-DSTBN0 -DSTBN1 HDSTBP1# HD51# -HD52 VSS_52 VSS_123
1
AE6 AG14 AE1 L6

-DSTBN1 -DBI1 HDSTBN1# HD52# -HD53 VSS_53 VSS_124
AG4 AE14 AE4 L4
-DSTBN2 -DSTBP2 DBI1# HD53# -HD54 VSS_54 VSS_125
AD11 AG15 AE18 L1
-DSTBN3 -DSTBN2 HDSTBP2# HD54# -HD55 VSS_55 VSS_126
AE11 AG16 AE20 U29
-DBI[0..3] -DBI2 HDSTBN2# HD55# -HD56 VSS_56 VSS_127
(4) -DBI[0..3] AH9 AG17 AE29 U15
-DBI0 -DSTBP3 DBI2# HD56# -HD57 VSS_57 VSS_128
AC16 AH15 P14 U4
-DBI1 -DSTBN3 HDSTBP3# HD57# -HD58 CPU_CORE VSS_58 VSS_129
AC15 AC17 P16 U1
-DBI2 -DBI3 HDSTBN3# HD58# -HD59 VSS_59 VSS_130
AD15 AF16 W1 T22
-DBI3 DBI3# HD59# -HD60 VSS_60 VSS_131
AE15 W4 T16
HD60# VSS_61 VSS_132
1
AH17 -HD61 AA1 T14
-H_ADS HD61# -HD62 R535 VSS_62 VSS_133
(4) -H_ADS V3 AD17 AA4 T8
-H_TRDY ADS# HD62# -HD63 49.9 VSS_63 VSS_134
(4) -H_TRDY U7 AE16 AA8 T6
-H_DRDY HTRDY# HD63# 0603 VSS_64 VSS_135
(4) -H_DRDY V4 AA29 R26
-H_DEFER DRDY# 1% VSS_65 VSS_136
(4) -H_DEFER Y4 AB6 R17
-H_HITM DEFER# VSS_66 VSS_137
2
(4) -H_HITM Y3 AB17 AB9 R15
-H_HIT HITM# HVREF_0 VSS_67 VSS_138
(4) -H_HIT Y5 AB11 AB10 R13
HIT# HVREF_1 VSS_68 VSS_139
1
-H_LOCK W5 Y8 AB12 R4
(4) -H_LOCK HLOCK# HVREF_2 VSS_69 VSS_140
1
-H_BR0 V7 R8 C564 R536 V22 R1
(4) -H_BR0 BR0# HVREF_3 100 VSS_70 VSS_141
-H_BNR W3 M7 0.1U
(4) -H_BNR BNR# HVREF_4 0603
-H_BPRI Y7 0603 82845
(4) -H_BPRI BPRI# 50V 1%
-H_DBSY
2
(4) -H_DBSY V5 BGA568_25
-H_RS0 DBSY#
2
W2
-H_RS1 RS0#
W7
-H_RS2 RS1#
W6
-CPURST RS2#
AE17
-H_RS[0..2] CPURST#
(4) -H_RS[0..2]
(4) -CPURST 82845
BGA568_25
10 mil trace, 7 mil
B space, Cap place B
near MCH and

between two
resistors.
PLACE AT MCH845 END
CPU_CORE
1
R537 C562
301 0.01U
0603 0603
2
HYSWING
2
1
R540
150
0603
2
HXSWING, HYSWING 12 mil trace, 10 mil space

A A
Title
Brookdale-MCH845(1/2)
Size Document Rev

Custom 411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
+1.5VS CPU_CORE
AGP_AD[0..31] U3A MA[0..12]

(10) AGP_AD[0..31] MA[0..12] (9) U3B
AGP_AD0 R27 G22 MA0
AGP_AD1 G_AD0 SMA0 MA1
R28 E21 AG29 AJ23
AGP_AD2 G_AD1 SMA1 MA2 VCC1_5_0 VTT_0
T25 F21 AC29 AG23
R25 G21 W29 AJ21
T26 E20 R29 AG21
T27 G20 AE26 AF20
U27 E19 AA26 AE21 Power rail for
D U28 F19 U26 AD20 D
G_AD7 SMA7 VCC1_5_6 VTT_6
AGP_AD8
AGP_AD9
V26
G_AD8 SMA8
G19 MA8
MA9
AJ25
VCC1_5_7 VTT_7
AB20 SDR, still
V27 G18 AF23 AJ19
AGP_AD10 T23
G_AD9
G_AD10
SMA9
SMA10
E17 MA10 AD23
VCC1_5_8
VCC1_5_9
VTT_8
VTT_9
AG19 exist during
AGP_AD11 U23 E15 MA11 AA22 AE19
AGP_AD12 T24
G_AD11 SMA11
G12 MA12 W22
VCC1_5_10 VTT_10
AC19
STR.
AGP_AD13 G_AD12 SMA12 MD[0..63] VCC1_5_11 VTT_11
U24 MD[0..63] (9) U22 AF18
AGP_AD14 G_AD13 MD0 VCC1_5_12 VTT_12 +3VS
U25 F27 R22 AD18
AGP_AD15 G_AD14 SDQ0 MD1 VCC1_5_13 VTT_13 JS2
V24 E27 AD21 AB18
AGP_AD16 G_AD15 SDQ1 MD2 VCC1_5_14 VTT_14
Y27 B28 AB21 AA9 1 2
Y26 C27 P17 AB8
AGP_AD18 G_AD17 SDQ3 MD4 VCC1_5_16 VTT_16 SHORT-SMT4
AA28 D26 U16 U8
AGP_AD19 G_AD18 SDQ4 MD5 VCC1_5_17 VTT_17 +3V
AB25 E25 R16 M8
AB27 B25 N16 JO3
AGP_AD21 G_AD20 SDQ6 MD7 VCC1_5_19
AA27 D24 T15 G29 1 2
AGP_AD22 G_AD21 SDQ7 MD8 VCC1_5_20 VCCSM_0
AB26 F23 P15 C29
G_AD22 SDQ8 VCC1_5_21 VCCSM_1
1
AGP_AD23 Y23 B23 MD9 U14 L23 C55 C83 C590 C582 C589 C588 OPEN-SMT5
AB23 C22 R14 D25 10U 10U 0.1U 0.1U 0.1U 0.1U
AGP_AD25 G_AD24 SDQ10 MD11 VCC1_5_23 VCCSM_3 1206 1206 0603 0603 0603 0603
AA24 C21 N14 A25
AGP_AD26 G_AD25 SDQ11 MD12 VCC1_5_24 VCCSM_4 10V 10V 50V 50V 50V 50V
2
AA25 D20 P13 H24
AB24 C19 D23
AGP_AD28 G_AD27 SDQ13 MD14 +1.8VS VCCSM_6
AC25 C18 L25 K22
AC24 C17 L29 H22
AC22 B13 N26 F22
AD24 E13 N23 A21
-AGP_CBE[0..3] G_AD31 SDQ17 MD18 VCC1_8_3 VCCSM_10
(10) -AGP_CBE[0..3] C12 M22 H20
-AGP_CBE0 SDQ18 MD19 VCC1_8_4 VCCSM_11
V25 B11 D19
-AGP_CBE1 G_CBE0# SDQ19 MD20 VCCSM_12
V23 E11 H18
Y25 C10 F18
AA23 F9 A17
G_CBE3# SDQ22 MD23 VCCSM_15
C9 H16
66M_MCH66IN SDQ23 MD24 VCCSM_16
(8) 66M_MCH66IN P22 E8 D15
-AGP_FRAME 66IN SDQ24 MD25 VCCSM_17
(10,14) -AGP_FRAME Y24 E7 H14
-AGP_DEVSEL W28 G_FRAME# SDQ25 MD26 +1.5VS VCCSM_18
(10,14) -AGP_DEVSEL C7 F14
-AGP_IRDY G_DEVSEL# SDQ26 MD27 VCCSM_19
(10,14) -AGP_IRDY W27 D6 A13
-AGP_TRDY G_IRDY# SDQ27 MD28 VCCSM_20
(10,14) -AGP_TRDY W24 B5 H12
-AGP_STOP G_TRDY# SDQ28 MD29 VCCSM_21
(10,14) -AGP_STOP W23 D4 D11
AGP_PAR G_STOP# SDQ29 MD30 VCCSM_22
(10) AGP_PAR W25 C3 H10
-AGP_REQ G_PAR SDQ30 MD31 VCCSM_23
(10,14) -AGP_REQ AG24 B2 F10
G_REQ# SDQ31 VCCSM_24
1
-AGP_GNT AH25 G28 MD32 A9
(10,14) -AGP_GNT G_GNT# SDQ32 MD33 VCCSM_25
R8 1 2 1% GRCOMP AD25 E28 H8
40.2 0603 AGP_VREF GRCOMP SDQ33 MD34 L509 L512 VCCSM_26
(10) AGP_VREF AA21 C28 D7
C AGPREF SDQ34 MD35 4.7UH-10% 4.7UH-10% VCCSM_27 C
D27 F6
AGP_ADSTB0 SDQ35 MD36 3225 3225 VCCSM_28
(10,14) AGP_ADSTB0 R24 B27 A5
-AGP_ADSTB0 AD_STB0 SDQ36 MD37 VCCSM_29
(10,14) -AGP_ADSTB0 R23 F25 G4
AGP_ADSTB1 AD_STB0# SDQ37 MD38 VCCSM_30
2
(10,14) AGP_ADSTB1 AC27 C25 G1
-AGP_ADSTB1 AD_STB1 SDQ38 MD39 VCCSM_31
(10,14) -AGP_ADSTB1 AC28 E24 T13 C1
AGP_SBA[0..7] AD_STB1# SDQ39 MD40 VCCA0 VCCSM_32
(10) AGP_SBA[0..7] C24 U13 J7
AGP_SBA0 SDQ40 MD41 VSSA0 VCCSM_33
AH28 E23 T17 J5
AGP_SBA1 SBA0 SDQ41 MD42 VCCA1 VCCSM_34
AH27 D22 U17 K6
SBA1 SDQ42 VSSA1 VCCSM_35
1
AGP_SBA2 AG28 E22 MD43 C570 C571 K24
AGP_SBA3 SBA2 SDQ43 MD44 + + VCCSM_36
AG27 B21 33U 33U K26
AGP_SBA4 SBA3 SDQ44 MD45 VCCSM_37
AE28 C20 3528 3528
AGP_SBA5 SBA4 SDQ45 MD46 6.3V 6.3V
AE27 D18 82845
AGP_SBA6 SBA5 SDQ46 MD47
2
AE24 E18 BGA568_25
AGP_SBA7 SBA6 SDQ47 MD48
AE25 E14
AGP_SBSTB SBA7 SDQ48 MD49
(10,14) AGP_SBSTB AF27 C13
-AGP_SBSTB SB_STB SDQ49 MD50
(10,14) -AGP_SBSTB AF26 E12
SB_STB# SDQ50 MD51
F11
-AGP_RBF SDQ51 MD52
(10,14) -AGP_RBF AE22 C11
-AGP_WBF RBF# SDQ52 MD53
(14) -AGP_WBF AE23 E10
-AGP_PIPE WBF# SDQ53 MD54
(14) -AGP_PIPE AF22 D10
AGP_ST0 PIPE# SDQ54 MD55
(10,14) AGP_ST0 AG25 B9
AGP_ST1 ST0 SDQ55 MD56
(10,14) AGP_ST1 AF24 E9
AGP_ST2 ST1 SDQ56 MD57
(10,14) AGP_ST2 AG26 D8
HUB_D[0..10] ST2 SDQ57 MD58
(13) HUB_D[0..10] B7
HUB_D0 SDQ58 MD59
P25 E6
HUB_D1 HI_0 SDQ59 MD60
P24 C6
N27 C4
P23 B3
M26 D3
HUB_D5 HI_4 SDQ63
M25 C16 1
HUB_D6 HI_5 SCB0 TP540
L28 E16 1 TP522
HUB_D7 HI_6 SCB1
L27 C15 1
M27 D14 1
N28 B17 1
+1.8VS HUB_D10 HI_9 SCB4 TP28
M24 D16 1
HUB_STB HI_10 SCB5 TP538
(13) HUB_STB N25 B15 1 TP541
-HUB_STB HIU_STB SCB6 CPU_CORE +1.8VS
(13) -HUB_STB N24 C14 1
HIU_STB# SCB7 TP539
1 40.2 21% HUB_RCOMP P27
R16 0603 HUB_VREF HLRCOMP CKE0
P26 G9 CKE0 (9)
HI_REF SCKE0 CKE1
F4 CKE1 (9)
SCKE1
1
-PCIRST J27 G10 CKE2 C33 C32 C579 C554 C555 C558 C578 C580
B
(10,13,16,18) -PCIRST RSTIN# SCKE2 CKE3 CKE2 (9) B
H27 F5 CKE3 (9) 10U 10U 0.1U 0.1U 0.1U 0.1U 0.1U 4.7U
RSVD SCKE3
1 -MCH_TEST H26 G11 1 1206 1206 0603 0603 0603 0603 0603 0805
TP524 TESTIN# SCKE4 TP532 10V 10V 50V 50V 50V 50V 50V +80-20%
2
E5 1
SCKE5 MEM_BS0 TP537
1 G5 F17 MEM_BS0 (9)
TP21 SCK11 SMBA0 MEM_BS1
TP528 1 H5 G17 MEM_BS1 (9)
SCK10 SMBA1
1 F15
TP523 SCK9 -CS0
1 G16 H23 -CS0 (9)
TP530 SCK8 SCS0# -CS1
1 E3 J23 -CS1 (9)
TP20 SCK7 SCS1#
1 F3 G7 1
+1.8VS SDRAMCLK5 R570 TP19 22 SCK6 SCS2# TP534
(9) SDRAMCLK5 1 2 0603 G14 G8 1 TP533
SDRAMCLK4 R569 1 22 SCK5 SCS3# -CS4
(9) SDRAMCLK4 2 0603 G15 J24 -CS4 (9)
SCK4 SCS4# -CS5
1 C2 G24 -CS5 (9)
TP23 SCK3 SCS5# +1.5VS
1 E2 H7 1
R575 TP24 1 SCK2 SCS6# TP526
1
SDRAMCLK1 22 2 0603 G13 F7 1

(9) SDRAMCLK1 SCK1 SCS7# TP536
1
C576 R10 SDRAMCLK0 R574 1 22 2 0603 F13 G25 1

150 (9) SDRAMCLK0 SCK0 SCS8# TP531
0.01U H25 1
SCS9# TP525
1
0603 0603 -SRASA R18
(9) -SRASA G23 G6 1 C553 C34 C36 C563 C565 C557
-SCASA SRAS# SCS10# TP22
2
(9) -SCASA J25 H6 1 1 2 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U

-SWEA SCAS# SCS11# TP527 20 1% 0603 0603 0603 0603 0603 0603
2
(9) -SWEA G27

HUB_VREF SWE# 0603 50V 50V 50V 50V 50V 50V
2
HUB_VREF (13) J28
SMRCOMP
1 AD27 G3
TP500 RSVD0 RDCLKIN
1
1 AD26 H3 R26 1 2 0_DFS

TP501 RSVD1 RDCLKO Layout note: Trace length is 1.5" exactly.
1
C573 R13 C575 C157 C45 1 K25 0603

TP517 RSVD2
1
10U/NA 150 0.1U 0.1U 0.1U 1 K23 J21 C58 Place close to MCH
1206 0603 0603 0603 0603 TP518 RSVD3 SDREF0 +3VS +3V
TP535 1 F26
RSVD4 SDREF1
J9 10P/NA R01
10V 50V 50V 50V 0603
2
1 D12
TP31 RSVD5
2
1 C26
TP25 RSVD6
1 C23
TP26 RSVD7
1 C8 1 2
TP32 RSVD8 R553 0_DFS 0603
TP33 1 C5 R547
RSVD9
Layout note: Close to MCH TP27
1 B19
RSVD10
1 2
Layout note: Close to ICH2
1
82845 49.9 1 2 R554

1
BGA568_25 C581 R559 0603 0/NA 0603

0.1U 49.9 1%
0603 0603
50V 1%
2
10 MIL TRACE,150 LATE W/ 7MIL SPACE

A A
Layout note: Place as close to MCH as possible
Title
Brookdale-MCH845(2/2)
Size Document Rev

Custom 411671200001 02
Number
5 4 3 2 1
A B
CLOCK GENERATOR
+3VS +3VCLKCPU
L517
1 2
120Z/100M FS2 FS1 FS0 CPUCLK
2012 X502
1
1
C626 C623 C624 C625 1 3
0.1U 0.1U 0.1U 2.2U 0 0 1 100MHZ 2
0603 JL5 0603 0603 0805 4
50V 50V 50V +80-20% 14.318MHZ
2
2
1 2
0 1 1 133MHZ
1
JP_NET20 C618 C617
GNDCPU 5P 5P
+3VS 0603 0603
10% 10%
2
USBCLK_ICH (13)
1 33 2 14M_ICH (13)
1
R596 0603
+3VS +3VCLKPCI R40 R45 U507 33
L516 1K/NA 1K -HCLK_MCH (6)
Layout note: Place crystal within 2 39 0603 1 R624 2
0603 0603 X1 48MHZ_USB HCLK_MCH (6)
1 2 500 mils of CLK Gen. 38 1 TP36
120Z/100M 48MHZ_DOT 33
3 1 2 SIO_14.318MHZ (18)
2012 X2 R595 0603
2
35 1 TP37
3V66_1/VCH_CLK
1
2
C619 C620 C621 C622 FS0 29 2
FS1 (9,13) SMBDATA SDATA

0.1U 0.1U 0.1U 2.2U 30 56 -HCLK_CPU (4)
0603 0603 0603 0805 (4) H_BSEL0 FS2 (9,13) SMBCLK SCLK REF
50V 50V 50V +80-20% FS0 HCLK_CPU (4)
2
54
FS0
1
FS1 55 52 1 2 R592 1 2 R528
FS1 CPUCLKT0
1
R44 R50 FS2 40 49 0603 133 2 R599 0603 49.9
1 1% 2 R598 C616 C637
1K 1K 0603 R5971K FS2 CPUCLKT1 0603 133
45 2 R608 0603 49.9
1 1% 2 R563 10P/NA 10P/NA
R528,R529 AS CLOSE AS PISSOBLE TO CPU
0603 0603 +3VS CPUCLKT2 0603 33 0603 49.9 1% 0603 0603
1 2 25
*PD#
2 R594 2 R529 10% 10%
2
34 51 1 1
PCI_STOP# CPUCLKC0 0603 133 2 R603 0603 49.9 1% 2 R602
2
53 48 1 R563,R560 AS CLOSE AS PISSOBLE TO MCH (NB)
CPU_STOP#* CPUCLKC1 0603 133
44 2 R612 0603 49.9
1 1% 2 R560
8.2K 1 CPUCLKC2
2 R618 43 0603 33 0603 49.9 1%
+3VS 0603 -VTT_PWRGD MULTSEL0* R607
28 10 1 2 PCICLK_CARD (15)
+3VS +3VCLKANA VTT_PWRGD# PCICLK0 0603 133 R610
11 2 PCICLK_LAN (16)
L518 +3VCLKANA PCICLK1 0603 133 R609
1 12 2 PCICLK_LPC (18)
VDDREF PCICLK2 0603 133 R616
1 2 37 13 2 PCICLK_ICH (13)
120Z/100M VDD48 PCICLK3 0603 133
26 16 TP550
2012 +3VCLK66 VDDA PCICLK4
19 17 1
VDD3V66_0 PCICLK5 TP544
1
C645 C642 C644 C643 C649 32 18 1 TP543

VDD3V66_1 PCICLK6
0.1U 0.1U 0.1U 0.1U 2.2U
0603 0603 0603 0603 0805 +3VCLKCPU 46
VDDCPU0
1
50V 50V 50V 50V +80-20%
2
50 5 1 TP551 C627 C628 C629 C671

VDDCPU1 PCICLK_F0
6 1 TP34 10P/NA 10P/NA 10P/NA 10P/NA
+3VCLKPCI PCICLK_F1 0603 0603 0603 0603
8 7 1
VDDPCI0 PCICLK_F2 TP552 10% 10% 10% 10%
2
14
VDDPCI1
4 21 1 2 R621 66M_MCH66IN (7)
CPU_CORE +3VS GND0 66MHZ_OUT0/3V66_2 0603 133
9 22 2 R620 66M_ICH (13)
GND1 66MHZ_OUT1/3V66_3 0603 133
15 23 2 R626 66M_AGP (10)
GND2 66MHZ_OUT2/3V66_4 0603 33
20
GND3
1
27 33 1
GND4 3V66_0 TP553
1
R628 31 24 1 C639 C635 C640
GND5 66MHZ_IN/3V66_5 TP38
1
+3VS +3VCLK66 10K 36 10P/NA 10P/NA 10P/NA

L519 R630 0603 GND6 0603 0603 0603
41
10K_DFS GND7 10% 10% 10%
2
1 2 47 42
120Z/100M 0603 GND8 IREF
2
2012 -VTT_PWRGD ICS950805

1
1
2
C641 C648 C647 C646 R01 GNDCPU TSSOP56

0.1U 0.1U 0.1U 2.2U R619
0603 0603 0603 0805 3 475
50V 50V 50V +80-20% R1 Q508 0603
2
2
1DTC144TKA 1%
2
GNDCPU
MTG1 MTG2
MTG/ID2.2/OD5.6 MTG/ID2.2/OD5.6
MTG17 MTG28 MTG7 MTG8 MTG9 MTG10 MTG11 MTG12 MTG13 FD1 FD2 FD3 FD4
MTG3 MTG4 MTG5 ID2.8/OD6.0 ID2.8/OD6.0 ID3.2/OD6.0 ID3.2/OD6.0 ID3.2/OD6.0 ID3.0/OD6.0 ID3.0/OD6.0 ID3.0/OD6.0 ID3.0/OD6.0 FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
1
ID2.8/OD7.6 ID2.8/OD6.5 ID2.8/OD7.6

3
2
1
3
2
1
3
2
1
2 7 2 7
4 12 4 12 4 12
1
5 11 5 11 5 11
3 6 3 6 6 10 6 10 6 10
AGND FD502 FD501 FD500 FD503
FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
4
7
8
9
7
8
9
7
8
9
E4 E500 E1 E2 E501 E3
1
TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL9 TOUCHPAD_METAL8 1
1
MTG15
1
MTG14 ID2.8/OD6.0
ID2.8/OD7.6
3
2
1
3
2
1
TP_GND TP_GND 13
4 12 4 12 MTG16 E5 E502 E504 E503 E505 E506
2
5 11 5 11 ID2.8/OD6 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8

MTG18 6 10 6 10 3 8
MTG19 MTG/ID2.2/OD5.6
MTG/ID2.2/OD5.6 4 7
7
8
9
7
8
9
1
5
6
1
8
1
2 7 E6 E507 E508 E509 E510 E511

2 7 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL9 TOUCHPAD_METAL9 TOUCHPAD_METAL8
MTG21 MTG22
3 6 ID2.8/OD7.6 ID2.8/OD7.6 GND_16
3
2
1
3
2
1
3 6
1
1
4 12 4 12
4
5 11 5 11
MTG20
4
6 10 6 10
ID5.0/OD7.6
E7 E512 E513 E514 E515
7
8
9
7
8
9
TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL9 TOUCHPAD_METAL5 TOUCHPAD_METAL5

1
1
TP_GND
TP_GND
AGND
Title
Clock Generator,Screw holes
Size Rev
R01 FOR EMI ISSUE Document
Custom 02
Number 411671200001
A B
A B
SYSTEM MEMORY
SO-DIMM Module
R01 +3V +3V
MA[0..14]
(7) MA[0..14]
Close to SO-DIMM Module
J503
J505 1 2 +3V
MA6 MAA6 1 2
9 8 1 2 MDD0 3 4 MDD32
MA7 MAA7 3 4
10 7 MDD0 3 4 MDD32 MDD1 5 6 MDD33
MA4 MAA4 RP7 5 6
2
11 6 MDD1 5 6 MDD33 MDD2 7 8 MDD34 2
7 8
1
MA1 12 5 MAA1 0*8_DFS MDD2 7 8 MDD34 MDD3 9 10 MDD35 C100 C106 C112 C102
MA2 MAA2 RPX8 9 10
13 4 MDD3 9 10 MDD35 11 12 10U/NA 10U/NA 10U/NA 10U/NA
MA0 MAA0 11 12 1206 1206 1206 1206
14 3 11 12 MDD4 13 14 MDD36
13 14 16V 16V 16V 16V
2
15 2 MDD4 13 14 MDD36 MDD5 15 16 MDD37
15 16
16 1 MDD5 15 16 MDD37 MDD6 17 18 MDD38
MA11 MAA11 17 18
9 8 MDD6 17 18 MDD38 MDD7 19 20 MDD39
MA12 MAA12 19 20
10 7 MDD7 19 20 MDD39 21 22
MA10 MAA10 RP9 21 22
11 6 21 22 -MDQMA0 23 24 -MDQMA4
MA9 MAA9 0*8_DFS 23 24
12 5 -MDQMA0 23 24 -MDQMA4 -MDQMA1 25
25 26
26 -MDQMA5 Close to SO-DIMM Module
MA8 13 4 MAA8 RPX8 -MDQMA1 25 26 -MDQMA5 27 28
MA5 MAA5 27 28 +3V
14 3 27 28 MAA0 29 30 MAA3
MA3 MAA3 29 30
15 2 MAA0 29 30 MAA3 MAA1 31 32 MAA4
31 32
16 1 MAA1 31 32 MAA4 MAA2 33 34 MAA5
-SWEA -MSWEA 33 34
(7) -SWEA 1 16 MAA2 33 34 MAA5 35 36
-CS5 -MCS5 35 36
(7) -CS5 2 15 35 36 MDD8 37 38 MDD40
37 38
1
-SRASA 3 14 -MSRASA RP3 MDD8 37 38 MDD40 MDD9 39 40 MDD41 C110 C103 C111 C104 C114
(7) -SRASA -MSCASA 39 40
-SCASA 4 13 0*8_DFS MDD9 39 40 MDD41 MDD10 41 42 MDD42 0.1U 0.1U 0.1U 0.1U 0.1U
(7) -SCASA -MCS4 41 42
-CS4 5 12 RPX8 MDD10 41 42 MDD42 MDD11 43 44 MDD43 0603 0603 0603 0603 0603
(7) -CS4 43 44 50V 50V 50V 50V 50V
-CS0 -MCS0
2
(7) -CS0 6 11 MDD11 43 44 MDD43 45 46
-CS1 -MCS1 45 46
(7) -CS1 7 10 45 46 MDD12 47 48 MDD44
47 48
8 9 MDD12 47 48 MDD44 MDD13 49 50 MDD45
MD7 MDD7 49 50 +3V
9 8 MDD13 49 50 MDD45 MDD14 51 52 MDD46
MD39 MDD39 51 52
10 7 MDD14 51 52 MDD46 MDD15 53 54 MDD47
MD6 MDD6 RP5 53 54
11 6 MDD15 53 54 MDD47 55 56
MD38 MDD38 0*8_DFS 55 56
12 5 55 56 57 58
MD5 MDD5 RPX8 57 58
13 4 57 58 59 60
59 60
1
MD37 14 3 MDD37 59 60 C109 C115 C116 C113 C118
MD36 15 2 MDD36 0.1U 0.1U 0.1U 4.7U_NA 4.7U_NA
MD4 16 1 MDD4 SDRAMCLK0 61 62 CKE0 0603 0603 0603 0805 0805
MDD11 SDRAMCLK4 CKE2 (7) SDRAMCLK0 61 62 CKE0 (7) 50V 50V 50V +80-20% +80-20%
MD11
2
9 8 (7) SDRAMCLK4 61 62 63 64
MD10 MDD10 CKE2 (7) 63 64 -MSCASA
10 7 63 64 -MSRASA 65 66
MD42 MDD42 RP6 -MSCASA 65 66 CKE1
11 6 -MSRASA 65 66 -MSWE A 67 68
67 68 CKE1 (7)
1
MD43 12 5 MDD43 0*8_DFS -MSWE A 67 68 CKE3 -MCS0 69 70 MAA12
CKE3 (7) 69 70
1
MD9 13 4 MDD9 RPX8 -MCS4 69 70 MAA12 R54 -MCS1 71 72

MD41 MDD41 R59 22 71 72 SDRAMCLK1
14 3 -MCS5 71 72 73 74
MD8 MDD8 22 SDRAMCLK5 0603 73 74 SDRAMCLK1 (7)
15 2 73 74 SDRAMCLK5 (7) 75 76
75 76
1
MD40 MDD40 0603
16 1 Near to 75 76 77
77 78
78
1
MD52 MDD52 R57
2
9 8 77 78 79 80
MD19 MDD19 SO-DIMM R60 79 80 22
2
10 7 79 80 81 82
81 82
1
MD50 11 6 MDD50 RP10 81 82 22 83 84 0603
C107 MDD16 83 84 MDD48
1
MD18 MDD18 0*8_DFS 0603 10P

12 5 C101 MDD16 83 84 MDD48 MDD17 85 86 MDD49
MD17 MDD17 RPX8 0603 85 86
12
13 4 10P MDD17 85 86 MDD49 MDD18 87 88 MDD50
MD49 MDD49 0603 87 88
2
14 3 MDD18 87 88 MDD50 MDD19 89 90 MDD51 C108
MD16 MDD16 89 90
2
15 2 MDD19 89 90 MDD51 91 92 10P

91 92
1
MD48 16 1 MDD48 91 92 C117 MDD20 93 94 MDD52 0603
MD27 MDD27 93 94
Near to
2
9 8 MDD20 93 94 MDD52 10P MDD21 95 96 MDD53
MD60 MDD60 0603 95 96 +5V
MD25
10 7
MDD25
MDD21 95 96 MDD53 Near to MDD22 97
97 98
98 MDD54 SO-DIMM
RP12 Near to
2
11 6 MDD22 97 98 MDD54 MDD23 99 100 MDD55
MD26 12 5 MDD26 0*8_DFS MDD23 99 100 MDD55
SO-DIMM 101
99 100
102
MD58 13 4 MDD58 RPX8 101 102
SO-DIMM MAA6 103
101 102
104 MAA7
103 104
1
MD24 14 3 MDD24 MAA6 103 104 MAA7 MAA8 105 106 MEM_BS0
MDD57 105 106 MEM_BS0 (7)
MD57 15 2 MAA8 105 106 MEM_BS0 107 108 R51
MDD22 MEM_BS0 (7) 107 108 10K
MD22 16 1 107 108 MAA9 109 110 MEM_BS1
MDD2 109 110 MEM_BS1 (7) 0603
MD2 1 16 MAA9 109 110 MEM_BS1 MAA10 111 112 MAA11
MDD34 MEM_BS1 (7) 111 112
MD34 2 15 MAA10 111 112 MAA11 113 114
MD3 MDD3 113 114
2
3 14 113 114 -MDQMA2 115 116 -MDQMA6
MD35 MDD35 RP4 115 116
4 13 -MDQMA2 115 116 -MDQMA6 -MDQMA3 117 118 -MDQMA7
MD1 MDD1 0*8_DFS 117 118
5 12 -MDQMA3 117 118 -MDQMA7 119 120
MD33 MDD33 RPX8 119 120
6 11 119 120 MDD24 121 122 MDD56
MD0 MDD0 121 122
7 10 MDD24 121 122 MDD56 MDD25 123 124 MDD57 3
MD32 MDD32 123 124 Q6 R1
8 9 MDD25 123 124 MDD57 MDD26 125 126 MDD58 2 DRAMENA (13)
MD15 MDD15 125 126 DTC144TKA1
9 8 MDD26 125 126 MDD58 MDD27 127 128 MDD59
MD47 MDD47 127 128
10 7 MDD27 127 128 MDD59 129 130
MD46 MDD46 RP8 129 130
11 6 129 130 MDD28 131 132 MDD60
MD14 MDD14 0*8_DFS 131 132
12 5 MDD28 131 132 MDD60 MDD29 133 134 MDD61
MD13 MDD13 RPX8 133 134
13 4 MDD29 133 134 MDD61 MDD30 135 136 MDD62
MD45 MDD45 135 136
14 3 MDD30 135 136 MDD62 MDD31 137 138 MDD63
MD12 MDD12 137 138
15 2 MDD31 137 138 MDD63 139 140
MD44 MDD44 SMBDATA0 139 140 SMBCLK
16 1 139 140 141 142
MD56 MDD56 SMBDATA1 SMBCLK 141 142 SMBCLK (8,13)
9 8 141 142 143 144
MD23 MDD23 SMBCLK (8,13) 143 144
10 7 143 144
MD55 11 6 MDD55 RP11 DIMM144P/0.8MM/H4
MD53 12 5 MDD53 0*8_DFS AMP 1123693-1
DIMM144P/0.8MM
MD54 13 4 MDD54 RPX8
G
MD21 14 3 MDD21
MD51 15 2 MDD51 G
MD20 16 1 MDD20
MD31 9 8 MDD31
MDD63
BANK2/3 BANK0/1 SMBDATA0 S D D S SMBDATA1
MD63
S
D
10 7
D
S
MD30 11 6 MDD30 RP13 NO SUPPORT ECC FUNCTION NO SUPPORT ECC FUNCTION
2
MD62 12 5 MDD62 0*8_DFS Q8
MD61 13 4 MDD61 RPX8 R168 Q7 2N7002 R169
1 MD29 14 3 MDD29 FDV302P 1
MD28 MDD28 100K SOT23_FET 100K

15 2
MDD59 0603 R01 0603
MD59 16 1
1
MD[0..63]
(7) MD[0..63]
R02 R02
1 16 -MDQMA4
-MDQMA5 SMBDATA (8,13)
2 15
3 14 -MDQMA2 RP14
4 13 -MDQMA6 0*8_DFS
5
6
12
11
-MDQMA3
-MDQMA7
RPX8 Layout Note: Layout Note:
7 10 -MDQMA0
8 9 -MDQMA1
SDRAMCLK0,1,4,5 as don't over 2 vias as possible
Trace Width 5mils Trace Width 5mils

Trace Spacing 12mils Trace Spacing 12mils
Group Spacing (spacing from other signal groups) 12mils Group Spacing (spacing from other signal groups) 12mils
-SCS[0..11],SCKE[0..7] -SCS[0..11],SCKE[0..7]
SMA[0..12],SBS]0..1] SMA[0..12],SBS]0..1]
Data signals
Data signals SRAS#,SCAS#,SWE# SRAS#,SCAS#,SWE#
MCH DIMM1 DIMM2 MCH DIMM1 DIMM2
Title
2"<L1<4" 0.4"<L2<0.6" 2"<L1<3" 0.4"<L2<0.6" SO-DIMM Memory X 2
Size Document Rev

411671200001 02
Number
A B
1 2 3 4 5 6 7 8
GPIO [13:0:] have internal pull-down

GPIO[1:0] - AGP skew straps : allow for the adjustment GPIO[8] - ID disable : left open innormal operation
of the phase between AGP 1X CLK n ad PCICLK.
GPIO[9] - External I2C : Data
GPIO[3:2] - X1CLK_skew straps : allow for the GPIO [10:9] for external
adjustment of the phase between X1CLK and ROM or capture use.
GPIO[10] - External I2C : CLK
X2CLK.
GPIO[6:4] - Bus configuration straps : This straps are GPIO[13:11] - ROMIDCFG Straps :If the graphic subsystem
controlling the bus type, the clock PLL select nd
a the IDSEL. has no ROM attached, these straps serve for controlling the
A
Default is [000] - AGP 4X. chip ID. A
GPIO[7] - VGA disable : default position is 0 .e.

(i VGA
enable)
M6
MEMORY
AGP_AD[0..31] U516A U516B
(7) AGP_AD[0..31] AGP_AD0 D24 Y2 1 A26 B13
AGP_AD1 AD0 GPIO0 TP515 DQ0 MA0
C26 Y1 1 TP516 B25 A13
AGP_AD2 AD1 GPIO1 DQ1 MA1
D25 W3 1 A25 C12
D26 W2 1 A24 B12
E23 W1 1 B23 A12
E25 V4 1 TP529 A23 D11
E24 V3 1 TP519 C22 C11
E26 V2 B22 B11
F26 V1 C21 A11
G23 U3 B21 C10
AD9 GPIO9 DQ9 MA9
ZV PORT/ EXT TMDS/ GPIO/

AGP_AD10 G25 U2 A21 B10
G24 U1 D20 A10
G26 T4 C20 D9
AGP_AD13 AD12 GPIO12 ZV_Y[0..7] DQ12 MA12
H24 T3 ZV_Y[0..7] (15) B20 C9
H26 A20
AGP_AD15 AD14 ZV_Y0 DQ14
H25 AA4 C19 A22
AGP_AD16 AD15 ZV_LCDDATA0 ZV_Y1 DQ15 DQM#0
L23 AB1 B18 D21
L26 AB2 A18 A16
L24 AB3 C17 C15
M26 AB4 B17 F2
M24 AC1 A17 G1
AGP_AD21 AD20 ZV_LCDDATA5 ZV_Y6 ZV_UV[0..7] DQ20 DQM#5
N25 AC2 ZV_UV[0..7] (15) D16 N2
+3VS AGP_AD22 AD21 ZV_LCDDATA6 ZV_Y7 DQ21 DQM#6
M25 AC3 C16 N3
AGP_AD23 AD22 ZV_LCDDATA7 ZV_UV0 DQ22 DQM#7
N26 AD1 B16
AGP_AD24 AD23 ZV_LCDDATA8 ZV_UV1 DQ23
P23 AD2 B15 A19
R546 1 20K -STP_AGP AD24 ZV_LCDDATA9 ZV_UV2 DQ24 QS0
2 0603 AGP_AD25 P26 AD3 A15 B19
AGP_AD26 AD25 ZV_LCDDATA10 ZV_UV3 DQ25 QS1
P24 AE1 D14 D18
R25 AE2 C14 C18
R545 1 20K -AGP_BUSY AD27 ZV_LCDDATA12 ZV_UV5 DQ27 QS3
2 0603 AGP_AD28 R24 AF1 B14 J4
R26 AF2 A14 K1
T23 AF3 D13 K2
B R538 1 20K -M6_SUS_STAT AD30 ZV_LCDDATA15 DQ30 QS6 B
2 0603 AGP_AD31 T25 AE3 1 C13 K3
-AGP_CBE[0..3] AD31 ZV_LCDDATA16
AF4 1
TP506
B1
DQ31
MEMORY QS7
ROM
(7) -AGP_CBE[0..3] -AGP_CBE0 ZV_LCDDATA17 TP507 DQ32
F23 AE4 1 C1 A9
-AGP_CBE1
-AGP_CBE2
J25
C/BE#0
C/BE#1
ZV_LCDDATA18
ZV_LCDDATA19
AD4 1
TP503
TP502
C2
DQ33
DQ34
INTERFACE RAS#
L25 AF5 1 D1 C8
-AGP_CBE3 C/BE#2 ZV_LCDDATA20 TP508 DQ35 CAS#
N23 AE5 1 TP504 D2
C/BE#3 ZV_LCDDATA21 DQ36
PCI/AGP
ZV_LCDDATA22
AD5 1 TP10 ZV_LCDDATA [23:0:] have internal pull-down E1
DQ37 WE#
D8
66M_AGP AA26 AC5 1 E2
(8) 66M_AGP -PCIRST PCICLK ZV_LCDDATA23 TP13 DQ38
(7,13,16,18) -PCIRST
AA23
RST# ZV_LCDDCNTL [3:0:] have internal pull-down F1
DQ39 CS#0
B9
-AGP_REQ AA25 Y4 ZV_SYNC G2
(7,14) -AGP_REQ REQ# ZV_LCDCNTL0 ZV_HREF ZV_SYNC (15) DQ40
ATI Advice. -AGP_GNT Y24 AA1 G3 B8
(7,14) -AGP_GNT GNT# ZV_LCDCNTL1 ZV_HREF (15) DQ41 CS#1
AGP_PAR J23 AA2 1 H1 8M DDR use R586, R590(M6-M)
-AGP_STOP R572 0 0603 (7) AGP_PAR -M6_STOP PAR ZV_LCDCNTL2 ZV_PCLK TP513 DQ42
1 2 J24 AA3 ZV_PCLK (15) H2 A8
(7,14) -AGP_STOP -AGP_DEVSEL R573 -M6_DEVSEL STOP# ZV_LCDCNTL3 DQ43 CKE
1 0_DFS 2 0603 J26 H3 16M DDR use R586, R590, R585, R589(M6-D)
(7,14) -AGP_DEVSEL -AGP_TRDY R564 -M6_TRDY DEVSEL# TXOUT0- DQ44
1 0_DFS 2 0603 K24 AC8 J1 Y3
(7,14) -AGP_TRDY -AGP_IRDY -M6_IRDY TRDY# TXOUT_L0N TXOUT0+ TXOUT0- (12) DQ45 ROMCS#
(7,14) -AGP_IRDY
R568 1 0_DFS 2 0603 R01 K26
IRDY# TXOUT_L0P
AD8 TXOUT0+ (12) J2
DQ46
-AGP_FRAME R567 1 0 2 0603 -M6_FRAME K25 AC9 TXOUT1- J3 A6 R586 1 33 2 0603
(7,14) -AGP_FRAME -PCI_INTA FRAME# TXOUT_L1N TXOUT1+ TXOUT1- (12) DQ47 CLK0
AA24 AD9 L1 A7
(13,14,15) -PCI_INTA INTA# TXOUT_L1P TXOUT2- TXOUT1+ (12) DQ48 CLK0_IN
AE8 L2
-AGP_SERR TXOUT_L2N TXOUT2+ TXOUT2- (12) DQ49 R590 33 0603
W24 AF8 L3 B6 1 2
(14) -AGP_SERR SERR# TXOUT_L2P TXOUT2+ (12) DQ50 CLK0#
AC10 1 TP15 L4 B7
-STP_AGP TXOUT_L3N DQ51 CLK0#_IN
AB25 AD10 1 TP11 M1
-AGP_BUSY STP_AGP# TXOUT_L3P TXCLK- DQ52 R585 33 0603
AB26 AE9 M2 A4 1 2
-AGP_RBF AGP_BUSY# TXCLK_LN TXCLK+ TXCLK- (12) DQ53 CLK1
W26 AF9 M3 A5
(7,14) -AGP_RBF RBF# TXCLK_LP TXCLK+ (12) DQ54 CLK1_IN
LVDS
AGP_ADSTB0 F25 AD11 TX2OUT0- N1
(7,14) AGP_ADSTB0 AGP_ADSTB1 AD_STB0 TXOUT_U0N TX2OUT0+ TX2OUT0- (12) DQ55 R589 33 0603
(7,14) AGP_ADSTB1 P25 AC11 TX2OUT0+ (12) N4 B4 1 2
AGP_SBSTB AD_STB1 TXOUT_U0P TX2OUT1- DQ56 CLK1#
V25 AE11 P1 B5
AGP2X
(7,14) AGP_SBSTB
AGP_SBA[0..7] SB_STB TXOUT_U1N TX2OUT1+ TX2OUT1- (12) DQ57 CLK1#_IN
(7) AGP_SBA[0..7] TXOUT_U1P
AF11
TX2OUT1+ (12)
P2
DQ58 R01
AGP_SBA0 W25 AD12 TX2OUT2- P3 B3
AGP_SBA1 SBA0 TXOUT_U2N TX2OUT2+ TX2OUT2- (12) DQ59 CLKFB
V24 AC12 P4
AGP_SBA2 SBA1 TXOUT_U2P TX2OUT2+ (12) DQ60
V26 AD13 1 TP12 R1 T2 +AGP_MEM_REF
AGP_SBA3 SBA2 TXOUT_U3N DQ61 VREF
V23 AE13 1 R2
AGP_SBA4 SBA3 TXOUT_U3P TX2CLK- TP554 DQ62 R19 4.7K 2 0603
U26 AE12 R3 T1 1 +1.8VS
AGP_SBA5 SBA4 TXCLK_UN TX2CLK+ TX2CLK- (12) DQ63 MEMVMODE
U24 AF12
AGP_SBA6 SBA5 TXCLK_UP TX2CLK+ (12)
T26 MOBILITY-M6
AGP_SBA7 SBA6 LCD_ID0 Connect to VDDC(1.8V) for VDDR 2.5V
T24 AD7 LCD_ID0 (12) BGA420_64_1MM
SBA7 LTGIO0 LCD_ID1 Pin has internal pulldown for default of VDDR 3.3V
AD6
AGP_ST0 LTGIO1 LCD_ID2 LCD_ID1 (12)
(7,14) AGP_ST0 Y26 AC7
AGP_ST1 ST0 LTGIO2 LCD_ID2 (12)
(7,14) AGP_ST1 Y23
AGP_ST2 ST1 ENPVDD
(7,14) AGP_ST2 Y25 AB10
ST2 DIGON -ENABKL ENPVDD (12) DIGON->Controls Panel Digital Power On/Off
AB9
C -AGP_SBSTB BLON# BLONb->Control Backlight On/Off C
U25
(7,14) -AGP_SBSTB -AGP_ADSTB0 SB_STB#
F24 AE19
DAC2 AGP4X
(7,14) -AGP_ADSTB0 -AGP_ADSTB1 ADSTRB0# TX0M

N24 AF19
(7,14) -AGP_ADSTB1 ADSTRB1# TX0P
AE20
+3VS AGP_VREF TX1M
B26 AF20
TMDS
R581 47 0603 AGP_VREF AGPREF TX1P

1 2 C25 AE21
AGPTEST TX2M
AF21
TX2P
AE18
TXCM
1
C574 R533 1 845 2 0603 AE16 AF18

R2SET TXCP +5VS
0.1U
0603 AF16 AD20 DVIDDCCLK & DVIDDCDATA
50V (22) TV_CRMA C_R DVIDDCCLK VDDR_MEM2.5
2
AF15 AC20 have internal pull-down

(22) TV_LUMA Y_G DVIDDCDATA
1
U503 AF14
SSOUT (22) TV_COMP COMP_B R22
1 8 AE14 AD21
CLKIN VDD (22) CSYNC H2SYNC HPD
1
2 7 1 AF13 10K
MRA SR0 SSIN TP510 V2SYNC 0603
1 3 6 AF24 R25
TP511 SR1 MODOUT R RED (12) 1K
4
VSS SSON
5 1 CRT2DDCCLK & CRT2DDCDATA TP509 1 AF6
CRT2DDCCLK G
AF23 GREEN (12)
TP512 0603
2
have internal pull-down TP505 1 AF7 AF22 BLUE (12)
CRT2DDCDATA B 1%
P2040B AE24
HSYNC HSYNC (12) ENPBLT (22)
2
SO8 AE23 VSYNC (12)
SSIN VSYNC
AE6
CLK SSC
DAC1
SSIN
3
R01 SSOUT AE7 AE22 R14 1 499 2 0603 1%
SSOUT RSET +AGP_MEM_REF
AD24 Internal DAC reference 2 2 -ENABKL
MONID0 (13) -ENABKL_MSK
1
AD25
MONID1
1
AF25 DTC144WK DTC144WK C60 R20
XTALIN Q12 Q3 1K
AC26 SDA (12) 0.01U
VGADDCDATA 0603 0603
AF26 AC25 SCL (12)
+1.5VS XTALOUT VGADDCCLK 1%
2
-M6_SUS_STAT
2
R534 AE25 1 2 -SUS_STAT (13,18)
SUS_STAT# R539 0_DFS 0603
AC6
TESTEN
1 2 AC221
AUXWIN TP14 R01
2
1M Special output pin for Apple

R33 AGP_VREF 0603D R11 MOBILITY-M6 monitor
1K BGA420_64_1MM
1K 0603
0603
X500
1%
1
AGP_VREF (7) 1 3
2
2
C556 4 C559
1
D R35 C78 C76 18P 27MHZ 18P D

0.1U 0.1U 25V 25V
1K 0603 0603 0603D 10%
2
0603 50V 50V 10% 0603D

2
1%
1
Place near MCH Place near AGP
Title
VGA-M6(1/2)
Size Document Rev

Custom 411671200001 02
Number
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.8VS
+1.8VS VDD_DAC1.8
L6
U516C 1 2 (AVDD 90MA)
E5 AB11
VSS_0 VDDC_0
1
C3 H5 120Z/100M C48 C51 C50
VSS_1 VDDC_1 1608
B2 K5 4.7U 0.1U 0.1U
VSS_2 VDDC_2 0805 0603 0603
A1 M5
VSS_3 VDDC_3
1
+80-20% 50V 50V
2
D D4 R5 C63 C53 C68 C67 D
VSS_4 VDDC_4
T10 U5 0.1U 0.1U 1U 22U
VSS_5 VDDC_5 0603 0603 0603 1210
T11 W5
VSS_6 VDDC_6 50V 50V 10V VDD_PNLIO1.8
2
T12 AB8
VSS_7 VDDC_7 L7 (TXVDDR 40MA)
T13 AB14
VSS_8 VDDC_8 (LVDDR 40MA)
T14 AB7 1 2
VSS_9 VDDC_9
T15
VSS_10 VDDC_10
AB17 PLACE CLOSE TO M6-M
1
T16 AB19 120Z/100M C42 C41 C43
VSS_11 VDDC_11 1608
T17 W22 4.7U 0.1U 0.1U
VSS_12 VDDC_12 0805 0603 0603
K10 U22
VSS_13 VDDC_13 +80-20% 50V 50V
2
K11 R22
VSS_14 VDDC_14
K12
VSS_15 VDDC_15
M22 Select 3.3V or 2.5V to match
K13 K22
K14
VSS_16 VDDC_16
H22 internal memory core VDD
VSS_17 VDDC_17
K15 E19
VSS_18 VDDC_18
K16 E17
VSS_19 VDDC_19
K17 E15
VSS_20 VDDC_20 0
L10 E12 1 2 +3VS
VSS_21 VDDC_21
L11 E10
VSS_22 VDDC_22 R160 1210
L12 E8
VSS_23 VDDC_23
L13 AB12
VSS_24 VDDC_24
L14
VSS_25 0/NA 2
L15 D10 1 VDDR_MEM2.5
VSS_26 VDDM_0
L16 C7
VSS_27 VDDM_1 R694 1210
L17
VSS_28 VDDM_2
C23 RO1
1
M10 D12 C71 C70 C77 C73
VSS_29 VDDM_3
M11 D17 0.1U 0.1U 1U 22U
VSS_30 VDDM_4 0603 0603 0603 1210
M12 E3
VSS_31 VDDM_5 50V 50V 10V +1.8VS VDD_PLL1.8
2
M13 F4
VSS_32 VDDM_6 L507
M14
VSS_33
M15 B24 1 2
VSS_34 VDDQM_0
M16
VSS_35 VDDQM_1
F3 PLACE CLOSE TO M6-M
1
M17 D6 120Z/100M C569 C568
VSS_36 VDDQM_2 +12VS 1608
N10 C6 U505 4.7U 0.1U
VSS_37 VDDQM_3 0805 0603
N11 D15 AO4400
VSS_38 VDDQM_4 L510 +80-20% 50V
2
N12 D19 SO8
VSS_39 VDDQM_5
N13 D22 1 2
VSS_40 VDDQM_6 VDDR_MEM2.5
N14 G4 8
VSS_41 VDDQM_7 0_DFS
N15 7 3
VSS_42 +3V 0603D_DFS
N16 E6 6 2 VDDR_MEM2.5 VDD_PLL1.8_GND
VSS_43 VDDR1_0
N17 E7 5 1
VSS_44 VDDR1_1
D
P10 E9 1A
S
VSS_45 VDDR1_2
1
C C
R01
G
P11 E11 C605 C64 C66 C61
P12
VSS_46
VSS_47
CORE VDDR1_3
VDDR1_4
E13 0.1U
0603
0.1U
0603
1U
0603
22U
1210
R587
4.99K
4
P13 E14 1 2
VSS_48
& I/O VDDR1_5 50V 50V 10V 0603
2
P14 E16
VSS_49 VDDR1_6
2
P15 E18 R591 C611 1%
VSS_50 VDDR1_7
1
POWER C613 4.7K 470P C608 C604
2
P16 E20
VSS_51 VDDR1_8 10U 0603 0603 10U 0.1U
P17
VSS_52 VDDR1_9
E21 PLACE CLOSE TO M6-M 1206 1206 0603
1
R10 G5 1
VSS_53 VDDR1_10
2
R11 H4
VSS_54 VDDR1_11 Q505 +1.8VS VDD_PNLPLL1.8
R12 J5
VSS_55 VDDR1_12
1
SCK431LCSK-.5 L4
3
R13 K4
VSS_56 VDDR1_13 SOT23N R588
R14 L5 1 2
VSS_57 VDDR1_14 4.7K_1%
R15 M4
VSS_58 VDDR1_15
1
R16 N5 0603 120Z/100M C35 C37 C38
VSS_59 VDDR1_16 1608
R17 P5 4.7U 0.1U 0.1U
VSS_60 VDDR1_17 0805 0603 0603
2
U10 R4
VSS_61 VDDR1_18 +3VS L5 +80-20% 50V 50V
2
U11 D7
VSS_62 VDDR1_19
U12 1 2
VSS_63
U13
VSS_64 0_DFS
U14 T5
VSS_65 VDDR3_0 0603D_DFS
U15 U4 VDD_PNLPLL1.8_GND
VSS_66 VDDR3_1
U16 V5
VSS_67 VDDR3_2
1
1
U17 W4 C47 C52 C44 C49
VSS_68 VDDR3_3
C4
VSS_69 VDDR3_4
Y5 0.1U 0.1U 1U 22U R01
D3 AA5 0603 0603 0603 1210
VSS_70 VDDR3_5 50V 50V 10V
2
2
E4 AC4
VSS_71 VDDR3_6
F5 AB5
VSS_72 VDDR3_7
D5 AB6
VSS_73 VDDR3_8
VDDR3_9
AB15 PLACE CLOSE TO M6-M
AE26 AB16
VDD_PLL1.8 PVDD VDDR3_10 +1.8VS VDD_MEMPLL1.8
AD26 AB18
PVSS VDDR3_11 L514
AB20
VDDR3_12
AC13 AB21 1 2
VDD_PNLIO1.8 LVDDR_0 VDDR3_13
AD14 AB22
LVDDR_1 VDDR3_14
1
AB13 AC17 120Z/100M C610 C606 C602
LVSSR_0 VDDR3_15 1608
AC14 AC23 4.7U 0.1U 0.1U
VDD_PLL1.8_GND LVSSR_1 VDDR3_16 0805 0603 0603
AC24
VDDR3_17 +1.5VS L515 +80-20% 50V 50V
2
AE10
LPVDD
AF10 1 2
LPVSS
AC19 E22 0_DFS
B TXVDDR_0 VDDP_0 0603D_DFS B
AD19 F22 VDD_MEMPLL1.8_GND
TXVDDR_1 VDDP_1
AD18 G22
TXVSSR_0 VDDP_2
1
AD17 H23 C596 C75 C72 C59

TXVSSR_1 VDDP_3
AC18
TXVSSR_2 VDDP_4
J22 0.1U 0.1U 1U 22U R01
K23 0603 0603 0603 1210
VDDP_5 50V 50V 10V
2
AE17 L22
VDD_PNLPLL1.8 TPVDD VDDP_6
AF17 M23
TPVSS VDDP_7
N22
VDDP_8
VDD_DAC2.5
AD16
A2VDD VDDP_9
P22 PLACE CLOSE TO M6-M VDDR_MEM2.5
AD15 R23
A2VDDQ VDDP_10 VDD_DAC2.5
AC15 T22
VDD_PNLPLL1.8_GND A2VSSN_0 VDDP_11 L506
AC16 U23
A2VSSN_1 VDDP_12
AE15 V22 1 2
A2VSSQ VDDP_13
W23
VDDP_14
1
AD23 Y22 120Z/100M C561 C560
VDD_DAC1.8 AVDD VDDP_15 1608
AD22 AA22 4.7U 0.1U
AVSSN VDDP_16 0805 0603
AC21 AB23
AVSSQ VDDP_17 +80-20% 50V
2
AB24
VDDP_18
A2 D23
VDD_MEMPLL1.8 MPVDD VDDP_19
A3 C24
MPVSS VDDP_20 VDD_MCLK2.5
L11
C5
VDD_MCLK2.5 VDDRH
1 2
MOBILITY-M6
VDD_MEMPLL1.8_GND BGA420_64_1MM 120Z/100M
1
1608 C79 C74
4.7U 0.1U
0805 0603
+80-20% 50V
2
A A
Title
VGA-M6(2/2)
Size Document Rev

411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
LCD & CRT INTERFACE LED INDICATOR
D15 D13 D14

NUM CAP SCROLL (NA D13,D14,D15,R157
,R683,R684 For LCD 15")
1
C713 C712 C711 +5VS
1U/NA 1U/NA 1U/NA
0603 0603 0603
1
R157 R683 R684
470 470 470
D (17,19) -SCROLL
(17,19) -NUM
(17,19) -CAP
0603 0603 0603
D
2
D15
K A PG1102W
LCD ID SELECT D13
D14
K A PG1102W
DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 K A PG1102W
UNIPAC 0 0 1
HYUNDAI 0 1 0 LED_DATA 1
U514
3
+5VAS
-SCROLL
(19) LED_DATA A QA
74VHC164
HANNSTAR 0 1 1 2
B QB
QC
QD
4
5
6
-NUM
-CAP
-AC_POWER
Unipac(SXGA) 1 0 0 (19) LED_CLK
LED_CLK 8
CLK
QE
QF
QG
10
11
12
-BATT_LED
-BATT_R
-AC_POWER (22)
-BATT_LED (22)
-BATT_R (22)
-H8_RESET 9 13 -BATT_G
HannStar(SXGA) 1 0 1 (19) -H8_RESET
7
CLR
GND
QH
VCC
14
-BATT_G (22)
HannStar(XGA)15" 1 1 0
1
74VHC164 C714 C719
TSSOP14 0.1U 1U
0603 0603
Sumsung(SXGA+)15" 1 1 1 50V R01
2
LCD CONNECTOR
LCD 14" 330mA,15"800mA Q500 AO4400 SO8
C LCDVCC 1
J2
2 LCDVCC
120Z/100M 2012
L505 1 2 2
F502
1 3
8
7
+3VS
C
3 4 Close to LCD Connector 2 6
5 6 mircoSMDC110 1 5
D
TX2CLK+ TXCLK+
S
(10) TX2CLK+ 7 8 TXCLK+ (10) CLOSE TO NDS 9410
G
TX2CLK- 9 10 TXCLK- C1 C503 C510 C512 C506
(10) TX2CLK- TXCLK- (10)
1
11 12 1000P 0.1U 1000P 10U 0.1U C507 C508
TX2OUT0+ TX2OUT1+ 0603 0603 0603 1206 0603 +12VS
4
(10) TX2OUT0+ 13 14 TX2OUT1+ (10) 0.1U 10U_NA
TX2OUT0- TX2OUT1- 50V 10V 50V 0603 1206
2
(10) TX2OUT0- 15 16 TX2OUT1- (10) 50V 10V
2
17 18 1 2
TX2OUT2+ 19 20 TXOUT0+
(10) TX2OUT2+ TXOUT0+ (10)
TX2OUT2- 21 22 TXOUT0- R501 470K
(10) TX2OUT2- TXOUT0- (10)
23 24 3 Q2 0603
TXOUT2+ 25 26 TXOUT1+ R1 2
(10) TXOUT2+ TXOUT1+ (10)
TXOUT2- 27 28 TXOUT1- 1
(10) TXOUT2- TXOUT1- (10)
29 30 DTC144TKA
LCD_ID0 31 32 1 RP1 8
(10) LCD_ID0 LCD_ID1 +3VS
(10) LCD_ID1 33 34 2 7
LCD_ID2 35 36 3 6 ENPVDD
(10) LCD_ID2 ENPVDD (10)
37 38 4 5
39 40
Internal 10K
4
3
2
1
VIL--->2V GND1 6.8K*4

RP520 GND2 1206
47K*4
1206 MA/20PX2/ST
ACES
R01 87216-4000
5
6
7
8
Layout Note:
+5V
S/W/W/S=12/6/6/12 mils
as short as possible
U500
キキキキキǐキキ
1 8
B +5VS 2 7 B
3 6
1
F501 4 5
+3VS +5VS mircoSMDC110
2
PACDN006/NA SSOP8
2 D2
A
1
DDC2B 1Amp 3
R544 R543 EC11FS2 1
4.7K 4.7K Close to VGA Connector
(40mil-60mil) D500
0603 0603 BAV99_NA 16
K
(10) RED RED 2 L500120Z/100M 1608 GND_CRT15
2
1 1
DDC2B
External VGA Connector

9
(10) GREEN GREEN 1 2 L501120Z/100M 1608 2
W/S=16/12/12/12/16 mils (10) BLUE BLUE
10
1 2 L502120Z/100M 1608 3
11
4
12 J1
5 VGA
G 4 5 13 SUYIN
Q502 3 6 6 7535S-15G2T-05
(10) SDA SDA S D 2 7 14
S
D
1 8 7
15
2N7002 FA500 8
(10) HSYNC HSYNC 120OHM/100MHZ
Close to VGA Connector 17
4
3
2
1
4
3
2
1
4
3
2
1
C501
4
3
2
1
CP506 CP501 CP500 10U_NA

(10) VSYNC VSYNC 22P*4 RP501 22P*4 22P*4 1206
1206 1206 1206 10V JL1
2
75*4
G Q501 1206 1 2
A (10) SCL SCL S D SHORT-SMT3 A
S
D
JL500
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
1 2
2N7002
SHORT-SMT3
GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15

GND_CRT15
Title
LCD & CRT Interface
Size Document Rev

411671200001 02
Number
5 4 3 2 1
5 4 3 2 1
+3V_ICH
CPU_CORE +5V +3VS
1
NC7S32 OR
1
+3V R158 C681 C685
Supply Voltage(Vcc) 2.0V to 6.0V 4.7K 1U 0.1U D10
1
0603 C171 C177 C178 C176 0805C 0603D
16V 50V BAT54
2
U16 1U 0.1U 0.1U 0.1U
-PCIRST 0805C 0603D 0603D 0603D
2
5 1
VCC A 16V 50V 50V 50V
3
(15,16) -PCIRST_N 4 2
Y B D16
3 2V~3.6V 4uA
GND 1K
3 1 1 2
VCC_RTC R69 0603 +5VS
NC7S32
U17A SOT70 BAT54
3
R1 2 -PCIRST_MSK +5VS_ICHREF
1
DTC144TKA R01
1
(15,16) AD[0..31] C703 C706 C122
1
AD0 AA4 D11 -H_A20M C213 0.1U 0.1U 1U
D
AD1 AD0 A20M# -SLP -H_A20M (4) Q15 D
AB4 A12 0.1U 0603 0603 0603
AD2 AD1 CPUSLPA# -H_FERR -SLP (4) 50V 50V
0603D
2
Y4 R22 -H_FERR (4)
AD3 AD2 FERR# -H_IGNNE 50V
2
W5 A11 -H_IGNNE (4)
AD4 AD3 IGNNE# -H_INIT
W4 C12 -H_INIT (4)
AD5 AD4 INIT# H_INTR
Y5 C11
M20
H_INTR (4)
U21
D12
D13
V19
AD6 AD5 INTR H_NMI
K2
AB3 B11 H_NMI (4)
AD7 AD6 NMI -H_SMI U17B
AA5 B12 -H_SMI (4)
AD8 AD7 SMI# -H_STPCLK
AB5 C10
VCCRTC
VCC_CPU1
VCC_CPU2
V5REF1
V5REF2
V5REF_SUS
AD9 AD8 STPCLK# -RCIN -H_STPCLK (4)
Y3 B13 -RCIN (19) E21 -PCS1 (14)
AD10 AD9 RCIN# ICH_A20GATE -PCIRST_MSK PDCS1#
W6 C13 ICH_A20GATE (19) W15 C15 -SCS1 (14)
AD11 AD10 A20GATE H_PWRGD -1394WR GPIO25 SDCS1#
W3 A13 H_PWRGD (4) (15) -1394WR V21 E19 -PCS3 (14)
AD12 AD11 CPUPWRGD -THRM GPIO24 PDCS3#
Y6 HUB_D[0..10] (7) (19) -THRM AA13 D15 -SCS3 (14)
AD13 AD12 HUB_D0 -SUSB THRM# SDCS3#
Y2 A4 (15,19,22) -SUSB W16
AD14 AD13 HL0 HUB_D1 -SUSC SLP_S3#
AA6 B5 (19,22) -SUSC AB18 F20 PDA0 (14)
AD15 AD14 HL1 HUB_D2 PWROK SLP_S5# PDA0
Y1 A5 (19) PWROK R20 F19 PDA1 (14)
AD16 AD15 HL2 HUB_D3 -RSMRST PWROK PDA1
V2 B6 Y16 E22 PDA2 (14)
AD17 AD16 HL3 HUB_D4 -PWRBTN RSM_PWROK PDA2
AA8 B7 (19) -PWRBTN W21 A16 SDA0 (14)
AD18 AD17 HL4 HUB_D5 +1.8VS -WAKE_UP PWRBTN# SDA0
V1 A8 (19) -WAKE_UP AA17 D16 SDA1 (14)
AD19 AD18 HL5 HUB_D6 -RSMRST RI# SDA1
AB8 B8 R21 B16 SDA2 (14)
AD20 AD19 HL6 HUB_D7 VCC_RTC -SUS_STAT RSMRST# SDA2
U4 A9 (10,18) -SUS_STAT Y17
AD20 HL7 SUSSTAT#
2
AD21 W9 C8 HUB_D8 1 SUS_CLK32K AA18 G22
AD22 AD21 HL8 HUB_D9 SMBDATA SUSCLK# PDDREQ PDREQ (14)
U3 C6 R82 TP549 AA16 B18
AD22 HL9 (8,9) SMBDATA SMBDATA SDDREQ SDREQ (14)
2
AD23 Y9 C7 HUB_D10 SMBCLK AB16 F22
AD24 AD23 HL10 40.2 (8,9) SMBCLK -SMB_ALERT SMBCLK PDDACK# -PDACK (14)
U2 C5 1 TP546 R154 AB17 B17
AD25 AD24 HL11 HUB_STB 0603 SMBALERT#/GPIO11 SDDACK# -SDACK (14)
AB9 A6 8.2K G19
AD26 AD25 HL_STB HUB_STB (7) 1% GPIO6 PDIOR# -PDIOR (14)
-HUB_STB 0603D
1
U1 A7 -HUB_STB (7) Y11 D17 -SDIOR (14)
AD27 W10 AD26 HL_STB# -PCI_INTH GPIO6 SDIOR#
A3 (14) -PCI_INTH M4 G21 -PDIOW (14)
AD28 AD27 HLCOMP -INTRUDER PIRQH#/GPIO5 PDIOW#
1
T4 B4 HUB_VREF (7) T19 C17 -SDIOW (14)
AD29 AD28 HUBREF INTRUDER# SDIOW#
Y10 G20 PIORDY (14)
AD30 AD29 -PCI_INTA -RTC_RST PIORDY
T3 P1 -PCI_INTA (10,14,15) T20 A17 SIORDY (14)
AD31 AA10 AD30 PIRQA# -PCI_INTB RTC_VBIAS RTCRST# SIORDY PDD[0..15]
P2 -PCI_INTB (14) T21 PDD[0..15] (14)
AD31 PIRQB# VBIAS
1
-CBE[0..3] P3 -PCI_INTC C195 RTC_X1 U22 H19 PDD0
(15,16) -CBE[0..3] -CBE0 PIRQC# -PCI_INTD -PCI_INTC (14,15) RTC_X2 RTCX1 PDD0 PDD1
AA3 N4 -PCI_INTD (14,16) 0.1U T22 H22
-CBE1 C/BE0# PIRQD# 0603 RTCX2 PDD1 PDD2
AB6 J19
-CBE2 C/BE1# IRQ14 50V 66M_ICH PDD2 PDD3
2
Y8 F21 IRQ14 (14) (8) 66M_ICH D4 J22
-CBE3 C/BE2# IRQ14 IRQ15 14M_ICH CLK66 PDD3 PDD4
AA9 C16 IRQ15 (14) (8) 14M_ICH M19 K21
C/BE3# IRQ15 USBCLK_ICH CLK14 PDD4 PDD5
N20 (8) USBCLK_ICH P20 L20
-DEVSEL APICCLK 0603 1 R152 CLK48 PDD5 PDD6
(14,15,16) -DEVSEL AB7 P22 2 10K M21
-FRAME DEVSEL# APICD0 0603 1 R651 -ACRST PDD6 PDD7
(14,15,16) -FRAME V3 N19 2 10K (16,17) -ACRST V22 M22
-IRDY FRAME# APICD1 SERIRQ ACSYNC R674 1 22 AC_RST# PDD7 PDD8
(14,15,16) -IRDY W8 N21 SERIRQ (14,15,18) (16,17) ACSYNC 2 0603 P19 L22
-TRDY IRDY# SERIRQ ACBITCLK AC_SYNC PDD8 PDD9
(14,15,16) -TRDY V4 (16,17) ACBITCLK R19 L21
C -STOP TRDY# -PCI_REQ0 ACSDOUT R147 1 22 AC_BITCLK PDD9 PDD10 C
(14,15,16) -STOP W1 R2 -PCI_REQ0 (14,15) (16,17) ACSDOUT 2 0603 P21 K22
PAR STOP# REQ0# -PCI_REQ1 ACSDIN AC_SDOUT PDD10 PDD11
(15,16) PAR W2 R3 -PCI_REQ1 (14,16) (17) ACSDIN Y22 K20
-PCIRST PAR REQ1# -PCI_REQ2 MSDIN AC_SDIN0 PDD11 PDD12
(7,10,16,18) -PCIRST AA15 T1 -PCI_REQ2 (14) (16) MSDIN W22 J21
-LOCK PCIRST# REQ2# -PCI_REQ3 SBSPKR AC_SDIN1 PDD12 PDD13
(14) -LOCK AA7 AB10 -PCI_REQ3 (14) (17) SBSPKR N22 J20
-SERR PLOCK# REQ3# -PCI_REQ4 SPKR PDD13 PDD14
(14,15,16) -SERR W7 P4 -PCI_REQ4 (14) (18) LAD[0..3] H21
-PERR SERR# REQ4# -PCI_REQ5 LAD0 PDD14 PDD15
(14) -PERR Y7 L3 -PCI_REQ5 (14) Y12 H20
-PME PERR# REQB#GPIO1/REQ#5 AC_SDIN0 FOR Audio Codec. LAD1 LAD0/FWH0 PDD15 SDD[0..15]
(15,16) -PME Y15 W12 SDD[0..15] (14)
-PCI_REQA PME# -PCI_GNT0 AC_SDIN1 FOR MDC. LAD2 LAD1/FWH1 SDD0
(14) -PCI_REQA M3 M2 -PCI_GNT0 (14,15) AB13 D18
-PCI_GNTA REQA#/GPI0 GNT0# -PCI_GNT1 LAD3 LAD2/FWH2 SDD0 SDD1
1 L2 M1 -PCI_GNT1 (14,16) AB12 B19
TP39 PCICLK_ICH GNTN#/GPIO16 GNT1# -PCI_GNT2 -LDRQ LAD3/FWH3 SDD1 SDD2
(8) PCICLK_ICH W11 R4 -PCI_GNT2 (14) (18) -LDRQ Y13 D19
PCICLK GNT2# -PCI_GNT3 LDRQ0# SDD2 SDD3
T2 -PCI_GNT3 (14) 1 W13 A20
-PCI_INTE GNT3# -PCI_GNT4 TP548 -LFRAME LDRQ1# SDD3 SDD4
(14) -PCI_INTE N3 R1 -PCI_GNT4 (14) (18) -LFRAME AB11 C20
-PCI_INTF GPI02/PIRQE# GNT4# -PCI_GNT5 LFRAME#/FWH4 SDD4 SDD5
(14) -PCI_INTF N2 L4 -PCI_GNT5 (14) AA12 C21
-PCI_INTG GPI03/PIRQF# GNTB#/GPIO17/GNT5# FS0/FWH5 SDD5 SDD6
(14) -PCI_INTG N1 D22
GPI7 GPIO4/PIRQG# USBP0+ SDD6 SDD7
AA11 G2 W17 E20
-SCI GPIO7 LAN_RXD0G2 USBP0- USBP0_P SDD7 SDD8
(19) -SCI Y14 G1 Y18 D21
-EXTSMI GPIO8 LAN_RXD0G3 USBP1+ USBP0_N SDD8 SDD9
(19) -EXTSMI W14 H1 AB19 C22
GPI13 GPIO12 LAN_RXD0G4 USBP1- USBP1_P SDD9 SDD10
AB15
GPIO13 LAN_TXD0
F3 NO MDC NEED PULL DOWN 10K USBP2+
AA19
USBP1_N SDD10
D20
SDD11
-CDROM_RST A15 F2 W18 B20 +3V_ICH +3VS
(14) -CDROM_RST GPIO18 LAN_TXD1 USBP2- USBP2_P SDD11 SDD12
-ENABKL_MSK D14 F1 Y19 C19
(10) -ENABKL_MSK -CDROM_PWRON C14 GPIO19 LAN_TXD2 MSDIN USBP3+ USBP2_N SDD12 SDD13
1 10K 2 AB20 A19
(14) -CDROM_PWRON GPIO20 USBP3_P SDD13
1
-HDD_PWRON L1 G3 R136 0603D USBP3- AA20 C18 SDD14
(14) -HDD_PWRON DRAMENA GPIO21 LAN_CLK USBP3_N SDD14 SDD15
B14 H2 A18 R128
(9) DRAMENA -HDD_RST GPIO22 LAN_RSTSYNC -USBOC0 SDD15
A14 W19 R153 0603D 10K
(14) -HDD_RST -GATE1394 GPIO23 (22) -USBOC0 OC0#
AB14 Y20 U19 1 10K 2 0603
VCCSUS1_8_0
VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS1_8_4
(15) -GATE1394 SPK_OFF GPIO27 -USBOC2 OC1# SMLINK0

AA14 Y21 V20 1 10K 2
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
(17) SPK_OFF GPIO28 (22) -USBOC2 OC2# SMLINK1 VRMPWRGD

VCC3_3_0
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC1_8_0
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
R155 0603D
2
VCCUSB1
VCCUSB2
W20 B15
VCCA1_8
OC3# VRMPWRGD
VCCPX1
VCCPX2
VCCPS2
VCCPS1
U20 1 10K 2
BATLOW/TP0 +3V_ICH
10K/NA R74 0603 K4 R661 0603D
+1.8V_ICH EE_CS
+3VS 1 2 K3 P9
EE_DIN VSS_70
J4 P14
EE_DOUT VSS_69
G18
R18
H18
U18
D10
P18
E18
E17
E16
E15
E14
V17
V18
K19
V14
V15
V16
F18
T18
L19
J3 P13
J18
82801
G5
R5
U5
D2
H5
V5
V6
V7
V8
E5
P5
V9
VRMPWRGD (21)
T5
F5
EE_SHCLK VSS_68
J5
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
BGA288_36_36
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
1
+3V_ICH A1
R650 VSS_0
A10
+3VS 0_DFS VSS_1
AA21
AA22
AB21
AB22
1
M10
M11
M12
M13
M14
AA1
AA2
AB1
AB2
N10
N11
N12
N13
N14
A21
A22
B10
B21
B22
K10
K11
K12
K13
K14
P10
P11
P12
0603
L10
L11
L12
L13
L14
J10
J11
J12
J13
J14
M9
C2
C3
C4
C9
D3
D5
D6
D7
D8
D9
N9
A2
B1
B2
B3
B9
E6
E7
E8
E9
K1
K9
82801
L9
J9
For Vccsus & vccusb pin R100 BGA288_36_36
10K
2
0603
Tr>10mS
1
C682 C127 C128 C129

B -RSMRST
2
4.7U 0.1U 0.1U 0.1U B
+3V_ICH +1.8VS 0805 0603 0603 0603
1
+80-20% 50V 50V 50V C181
2
1
1U
+3VS +3V_ICH 0603D R89 R75
10K/NA 10K/NA
2
0603D 0603D
10K 2 GPI7 10K -PCIRST_MSK
2
1 1 2
R87 0603 R99 0603
1 10K 2 -ENABKL_MSK 1 10K 2 -GATE1394
R129 0603 R97 0603 USBP1+
1 10K 2 -CDROM_RST 1 10K 2 GPI13 USBP1- +5VA
R112
1
0603
10K 2 DRAMENA
R656
1
0603
10K 2 -EXTSMI
USBP3+
USBP3- RTC CIRCUITRY
1
R111 0603 R93 0603 Close to ICH2

1 10K/NA 2 -HDD_RST 1 10K 2 -SCI R689
R110 0603 R94 0603 330K (2.0V~3.3V) R123 0603
1 10K 2 GPIO6 1 10K 2 SPK_OFF 0603 USBP0- 1 22 2 USBP0_0- 66M_ICH
USBP0_0- (22)
1
R86 0603 R96 0603 D509 VCC_RTC

10K 2 -PCIRST 10K 2 -1394WR R131 R130 R126 R125 W/S=6/12 mils 14M_ICH
2
1 1 1
R101 0603 R144 0603 15K 15K 15K 15K 3 R114 0603
1
1 8.2K 2 -THRM 1 8.2K 2 -SMB_ALERT 0603D 0603D 0603D 0603D 2 USBP0+ 1 22 2 USBP0_0+ USBCLK_ICH
USBP0_0+ (22)
1
R90 0603 R118 0603 R159 C650
10K 2 -RCIN 8.2K 2 -WAKE_UP 1M
2
1 1 BAV70LT1 1U
1
1
R120 0603D R117 0603 0603 SOT23N 0603 C197 C187
1
10K 2 ICH_A20GATE 1% R632
2
1 22P 22P
R119 0603D 1K 0603 0603 R77 R654 R662
2
1 8.2K/NA 2 ACSDOUT 0603D R634 15 15 15
2
R150 0603D 1 2 -RTC_RST 0603D 0603D 0603D
2
AC_SDOUT PULL HIGH FOR SAFEMODE. 8.2K 0603D
2
CLOSE ICH2
1
C652
+1.8VS 1U
1
+3V R633 0603 C138 C678 C698
2
1 2 10P 10P 10P

0603D 0603D 0603D
1
8.2K 2 SMBDATA 1K 0603D C651
2
1
1
C131 C126 C130 C155 C690 C699 C150 C170 R107 0603 0.047U Close to ICH2
1
4.7U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 1 8.2K 2 SMBCLK 0603D
0805 0603 0603 0603 0603 0603 0603 0603 R108 0603 RTC BATTERY CONN. BT1 RTC_VBIAS R135 0603
2
+80-20% 50V 50V 50V 50V 50V 50V 50V 1 10K/NA 2 -PME USBP2- 22 USBP2_2-
2
A 1 2 USBP2_2- (22) A
BH-800.1K
1
R605 0603
R146
ICN2 INTERNAL PULL UP 10M W/S=6/12 mils
2
0603D R127 0603

+3VS C212 USBP2+ 22 USBP2_2+
1 2 USBP2_2+ (22)
+3V_ICH RTC_X1
2
1 2
1
12P 0603 C205 C203
1
5% 22P 22P
1
C208 C125 C137 C136 C145 C144 C143 C695 C679 C680 C673 C683 C153 C147 C677 C140 X3 R145 0603 0603
0.1U 0.1U 0.1U/NA 0.1U 32.768KHZ 10M
2
4.7U 4.7U 47P 0.1U 47P 0.1U 47P 0.1U 4.7U 0.1U 0.1U 0.1U
0805 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 CM200 0603D
+80-20% +80-20% 50V 50V 50V 50V 50V 50V 50V +80-20% 50V 50V 50V C211
2
RTC_X2 Title
2
1 2
ICH2
R01 12P 0603
5% Size Document Rev
411671200001 02
Number
5 4 3 2 1
A B
AGP BUS AGP_ST1 AGP_ST0 MCH STRAP

ENHANCED IDE +3VS +3VS
1
+1.5VS
R91 R84
X 0 DDR 10K 4.7K
RP509 6.8K*4 1206 0603 0603 PDD[8..15]
-AGP_DEVSEL 1 8
X 1 SDR PDD[0..7] J14 PDD[8..15] (13)
(7,10) -AGP_DEVSEL -AGP_FRAME (13) PDD[0..7]
2
(7,10) -AGP_FRAME 2
3
7
6
0 X 533MHZ PDD7
1
3
1 2
2
4 PDD8
-AGP_IRDY PDD6 3 4 PDD9
(7,10) -AGP_IRDY 4 5 1 X 400MHZ 5 6
PDD5 5 6 PDD10
7 8
7 8
Primary EIDE Connector

RP507 6.8K*4 1206 PDD4 9 10 PDD11
-AGP_PIPE PDD3 9 10 PDD12
(7) -AGP_PIPE 1 8 11 12
PDD2 11 12 PDD13
2 7 13 14
-AGP_STOP +1.5VS PDD1 13 14 PDD14
(7,10) -AGP_STOP 3 6 15 16
-AGP_TRDY PDD0 15 16 PDD15
(7,10) -AGP_TRDY 4 5 17 18
17 18
19 20
RP506 6.8K*4 1206 PDREQ 19 20
(13) PDREQ 21 22
-AGP_RBF -PDIOW 21 22
(7,10) -AGP_RBF 1 8 (13) -PDIOW 23 24
23 24
2
-AGP_WBF -PDIOR R79
(7) -AGP_WBF 2 7 (13) -PDIOR 25 26
-AGP_REQ R550 R557 R548 PIORDY 25 26
(7,10) -AGP_REQ 3 6 (13) PIORDY 27 28 1 2
-AGP_GNT 6.8K 6.8K 6.8K/NA -PDACK 27 28
(7,10) -AGP_GNT 4 5 (13) -PDACK 29 30
IRQ14 29 30 470
0603 0603 0603 (13) IRQ14 31 32
PDA1 31 32 0603
(13) PDA1 33 34
AGP_ADSTB0 R578 2 6.8K 5% 1 0603 5% 5% 5% PDA0 33 34 PDA2
1
(7,10) AGP_ADSTB0 (13) PDA0 35 36 PDA2 (13)
35 36 -PCS3
37 38 -PCS3 (13)
AGP_ADSTB1 R27 AGP_ST0 37 38 -PCS1
(7,10) AGP_ADSTB1 2 6.8K 5% 1 0603 (7,10) AGP_ST0 39 40 -PCS1 (13)
AGP_ST1 39 40 -HDD_RST
(7,10) AGP_ST1 41 42 1 2 -HDD_RST (13)
41 42
1
AGP_SBSTB R561 1 6.8K 5% 2 0603 AGP_ST2 +5VS 43 44
(7,10) AGP_SBSTB (7,10) AGP_ST2 43 44
R71 R56
-AGP_SERR R558 1 6.8K/NA 2 0603 5.6K MA/22PX2/ST 33
(10) -AGP_SERR
1
5% 0603 C16822-X44XX 0603
2
R551 R556 R552
2K/NA 2K/NA 2K/NA R156
2
0603 0603 0603
-AGP_ADSTB0 R576 1 6.8K 5% 2 0603 470
(7,10) -AGP_ADSTB0 0603
FOR 15" CD_ROM CONNECTOR
2
2 2
-AGP_ADSTB1 R24 1 6.8K 5% 2 0603
1
(7,10) -AGP_ADSTB1 A K
-BRSTDRV1
-AGP_SBSTB R562 1 6.8K 5% 2 0603 D12 PG1102W J23
(7,10) -AGP_SBSTB CDROM_LEFT CDROM_RIGHT
1 2
CDROM_COMM 1 2
3 4
R156 ,D12 For 15" Platform
K
+5VS -BRSTDRV2 3 4 SDD8
5 6
D513 SDD7 5 6 SDD9
JO29 7 8
PLACE CLOSE TO VGA (17,19) -HDDACTP
-HDDACTP 1 2
EC10QS04
SDD6
SDD5
9
11
7
9
8
10
10
12
SDD10
SDD11
SDD4 11 12 SDD12
OPEN-SMT4 13 14
SDD3 13 14 SDD13
A
R01 15
15 16
16
SDD2 17 18 SDD14
Q13 17 18
PCI BUS D S
SDD1
SDD0
19
21
23
19
21
20
22
20
22
24
SDD15
SDREQ
-SDIOR
D
S
-SDIOW 23 24
25 26
25 26
1
G C201 Close to IDE Connector SIORDY 27 28 -SDACK
AO3400 IRQ15 27 28
0.1U 29 30
0603 SDA1 29 30
31 32
31 32
1
+12VS 1 R137 50V SDA0 SDA2
2
2 C184 C198 C182 33 34
-SCS1 33 34 -SCS3
0.1U 0.1U 4.7U 35 36
35 36
3
+3VS +3VS 0603 1M 0603 0603 1206 -CDACTP 37 38 CDROMPWR
Q14 50V 50V 16V CDROMPWR 37 38 CDROMPWR
2
39 40
CDROMPWR 39 40 CDROMPWR
(13) -HDD_PWRON 2 41 42
DTC144WK 41 42
43 44
R138 43 44
45 46
CABLE_SEL 45 46
RP15 1 2 47 48
-DEVSEL +3VS 47 48
(13,15,16) -DEVSEL 1 10 49 50
-FRAME -PCI_GNT0 49 50
(13,15,16) -FRAME 2 9 -PCI_GNT0 (13,15)
-IRDY -PCI_GNT1 10K
1
(13,15,16) -IRDY 3 8 -PCI_GNT1 (13,16) GND1
-PERR -PCI_GNT2 0603 GND1
(13) -PERR 4 7 -PCI_GNT2 (13) GND2
-PCI_GNT3 GND2
5 6 -PCI_GNT3 (13) GND3
GND3
GND4
GND4
8.2K*8 1206
RP16 FM/25PX2-R/A/NA
-LOCK 1 10 C12441-X50XX
(13) -LOCK -SERR -PCI_GNT4
(13,15,16) -SERR 2 9 -PCI_GNT4 (13)
-STOP 3 8 -PCI_REQ0
(13,15,16) -STOP -TRDY -PCI_REQ1 -PCI_REQ0 (13,15)
(13,15,16) -TRDY 4 7 -PCI_REQ1 (13,16)
5 6 -PCI_REQ2
-PCI_REQ2 (13)
8.2K*8 1206 -BRSTDRV2 1 33 2 -CDROM_RST (13)
RP17
-PCI_REQA 1 10 R55 0603 W/S=16/12/12/16 mils
(13) -PCI_REQA -PCI_INTA -PCI_REQ3
2 9 +3VS +3VS
(10,13,15) -PCI_INTA -PCI_INTB -PCI_REQ4 -PCI_REQ3 (13) CDROM_COMM
(13) -PCI_INTB 3 8 -PCI_REQ4 (13) CDROM_COMM (17)
-PCI_INTC 4 7 -PCI_REQ5 CDROM_LEFT
(13,15) -PCI_INTC SERIRQ -PCI_REQ5 (13) CDROM_RIGHT CDROM_LEFT (17)
5 6 SERIRQ (13,15,18) CDROM_RIGHT (17)
1
8.2K*8 1206 R37 R36 To Audio Codec
RP18 4.7K 10K J10
-PCI_INTD 1 10 0603 0603 1 2 SDD[8..15]
(13,16) -PCI_INTD -PCI_INTE 1 2 SDD[8..15] (13)
2 9 SDD[0..7] 3 4
-PCI_GNT5 -PCI_INTF -PCI_INTE (13) (13) SDD[0..7] 3 4 SDD8
2
3 8 5 6
Secondary EIDE Connector

(13) -PCI_GNT5 -PCLKRUN -PCI_INTG -PCI_INTF (13) SDD7 5 6 SDD9
(15,16) -PCLKRUN 4 7 -PCI_INTG (13) 7 8
-PCI_INTH SDD6 7 8 SDD10
5 6 -PCI_INTH (13) 9 10
SDD5 9 10 SDD11
11 12
SDD4 11 12 SDD12
8.2K*8 1206 13 14
SDD3 13 14 SDD13
15 16
SDD2 15 16 SDD14
17 18
SDD1 17 18 SDD15
19 20
SDD0 19 20 SDREQ
21 22 SDREQ (13)
21 22 -SDIOR
23 24 -SDIOR (13)
-SDIOW 23 24 -SDACK
(13) -SDIOW 25 26 -SDACK (13)
SIORDY 25 26 SDA2
(13) SIORDY 27 28 SDA2 (13)
IRQ15 27 28
(13) IRQ15 29 30
SDA1 29 30
(13) SDA1 31 32
SDA0 31 32
(13) SDA0 33 34
-SCS1 33 34
(13) -SCS1 35 36
35 36 CDROMPWR
37 38
37 38
39 40
39 40
ISA BUS R682

41
43
41 42
42
44
Close to IDE Connector
K
43 44
1 2 A K 45 46
45 46
1
+5VS CABLE_SEL 47 48 D508 C591 C595 C587
D11 PG1102W 47 48
49 50 0.1U 0.1U 4.7U
49 50
1
470 EC10QS04 0603 0603 1206
1
0603 R582 50V 50V 16V
2
GND1
GND1 5.6K
A
+3VS +3VS R29 GND2 R01
-CDACTP 470/NA GND2 0603
(17,19) -CDACTP GND3
0603 GND3
GND4
SD[0..7] GND4
2
SD[0..7] (18,19)
2
RP514
1
SD4 1 10
R682 ,D11 For 15" Platform FM/25PX2-R/A
C12441-X50XX
1
SD5 2 9 SD0
SD6 3 8 SD1
SD7 4 7 SD2
5 6 SD3
4.7K*8/NA 1206 -SCS3

(13) -SCS3
RP516
SA0 1 10
(18) SA0 SA1 SA4
2 9 +5VS
(18) SA1 SA2 SA5 SA4 (18)
(18,19) SA2 3 8 SA5 (18) JO500
SA3 4 7 SA6 1 2
(18) SA3 SA7 SA6 (18)
5 6 SA7 (18)
OPEN-SMT4
4.7K*8/NA 1206
RP519
SA12 1 10 Q503
(18) SA12 SA13 SA8
(18) SA13 2 9 SA8 (18)
SA14 3 8 SA9 D S
D
S
(18) SA14 SA15 SA10 SA9 (18) MTG23
(18) SA15 4 7 SA10 (18)
1
5 6 SA11 1 G C593
SA11 (18)
AO3400 0.1U
4.7K*8/NA 1206 0603
ID2.8/OD5.5 +12VS 1 R577 50V
2
RP513 2
SA16 1 10
(18) SA16
3
SA17 2 9 0603 1M
(18) SA17 SA18 3 8 Q504
(18) SA18 SA19
(18) SA19 4 7 (13) -CDROM_PWRON 2 DTC144WK
5 6
R580
4.7K*8/NA 1206 1 2
RP517 +3VS
IRQ1 1 10
(18,19) IRQ1 IRQ12 -MCCS 10K
1
(18,19) IRQ12 2 9 -MCCS (18,19)
3 8 -IOR 0603 Title
-MEMR -IOW -IOR (18,19)
4 7 HDD, CDROM Connector & PULL-UP RESISTER
(18) -MEMR -IOW (18,19)
5 6
Size Document Rev
4.7K*8/NA 1206 C 411671200001 02
Number
R01
A B
5 4 3 2 1
+3V +5V -VCCEN0

PCMCIA CONTROLLER & CARD BUS SCOKET +3V -VCCEN1
VPPEN0
VPPEN1
1
2
R46 R47
JS8 0_DFS 0/NA
0603 0603 For PCMCIA Controller Decoupling
SHORT-SMT3
VCCA
2
Card Bus Socket
1
CB_+3V
CB_+3V
1
C614 C615 C92 C95 C89 C98
0.1U 0.1U 0.1U 0.1U 0.1U 10U_NA VCCA
0603 0603 0603 0603 0603 1206
W13
M14
M18
M19
R10
H19
U12
R19
H15
A13
A12
V12
A15
E11
P14
F17
L15
J18
W7
W5
M1
M5
50V 50V 50V 50V 50V 10V
G1
R9
AD[0..31]
V6
P3
B9
A7
E7
E1
A5
2
U7
L2
J5
(13,16) AD[0..31]
AD0 U9
VCCP0
VCCP1
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCCI
VCCL
VCCCB0
VCCCB1
VCCD0
VCCD1
VPPD0
VPPD1
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
D AD0 D
AD1 V9 L18 CAD0
AD1 CAD0
1
AD2 W9 L14 CAD1 C594
AD3 AD2 CDA1 CAD2
W8 L17 0.1U
AD4 AD3 CDA2 CAD3 CB_+3V 0603
V8 K18
AD5 AD4 CAD3 CAD4 50V
2
U8 K19
AD5 CAD4
1
AD6 R8 K15 CAD5 C91 C90 C96 C94 C97 J8
AD7 AD6 CAD5 CAD6
V7 K17 0.1U 0.1U 0.1U 0.1U 0.1U 1 35
AD8 AD7 CAD6 CAD7 0603 0603 0603 0603 0603 CAD0 -CCD1
P8 J19 2 36
AD9 AD8 CAD7 CAD8 50V 50V 50V 50V 50V CAD1 CAD2
2
W6 J17 3 37
AD9 CAD8
1
AD10 R7 J15 CAD9 CAD3 4 38 CAD4 C46
AD11 AD10 CAD9 CAD10 CAD5 CAD6
U6 H18 5 39 270P
AD12 AD11 CAD10 CAD11 CAD7 R2_D14 0603
V5 H17 6 40
AD13 AD12 CAD11 CAD12 -CCBE0 CAD8 10%
2
P7
AD13 CAD12
G19 Close to PCI4410 7 41
AD14 R6 H14 CAD13 CAD9 8 42 CAD10
AD15 AD14 CAD13 CAD14 CAD11 CVS1
U5 G17 9 43
N6 G18 10 44
AD17
AD18
N3
N2
AD16
AD17
AD18
PCI4410 uBGA209 CAD15
CAD16
CAD17
G14
B15
CAD16
CAD17
CAD14
-CCBE1
11
12
45
46
CAD15
CAD16
+3V AD19 N1 C14 CAD18 CPAR 13 47 R2_A18
AD20 AD19 CAD18 CAD19 -CPERR -CBLOCK
M2 B14 14 48
AD21 AD20 CAD19 CAD20 VPPA -CGNT -CSTOP
U8 L5 A14 15 49
AD22 AD21 CAD20 CAD21 -CINT -CDEVSEL
(13,16) -PCIRST_N 1 5 L6 C13 16 50
A VCC -CBRST AD23 AD22 CAD21 CAD22 VPPA
(13) -GATE1394 2 4 L3 B13 17 51
B Y AD24 AD23 CAD22 CAD23
3 K5 C12 18 52
GND AD25 AD24 CAD23 CAD24 CCLK -CTRDY
K3 A11 19 53
AD26 AD25 CAD24 CAD25 -CIRDY -CFRAME
NC7S08 K2 B11 20 54
AD26 CAD25
1
SC70 AD27 K1 C11 CAD26 C80 -CCBE2 21 55 CAD17
J6 C9 10P/NA 22 56
AD28 CAD27
1
R606 0603 AD29 J3 F9 CAD28 VCCA C82 0603 CAD20 23 57 CVS2
AD30 AD29 CAD28 CAD29 10% CAD21 -CRST
2
+3V 1 2 J2 E9 0.1U 24 58
10K/NA AD31 AD30 CAD29 CAD30 0603 CAD22 -CSERR
J1 A8 25 59
TP35 AD31 CAD30 CAD31 ZV_Y[0..7] 50V CAD23 -CREQ
2
1 W10 C8 ZV_Y[0..7] (10) 26 60
MFUNC0 CAD31
1
SDATA V10 CAD24 27 61 -CCBE3
-CARD_RI MFUNC1 ZV_Y0 R579 CAD25 CAUDIO
(19) -CARD_RI P10 R13 28 62
SERIRQ MFUNC2 ZV_Y(0) ZV_Y1 47K CAD26 CSTSCHG
(13,14,18) SERIRQ W11 U14 29 63
SCLK MFUNC3 ZV_Y(1) ZV_Y2 0603 CAD27 CAD28
U11 W15 30 64
ZV_ACT MFUNC4 ZV_Y(2) ZV_Y3 CAD29 CAD30
P11 V15 31 65
-PCLKRUN MFUNC5 ZV_Y(3) ZV_Y4 R2_D2 CAD31
2
(14,16) -PCLKRUN R11 R14 32 66
MFUNC6 ZV_Y(4) ZV_Y5 -CCLKRUN -CCD2
U15 33 67
PCICLK_CARD ZV_Y(5) ZV_Y6
(8) PCICLK_CARD M6 W16 34 68
PCLK ZV_Y(6)
1
T19 ZV_Y7 ZV_UV[0..7] C93
C -CBRST ZV_Y(7) ZV_UV[0..7] (10) C
V11 GND1 GND3 270P
-CARDSPK G_RST ZV_UV0 0603
(17) -CARDSPK U10 R17 GND2 GND4
-PME SPKROUT ZV_UV(0) ZV_UV1 10%
2
(13,16) -PME P9 N14
RI_OUT/PME ZV_UV(1) ZV_UV2
(13,19,22) -SUSB W12 P15 0.635/H5/68P
-CBRST SUSPEND ZV_UV(2) ZV_UV3
M3 P17 CL640
-PCI_GNT0 RST ZV_UV(3) ZV_UV4 +5VS
(13,14) -PCI_GNT0 H1 R18 HIROSE
R39 -PCI_REQ0 GNT ZV_UV(4) ZV_UV5
(13,14) -PCI_REQ0 H2 N15
AD19 REQ ZV_UV(5) ZV_UV6
1 0603 2 L1 P18 U506
100 -FRAME IDSEL ZV_UV(6) ZV_UV7 ZV_ACT
(13,14,16) -FRAME P2 N17 1 5
-IRDY FRAME ZV_UV(7) A VCC
(13,14,16) -IRDY N5 2 4 ZV_SCLK (17)
-TRDY IRDY ZV_PCLK B Y
(13,14,16) -TRDY R1 M17 ZV_PCLK (10) 3
+3VS -DEVSEL TRDY ZV_PCLK ZV_DATA GND
(13,14,16) -DEVSEL P6 M15 ZV_DATA (17)
-STOP DEVSEL ZV_SDATA ZV_LRCLK
(13,14,16) -STOP R2 N19 ZV_LRCLK (17) NC7S08/NA
STOP ZV_LRCLI ZV_MCLK
1 R41 2 4.7K 0603 P5 N18 ZV_MCLK (17)
SC70
-SERR PERR ZV_MCLK ZV_SCLK1
(13,14,16) -SERR R3 P19 1 2
-CBE[0..3] PAR SERR ZV_SCLK ZV_SYNC
(13,16) -CBE[0..3] (13,16) PAR T1 V14 ZV_SYNC (10)
PAR ZV_VSYNC ZV_HREF 0_DFS R593 0603
W14 ZV_HREF (10)
-CBE0 ZV_YHREF
U7
-CBE1 C/BE0 -CCBE0
W4 J14
-CBE2 C/BE1 CC/BE0 -CCBE1 +5V +3V
P1 F19
-CBE3 C/BE2 CC/BE1 -CCBE2 R42
K6 F13
C/BE3 CC/BE2 -CCBE3 -VCCEN0
B12 1 2 3 1
-PCI_INTA CC/BE3
(10,13,14) -PCI_INTA V13
PHY_RSVD10
PHY_RSVD11
PHY_RSVD12
-PCI_INTC IBTA -CCD1
PHY_RSVD0
PHY_RSVD1
PHY_RSVD2
PHY_RSVD3
PHY_RSVD4
PHY_RSVD5
PHY_RSVD6
PHY_RSVD7
PHY_RSVD8
PHY_RSVD9
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
U13 L19
PHY_CTL(0)
PHY_CTL(1)
(13,14) -PCI_INTC
PHY_LREQ
INTB CCD1
1
LEDA_SKT
CSTSCHG
-CCD2 47K Q4
CCLKRUN
A9
CDEVSEL
PHY_CLK
CFRAME
CCD2
CBLOCK
CRSVD0
CRSVD1
CRSVD2
0603
CAUDIO
R52 R53 DTC144WK
LINKON
P12
CSERR
CPERR
CSTOP
CTRDY
CIRDY
RSVD
CREQ
CGNT
CPAR
CRST
CCLK
P13 F11 CVS1 4.7K 4.7K
CINT
RSVP CVS1
LPS
E13 CVS2 0603 0603
CVS2 -1394WR
2
-1394WR (13)
G15
R12
D19
C10
C15
E12
E10
E19
B10
E18
A10
E17
A16
E14
K14
F14
F15
F12
F10
F18
2
G6
G5
G3
G2
C6
C5
D1
H6
H5
H3
C7
B6
B5
E6
A4
E3
E2
E8
B7
A6
B8
F6
F5
F3
F2
F1
F7
F8
PCI4410GHK
U9
BGA_GHK_209 SDATA
1 5
A0 SDA
PHY_LREQ
PHY_CTL0
PHY_CTL1
R43
PHY_CLK
2 6 SCLK
PHY_D0
PHY_D1
PHY_D2
PHY_D3
PHY_D4
PHY_D5
PHY_D6
PHY_D7
-CDEVSEL
-CCLKRUN
A1 SCLK
2 0603
-CFRAME
CSTSCHG
-VCCEN1
-CBLOCK
1 2 3 1
PHY_LKON
-CSERR
-CPERR
CAUDIO
-CTRDY
R2_D14
R2_A18
-CSTOP
PHY_LPS
-CIRDY
-CREQ
R2_D2
-CGNT
3 7
-CRST
CPAR
-CINT
A2 WC- Q5
4 8 47K DTC144WK
1394AVDD +3V 22 GND VCC 0603
Closed to PHY NM24C02N
1
SO8 C99
B
2
0.1U B
The singals need to be 0603 -1394WR
1
1
50V Write Protect when high.
2
C162 C175 C151 C154 C124
0.1U the same,length must
R38
0.1U 0.1U 0.1U 0.1U

0603 0603 0603 0603 0603 not execeed 4 inches
50V 50V 50V 50V 50V
2
(17) TPB1-
CCLK
(17) TPB1+
The length TPA+ and TPA- must (17) TPA1-
PHY_AGND +3V 1394AVDD +3V +3V
L20 be the same.Also,TPB+ and TPB-
(17) TPA1+
1 2 must be the same.Both pair
need to be as close the same
120Z/100M
1608 length as possible. CHOKE_PLP3216S
(NA J21 For LCD 15")
30
31
42
51
52
25
26
61
62
16
56
U14 PLP3216S U504

PHY_CTL0 4 37 TPA+ -VCCEN0 1 16 VCCA
PLLVDD
AVDD0
AVDD1
AVDD2
AVDD3
AVDD4
DVDD0
DVDD1
DVDD2
DVDD3
NC5
PHY_CTL1 CTL0 TPA+ TPA- J21 VCCD0 SHDN +3V

5 36 -VCCEN1 2 15 VPPEN0
CTL1 TPA- TPB- +3V VCCD1 VDDP0 VPPEN1
Close to PHY 1 2 1
1
3
3.3VA VDDP1
14
PHY_D0 6 46 TPB+ 2 4 13
D0 NC0 2 3.3VB AVCCA
1
PHY_D1 7 45 TPA- 4 3 3 +5V 5 12

D1 NC1 R103 R115 TPA+ L23 3 5VA AVCCB VPPA
PHY_D2 8 4 6 11
D2 TPB+ 56 56 4 5VB AVCCC
PHY_D3 9
D3 TPB+
35 Close to TPS2211 7
GND AVPP
10
PHY_D4 10 34 TPB- 0603 0603 GND1 8 9
D4 TPB- GND1 OC 12V +12V
1
+3V PHY_D5 11 GND2 C612 C609 C603 C600
D5 GND2
Close to TPS2211
2
PHY_D6 12 44 0.1U 0.1U 0.1U 0.1U TPS2211 SSOP16

D6 NC2
1
PHY_D7 13 43 IEEE1394/4P 0603 0603 0603 0603 C599 C598 C601 C607
D7 NC3 50V 50V 50V 50V
2
LINKTEK 0.1U 4.7U_NA 0.1U 4.7U_NA
20 38 AVR20-4XXX0X 0603 1206 0603 1206
R80 PC0 TPBIAS 50V 16V 50V 16V
2
21 47 1 2
PC1 NC4
1
1K 22 Close to PHY C200

0603 PC2 C161
54 1 2 1U 4 3
FILTER0
1
PHY_LKON 1 2 19 55 0.1U 0603 L24

PHY_CLK C/LKON FILTER1 50V R105 R106
2
1 2 2
SYSCLK 0603 56 56
23 53
R73 PHY_LREQ ISO RESET 0603 0603 PLP3216S
1 27 R01
10 LREQ TESTM CHOKE_PLP3216S
1
0603 PHY_LPS PHY_XI

2
15 59
LPS XI
1
24 C156 R98
CPS PHY_XO
A 60 0.1U 110K_NA A
XO
1
3 0603 0603
PLLGND0
PLLGND1
CNA
1
R83 50V R124

2
14 40 C199
DGND0
DGND1
DGND2
DGND3
AGND0
AGND1
AGND2
AGND3
AGND4
AGND5
10K PD R0 4.99K
2
28 41 270P
0603 SE R1 0603 0603
29
SM
1
1% 10% PHY_XI
2
1 2
1
R104 R116
2
2
32
33
39
48
49
50
17
18
63
64
57
58
R72 R85 R92 R95 TSB41AB1 6.34K 1M C152

2
4.7K 1K 1K 1K PQFP64_0.5MM 0603 0603 10P

2
0603 0603 0603 0603 1% 1% 0603

X1 R81
2
24.576MHZ 1M_NA
2
Meet 6.3K ohm. 0603

C134
1
PHY_AGND L19 PHY_XO Title

1 2
1 2 PCMCIA/1394 Controller & Socket
120Z/100M
2012 10P Size Document Rev
0603 02
Number 411671200001
PHY_AGND
5 4 3 2 1
5 4 3 2 1
+3V +3V_LAN
L12 120Z/100M 1608

1 2
AD[0..31]
(13,15) AD[0..31]
JS4
1 2
SHORT-SMT4
D D
JS6
1 2
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
SHORT-SMT4
L_GND
+3V_LAN
128
127
126
125
123
122
121
120
108
107
105
104
103
102
101
100
U4
45
44
43
42
41
39
38
37
34
33
32
31
29
28
27
26
13
11
10
9
8
6
5
4
1
-CBE[0..3] C65 C81 C87 C85 C86
-CBE[0..3] (13,15)
82 2.2U 2.2U 0.1U 0.1U 0.1U
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
RTT2 -CBE0 1206 1206 0603 0603 0603
81 36
RTT3 CBE0# -CBE1 16V 16V 50V 50V 50V
2
24
TXD+ CBE1# -CBE2 +3VS +3V
92 14
TXD- TXD+ CBE2# -CBE3
91 2
TXD- CBE3#
RXIN+ 87 99 1 TP16 +3V_LAN
RXIN+ LED0
1
RXIN- 86
RXIN- TP17 R584 R571
98 1
LED1 4.7K 1K
(13,14) -PCI_INTD 114
INTA#
1
16 97 1 TP18 0603 0603 C84 C62 C586 C592 C597 C88
(13,14,15) -IRDY IRDY# LED2
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
0_DFS -PCI_REQ1 0603 0603 0603 0603 0603 0603
2
(13,14) -PCI_REQ1 118 15 -FRAME (13,14,15)
R31 REQ# FRAME# 50V 50V 50V 50V 50V 50V
2 0603
2
(13,15) -PCIRST_N 1 (13,14,15) -TRDY 17 19 -DEVSEL (13,14,15)
TRDY# DEVSEL#
22 -SERR (13,14,15)
R30 SERR#
(7,10,13,18) -PCIRST 1 0/NA 2 0603 115 95
RST# ISOLATE# AD18
54 3 1 2
NC0 IDSEL
1
85 110 R583 100 0603
GND ROMCS# R565 +3V_LAN AVDD_LAN
(13,15) -PME 76
LAN_WAKE PME# 15K
(19) LAN_WAKE 83
+3V_LAN LWAKE 0603 L10 120Z/100M 1608
23 PAR (13,15)
L_AGND U5 PAR
50 1 2
EECS
2
8 1 47 20 -STOP (13,14,15)
VCC CS MA0 STOP#
1
2 48 C54 C56 C57 C583
SK MA1
1
C69 3 49 21 4.7U 0.1U 0.1U 0.1U

DI MA2 PERR# 0_DFS L_GND 1206 0603 0603 0603
0.1U 5 4 51
GND DO MA3 16V 50V 50V 50V
1 0_DFS 0603 R32 2 0603
2
2 52 116 1 PCICLK_LAN (8)
50V 9346A MA4 CLK -PCI_GNT1
2
53 117 -PCI_GNT1 (13,14)

R164 0603 MA5 GNT#
57
R165 5.6K 0603 MA6
60 79 1 2
C MA7 XTALIN L_AGND C
+3V 1 2 61
MA8 C584
63
MA9
2
L_AGND 64 75 10P
MA10 CLKRUN#
3
2
65 78 4 0603
MA11 XTALOUT
R02 66
67
MA12 NC2
88
89 X501
R566
1M_NA
MA13 NC3 25MHZ 0603
68 94
GND11
GND12
GND13
GND14
GND15
RTSET
VDD10
VDD11
VDD12
VDD13
VDD14
MA14 NC4
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND8
GND9
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD9
1
69
NC5
NC6
NC1
MA15
1 0_DFS 2 70 1 2
MA16
R696 0603 C585
106
109
119
111
112
113
124
12
25
35
46
58
59
72
73
77
90
96
18
30
40
56
55
62
71
74
80
84
93
RTL8139CL 10P
7
PQFP128A_0.5MM 0603
+3V_LAN
L_AGND
-PCLKRUN (14,15)
1 0_DFS 2 AVDD_LAN
R697 0603 L9 120Z/100M 1608 L_GND

1 2 L_AGND
R23 1 2
1.8K 0603 1%
L_AGND
RJ45
R01-->R02
J9
1 FOR ESD ISSUE
PJ7 1
2
PJRX- 2
3
3
4
PJ4 4
5 GND1
PJRX+ 5 GND1
6 GND2
PJTX- 6 GND2 +3V +5V
7 GND3
PJTX+ 7 GND3 J11
8 GND4
B 8 GND4 MONO_OUT R65 0603 B
(17) MONO_OUT 1 2
MODEM_SPK
Modem Dougther Board

3 4 1 0_NA 2
MODEM_SPK (17)
8PX1/1.016MM 5 6
CONN_PJS-AST_8 7 8
1
1
GND_16 9 10 C120
+3V 11 12 0.1U
13 14 R64 4.7K 0603
1
JO516 JO31 JO32 JO35 50V
2
C577 15 16 1 2
0.1U JO30 JO512 GND_45 17 18 0603
0603 19 20 CLOSE TO MDC
50V ACSYNC
2
21 22 ACSYNC (13,17)
ACSDOUT R63 22 2 0603 MSDIN
2
23 24 1
Layout Note: L_AGND FOR EMI (13,17) ACSDOUT
(13,17) -ACRST
-ACRST 25 26 R62 1 22 2 0603
MSDIN (13)
CHOKE_PLP3216S CLOSE TO MDC 27 28
1
キキキキキǐキキ C39 PLP3216S 29 30 R61 1 22 2 0603 ACBITCLK

ACBITCLK (13,17)
1
1
0.1U C657
キ, EX: GND SHIELDING 0603
50V
R549
51
R555
51
0.1U
0603
FM/0.8MM/H2.4
2
1 2 AMP C-179373
1
S/W/W/S=12/6/6/12 mils 0603 0603 50V
2
C119
L_AGND 4 3 10P/NA
U2
as short as possible L513 0603
2
RXIN+ PJRX+
2
1 16
RXIN- RD+ RX+ PJRX-
2 15
RD- RX-
3 14
R15 0_DFS 0603 RDC RXC
R01
AVDD_LAN 1 2 6 11
TXD+ TDC TXC PJTX+
7 10
TXD- TD+ TX+ PJTX-
8
TD- TX-
9 MDC HARDWARE STRAP
HIGH LOW
1
1 2 4 12
NC0 NC2
1
C572 R542 R541 C567 C40 5 13

51 51 NC1 NC3 PJ4
22P 22P 0.1U 4 3 PIN 16 AUDIO CODEC ON MOTHER BD AUDIO CODEC ON DAUGHTER BOARD
0603 0603 0603 0603 0603 L508 H0011
50V PJ7 MDC SCREW HOLE
2
XFMR_H0009
AVDD_LAN
2
PLP3216S JO501
L511 CHOKE_PLP3216S MDC_GND1
1 1 2
1
L21
1 2 L_AGND
R17 R12 R530 R531 1 2 MTG24 SHORT-SMT3
75 75 75 75 120Z/100M ID2.8/OD5.0 JO502
120Z/100M 0603 0603 0603 0603 2012 1 MDC_GND2 1 2
1
A
1608 C502 A
1000P MTG25 SHORT-SMT3
2
1808 ID2.8/OD5.0
3KV
RJ11
1
JS500 C566
2
10%
1
1 2 1000P
1808 J4 S500 J13
5 1
SHORT-SMT4 3KV L1 Protector
2
10% 1 1
1
2 3 2 2
50UH 1808A 2
2
GND1
ST/MA-2 CHOKE_WLT04020201 GND1
GND2
HIROSE GND2
GND_45
2
GND_45 DF13-2P-1.25V C500 1.016MM/H8.6
1000P L25 OCTEKCONN Title
1808 PJS-OXSXT LANPHY,MDC
L22 F500 3KV 120Z/100M
1
10% 2012 Size Rev
1 2 1 2 Document
120Z/100M 411671200001 02
2012 mircoSMDC110 Number
1
R02 Date: Friday, December 28, 2001 Sheet 16 of 22
5 4 3 2 1
5 4 3 2 1
AUDIO CODE & AMPLIFIER
+5VS +3VS_SPD
+3VS
(ADD J17 For LCD 15")
J17
1
1 2
SPKROUT+ 1 2 SPKROUT- R121 R109
3 4
VR1_2 3 4 VR1_5 L14 6.8K_DFS 6.8K_DFS
5 6
AOUT_L 5 6 AOUT_R 120Z/100M 5% 5%
7 8
LINE_OUT_5 7 8 LINE_OUT_2 1608 AVDDAD +12VS
9 10 U511
-DEVICE_DECT 9 10 MIC_3 R01
2
11 12 L78L05ACU
-DECT_HP/OPT 11 12 MIC_2 ACBITCLK L540
2
SOT89N
D (15) TPB1-
TPB1-
13
15
13
15
14
16
14
16 TPA1-
TPA1- (15) 1 2 1
O I
3 D
1
TPB1+ 17 18 TPA1+ C666 Close to Codec Close to Codec Close to 78L05
(15) TPB1+ 17 18 TPA1+ (15)
19 20 10P 120Z/100M
GND
19 20
1
T_DATA 21 22 T_CLK 0603 C146 C665 C668 C702 C672 C684 2012 C674
(18,19) T_DATA 21 22 T_CLK (18,19)
SPDIFOUT -SCROLL
R02
2
23 24 -SCROLL (12,19) 10U_NA 0.1U 0.1U 0.1U 0.1U 10U 0.1U
23 24 -NUM 1206 0603 0603 0603 0603 1206 0603
+5V 25
25 26
26 -NUM (12,19) AGND
-CAP -CDACTP 10V 50V 50V 50V 50V 10V 50V
2
(12,19) -CAP 27 28 -CDACTP (14,19)
-HDDACTP 27 28 L522
(14,19) -HDDACTP 29 30
SPKLOUT+ 29 30 SPKLOUT-
31 32 1 2
31 32
HDR/MA/1.27MM/NA BEAD R652
-ACRST AGND AGND AGND 0805C 1 2 MODEM_SPK
S100-0112-321 (13,16) -ACRST MODEM_SPK (16)
SPEED R02
1
U15 10K 0603
25
38
1
9
1
ACSDOUT R655 C687
(13,16) ACSDOUT 1K
AGND 23 C196 1 2 2.2U 0805 +80-20% 0.1U_NA
DVDD1
DVDD2
AVDD1
AVDD2
LINE/IN/L 0603 0603
ACSDIN 22 C183 1 2 2.2U 0805 +80-20% 50V
2
(13) ACSDIN 1 2 24
R645 0603 LINE/IN/R
2
11 21 MIC1 C194 1 2 1U 10V 0603 MIC
ACSYNC RESET# MIC1
(13,16) ACSYNC 5
SDATA/OUT MIC2 C188 1 1U 10V 0603
8
SDATA/IN MIC2
22 2 AGND
10 R01
ACBITCLK 22 SYNC C193 1 1U 10V 0603 R134 1 1K CDROM_RIGHT
(13,16) ACBITCLK 1 2 6 20 2 2 0603 CDROM_RIGHT (14)
R648 0603 BIT/CLK CD/R
CLOSE TO CODEC 18 C191 1 2 1U 10V 0603 R132 1 1K 2 0603 CDROM_LEFT
CD/L CDROM_LEFT (14)
2
XTL/IN C192 1 1U 10V 0603 R133 1 CDROM_COMM
19 2 2 0 0603
CDROM_COMM (14)
CD/GND
1 R88 2 3
XTL/OUT C189 1 1U 10V 0603 VIDEO_L AVDDAD
VIDEO/L
16 2 ZV AUDIO
2
0603 1M 12 U512
PC_BEEP C190 1 1U 10V 0603 VIDEO_R R142 R140 R141
17 2
VIDEO/R 0 ZV_DATA
7 1 ZV_DATA (15)
C186 1 1U 10V 0603 100K 100K 0603 VA+ SDATAI ZV_SCLK
X2 14 2 8 2 ZV_SCLK (15)
AUX/L 0603 0603 AOUTL SCLK ZV_LRCLK
1 2 5 3 ZV_LRCLK (15)
0603 10V 1U AOUTR LRCK ZV_MCLK
2 C163 C202 1 1U 10V 0603 R01
1
1 31 15 2 6 4 ZV_MCLK (15)
24.576MHZ BPCFG AUX/R AGND MCLK
1
C148 0603 10V 1U 1 2 C164 32 35 AOUT_L

FLT3D LINE/OUT/L
1
10P C167 AGND AGND AGND CS4334/NA
1
0603 10P 0603 10V 1U 1 2 C160 33 36 AOUT_R C697 SO8
0603 FLTI LINE/OUT/R 0.1U/NA
2
C 0603 50V 2 C158 C185 1 1U 10V 0603 0603

C
2
1 34 13 2
1000P_NA FLTO PHONE 50V
2
37 C142 1 2 1U 10V 0603 MONO_OUT
MONO_OUT MONO_OUT (16)
+5VS 40
C159 NC1
43
C667 NC2 C141 1
AGND 1 2 44 39 2 1000P 50V 0603
0.1U_NA 50V 0603 NC3 ALT_LINE_OUT_L
1 2 45
ID0# INTERNAL MICROPHONE
46 41 C132 1 2 1000P 50V 0603 J16
C165 ID1# ALT_LINE_OUT_R
MIC
47
EAPD AGND 1
C675 0.1U 50V 0603 0.1U 1 2 SPDIFOUT 48 29 C173 1 2 1000P 50V 0603 2 HIROSE
SBSPKR 50V 0.1U_NA 50V 0603 S/PDIF_OUT AFLT1 ST/MA-2
(13) SBSPKR 1 2
1
U510 0603 30 C174 1 2 1000P 50V 0603 C676 DF13-2P-1.25V
C669 C670 AFLT2
1 5 47P_NA
-CARDSPK A VCC 0603
1 2 2 4 1 2 1 2 27 20mil AGND
DVSS1
DVSS2
AVSS1
AVSS2
(15) -CARDSPK B Y REFFLT
2
3
GND R646 0.1U 28
VREFOUT
1
2
0.1U NC7S32 200K 0603 Very Close to Codec AGND
1
50V SC70/SOT70 0603 R647 50V C133 R657 R653
26
42
1
1
0603
R02 20K CHIP ALC201 CS4299 ALC201 0_DFS 0_DFS
4
7
C172 C180 C179 1000P/NA
0603 PQFP48_0.5MM 0.1U 0.1U 1U 0603 0603 0603 AVDDAD
R649 Cap pin31: 1U X 0603 0603 0603
2
47K 50V 50V R01
2
1
10V
1
0603 Cap pin32: 1U 0.01U
R663
2
Cap pin33: 1U X AGND AGND AGND AGND AGND AGND AGND AGND 40.2K/NA
0603
Cap p33/34 X 1000P 1%
2
CHIP ALC2000 AD1881 CS4299 R668 2.7K 0603
1 2
Cap. pin29: 1000P 270P 1000P AVDDAD
+3V_ICH +5VS
Cap. pin30: 1000P 270P 1000P R669 47K 0603 R670 47K 0603
L17 1 2 1 2
1
1
1 2
2
1
R166 C68610U 10V 1206 R148
1
10K 1 2 68K L535
120Z/100M 0603
C700
0.1U 0603 (NA J22,L525,
2012 AGND 0603 120Z/100M_DFS L530 For LCD 15")
R1
50V R6800/NA 0603

2
2
SPK_OFF 1 3 MUTE_IN 1 2 AGND 1608 External Micro Phone Jack
(13) SPK_OFF
2
B L18
Q16 DTC144TKA AGND
8
VCC+ 1IN+
U513
3
R671 4.7K
1 2
0603
5
J22
R.CH B
1 2
1 2 1
1OUT 1IN-
2 0.068U
R02 MIC_3
4
3
R167 0/NA 0603 5 1 2 MIC_2 1 2 2
2IN+
R02 L525 120Z/100M 1608
L.CH
7 6 1
120Z/100M 2OUT 2IN- C701 25V 0805
4
VCC-
1
2012 AGND
+5VS 5V_AMP MC33078D R151
6.8K
R149
100K R02 RA/D3.6/5P
HCH
1
L26 0603 0603 IDJ-B27-F6T
AGND C705 C696
1 2 C704 220P 10% 0603 5% 220P/NA 220P/NA
5V_AMP C209 0603 0603
12
2
1 2
120Z/100M 10% 10% 1608
2
C710 R678 0603 R667 0603
R02 2012 C210 220U 10V EW6.3 10U 1 2
1
1 2 1 2 1 2 1 R679 22K 0603 10V L530 120Z/100M
+
2
15K 1% R659 1206
2
1 2
2.2U 10K 1% 10K
0805 C694 0603
(NA VR1,C717,C718 (NA J20,J18 For LCD 15") AGND AGND AGND AGND CAGND
+80-20% 1 2 0603
For LCD 15") Amplifier Internal Speaker Connector -DEVICE_DECT Line Out Phone Jack
2
AOUT_R/L Cap x2 - SIZE0805 470P 10% U18 J20 L524 120Z/100M 1608
VR1_5 21 22 SPKROUT+ 1 HIROSE LINE_OUT_5 1 2 L537 120Z/100M 1608 J19
RLINE IN R OUT+ SPKROUT- ST/MA-2
20
RHP IN R OUT-
15 2 R 1 2 5 6
VR1 0603 DF13-2P-1.25V L523 120Z/100M 1608 AGND 1 2 4 11
10K 1 R666 2 3 SPKLOUT+ 1 J18 LINE_OUT_2 1 2 L538 120Z/100M 1608 2
L OUT+
5
C717 4.7U 0805 +80-20% 10K 1% 4 10 SPKLOUT- 2 L HIROSE 3

LLINE IN L OUT-
1
AOUT_R 1 2 4 7 5 ST/MA-2 R143 R122 1 4.7K 2 -DECT_HP/OPT 1 2 1

C709 R677 C693 LHP IN 5V_AMP
6 0603 18 DF13-2P-1.25V C689 R673 0603 L539 120Z/100M 1608
RVDD
1
AOUT_L 1 2 1 3 1 2 1 2 1 2 0603 7 1K 100P 1K C688 L528 120Z/100M 1608 7

LVDD LED
6 100P 1 2 8 Drive
C718 4.7U 0805 +80-20% 2.2U 10K 1% 470P 10% L BYPASS C204 220U 10V EW6.3 0603 0603 0603 0603 L531 120Z/100M 1608 IC
19 1 9
0805 R BYPASS GND0 SPDIFOUT 1
2
2
+
12 1 2 2
GND1
1
+80-20% C169 C207 13 Very Close to TPA0202 Pin 18/7 L529 2F1138-TJ1
GND2
1
1U 1U 14 24 2 1 FOXCONN
SE/BTL# GND3
1
R01 AGND 0603 0603 16 C168 C206 C166 120Z/100M

MUTE_IN HP/LINE# + 100U 1608
2
11 2 0.1U 0.1U
JO33 JO34 MUTE IN NC0 0603 0603 16V
9 17
MUTE OUT NC1 50V 50V EW6.3
2
C708 R676
AGND AGND R02 NC2
23 AGND (NA L523,L524,L536,L532,
0603 R665 0603 CAGND
2
8 2 1 2 1
SHUTDOWN
1 2 1 2 1 2 Q514 +3VS_SPD L527,L528,L531,L537,L538,
15K 1% AGND AGND AGND 5V_AMP +3VS DTA144WK
2
30 25 3 4 3 4
A 2.2U
0805
10K 1%
C692
31
32
G6
G7
G8
G1
G2
G3
26
27 1 3 L532 L536
L539,J19 For LCD 15")
A
1
+80-20% 1 2 0603 33 28
G9 G4
1
34 29 R102 R685
470P 10% G10 G5 47K 10K
VR1_2 TPA0202_GND TSSOP24_TPA0102 0603 0603 2
AGND AGND AGND CHOKE_PLP3216S CHOKE_PLP3216S
R113 L527 PLP3216S PLP3216S
2
0603 120Z/100M
2
1 2
1 R664 2 1608
10K 1%
C707 R675 0603 C691 100K Q10
3 3
2 0603 0603 R1 2 -DEVICE_DECT Q515 R1 2 -DECT_HP/OPT
1
1 2 1 2 1
Signal HI LOW 1 DTC144TKA
1 Title
2.2U 10K 1% 470P 10% DTC144TKA AUDIO CODEC & AMPLIFIER
0805
+80-20% SPK_OFF Shut Down Normal Size Document Rev
-DEVICE_DECT 411671200001 02
Number
5 4 3 2 1
A B
(NA L13,L15,L16,C139,
C149,C135,J15 For LCD 15")
+5V
TOUCH_PAD
L13 120Z/100M 1608
1 2 1 J15 J501
T_DATA L15 1 2 120Z/100M 1608 2
(17,19) T_DATA T_CLK L16 1 TP_VCC
(17,19) T_CLK 2 120Z/100M 1608 3 HIROSE 1 HIROSE
4 DATA 2 ST/MA-4
ST/MA-4
CLK 3 DF13-4P-1.25V
DF13-4P-1.25V 4
J500
1
C139 C149 C135
47P 47P 0.1U
0603 0603 0603 GND2 TP_GND
50V
2
GND1
D3
8 2
7 3
6 SW2 1
5 RIGHT 1 3
4 LEFT 2 4 BAV99
3 5
2 SCRL_UP
SCRL_DOWN
RIGHT
1 12V/50MA
STS-042-A D4
2
ACES 3
HDR/MA-8 SW3 1
88206-0800 TP_GND 1 3
2 4 BAV99
5
2 LEFT 2
Flash ROM 12V/50MA

SD[0..7] SA[0..17] STS-042-A D1
(14,19) SD[0..7] SA[0..17] (14,19)
U12 2
SD0 13 12 SA0 3
+5VS SD1 O0 A0 SA1
14 11 SW1 1
SD2 O1 A1 SA2
15 10 1 3
SD3 O2 A2 SA3 BAV99
17 9 2 4
O3 A3
1
SD4 18 8 SA4 5
2M ROM------PULL VCC R162 SD5 19
O4 A4
7 SA5
4M ROM------SA18 O5 A5 SCRL UP
Flash ROM
0/NA SD6 20 6 SA6 12V/50MA
0603 SD7 O6 A6 SA7 D6
21 5 STS-042-A
O7 A7 SA8
27 2
R163 A8 SA9
2
26 3
A9 SA10
(14) SA18 1 2 1 23 SW4 1
VPP A10 SA11
25 1 3
0_DFS 0603 +5VS A11 SA12 BAV99
4 2 4
A12 SA13
28 5
A13
A14
29 SA14 SCRL DOWN
Close to EEPROM 3 SA15 12V/50MA
A15
R01-->R02 32
VCC A16
2 SA16 STS-042-A TP_GND
1
C123 30 SA17
A17 -ROMCS
0.1U 22 -ROMCS (19)
0603 CE# -MEMR
24 -MEMR (14)
50V OE#
2
16 31 -MEMW TP_GND
VSS WE#
28F020-PLCC
STRAP OPTION
+3VS XCNF2 XCNF1 XCNF0 FUNCTIONALITY
X 0 0 NO BIOS
X 0 1 NORMAL MODE , XRDY DISABLE
1
C660 C653 C656 C664
0.1U 0.1U 0.1U 0.1U 0 1 0 LATCH MODE ,XA12-19, XRDY ENABLE
50V 50V 50V 50V 1 1 0 LATCH MODE , GPIO 10-17 , XRDY ENABLE
2
0603DA 0603DA 0603DA 0603DA
0 1 1 LATCH MODE , XA12-19, XRDY DISABLE
14
39
63
88
U509 1 1 1 LATCH MODE , GPIO 10-17 ,XRDY DISABLE
LAD[0..3] P_LPD[0..7]
VDD0
VDD1
VDD2
VDD3
(13) LAD[0..3] P_LPD[0..7] (22)
LAD0 15 52 P_LPD0 BASE ADDRESS SELECT
+3VS +3VS LAD1 LAD0 PD0/INDEX# P_LPD1 +3VS
16 50
LAD2 LAD1 PD1/TRK0# P_LPD2
17
LAD2 PD2/WP#
48 R303 INDEX REGISTER DATA REGISTER
R01 LAD3 18 46 P_LPD3
LAD3 PD3/RDATA#
1
1
45 P_LPD4
R637 R639 PCICLK_LPC PD4/DSKCHG# P_LPD5 R640
(8) PCICLK_LPC 8
LCLK PD5/MSEN0
44 MOUNTED 4EH 4FH
10K 10K/NA -PCIRST 9 43 P_LPD6 10K
(7,10,13,16) -PCIRST -LFRAME LRESET# PD6/DRATE0 0603
0603 0603 12 42 P_LPD7 OPEN 2EH 2FH
R638 (13) -LFRAME -LDRQ LFRAME# PD7/MSEN1
(13) -LDRQ 11
-SUS_STAT -LPCPD LDRQ# PIO/-PNF
2
2
(10,13) -SUS_STAT 1 2 7 35
-CLKRUN LPCPD# PNF/XRDY P_SLCT
6 36 P_SLCT (22)
0_DFS SERIRQ CLKRUN#/GPIO36 SLCT/WGATE# P_PE
(13,14,15) SERIRQ 10 37 P_PE (22)
0603 SERIRQ PE/WDATA# P_BUSY
+3VS 1 10K/NA 2 19 40 P_BUSY (22)
R641 0603 SMI#/GPIO35 BUSY_WAIT#/MTR1# -P_ACK
41 -P_ACK (22)
SIO_14.318MHZ ACK#/DR1# -P_SLIN
R01 (8) SIO_14.318MHZ 20
CLKIN SLIN#_ASTRB#/STEP#
47
-P_INIT -P_SLIN (22)
49 -P_INIT (22)
INIT#/DIR# -P_ERR +3VS +3VS +3VS
51 -P_ERR (22)
ERR#/HDSEL# -P_AFD
21 53 -P_AFD (22)
DSKCHG# AFD#_DSTRB#/DENSEL -P_STB
22 54 -P_STB (22)
HDSEL# STB#_WRITE#
1
23
RDATA# R644 R643 R635 J506
24
WP# -COM1DCD 10K 10K/NA 10K -COM1DCD
25 55 1
TRK0# DCD1# -COM1DSR 0603 0603 0603 -COM1DSR 1
26 56 2
WGATE# DSR1# COM1RXD COM1RXD 2
27 57 3
WDATA# SIN1 -COM1RTS COM1TXD XCNF0 -COM1RTS 3
2
28 58 4
SETP# RTS1#/TEST COM1TXD COM1TXD 4
29 59 5
DIR# SOUT1/XCNF0 -COM1CTS -COM1CTS 5
30 60 6
DR0# CTS1# -COM1DTR -COM1DTR 6
31 61 7
MTR0# DTR1#_BOUT1/BADDR -COM1RI -COM1RI 7
1
32 62 8 1
INDEX# RI1# 8
33 +3VS 9
DENSEL -MEMW XCNF1 9
34 10
DRATE0/IRSL2 IRTX 10
70 IRTX (22) 11
IRTX IRRX 11
69 IRRX (22) 12
SA0 IRRX1 FIRSEL 12
(14) SA0 95 68 FIRSEL (22)
SA1 XA0/GPIO20 IRRX2_IRSL0
(14) SA1 94 67
SA2 XA1/GPIO21 IRSL1 FFC-12P/0.5MM/NA
(14,19) SA2 93 66
SA3 XA2/GPIO22 IRSL3/PWUREQ# SD0[0..7]
(14) SA3 92 SD[0..7] (14,19)
-XSTB XA3/GPIO23
91 U11
TP545 XCNF2 XA4/GPIO24/XSTB0# SD0 SD0 SA4
1 90 3 3 2 SA4 (14)
IRQ1 XA5/XSTB1#/XCNF2 XD0/GPIO00/JOYABTN1 SD1 SD1 D0 Q0 SA5
(14,19) IRQ1 87 2 4 5 SA5 (14)
IRQ12 XA6/GPIO26/PRIQA/XSTB2# XD1/GPIO01/JOYBBTN1 SD2 SD2 D1 Q1 SA6
(14,19) IRQ12 86 1 7 6 SA6 (14)
XA7/GPIO27/PIRQB XD2/GPIO02/JOYAY SD3 SD3 D2 Q2 SA7
85 100 8 9 SA7 (14)
XA8/GPIO30/PIRQC XD3/GPIO03/JOYBY SD4 SD4 D3 Q3 SA8
84 99 13 12 SA8 (14)
-IOR XA9/GPIO31/MTR1#/PIRQD XD4/GPIO04/JOYBX SD5 SD5 D4 Q4 SA9
(14,19) -IOR 83 98 14 15 SA9 (14)
-IOW XA10/GPIO32/XIORD#/MDRX XD5/GPIO05/JOYAX SD6 SD6 D5 Q5 SA10
(14,19) -IOW 82 97 17 16 SA10 (14)
SA12 XA11/GPIO33/XIOWR#/MDTX XD6/GPIO06/JOYBBTN0 SD7 SD7 D6 Q6 SA11
(14) SA12 81 96 18 19 SA11 (14)
SA13 XA12/GPIO10/JOYABTN1/RI2# XD7/GPIO07/JOYABTN0 D7 Q7
(14) SA13 80
SA14 XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2 -MEMW
(14) SA14 79 4 1 20 +3VS
SA15 XA14/GPIO12/JOYAY/CTS2# XWR#/XCNF1 -MEMR -XSTB OC VCC
(14) SA15 78 5 -MEMR (14) 11 10
SA16 XA15/GPIO13/JOYBY/SOUT2 XRD#/GPIO34/WDO# -MCCS G GND
(14) SA16 77 73 -MCCS (14,19)
XA16/GPIO14/JOYBX/RTS2# XIOWR#/XCS1#/MTR1#/DRATE0
1
SA17 76 71 74AHC373_V C105
(14) SA17 SA18 XA17/GPIO15/JOYAX/SIN2 XIORD#/GPIO37/IRSL2/DR1# -ROMCS
(14) SA18 75 72 -ROMCS (19) 0.1U
XA18/GPIO16/JOYBBTN0/DSR2# XCS0#/DR1#/XDRY/GPIO25
1
SA19 74 TSSOP20
(14) SA19 XA19/DCD2#/JOYABTN0/GPIO17 50V
R58
2
10K 282574373004
VSS0
VSS1
VSS2
VSS3
0603DA
0603
2
PC87393
13
38
64
89
284587393002
PQFP100_0.5MM
MITAC INTERNATIONAL CORP.
Title
TOUCH PAD,BIOS,SUPER-IO
Size Document Number Rev

Custom 411671200001 02

A B
A B
NA RP521,R693,R691 FOR 8175 QK-B

RP521 1206 BX BE# H8 Mode Select Table
KI1 1 0*4 8 -SCROLL_KI1 NA RP521,R693,R692 FOR 8175 LED-B
KI2 -NUM_KI2 U515 QK-B L L
2 7 MD0 MD1 MODE Description
KI3 3 6 -CAP_KI3 KI1 3 2 -SCROLL_KI1
KI4 -CDACTP_KI4 KI2 1A1 1B1 -NUM_KI2 LED H L
4 5 7 6
KO1 -HDDACTP_KO1 KI3 2A1 2B1 -CAP_KI3 +5VA
1 2 11
3A1 3B1
10 0 1 MODE1 Expended mode with On-Chip ROM disable
R693 0 0603 KI4 17 16 -CDACTP_KI4
KO1 4A1 4B1 -HDDACTP_KO1 BAV99
21
5A1 5B1
20 1 0 MODE2 Expended mode with On-Chip ROM enable
2 I_LIMIT (22)
1
-SCROLL 4 5 3 C527 1 1 MODE3 Single-Chip mode
(12,17) -SCROLL -NUM 1A2 1B2
(12,17) -NUM 8 9 1 1U_NA
+5VA -CAP 2A2 2B2 D501 0603
(12,17) -CAP 14 15
+5VS_LEDB -CDACTP 3A2 3B2
2
(14,17) -CDACTP 18 19
-HDDACTP 22 4A2 4B2 +5V BAV99
(14,17) -HDDACTP 23
BAV99 5A2 5B2 +5VA H8_VDD5 +5VA
2
L520
2 1 10K/NA 2 13 24 3 +5VS
BX VCC +5V
3 1 Close to H8-3437F 1 2 Close to H8-3437F
1 R691 0603 1 100K/NA 2 1 12 D502
BE GND
3
D503 R692 0603
1
BAV99 SN74CBTH3383/NA BAV99 C631 C632 C658 120Z/100M C654 C655 D510
2 SSOP24 2 0.1U 0.1U 0.1U 1608 0.1U 0.1U +1.8VS
BAV70LT1
1
3 3 0603 0603 0603 0603 0603
50V 50V 50V 50V 50V R636
2
1 1
D505 D504 10K
2
J5
BAV99 -HDDACTP_KO1 1 2 -SCROLL_KI1 0603
2 KO0 3 4 -NUM_KI2 BAV99 RP518 33*4
-PWRSW -CAP_KI3 1206
2
3 5 6 2 GND_H8 Come From Battery
1 7 8 -CDACTP_KI4 3 BAT_TEMP 1 8 BAT_T
+5VS BAT_VOLT BAT_V BAT_T (20)
D507 9 10 1 2 7 BAT_V (20)
4
3
2
1
1
+5VS_LEDB D506 L521 3 6 BAT_C
BAT_C (20)
1
SPEED 1 2 RP510 R4 C661 C663 4 5 BAT_D
10K BAT_D (20)
S100-0000-101 1K*4 0.1U 0.1U
HDR/SHR/MA/5PX2 1206 1% 0603 0603
GND_H8 JP_BEAD_DFS 50V 50V
2
59
37
70
71
92
15
46
36
H8_THRM_CLK (4)
4
0603B_DFS U508
2
EASY START BTN/LED INDICATOR
AVREF
AVCC
VCC1
VCC2
VSS1
VSS2
VSS3
VSS4
VCCB
AVSS
5
6
7
8
J12
GND_H8 H8_THRM_DATA (4)
KO0 2 1 JO4 1 KO0 79 38
KO1 KO1 P10/A0 P70/AN0
2
2 1 JO5 2 78 39 2

2 1 JO6 3 77 40 Cover Switch Signal HI LOW
2 1 JO7 4 76 41
KO4 KO4 P13/A3 P73/AN3 R629
2 1 JO8 5 75 42 SW6
2 1 JO9 6 74 43 1 2 1 3 -LID Normal Suspend
P15/A5 P75/AN5
Internal Keyboard
KO6 2 1 JO10 7 KO6 73 44 2 4 +5V +3V_ICH

P16/A6 P76/AN6/DA0 CHG_I (22)
2
KO7 2 1 JO11 8 KO7 72 45 BLADJ C638
KO8 KO8 P17/A7 P77/AN7/DA1 BLADJ (22)
2 1 JO12 9 67 93 SA2 2.2U 1K MPU-101-80 ICN2 INTERNAL PULL UP
P20/A8
Micro P80/HA0 SA2 (14,18)
1
KO9 2 1 JO13 10 KO9 66 94 H8_A20GATE 16V 0603
P21/A9 P81/GA20
1
KO10 1 JO14 KO10 -H8_KBCS 1206 R139
1
2 11 65 95
KO11 2 1 JO15 12 KO11 64
P22/A10
P23/A11 Controller P82/CS1
P83/IOR
96 -IOR
-IOR (14,18)
R660 10K/NA
Connector
KO12 2 1 JO16 13 KO12 63 97 -IOW AGND 10K 0603

KO13 KO13 P24/A12 P84/IRQ2/TXD1/I -IOW (14,18) 0603
2 1 JO17 14 62 98 -H8_MCCS
-LID (22)
KO14 KO14 P25/A13 P85/IRQ4/RXD1/C
1 JO18 BAT_CLK
2
2 15 61 99 (NA C638,R629,SW6 For LCD 15")
KO15 KO15 P26/A14 P86/IRQ5/SCK1/S -H8_SUSC -PWRBTN
1 JO19
2
2 16 60 25 -PWRBTN (13)
KI0 SD0 P27/A15 P90/IRQ2/ESC2 -LID
2 1 JO20 17 82 24
KI1 SD1 P30/HDB0/D0 P91/IRQ1/EIOW
2 1 JO21 18 83 23 -POWERBTN 1 2 -PWRSW
KI2 SD2 P31/HDB1/D1 P92/IRQ0 -H8_THRM
2 1 JO22 19 84 22 3
P32/HDB2/D2 P93/RD
1
KI3 2 1 JO23 20 SD3 85 19 SW_+5V A C634 R617 2 R1 Q513
KI4 SD4 P33/HDB3/D3 P94/WR SW_+5V A (20)
2 1 JO24 21 86 18 -H8_ICH2BTN 0.1U 1K 1DTC144TKA
KI5 SD5 P34/HDB4/D4 P95/AS
2 1 JO25 22 87 17 H8_A20GATE 50V 0603
KI6 SD6 P35/HDB5/D5 P96/0
1 JO26 BAT_DATA 0603
2
2 23 88 16
KI7 SD7 P36/HDB6/D6 P97/WAIT/SDA
2 1 JO27 24 89 6 H8_MODE0
P37/HDB7/D7 MD0 H8_MODE1 -H8_ICH2BTN
49 5
SD[0..7] -H8_WAKE_UP P40/TMCI0 MD1 LED_CLK
(14,18) SD[0..7] 50 91 LED_CLK (12)
FPC/FFC/1MM/24P -H8_SMI P41/TMO0 PB0/XDB0 LED_DATA
51 90 LED_DATA (12)
85203-24-02 H8_SCI P42/TMRI0 PB1/XDB1 FAN0_SPD
52 81
ACES IRQ1 P43/TMCI1/HIRQ1 PB2/XDB2 FAN1_SPD
(14,18) IRQ1 53 80
IRQ12 P44/TMO1/HIRQ1 PB3/XDB3 CHARGING
(14,18) IRQ12 54 69 CHARGING (22)
-FAN0 P45/TMRI1/HIRQ1 PB4/XDB4
55 68
-FAN1 P46/PW0 PB5/XDB5 C662 0.1U 50V 0603
56 58
(22) PWR_ON PWR_ON H8_PWRON P47/PW1 PB6/XDB6 T_DATA
14 57 T_DATA (17,18)
-H8_RCIN P50/TXD0 PB7/XDB7 -RI
13 48 1 2 -CARD_RI (15)
LEARNING P51/RXD0 PA0/KEYIN8 -BATT_DEAD
(22) LEARNING 12 47
KI0 P52/SCK0 PA1/KEYIN9
26 31
KI1 P60/KEYIN0/FTCI PA2/KEYIN10 -ADEN Q512
27 30 -ADEN (20)
P61/KEYIN1/FTOA PA3/KEYIN11
3
KI2 28 21 H8_PWROK DTC144WK
KI3 P62/KEYIN2/FTIA PA4/KEYIN12
29 20
KI4 P63/KEYIN3/FTIB PA5/KEYIN13 Q510
32 11 3 2 LAN_WAKE LAN_WAKE (16)
KI5 P64/KEYIN4/FTIC PA6/KEYIN14 T_CLK
33 10 T_CLK (17,18)
R1 2 BATT_DEAD BATT_DEAD (20)
KI6 P65/KEYIN5/FTID PA7/KEYIN15 -H8_STBY +5VA
34 8 1
KI7 P66/KEYIN6/IRQ6 /STBY/FVPP -H8_SUSB DTC144TKA
35 7
P67/KEYIN7/IRQ7 /NMI -H8_RESET
1
/RES
1
2
XTAL R622
1
3
+5VS +5V EXTAL
100
/RESO 10K
R627 0603
H8/F3437S PQFP100_0.5MM
Close to SI2301DS
2
1 2
R01
1
1
C659 1M 0603 C636
0.1U R642 X503 0.1U
1
0603 470K -SCI 1 2 0603

50V 0603 (13) -SCI 50V
R687 Q509 Q511
2
2
A
10K AO3401 3 16MHZ

S
1
CPU_FAN Control 0603 D7 R1 H8_SCI C633 TXC8X4.5
2
S GG 2 C630
D 1 68P 68P
J7 RLS4148 DTC144TKA 0603 0603
2
External Pull Up/Down

5% 5% For H8-3437F Reset
2
D
K
1 Signal HI LOW +5VA +5VA

FAN
2 U10 +5VA
1
HIROSE FAN1_SPD ADM809 SOT23N RP515

3 C720
ST/MA-3 + 220U/NA -FAN FAN Off FAN On +3V_ICH 2 3 1 10
(12) -H8_RESET RESET# VCC -RI
DF13-3P-1.25V 7343 -ADEN 2 9
10V H8_MODE0 3 8 -BATT_DEAD
GND
2
R02 H8_MODE1 -POWERBTN
2
4 7
5 6
+5VA +5VA
Threshold : 4.38V
1
47K*8 1206
R1
RP512
1
-WAKE_UP 3 1 -H8_WAKE_UP KI0 1 10
(13) -WAKE_UP KI4
+5VS +5V R78 R66 KI1 2 9
Q9 DTC144TKA 10K 10K KI2 3 8 KI5
Close to SI2301DS U13 0603 0603 KI3 4 7 KI6
R01 -EXTSMI 3 2 -H8_SMI 5 6 KI7
(13) -EXTSMI 1A1 1B1
1
PWROK H8_PWROK
2
C4 (13) PWROK 4 5
1A2 1B2
1
0.1U R1 ICH_A20GATE 7 6 H8_A20GATE 47K*8 1206

470K (13) ICH_A20GATE -ROMCS 1A3 1B3 -H8_KBCS
R688 0603 8 9
Level Shift
50V 0603 (18) -ROMCS -THRM 1A4 1B4 -H8_THRM
10K Q1
2
(13) -THRM 11 10
A
0603 AO3401 1A5 1B5 BAT_CLK R631 1 2 10K

S
-DC/DC_FAN Control D5 -FAN0 -MCCS -H8_MCCS 0603

2
G (14,18) -MCCS 14 15
RLS4148
S G
-RCIN 2A1 2B1 -H8_RCIN BAT_DATA R623 1 2 10K
2
(13) -RCIN 17 16
J502
D 2A2 2B2 0603
18 19
2A3 2B3
1
21 20 1
2A4 2B4
D
K
1 Signal HI LOW 22 23 +5VS +5VA +5V

1 2A5 2B5
FAN
2 JS9
2 FAN0_SPD R68
3 1 24 1 2
3 1OE# VCC RP511
-DC/DC_FAN FAN Off FAN On (20) -SW_+5VA 1 2 13
2OE# GND
12
SHORT-SMT3 JO28 T_CLK 1 8
1
DF13-3P-1.25H 0/NA SN74CBTD3384 1 2 T_DATA 2 7

0603 R67 QSOP24A Close to 74CBTD3384DBQ -LID 3 6
0_DFS OPEN-SMT3 4 5
0603 1 C121
0.1U
R01 0603 4.7K*4
2
50V 1206
2
VDD3 ON then through R/C to generate -RSMRST.

-RSMRST(SB I/P) +5VA +5VA
Power switch ON. Power switch OFF

-POWERBTN(H8 I/P)
1
R611 R604
H8(Pin 40) detect powebtn,then delay 100ms to o/p -MVP4BT pulse(1us) to SB.. 10K 10K
0603 0603
-H8_ICH2BTN(H8 O/P)
ICH2 received -H8_ICH2BTN(H8 O/P), then o/p -SUSB-C. Into S4 Resume 2
2
-H8_SUSB -H8_SUSC
-SUS[B-C](SB O/P) 3 3
Q507 R1 2 Q506 R1 2
DTC144TKA -SUSB (13,15,22) DTC144TKA -SUSC (13,22)
H8's pin14 PWR_ON on VCC3/5 then Vcore/Vtt/Vcc25. 1 1
ALL POWER
H8 detect -SUSC,then delay 150ms then o/p PWROK. H8 OFF this pin before o/p PWRON low.. Title
Micro Controller
PWROK(H8 O/P)
Size Document Rev
Custom 411671200001 02
Number
A B
A B C D E
+5VAS
DVMAIN PU10
DVMAIN SI4835DY
SO8
8
1
7 3
PR564 PR567 DBATT 6 2 DVMAIN
475K 100K DBATT 5 1
0603 0603 PU11
S
8
1% SI4835DY
G
SO8
2
3 +
BATT_DEAD PR554
4
1 BATT_DEAD (19) 8
2 - 7 3 1 2
PU513A 6 2
4 5 1 4
2
LMV393M +5VA 1M
D
4
S
SSOP8 PR559 0603
G
100K
4
0603
1
1
PR563
1
1
PR566 PC556 100K
D
100K 0.1U 0603
0603 0603 D PQ508
1% 50V -ADEN 2N7002
2
(19) -ADEN G S
J33
S
1
1
3
PR561 3
3
4
PQ509 4
ADINP 1 2 2 5
5
6
DTC144WK PL9 6
7
169K 7
1 2 8
0603 8
9
1% 120Z/100M 2012 9
1
11
PL10 11
PF2 1 2 11P/2.5MM/H3/NA
1 2 CEN
120Z/100M 2012 BPH-S-11-G-J1A
6.5A/32VDC
PF1 PL11
1 2 1 2
J28
1
PR569 6.5A/32VDC 120Z/100M 2012 1
1
1
1 2 PR562 PC30 2
301K 2
0.1U 3
+5VAS 1M 0603 0603 3
4
0603 1% 50V 4
2
5
1% +5VA 5
2
6
(19) BAT_V BAT_V 6
7
7
7P/2.5MM/H4
1
CEN
1
1
PR570 PC555 PR565 (19) BAT_C BAT_C SB-07A-4.0-A2
3 PR572 12.1k 100K +5VAS 3
0.1U
4.7K 0603 0603 0603 BAV99/NA
0603 1% 50V 1%
2
8 2
1
1%
2
3
PR18
2
1 2 5 + 1
7 LI_OVP 4.99K
LI_OVP (22) 0603 PD507
1 2 6 -
PU513B 1%
PR568 (19) BAT_T BAT_T (19) BAT_D
2
2
1
402K LMV393M
4
SSOP8 PC32 PC31

1
1
PQ510 0603 PR571 PC557 0.01U 1000P
1
1% 43.2K 0.1U PR17 BAV99/NA 0603 0603
1 PC34 PC33
SCK431LCSK-5 0603 0603 20K
2
1000P 0.1U 2
SOT23N 1% 50V 0603 0603 0603
2
3
1% 50V
3
2
1
2
PD508
Don't Stuff
DBATT
DBATT
1
PC35 PC36
47P_NA 47P_NA
0603 0603
2
2 2
+5VA
MTG26
3
2
1
ID2.8/OD7.6 J29
4 12 1
5 11 2
6 10 3
1
4
PR16 5
470K
7
8
9
6
0603 7
2
PQ2 R/A-7P/2.5MM/NA
-SW_+5VA (19)
+5VA +5VAS SUYIN
3
DTC144WK 250005MR07G100ZU
2 PQ512
J30
S
D
S D
1
+5V 1
G
1
G
AO3401
1
3
PR573 3
4
4
1
100K 5
PR616 0603 5
6
+3V_ICH 3V Resume Power 0
0805
7
6
7
MTG27
2
PD503 8
PU8 +5VA -ADEN ID2.8/OD7.6 8
A K -ADEN (19) 9
9
3
2
1
2
1
GND
3 2 BAS32L 4 12 11
VOUT VIN +3V 11
5 11
K
RLZ3.6B 6 10 11P/2.5MM/H3/NA
1
PC22 PC27 TC55RP3302EMB PC29 3 PQ511 CEN

1
0.1U 4.7U SOT89N 4.7U PL8 PC26 R1 2 BPH-S-11-G-J1A

0603 D8 0805 0805 120Z/100M
7
8
9
0.1U 1
50V +80-20% +80-20% 1608 0603 +5V
2
50V
A
DTC144TKA
2
2
1 1
JS7 PU7 G PQ1

G
1 2 8 6
ALWAYS IN 5VTAP
2 1 S D
SHORT-SMT4 SENSE OUT
S
D
7 5
SW_+5V A F/B ERR-
(19) SW_+5V A 3 4
K
SHUTDN GND
1
LP2951-02BM PD7 PC25 PC24

PC21 SO8 0.1U 10U AO3401
0.1U UDZS5.1B 0603 1206
50V SOD323 50V 10V
2
5V Resume Power
A
0603
Title
BATTERY CONNECTOR & 3V,5V-RESUME POWER
Size Document Rev

C 411671200001 02
Number
A B C D E
5 4 3 2 1
+5V
1
PR21
0
0603
2
1
1
PC40 PC41
0.1U 4.7U
0603 0805
PL500 50V +80-20%
2
1 2
BEAD
0805C
D D
DVMAIN PL501
1 2
BEAD
1
0805C PC503 PC512 PC504 PC511 PC502 PC509 PC505 PC513 PC506 PC514 PC517 PC507 PC510 PC508
PC46 PC47
1
+ 100U + 100U PC500 PC501 0.1U 0.1U 0.1U 0.1U 10U 10U 10U 10U 10U 10U 10U 10U 10U 10U
0.01U 0.01U 0603 0603 0603 0603 1812 1812 1812 1812 1812 1812 1812 1812 1812 1812
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
0603 0603 50V 50V 50V 50V
2
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2
1
PR528
1M
0603
PR526 10
2
1 2
+5VA PR520 10
1 2
PC518 1U 25V PR505 10

1 2 2 1
5
6
7
8
5
6
7
8
1
PR527 0805 D PU500 D PU503

PR521 1K SI4892DY SI4892DY
(13) VRMPWRGD G G
1M 0603 PR619 0 SO8 SO8
0603 PU508 1 2 4 4
PC521 0.1U PR2
2
RUN/SS .003
2
1 2 1 23
RUNN/SS PGOOD S S PC3 PC5 PC582 PC572 PC573 PC38
1 2
D
PR513 PC524 2 35 820U 820U 100U 100U 100U 0.1U
SENSE1+ TG1
1
PQ501 PR524 2.7K 10K 1% 1000P PC520 0.1U PR1 4V 4V 7343 7343 7343 50V
1
2
3
1
2
3
D
2N7002 PR516 PL1 .005 6.3V 6.3V 6.3V 0603
G S 1 2 1 2 3 34
49.9K SENSE1- SW1
1 2 1 2
5
6
7
8
5
6
7
8
5
6
7
8
S
0603 EAIN 4 33
D
PC523 1000P 1% EAIN BOOST1 PU1 PU502 PU501

D D D
PQ500 SI4362DY SI4362DY SI4362DY 0.7UH
2
D 5 32
K
PLLFLTR VIN
1
2N7002 PR620 0 G SO8 G SO8 G SO8 HK-RM136
G S
(5) CPU_CORE_EN
1
6 31 1 2 4 4 4 PD1 30% + + + + +
PLLIN BG1
1
S
PC529
EC31QS03L
1
C 0.1U C
7 30
NC0 EXTVCC
1
PR512 PR519 6.8K 50V PC519
2
1 S S S
1M
A
Ith PR502 10U
2
1 2 1 2 8 29 3
0603 PC527 ITH INTVCC 10 1206
1
2
3
1
2
3
1
2
3
2
470P PC528 100P PD500 10V
2
9 28
SGND PGND 0603 BAW56
2
1 2
5
6
7
8
5
6
7
8
JS501
2
10 27
VDIFFOUT BG2 PU507 PU506
1 2 1 2 D D
11 26 SI4892DY SI4892DY CPU_CORE
SHORT-SMT4 PR523 VOS- BOOST2 PC515 G SO8 G SO8
15K 12 25 4 4 PR4
0603 VOS+ SW2 .003
1% 13 24 0.1U 1 2 PC6 PC7 PC583 PC574 PC575 PC39
SENSE2- TG2 S S 820U 820U 100U 100U 100U 0.1U
14 36 PR622 0 4V 4V 6.3V 6.3V 6.3V 50V
SENSE2+ NC1 PL2 PR3 7343 7343 7343 0603
1
2
3
1
2
3
1 2
15 22 1 2 1 2
PC522 ATTENOUT VBIAS
5
6
7
8
5
6
7
8
5
6
7
8
16 21 .005
ATTENIN VID4
1
1000P PC516 D PU2 D PU504 D PU505 0.7UH
1
PC17 17 20 0.1U SI4362DY SI4362DY SI4362DY HK-RM136 + + + + +
47P VID0 VID3 0603 G SO8 G SO8 G SO8 PD2 30%
2
0603 50V
2
18 19 4 4 4
VID1 VID2 EC31QS03L
2
1 2
A
PR509 0_NA S S S
PR508 0_NA PR621 0
PR510 0_NA
1
2
3
1
2
3
1
2
3
1
PR517 0_NA LTC1709EG-9
PR518 0_NA PR514 10 SSOP36A PR501 PR500
0 0
0603 0603
PR515 10
2
+3VS
PR507 10K
PVID4
B PVID[0..4] PVID3 1 8 B
(4) PVID[0..4] PVID2 2 7
PVID1 3 6
PVID0 4 5
RP508
10K*4
1206
+3V_ICH +1.8V_ICH
1.8V,1.5V POWER +3VS 3

PU12
VIN
VOUT
2
+1.8VS
PU13 1
GND/ADJ
1
+12VS AO4400 PU514
1
SO8 PR19 PC9
AMS1085
1
1 5 1.2K + 100U PC10
VIN OUT SOT252N
1
8 2 PC37 0603 7343 0.1U
GND 1% 6.3V 0603
7 3 3 4 4.7U
+3V EN BYP 0805 50V
2
6 2 +1.5VS
2
5 1 AME8801MEE V 16V
D
SOT25
1
G
1
PR22 PC559 PC560 PC558
1
1K
4
1 2 1U 0.01U 4.7U
0603 0603 0603 0805 PR20
2
PR23 PC42 1% +80-20% 560

2
2
10V
1
PC43 4.7K 470P PC44 PC45 0603

2
10U 0603 0603 10U 0.1U 1%

1206 1206 0603
1
2
1
2
PQ3
1
SCK431LCSK-.5
3
SOT23N PR24
4.7K_1%
0603
A A
2
Title
CPU Vcore/VTT
Size Document Rev

02
Number 411671200001
5 4 3 2 1
A B C D E
ADINP
ADINP
ADINP_2
ADINP_2
ADINP_1
ADINP_1
(19) I_LIMIT 1 2
1
PR615 PC563
0 10U PR552
2
0603 1206
A
1
10V PC552 PR548
2
PR555
PR546 0.1U 12.1k 10 PD5 PD4
0603 0603 10
10K 50V 1% EC31QS03L EC31QS03L
K
E
B PQ505 PL14 BEAD 0805C
4 4
MMBT3906L
C 1 2
1
PR560 PL15 BEAD 0805C
1
100K 1 2 PC546 PC548 PL5 PL6
2
PR547 0603 1U 1U
33K 1% 25V 25V BEAD BEAD
0603 0805C 0805C
0805 0805
1
2
2
D
D PQ506
1
(20) LI_OVP G S 2N7002
PC18
1
PR557 PR558 PC19 PC20 + 100U
1K
S
33 0.1U 10U 25V

2 0603 0603 1206 20%
PC551 1U 1% BAW56 PD502 50V 25V
2
5
6
7
8
PR553 PC553
2
1 2 1
(19) CHARGING 1 2 PC554 10U 10V 3 D
1U PU512 PU9
1
1 2 2
PU511 G SI4835DY SI4835DY
47K PC550 0.01U 1 28 4 SO8 SO8
0603 DCIN IINP SO8
1 2 2 27 AO4400
PC549 0.01U LD0 CSSP PC542
3 26 8 8
CLS CSSN S PU5
1 2 4 25 0.1U 7 3 3 7
REF BST PL7 PR13
5 24 6 2 2 6
PC547 CCS DHI
1
2
3
6 23 1 2 1 2 5 1 1 5 DBATT
CCI LX
D
0.1U
S
D
1 2 1 2 7 22
S
CCV DL0V
G
50V 8 21 .035
G
GND0 DL0
5
6
7
8
0603 PR550 1K 9 20 10uH 2512
K
GND1 PGND
1
5%
4
10 19 D PC23
ICHG CSIP
1
11 18 PD6 + 100U PC541 PC544 PC543 PC28
ACIN CSIN G
12 17 25V 10U 10U 0.1U 10U
ACOK BATT EC31QS03L 1206 1206 0603 1206
13 16 4 20%
REFIN CELLS SO8
1
25V 25V 50V 25V
2
14 15 SI4832DY
ICTL VCTL
A
PR14 PR15 PR551
MAX1772 S PU6 1 1 1M
QSOP28 0603 0603 0603
TP542 I_CHG
1
2
3
1
1
2
1
3 PC545 PR549 3
0.1U 15K
1
1
0603 0603
PR532 50V 1% PR556
2
10 100K
2
1
PC564 PC565 0603
0603 10U 0.1U
1206 0603
2
2
10V 50V
2
3V Resume Power
1
1
PC540
1
1
PR541 PR534 0.1U PC539 PC538
D
PR537 100K 100K 0603 0.1U 0.1U
1M 0603 0603 50V 0603 0603 PQ507
2
D
0603 1% 1% 50V 50V 2N7002 S
2
PU510 G LI_OVP (20)
1%
2
2
8 6
IN 5VTAP DVCC3
S
2
2 1
SENSE OUT
7 5
F/B ERR-
3 4
SHUTDN GND
LP2951-3.3BM
1
1
SO8 PC537 PC535
1
PC536 0.1U 4.7U PR536 PR542 PR535

0.1U 0603 0805 10K 49.9K 100K
0603 50V +80-20% 0603 0603 0603
2
50V 1% 1% 1%
2
(19) CHG_I 1 2
PR539
1
1K
0603 PR533
1% 15K_NA
0603
1%
2
2 2
D
D PQ504
(19) PWR_ON G S 2N7002_NA
1
PR543
1M_NA
0603
J6
2
50 49 -LID (19)
50 49
(13) -USBOC0 48 47
48 47
(13) -USBOC2 46 45
FIRSEL 46 45 DP_LPD0 J3
(18) FIRSEL 44 43
P_LPD0 DP_LPD0 RP500 -SUSC 44 43 DP_LPD1
(18) P_LPD0 8 1 (13,19) -SUSC 42 41 +5V 1 2
P_LPD1 DP_LPD1 0*4_DFS IRRX 42 41 DP_LPD2
(18) P_LPD1 7 2 (18) IRRX 40 39 +5VS 3 4 +5VS
P_LPD2 DP_LPD2 1206 IRTX 40 39 DP_LPD3
(18) P_LPD2 6 3 (18) IRTX 38 37 5 6
P_LPD3 DP_LPD3 -DP_ACK 38 37 DP_LPD4
(18) P_LPD3 5 4 36 35 +3V 7 8 ALWAYS
P_LPD4 DP_LPD4 RP502 DP_BUSY 36 35 DP_LPD5
(18) P_LPD4 8 1 34 33 9 10
P_LPD5 DP_LPD5 0*4_DFS DP_PE 34 33 DP_LPD6 ADINP
(18) P_LPD5 7 2 32 31 +3VS 11 12
P_LPD6 DP_LPD6 1206 32 31 DP_LPD7 ADINP
(18) P_LPD6 6 3 (13) USBP0_0- 30 29 13 14
P_LPD7 DP_LPD7 30 29 DP_SLCT
(18) P_LPD7 5 4 (13) USBP0_0+ 28 27 15 16
P_SLCT DP_SLCT RP503 28 27 -DP_STB
(18) P_SLCT 8 1 26 25 17 18
-P_STB -DP_STB 0*4_DFS 26 25 -DP_AFD DVMAIN DVMAIN
(18) -P_STB 7 2 (10) CSYNC 24 23 19 20
-P_AFD -DP_AFD 1206 24 23 -DP_ERR
(18) -P_AFD 6 3 (10) TV_CRMA 22 21
22 21
1
-P_ERR 5 4 -DP_ERR 20 19 -DP_INIT HDR/10PX2/H8.4
(18) -P_ERR (10) TV_LUMA 20 19
1
-P_INIT 8 1 -DP_INIT RP504 18 17 -DP_SLIN PH/PS-D-RA-44-X-X C519 C511 C509
(18) -P_INIT -P_SLIN (10) TV_COMP 18 17 -AC_POWER
7 2 -DP_SLIN 0*4_DFS 16 15 CEN 0.1U 0.1U 0.1U
(18) -P_SLIN -P_ACK (13) USBP2_2- 16 15 -BATT_LED -AC_POWER (12)
-DP_ACK 1206 0603 0603 0603
2
(18) -P_ACK 6 3 (13) USBP2_2+ 14 13 -BATT_LED (12)
P_BUSY DP_BUSY +12V 14 13 -BATT_G 50V 50V 50V
2
(18) P_BUSY 5 4 12 11 -BATT_G (12)
P_PE 0603 R500 1 DP_PE 12 11 -BATT_R
(18) P_PE 2 10 9 -BATT_R (12)
0_DFS +5VAS BLADJ 10 9 ENPBLT
8 7 ENPBLT (10)
(19) BLADJ +12VS 8 7 PWR_ON
6 5 PWR_ON (19)
6 5 LEARNING C2 PC1 C716 C5 PC2 C6 C520
(13,15,19) -SUSB 4 3 LEARNING (19)
ADINP_2 4 3 ADINP_1 0.1U 10U 0.1U 0.1U 22U 0.1U 0.1U
R01 2
2 1
1 ADINP_1
ADINP_2 50V 10V 50V 50V 10V 50V 50V
0603 1206 0603 0603 1210 0603 0603
FM/22PX2/1.27
B06P-0110-441
SPEED
1 1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
C504
22P
0603
5%
2
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
CP502 CP503 CP504 CP505

22P*4 22P*4 22P*4 22P*4
1206 1206 1206 1206 Title
DC-DC CONNECTOR ,CHARGER
Size Document Rev

C 411671200001 02
Number
A B C D E
5 4 3 2 1
SYSTEM POWER (5V 3V 12V)
D D
PR509
DVMAIN 1 2 D2 1 2
DVMAIN
PL2 10 0603
1
BEAD PC16 PC14
PC9
0805C +
100U 0.1U 0.1U
25V 0603 0603
50V 50V
2
2
(2) PWR_ON 1 2
PR505 0
(2) -SUSC 1 2
PU506
1
SI4800DY PR504 0/NA 0603
1
SO8 PR3
PC504 1K PR511
4
0.1U 0603 1K
50V 0603
2
G
0603
2
5 1
S
D
2
6 2
7 3
1
C PC512 C
8
+3V 470P_NA
0603
2
10%
2
PL507 PR8 PL1 PR12 PR510
A4 1 2 1 2 A2 1 2 1M
0603 0_NA
0603
BEAD 0805C PU505
1
.015 10UH SI4832DY
1
4
PR15 2512 CDRH127-100MC SO8 PU1
PL506 37.4K 1% PC15
1 28
G
K
CSH3 RUN/ON3
1
1 2 PC8 PC7 PC515 0603 5 1 0.1U
S
D
1
PD503 + 100U/H2.8 + 330U 0.1U 1% 6 2 2 27 50V

BEAD 0805C 7343 0603 CSL3 DH3 0603
2
7343 7 3
EC10QS03L 10V 4V 50V 8 3 26 2 1
FB3 LX3
1
PC514 PC513
A
4.7U 0.1U +12V 1 2 4 25

12OUT BST3
1
1
1206 0603
PC11
1
1
16V 50V PR16 PL3 PC516 + 100U
2
PC20 5 24
100K I3 BEAD 0.1U VDD DL3
470P 25V
0603 0603 0805C 50V 6 23
A5 1% 10% I4 0603 SYNC SHDN
2
2
PD502
2
7 22
TIME/ON5 V+
A K 1
8 21 3
GND VL
1
PC6 PR19 0 2 PC13 PC511
PD1 0.1U 1 2 9 20 0.1U 4.7U
EC11FS2 0603 PR2 REF PGND 0603 1206
1
1
DC2010 50V BAW56 50V 16V
2
PC4 PC5 1 2 10 19
SKIP DL5
1
+ 100U + 100U
25V 25V 0 11 18
0603 RESET BST5
4
2
2
12 17 2 1
BKL_VMAIN FB5 LX5
G
(2) BKL_VMAIN PC12
5 1 13 16
S
D
CSL5 DH5 0.1U
6 2
1
7 3 14 15 50V
JS501 CSH5 SEQ 0603
8
1
MAX1632 SSOP28A
+5V SHORT-SMT3 PR508 1 2
1
PT1 0_NA
PU503
B SI4800DY 0603 PR503 PR501
2
2 4 B
PL501 SO8 0 0_NA
B3
2
1 2 1 2 1 3
PR1 10UH
2
1
1
BEAD .015 IND_CDRH125B PC2
0805C PR17 2512 1U PR502
G
PL504 100K_NA 1% 5 1 0603 0_NA
S
D
K
0603
2
1 2 6 2
PD504 1% 7 3
1
PC3 PC1 PC503

2
2
8
EC10QS03L
1
BEAD + 100U/H2.8 + 100U/H2.8 0.1U

1
PC501 0805C 7343 7343 50V

10V 10V
A
4.7U PC502 0603

1206 PU502
2
16V 0.1U SI4832DY

2
50V
1
0603 SO8
1
PR18 PC21
97.6K_NA 470P_NA
0603 0603
1% 10%
2
I5
2
I6
A A
Title
SYSTEM POWER
Size Document Rev

411671200004 0A
Number
Date: Monday, October 22, 2001 Sheet 1 of 3
5 4 3 2 1
5 4 3 2 1
PD2
2
3
1
BAV70LT1
PD3
2
3 ALWAYS
1
BAV70LT1
ADINP
JO502
D 1 2 D
JL2
OPEN-SMT4 1 2 ADINP_1
JO503
1 2 SHORT-SMT4
OPEN-SMT4 1 2
ADINP_2
PQ503 JL3 SHORT-SMT4
SI4835DY PR514
SO8 .1
8 1 2
3 7
2 6 PD6
L3 1 5 1 2 A K DVMAIN
D
DVMAIN
S
2
G
PR513 EC31QS03L
PR4 .1
1
470K
4
PC19 PD5
1
0603 PC10 + 100U PR10 PR11 A K PC17 PC18
PR5 0.1U 10K 10K 0.1U 1000P
25V
0603 0603 0603 0603 0603
1
1 2 EC31QS03L
D
50V 50V
2
PR9 PQ502
2
D PD4
LEARNING 1 2 G S 470K SI4835DY A K
LEARNING
1
0603 SO8
S
PR6 8 EC31QS03L
47K 100K PQ1 3 7
0603 0603 2N7002 2 6
SOT23_FET 1 5
D
S
2
G
PL502 120Z/100M 2012
1 2
4
J5
2DC-S315-X03 PF501 6.5A/32VDC PL503
1 1 2 L1 1 2 L2
3
K
2 120Z/100M
1
1
JACK-3P PC505 PC510 PC506 PC507 PC5082012
4
5
6
1U 0.1U 0.1U 0.1U 0.1U

0805 0603 0603 0603 0603 PC509 PD501
C 25V 50V 50V 50V 50V 0.1U RLZ24D C
2
A
50V
PQ2
SI2301DS +12VS PU501 PU504
AO4400 AO4400
SO8 SO8
+12V
S
D
S D
G 8 8
G
7 3 7 3
PR7 +5V 6 2 +5VS +3V 6 2 +3VS
1M 5 1 5 1
0603
D
S
S
G
G
2
4
PR506
1 2
1
470K PC517 PC518
D PQ3 0603 0.1U 0.1U
-SUSB G S 2N7002 0603 0603
-SUSB 50V 50V
2
S
1
PR515
1M
0603
B
2
PJ2
50 49
-USBOC0 50 49
(3) -USBOC0 48 47
48 47
1
-USBOC2 46 45 PJ1 C514 C513
(3) -USBOC2 FIRSEL 46 45 P_LPD0 0.1U_NA
(3) FIRSEL 44 43 P_LPD0 (3) +5V 1 2 0.1U
-SUSC 44 43 P_LPD1 50V 0603
(1) -SUSC 42 41 P_LPD1 (3) +5VS 3 4 +5VS
IRRX 42 41 P_LPD2 0603 50V
2
(3) IRRX 40
40 39
39 P_LPD2 (3) 5 6 Note : BKL_VMAIN is Power Trace
IRTX 38 37 P_LPD3 +3V 7 8 ALWAYS
(3) IRTX -P_ACK 38 37 P_LPD3 (3) ALWAYS ENPBLT1
36 35 P_LPD4 9 10 L510 1 2 BEAD J6
(3) -P_ACK P_BUSY 36 35 P_LPD5 P_LPD4 (3) ADINP
34 33 11 12 0603B 1
(3) P_BUSY P_PE 34 33 P_LPD6 P_LPD5 (3) +3VS ADINP 1
32 31 13 14 (1) BKL_VMAIN BKL_VMAIN L509 1 2 BEAD 2
(3) P_PE USBP0_0- 32 31 P_LPD7 P_LPD6 (3) 2
Inverter
30 29 15 16 0805C 3
(3) USBP0_0- USBP0_0+ 30 29 P_LPD7 (3) 3
28 27 P_SLCT 17 18 BLADJ L508 1 2 BEAD 4
(3) USBP0_0+ 28 27 P_SLCT (3) 4
26 25 -P_STB DVMAIN 19 20 DVMAIN 0603B 5
26 25 -P_STB (3) 5
24 23 -P_AFD FA501 6
(3) CSYNC 24 23 -P_AFD (3) -AC_POWER 6
22 21 -P_ERR HDR/10PX2/H8.49 1 8 7
(3) TV_CRMA 22 21 -P_ERR (3) -BATT_LED 7
20 19 -P_INIT PH-D-RA-44-X-X 2 7 8
(3) TV_LUMA 20 19 -P_INIT (3) -BATT_G 8
18 17 -P_SLIN CEN 3 6 9
(3) TV_COMP USBP2_2- 18 17 -AC_POWER -P_SLIN (3) 9
16 15 -BATT_R 4 5 10
(3) USBP2_2- USBP2_2+ 16 15 -BATT_LED -AC_POWER 10
(3) USBP2_2+ 14 13 -BATT_LED 11
14 13 -BATT_G 11
+12V 12 11 -BATT_G 12
12 11 -BATT_R 120OHM/100MHZ 12
10 9 -BATT_R
+5VAS 10 9 ENPBLT1
8 7 ENPBLT1 GND1
BLADJ +12VS 8 7 PWR_ON GND1
6 5 PWR_ON (1) GND2
6 5 GND2
1
-SUSB 4 3 LEARNING +5VAS 1 2 C512
-SUSB ADINP_2 4 3 ADINP_1 LEARNING
2 1 L507 0.1U MA/12PX1/ST
ADINP_2 2 1 ADINP_1 BEAD 0603 SPEED
0805C 50V
2
Y17-101-0001
MA/22PX2/1.27
SPEED
G442-8701-441
A A
Title
DC POWER
Size Document Rev

411671200004 0A
Number
5 4 3 2 1
5 4 3 2 1
+3V
1
D503 D502
Place two fuses on same location,
BAV99 BAV99
only use one fuse.
3
U2
TV OUT 3
VIN0 VOUT0
1 USB2VCC5
+5V
GND
J4 L503 L502 4 5 USB0VCC5
120Z/100M 120Z/100M VIN1 VOUT1
1 CSYNC (2)
1 1608 1608
2 TV_COMP (2) RT9701-CBL
2 TV_LUMA
2
3 1 2 1 2 TV_LUMA (2) SOT25
3 TV_CRMA
D 4 1 2 1 2 TV_CRMA (2) D
4
1
GND1 L504 L505
GND1 120Z/100M 120Z/100M R4
GND2
GND2 1608 1608 33K
4
3
2
1
C10801-10405 C506 0603
1 C504
1
MINI-DIN/4P C505 C503 100P 100P RP501
0603 0603 -USBOC2
2
100P 100P 75*4 (2) -USBOC2
0603 0603 10% 10% 1206 L1
1
10% 10%
2
2
1 2
1
L5 R3
C1
1 2 1000P 47K 120Z/100M
1
0603 0603 2012
5
6
7
8
C2 C501
2
10U_NA 0.1U
JP_BEAD_DFS 1206 0603
2
GND_TV 10V 50V
2
GND_TV
GND_USB
+5VS
(2) USBP2_2-
A
D501
4 3
BAS32L L2
1 2 200Z/100M
K
U501 CORE_ACM2520U
12 13
11 14
0*4 RP1
-P_STB 8 1 -PP_STB 10 15
(2) -P_STB -PP_AFD (2) USBP2_2+
-P_AFD 7 2
(2) -P_AFD PP_LPD0
P_LPD0 6 3 9 16
(2) P_LPD0
1
-P_ERR 5 4 -PP_ERR C508 C509
(2) -P_ERR
1
8 17
1206 Layout note: Same legth
R502
15K
R503
15K
47P/NA
0603
47P/NA
0603
2
7 18
0*4 RP2 J1 0603 0603
C
(2) P_LPD1
P_LPD1
-P_INIT
8 1 PP_LPD1
-PP_INIT
6 19 USBP0- C
2
7 2 26
(2) -P_INIT
(2) P_LPD2
P_LPD2
-P_SLIN
6
5
3
4
PP_LPD2
-PP_SLIN
5 20
STB# 1
USBP0+
(2) -P_SLIN
4 21 AFD# 14 GND_USB
1206 R1 LPD0 2
Parallel Port Connector

P_LPD3 1 2 PP_LPD3 3 22 ERR# 15
(2) P_LPD3 J2
2 23 LPD1 3
0 0603 1 24 INIT# 16 1
LPD2 1
4 2
SLIN# 2
17 3
PAC128401Q LPD3 5 GND 4
3
4
QSOP24A 18
LPD4 6 JO501 GND1
GND1
19 10mil 1 2 GND2
GND2
LPD5 7 GND3
SHORT-SMT4 GND3
20 GND4
LPD6 GND4
8 10mil
21 USB/4PX1
LPD7 9 5mil LINKTEK
U502 22 USBP- UAR80-4W510
12 13 ACK# 10 USB0VCC5 GND_USB
23 5mil
11 14 BUSY 11 USBP+
1
0*4 RP3 24 5mil
P_LPD4 8 1 PP_LPD4 10 15 PE 12 R5
(2) P_LPD4 PP_LPD5 33K
P_LPD5 7 2 25 10mil
(2) P_LPD5 PP_LPD6 0603
P_LPD6 6 3 9 16 SLCT 13
(2) P_LPD6 PP_LPD7
P_LPD7 5 4
(2) P_LPD7
10mil -USBOC0
2
8 17 27 (2) -USBOC0
1206 L4 J3
1
7 18 PIO 1 2 1
1
1
0*4 RP4 GND_IO2 7536S-25G2T GND_IO2 C4 R6 120Z/100M 2
(2) -P_ACK
-P_ACK 8 1 -PP_ACK 6 19 SUYIN GND 1000P 47K 2012 3
2
3
1
P_BUSY 7 2 PP_BUSY 0603 0603 C3 C502 4
(2) P_BUSY PP_PE 4
P_PE 10U_NA 0.1U
2
(2) P_PE 6 3 5 20
P_SLCT PP_SLCT 1206 0603
2
(2) P_SLCT 5 4 GND1
10V 50V GND1
2
4 21 GND2
1206 GND2
GND3
GND3
3 22 GND4
GND4
2 23 GND_USB
B 1 24 B
USB/4PX1
LINKTEK
UAR80-4W510
PAC128401Q GND_USB
(2) USBP0_0-
QSOP24A
GND_IO2 GND_IO2
FIR Module 4 3
L3
VCC3_IR 1 2
600Z/100M
U1 FIR CORE_ACM2520U
1
VCC
2
FIRSEL AGND
(2) FIRSEL 3
FIR_SEL
4
MD0
5 (2) USBP0_0+
+3VS VCC3_IR MD1
6
NC
7
GND
1
(2) IRRX IRRX 8
JL1 R501 2.7 (2) IRTX IRTX RXD R504 R505
9
TXD
1
1 2 1 2 10 15K 15K C510 C511
LEDA 0603 0603 47P/NA
2
SHORT-SMT4 2010 1% R2 11 0603 47P/NA

GND1
1
C515 0603
2
C507
10U_NA 0.1U 0_DFS HSDL-3600
1206 0603 0603
JL501 16V 50V
2
1 2
GND_USB
SHORT-SMT4
GND_FIR
IR Mode Select
IR Mode Select
A A
IRMODE0 IRMODE1 FIRSEL RX Function TX Function
MTG1 MTG2 MTG3 FD1 FD3 FD4 FD2
HI LOW X Shutdown Shutdown ID2.8/OD7.6 ID2.8/OD7.6 ID2.8/OD7.6 FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
L501
LOW LOW LOW Full Distance Power 1 2
3
2
1
3
2
1
3
2
1
LOW HI LOW SIR 2/3 Distance Power
1
120Z/100M 4 12 4 12 4 12
HI HI LOW SIR 1/3 Distance Power 2012 5 11 5 11 5 11
6 10 6 10 6 10
GND_IO2
LOW LOW HI MIR/FIR Full Distance Power FD501 FD503 FD504 FD502
Title
7
8
9
7
8
9
7
8
9
FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK

LOW HI HI MIR/FIR 2/3 Distance Power DC POWER
HI HI HI MIR/FIR 1/3 Distance Power Size Document Rev

0A
1
1
Number 411671200004
5 4 3 2 1
Reference Material
Intel Pentium 4 Processor mFC-PGA2 478Pin Intel. INC
INTEL 82845 Memory Controller Hub Intel. INC
INTEL 82801BA I/O Controller Hub Intel. INC
PCI4410 Manual-PC Card and OHCI Controller CHRONTEL. INC
Frequency Generator ICS950805 ICS. INC

Engineer Hardware Specification Technology.Corp/MiTAC
Engineer Software Specification Technology.Corp/MiTAC

SERVICE
SERVICE MANUAL
MANUAL FOR
FOR 8170
8170
Sponsoring Editor : Jesse Jan
Author : Jacey Liu
Assistant Editor : Janne Liu
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Jan. 2002
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com

8170 ServiceManual

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8170 ServiceManual

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Verfügbare Formate

SERVICE MANUAL FOR

BY: Jacey Liu

2. System Assembly & Disassembly ------------------------------------------------------------------------------------ 82

3. Definition & Location Connectors / Switches Setting ----------------------------------------------------------- 104

3.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 104

4. Definition & Location Major Components------------------------------------------------------------------------- 109

4.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 109

5. Pin Descriptions of Major Components ---------------------------------------------------------------------------- 112

5.1 Pentium 4(Willamette/Northwood) Micro-FCPGA 478 pin---------------------------------------------------------------------- 112

7. Maintenance Diagnostic ------------------------------------------------------------------------------------------------ 137

8. Trouble Shooting -------------------------------------------------------------------------------------------------------- 142

9. Spare Parts List ---------------------------------------------------------------------------------------------------------- 178

11. Circuit Diagram -------------------------------------------------------------------------------------------------------- 190

12. Reference ---------------------------------------------------------------------------------------------------------------- 215

1.Hardware Engineering Specification

1.1.2 System Overview

Audio 1. AC'97 Interface Codec. Sound Blaster Pro Compatible.

1.2 System Architecture

8170 System Block Diagram

1.2.2.2 CORE LOGIC

PCI Bus I/F

Table 1.1 MEMORY EXPANSION CAPACITY

Table 1.2 CRT CONNECTOR

PIN SIGNAL DESCRIPTION

Table 1.3 S-VIDEO CONNECTOR

Table 1.4 IEEE1394 CONNECTOR

Figure1.4 IEEE1394 Port

Table 1.5 MODEM CONNECTOR

Table 1.6 LAN CONNECTOR

Table 1.7 USB Port2

Figure 1.8 PARALLEL PORT CONNECTOR

1.2.2.6 GRAPHICAL SUBBSYSTEM

1.2.2.8 READ ONLY MEMORY(BIOS FLASH)

1.2.2.9 POWER MANAGEMENT FEATURES

1.2.2.10 KEYBOARD CONTROLLER

1.2.2.11 SUPER I/O

1.2.2.12 LEDS INDICATOR

Table 1.9 MODEM DAUGHTER BOARD CONNECTOR

1.3 Electrical Characteristic

Figure 1.9 Power on Sequence

1.3.2 Power On Suspend Sequence

Figure 1.10 Power on Suspend Sequence

1.3.3 Resume from Power Suspend Sequence

Figure 1.11 Resume from Power Suspend Sequence

1.3.4 Suspend to RAM Sequence

Figure 1.12 Suspend to RAM sequence

1.3.5 Resume from Suspend to RAM Sequence

Figure 1.13 Resume from Suspend to RAM Sequence

1.3.6 Suspend to Disk Sequence

Figure 1.14 Suspend to Disk Sequence

1.3.7 Resume from Suspend to Disk Sequence

Figure 1.15 Resume from Suspend to Disk Sequence

1.3.8 ICH2 GPI/O Pin Define

1.3.9 Power Consumption Of Suspend Mode

1.3.10 Clock Harmonic List

1.3.11 Audio Performance

Table 1.10 Digital Playback (PC-D-A) for line Output

Table 1.12 Analog Pass-Through(A-A) for Microphone input to line Output

Table 1.13 Digital Recording(A-D-PC) for Microphone input

Test Items Mobile System

APPENDIX A WILLAMETTE CPU CORE FEQUENCY SELECTION

Bus Ratio Core Freq LINT[1]#NMI A20M# IGNNE# LINT[0]#/INTR

VID4 VID3 VID2 VID1 VID0 Vcc_max

BSEL1 BSEL0 Function