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VREF 6 VOLT 9 VZ
REF
V- 7 8 NC
CA723C (CAN)
TOP VIEW
CURRENT LIMIT
TAB
CURRENT 10
FREQ
SENSE 1 9 COMP
INV V+
INPUT 2 8 UNREG
+ INPUT
ERROR
AMP
-
NON-INV 3 7 VC
INPUT VOLT
REF
VREF 4 6
VO
5
V-, (CASE INTERNALLY
CONNECTED TO TERM 5)
3-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
CA723, CA723C
V+ FREQUENCY
UNREGULATED COMPENSATION
TEMPERATURE- INPUT
COMPENSATED
ZENER
INVERTING
INPUT VC
VREF -
VOLT ERROR SERIES PASS
REF AMP TRANSISTOR
AMP +
NON-INVERTING VO REGULATED
INPUT
OUTPUT
VZ
CURRENT CURRENT
V- LIMIT SENSE
CURRENT
LIMITER
V+ VC
UNREGULATED R1 R3 R4 R5
INPUT 500Ω 25kΩ 1kΩ 1kΩ
Q8
Q3
D3 Q7 Q14
D1
6.2V Q15
R2 Q4 Q9
15kΩ R12
15kΩ VO
Q5 Q11 Q12
R6 D4
100Ω
VZ
C1 Q10
5pF Q13
Q1 FREQUENCY
D2 COMPENSATION
Q6 6.2V R9 R10 R11 Q16 CURRENT
R7 300Ω 20kΩ LIMIT
30kΩ R8 150Ω
5kΩ
CURRENT
SENSE
VREF NON-INVERTING V- INVERTING
INPUT INPUT
3-4
CA723, CA723C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
CA723 CA723C
PARAMETER TEST CONDITION MIN TYP MAX MIN TYP MAX UNITS
DC CHARACTERISTICS
f = 50Hz to 10kHz, - 86 - - 86 - dB
CREF = 5µF
3-5
CA723, CA723C
CA723 CA723C
PARAMETER TEST CONDITION MIN TYP MAX MIN TYP MAX UNITS
Equivalent Noise RMS Output Voltage, VN BW = 100Hz to 10kHz, - -20 - - 20 - µV
(Note 3) CREF = 0
NOTES:
2. Line and load regulation specifications are given for condition of a constant chip temperature. For high dissipation condition, temperature drifts
must be separately taken into account.
3. For CREF (See Figure 20)
-55oC
-0.1
50
125oC
-0.15
125oC
0 -0.2
0 10 20 30 40 0 20 40 60 80 100
DIFFERENTIAL INPUT - OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA)
FIGURE 2. MAX LOAD CURRENT vs DIFFERENTIAL INPUT- FIGURE 3. LOAD REGULATION WITHOUT CURRENT LIMITING
OUTPUT VOLTAGE
0.05
OUTPUT VOLTAGE (VO) = 5V OUTPUT VOLTAGE (VO) = 5V
INPUT VOLTAGE (VI) = 12V INPUT VOLTAGE (VI) = 12V
SHORT CIRCUIT PROTECTION 0.1 SHORT CIRCUIT PROTECTION
0 RESISTANCE (RSCP) = 10Ω RESISTANCE (RSCP) = 0
LOAD REGULATION (VO)
-0.05 0
AMBIENT TEMPERATURE (TA) = -55oC
-0.1 -55oC -0.1
FIGURE 4. LOAD REGULATION WITH CURRENT LIMITING FIGURE 5. LOAD REGULATION WITH CURRENT LIMITING
3-6
CA723, CA723C
1.2
OUTPUT VOLTAGE (VO) = REFERENCE
5
0.8
4
0.6 AMBIENT TEMPERATURE (TA) = -55oC
3
25oC
0.4
2
0.2 125oC
1
125oC
25oC
0 0
0 20 40 60 80 100 0 10 20 30 40
OUTPUT CURRENT (mA) INPUT VOLTAGE (V)
MAX. JUNCTION TEMP. (TJ) = 150oC MAX. JUNCTION TEMP. (TJ) = 125oC
150 THERMAL RESISTANCE = 150oC/W 150 THERMAL RESISTANCE = 125oC/W
MAXIMUM LOAD CURRENT (mA)
100 100
AMBIENT TEMPERATURE (TA) = 25oC
70oC
70oC
0 0
0 10 20 30 40 0 10 20 30 40
DIFFERENTIAL INPUT - OUTPUT VOLTAGE (V) DIFFERENTIAL INPUT - OUTPUT VOLTAGE (V)
FIGURE 8. MAX LOAD CURRENT vs DIFFERENTIAL INPUT- FIGURE 9. MAX LOAD CURRENT vs DIFFERENTIAL INPUT-
OUTPUT VOLTAGE OUTPUT VOLTAGE FOR CA723CE
0oC
70oC
-0.1 -0.1
70oC
-0.2 -0.2
0 20 40 60 80 100
0 10 20 30
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
FIGURE 10. LOAD REGULATION WITHOUT CURRENT FIGURE 11. LOAD REGULATION WITH CURRENT LIMITING
LIMITING
3-7
CA723, CA723C
1.2
AMBIENT TEMPERATURE (TA) = 25oC OUTPUT VOLTAGE (VO) = REFERENCE
0.8
4
AMBIENT TEMPERATURE (TA) = 25oC
0.6
3 0oC
0.4
2 70oC
0.2 1
70oC 0oC
0 0
0 10 20 40 60 80 100 0 10 20 30 40
OUTPUT CURRENT (mA) INPUT VOLTAGE (V)
FIGURE 12. CURRENT LIMITING CHARACTERISTICS FIGURE 13. QUIESCENT CURRENT vs INPUT VOLTAGE
0 0.1
-0.1 0
-0.2 -0.1
-0.3 -0.2
-5 5 15 25 35 45 -5 5 15 25 35 45
DIFFERENTIAL INPUT - OUTPUT VOLTAGE (V) DIFFERENTIAL INPUT - OUTPUT VOLTAGE (V)
FIGURE 14. LOAD REGULATION vs DIFFERENTIAL INPUT- FIGURE 15. LINE REGULATION vs DIFFERENTIAL INPUT-
OUTPUT VOLTAGE OUTPUT VOLTAGE
10
LOAD CURRENT (IL)
10 0.7 160
0
5 0.6 120
OUTPUT VOLTAGE (VO)
SHORT CIRCUIT LIMITING
-10 CURRENT WITH RSCP = 5Ω
0 0.5 80
-20
5 0.4 WITH RSCP = 10Ω 40
-30
10 0.3 0
-5 5 15 25 35 45 -50 0 50 100 150
TIME (µs) JUNCTION TEMPERATURE (oC)
FIGURE 16. LINE TRANSIENT RESPONSE FIGURE 17. CURRENT LIMITING CHARACTERISTIC vs
JUNCTION TEMPERATURE
3-8
CA723, CA723C
10
8 INPUT VOLTAGE (VI) = 12V
6 OUTPUT VOLTAGE (V ) = 5V
OUTPUT VOLTAGE DEVIATION (mA)
O
4 4 LOAD CURRENT (I ) = 50mA
FIGURE 18. LOAD TRANSIENT RESPONSE FIGURE 19. OUTPUT IMPEDANCE vs FREQUENCY
V+ VC V+ VC
VI VI
VREF VO VREF VO
RSCP RSCP
FIGURE 20. LOW VOLTAGE REGULATOR CIRCUIT FIGURE 21. HIGH VOLTAGE REGULATOR CIRCUIT
(VO = 2V TO 7V) (VO = 7V TO 37V)
3-9
CA723, CA723C
V+ VC VI VI
R5 VC
R2 VREF VZ 2kΩ V+
VREF VO
VO
R4
3kΩ CURRENT CURRENT R REGULATED
LIMIT LIMIT SCP OUTPUT 15V
CURRENT
SENSE CURRENT R1
INV. SENSE
R3 NON
R1 INV. INPUT INV.
3kΩ NON
INPUT V- COMP INV INPUT R2
C1 REGULATED INPUT V- COMP
100pF OUTPUT-15V C1
100pF
FIGURE 22. NEGATIVE VOLTAGE REGULATOR CIRCUIT FIGURE 23. POSITIVE VOLTAGE REGULATOR CIRCUIT (WITH
EXTERNAL NPN PASS TRANSISTOR)
VI
VI
R3
60Ω 2N5956
V+ OR V+ VC REGULATED
VREF VC VO 2N6108 VREF VO OUTPUT 5V
R3 RSCP
2.7kΩ 30Ω
R1 CURRENT R1 CURRENT R4
LIMIT LIMIT 5.6kΩ
RSCP
CURRENT CURRENT
SENSE SENSE
FIGURE 24. POSITIVE VOLTRAGE REGULATOR CIRCUIT FIGURE 25. FOLDBACK CURRENT LIMITING CIRCUIT
(WITH EXTERNAL PNP PASS TRANSISTOR)
3-10
CA723, CA723C
R5 R5
3.9kΩ 10kΩ V+ VC
VI = 85V VI
V+ VC
VREF VREF VO R6
VO 10kΩ
VZ VZ TI
TI
2N3442 R2 2N6211
R4
R1 R3
3kΩ CURRENT RSCP 3kΩ CURRENT
D1
LIMIT 1Ω LIMIT
D1 12V
NON CURRENT SK3062 CURRENT
12V INV. SENSE
SK3062 SENSE
INPUT NON
INV. INV.
INPUT INV. INPUT
R3 INPUT
3kΩ R2 R1 C1
V- R4 0.001µF
COMP C1 3kΩ V-
0.001µF COMP
REGULATED REGULATED
OUTPUT-50V OUTPUT-100V
Circuit Performance Data: Circuit Performance Data:
Line Regulation (∆V = 20V) 15mV Line Regulation (∆VI = 20V) 30mV
Load Regulation (∆IL = 50mA) 20mV Load Regulation (∆IL =100mA) 20mV
NOTE: For applications employing the TO-5 Style Package and NOTE: For applications employing the TO-5 Style Package and
where VZ is required, an external 6.2V zener diode should where VZ is required, an external 6.2V zener diode should
be connected in series with VO (terminal 6) be connected in series with VO (terminal 6)
FIGURE 26. POSITIVE FLOATING REGULATOR CIRCUIT FIGURE 27. NEGATIVE FLOATING REGULATOR CIRCUIT
VI VI
V+ VC V+ VC
VREF VO RSCP NOTE 2 VREF VO R4
R3 100Ω
REGULATED VZ 100Ω
OUTPUT 5V REGULATED
C OUTPUT 5V
R1 CURRENT R1
LIMIT CURRENT LIMIT
CURRENT
SENSE CURRENT SENSE
FIGURE 28. REMOTE SHUTDOWN REGULATOR CIRCUIT FIGURE 29. SHUNT REGULATOR CIRCUIT
WITH CURRENT LIMITING
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3-11